2010 Microchip Technology Inc. DS21754M-page 1
24AA512/24LC512/24FC512
Device Selection Table
Features:
Single Supply with Operation down to 1.7V for
24AA512 and 24FC512 Devices, 2.5V for
24LC512 Devices
Low-Power CMOS Technology:
- Active current 400 uA, typical
- Standby current 100 nA, typical
2-Wire Serial Interface, I2C Compatible
Cascadable for up to Eight Devices
Schmitt Trigger Inputs for Noise Suppression
Output Slope Control to Eliminate Ground Bounce
100 kHz and 400 kHz Clock Compatibility
Page Write Time 5 ms max.
Self-Timed Erase/Write Cycle
128-Byte Page Write Buffer
Hardware Write-Protect
ESD Protection >4000V
More than 1 Million Erase/Write Cycles
Data Retention > 200 years
Packages Include 8-lead PDIP, SOIJ, SOIC,
TSSOP, DFN, Chip Scale and 14-lead TSSOP
Pb-Free and RoHS Compliant
Temperature Ranges:
- Industrial (I): -40C to +85C
- Automotive (E):-40C to +125C
Description:
The Microchip Technology Inc. 24AA512/24LC512/
24FC512 (24XX512*) is a 64K x 8 (512 Kbit) Serial
Electrically Erasable PROM, capable of operation
across a broad voltage range (1.7V to 5.5V). It has
been developed for advanced, low-power applications
such as personal communications and data acquisi-
tion. This device also has a page write capability of up
to 128 bytes of data. This device is capable of both
random and sequential reads up to the 512K boundary.
Functional address lines allow up to eight devices on
the same bus, for up to 4 Mbit address space. This
device is available in the standard 8-pin plastic DIP,
SOIJ, SOIC, TSSOP, DFN, and 14-lead TSSOP
packages. The 24AA512 is also available in the 8-lead
Chip Scale package.
Block Diagram
Package Type
Part
Number
VCC
Range
Max. Clock
Frequency
Temp.
Ranges
24AA512 1.7-5.5V 400 kHz(1) I
24LC512 2.5-5.5V 400 kHz I, E
24FC512 1.7-5.5V 1 MHz(2) I
Note 1: 100 kHz for VCC < 2.5V
2: 400 kHz for VCC < 2.5V
HV Generator
EEPROM
Array
Page Latches
YDEC
XDEC
Sense Amp.
R/W Control
Memory
Control
Logic
I/O
Control
Logic
I/O
A0 A1 A2
SDA
SCL
VCC
VSS
WP
A0
A1
A2
VSS
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
24XX512
TSSOP
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
24XX512
DFN
A0
A1
A2
VSS
WP
SCL
SDA
24XX512
5
6
7
8
4
3
2
1VCC
PDIP/SOIJ/SOIC/TSSOP
9
10
11
12
13
14
NC
NC
NC
NC
NC
NC
Note 1: Available in I-temp, “AA” only.
CS (Chip Scale)(1)
123
45
678
VCC A1 A0
WP A2
SDA SCL VSS
(TOP DOWN VIEW,
BALLS NOT VISIBLE)
512K I2C Serial EEPROM
* 24XX512 is used in this document as a generic part number for the 24AA512/24LC512/24FC512 devices.
24AA512/24LC512/24FC512
DS21754M-page 2 2010 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins  4kV
TABLE 1-1: DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
DC CHARACTERISTICS
Electrical Characteristics:
Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to +125°C
Param.
No. Sym. Characteristic Min. Max. Units Conditions
D1 A0, A1, A2, SCL, SDA
and WP pins:
——
D2 VIH High-level input voltage 0.7 VCC —V
D3 VIL Low-level input voltage 0.3 VCC
0.2 VCC
V
V
VCC 2.5V
VCC < 2.5V
D4 VHYS Hysteresis of Schmitt
Trigger inputs
(SDA, SCL pins)
0.05 VCC —VVCC 2.5V (Note)
D5 VOL Low-level output voltage 0.40 V IOL = 3.0 ma @ VCC = 4.5V
IOL = 2.1 ma @ VCC = 2.5V
D6 ILI Input leakage current ±1 AVIN = VSS or VCC, WP = VSS
VIN = VSS or VCC, WP = VCC
D7 ILO Output leakage current ±1 AVOUT = VSS or VCC
D8 CIN,
COUT
Pin capacitance
(all inputs/outputs)
—10pFVCC = 5.0V (Note)
T
A = 25°C, FCLK = 1 MHz
D9 ICC Read Operating current 400 AVCC = 5.5V, SCL = 400 kHz
ICC Write 5 mA VCC = 5.5V
D10 ICCS Standby current 1 ATA = -40°C to +85°C
SCL = SDA = VCC = 5.5V
A0, A1, A2, WP = VSS
—5ATA = -40°C to +125°C
SCL = SDA = VCC = 5.5V
A0, A1, A2, WP = VSS
Note: This parameter is periodically sampled and not 100% tested.
2010 Microchip Technology Inc. DS21754M-page 3
24AA512/24LC512/24FC512
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to +125°C
Param.
No. Sym. Characteristic Min. Max. Units Conditions
1FCLK Clock frequency
100
400
400
1000
kHz 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC512
2.5V VCC 5.5V 24FC512
2THIGH Clock high time 4000
600
600
500
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC512
2.5V VCC 5.5V 24FC512
3TLOW Clock low time 4700
1300
1300
500
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC512
2.5V VCC 5.5V 24FC512
4TRSDA and SCL rise time (Note 1)
1000
300
300
ns 1.7V VCC< 2.5V
2.5V VCC 5.5V
1.7V VCC 5.5V 24FC512
5TFSDA and SCL fall time (Note 1)
300
100
ns All except, 24FC512
1.7V VCC 5.5V 24FC512
6THD:STA Start condition hold time 4000
600
600
250
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC512
2.5V VCC 5.5V 24FC512
7TSU:STA Start condition setup time 4700
600
600
250
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC512
2.5V VCC 5.5V 24FC512
8THD:DAT Data input hold time 0 ns (Note 2)
9TSU:DAT Data input setup time 250
100
100
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 5.5V 24FC512
10 TSU:STO Stop condition setup time 4000
600
600
250
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC512
2.5V VCC 5.5V 24FC512
11 TSU:WP WP setup time 4000
600
600
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 5.5V 24FC512
12 THD:WP WP hold time 4700
1300
1300
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 5.5V 24FC512
13 TAA Output valid from clock (Note 2)
3500
900
900
400
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC512
2.5V VCC 5.5V 24FC512
14 TBUF Bus free time: Time the bus
must be free before a new trans-
mission can start
4700
1300
1300
500
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC512
2.5V VCC 5.5V 24FC512
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please
consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
24AA512/24LC512/24FC512
DS21754M-page 4 2010 Microchip Technology Inc.
16 TSP Input filter spike suppression
(SDA and SCL pins)
50 ns All except, 24FC512 (Notes 1 and 3)
17 TWC Write cycle time (byte or page) 5 ms
18 Endurance 1,000,000 cycles Page Mode, 25°C, VCC = 5.5V
(Note 4)
AC CHARACTERISTICS (Continued)
Electrical Characteristics:
Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to +125°C
Param.
No. Sym. Characteristic Min. Max. Units Conditions
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please
consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
2010 Microchip Technology Inc. DS21754M-page 5
24AA512/24LC512/24FC512
FIGURE 1-1: BUS TIMING DATA
(unprotected)
(protected)
SCL
SDA
IN
SDA
OUT
WP
5
7
6
16
3
2
89
13
D4 4
10
11 12
14
24AA512/24LC512/24FC512
DS21754M-page 6 2010 Microchip Technology Inc.
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
2.1 A0, A1 and A2 Chip Address
Inputs
The A0, A1 and A2 inputs are used by the 24XX512 for
multiple device operations. The logic levels on these
inputs are compared with the corresponding bits in the
slave address. The chip is selected if the compare is
true.
Up to eight devices may be connected to the same bus
by using different Chip Select bit combinations. These
inputs must be connected to either VCC or VSS.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable logic device,
the chip address pins must be driven to logic ‘0’ or logic
1’ before normal device operation can proceed.
2.2 Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open-
drain terminal, therefore, the SDA bus requires a pull-
up resistor to VCC (typical 10 k for 100 kHz, 2 kfor
400kHz and 1MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.3 Serial Clock (SCL)
This input is used to synchronize the data transfer from
and to the device.
2.4 Write-Protect (WP)
This pin must be connected to either VSS or VCC. If tied
to VSS, write operations are enabled. If tied to VCC,
write operations are inhibited but read operations are
not affected.
3.0 FUNCTIONAL DESCRIPTION
The 24XX512 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24XX512 works as a slave. Both master and slave
can operate as a transmitter or receiver, but the
master device determines which mode is activated.
Name PDIP SOIC SOIJ TSSOP 14-lead
TSSOP DFN CS Function
A0 1 1 1 1 1 1 3 User Configured Chip Select
A1 2 2 2 2 2 2 2 User Configured Chip Select
(NC) 3, 4, 5 Not Connected
A2 3 3 3 3 6 3 5 User Configured Chip Select
VSS 4444 7 4 8Ground
SDA 5 5 5 5 8 5 6 Serial Data
SCL 6 6 6 6 9 6 7 Serial Clock
(NC) 10, 11, 12 Not Connected
WP 7 7 7 7 13 7 4 Write-Protect Input
VCC 8 8 8 8 14 8 1 +1.7V to 5.5V (24AA512)
+2.5V to 5.5V (24LC512)
+1.7V to 5.5V (24FC512)
2010 Microchip Technology Inc. DS21754M-page 7
24AA512/24LC512/24FC512
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line, while the clock line is high, will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1 Bus Not Busy (A)
Both data and clock lines remain high.
4.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3 Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must end with a Stop condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.
4.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this Acknowledge
bit. See Figure 4-2 for acknowledge timing.
A device that acknowledges must pull down the SDA
line during the Acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the acknowledge related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (24XX512) will leave the data line high to enable
the master to generate the Stop condition.
Note: The 24XX512 does not generate any
Acknowledge bits if an internal programming
cycle is in progress.
24AA512/24LC512/24FC512
DS21754M-page 8 2010 Microchip Technology Inc.
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
FIGURE 4-2: ACKNOWLEDGE TIMING
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
Start
Condition
SCL
SDA
(A) (B) (D) (D) (C) (A)
SCL 987654321 123
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line
at this point so the Transmitter can
continue sending data.
Data from transmitter
SDA
Acknowledge
Bit
Data from transmitter
2010 Microchip Technology Inc. DS21754M-page 9
24AA512/24LC512/24FC512
5.0 DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consists of a 4-bit control code; for the
24XX512 this is set as ‘1010 binary for read and write
operations. The next three bits of the control byte are
the Chip Select bits (A2, A1 and A0). The Chip Select
bits allow the use of up to eight 24XX512 devices on
the same bus and are used to select which device is
accessed. The Chip Select bits in the control byte must
correspond to the logic levels on the corresponding A2,
A1 and A0 pins for the device to respond. These bits
are in effect the three Most Significant bits of the word
address.
The last bit of the control byte defines the operation to
be performed. When set to a one a read operation is
selected and when set to a zero a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). Because all
A15…A0 are used, there are no upper address bits that
are “don’t care”. The upper address bits are transferred
first, followed by the Less Significant bits.
Following the Start condition, the 24XX512 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a 1010 code and appro-
priate device select bits, the slave device outputs an
Acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24XX512 will select a read or
write operation.
FIGURE 5-1: CONTROL BYTE FORMAT
5.1 Contiguous Addressing Across
Multiple Devices
The Chip Select bits A2, A1 and A0 can be used to
expand the contiguous address space for up to 4 Mbit
by adding up to eight 24XX512 devices on the same
bus. In this case, software can use A0 of the control
byte as address bit A16; A1 as address bit A17; and A2
as address bit A18. It is not possible to sequentially
read across device boundaries.
FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS
1010A2 A1 A0
SACKR/W
Control Code
Chip Select
Bits
Slave Address
Acknowledge Bit
Start Bit
Read/Write Bit
1 010A
2A
1A
0R/W A
11 A
10 A
9A
7A
0
A
8••••••
A
12
Control Byte Address High Byte Address Low Byte
Control
Code
Chip
Select
Bits
A
13
A
14
A
15
24AA512/24LC512/24FC512
DS21754M-page 10 2010 Microchip Technology Inc.
6.0 WRITE OPERATIONS
6.1 Byte Write
Following the Start condition from the master, the
control code (four bits), the Chip Select (three bits) and
the R/W bit (which is a logic low) are clocked onto the
bus by the master transmitter. This indicates to the
addressed slave receiver that the address high byte will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte
transmitted by the master is the high-order byte of the
word address and will be written into the Address
Pointer of the 24XX512. The next byte is the Least
Significant Address Byte. After receiving another
Acknowledge signal from the 24XX512, the master
device will transmit the data word to be written into the
addressed memory location. The 24XX512 acknowl-
edges again and the master generates a Stop
condition. This initiates the internal write cycle and
during this time, the 24XX512 will not generate
Acknowledge signals (Figure 6-1). If an attempt is
made to write to the array with the WP pin held high, the
device will acknowledge the command, but no write
cycle will occur, no data will be written and the device
will immediately accept a new command. After a byte
Write command, the internal address counter will point
to the address location following the one that was just
written.
6.2 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24XX512 in the same way
as in a byte write. But instead of generating a Stop
condition, the master transmits up to 127 additional
bytes, which are temporarily stored in the on-chip page
buffer and will be written into memory after the master
has transmitted a Stop condition. After receipt of each
word, the seven lower Address Pointer bits are inter-
nally incremented by one. If the master should transmit
more than 128 bytes prior to generating the Stop con-
dition, the address counter will roll over and the previ-
ously received data will be overwritten. As with the byte
write operation, once the Stop condition is received, an
internal write cycle will begin (Figure 6-2). If an attempt
is made to write to the array with the WP pin held high,
the device will acknowledge the command, but no write
cycle will occur, no data will be written and the device
will immediately accept a new command.
6.3 Write Protection
The WP pin allows the user to write-protect the entire
array (0000-FFFF) when the pin is tied to VCC. If tied to
VSS the write protection is disabled. The WP pin is
sampled at the Stop bit for every Write command
(Figure 1-1). Toggling the WP pin after the Stop bit will
have no effect on the execution of the write cycle.
Note: When doing a write of less than 128 bytes
the data in the rest of the page is refreshed
along with the data bytes being written.
This will force the entire page to endure a
write cycle, for this reason endurance is
specified per page.
Note: Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and end at addresses that are
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
2010 Microchip Technology Inc. DS21754M-page 11
24AA512/24LC512/24FC512
FIGURE 6-1: BYTE WRITE
FIGURE 6-2: PAGE WRITE
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
Control
Byte
Address
High Byte
Address
Low Byte Data
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
S1010 0
A
2A
1A
0P
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
Control
Byte
Address
High Byte
Address
Low Byte Data Byte 0
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
Data Byte 127
A
C
K
S1010 0
A
2A
1A
0P
24AA512/24LC512/24FC512
DS21754M-page 12 2010 Microchip Technology Inc.
7.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition, followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, then the Start bit and control byte
must be re-sent. If the cycle is complete, then the
device will return the ACK and the master can then
proceed with the next Read or Write command. See
Figure 7-1 for flow diagram.
FIGURE 7-1: ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes
2010 Microchip Technology Inc. DS21754M-page 13
24AA512/24LC512/24FC512
8.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
control byte is set to ‘1’. There are three basic types of
read operations: current address read, random read
and sequential read.
8.1 Current Address Read
The 24XX512 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by ‘1’. Therefore, if the previous read
access was to address ‘n’ (n is any legal address), the
next current address read operation would access data
from address n + 1.
Upon receipt of the control byte with R/W bit set to ‘1’,
the 24XX512 issues an acknowledge and transmits the
8-bit data word. The master will not acknowledge the
transfer but does generate a Stop condition and the
24XX512 discontinues transmission (Figure 8-1).
FIGURE 8-1: CURRENT ADDRESS
READ
8.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24XX512 as part of a write operation (R/W bit set to
0’). After the word address is sent, the master
generates a Start condition following the acknowledge.
This terminates the write operation, but not before the
internal Address Pointer is set. Then, the master issues
the control byte again but with the R/W bit set to a one.
The 24XX512 will then issue an acknowledge and
transmit the 8-bit data word. The master will not
acknowledge the transfer but does generate a Stop
condition which causes the 24XX512 to discontinue
transmission (Figure 8-2). After a random Read
command, the internal address counter will point to the
address location following the one that was just read.
8.3 Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24XX512 transmits
the first data byte, the master issues an acknowledge
as opposed to the Stop condition used in a random
read. This acknowledge directs the 24XX512 to
transmit the next sequentially addressed 8-bit word
(Figure 8-3). Following the final byte transmitted to the
master, the master will NOT generate an acknowledge,
but will generate a Stop condition. To provide
sequential reads, the 24XX512 contains an internal
Address Pointer which is incremented by one at the
completion of each operation. This Address Pointer
allows the entire memory contents to be serially read
during one operation. The internal Address Pointer will
automatically roll over from address FFFF to address
0000 if the master acknowledges the byte received
from the array address FFFF.
Bus Activity
Master
SDA Line
Bus Activity
PS
S
T
O
P
Control
Byte
S
T
A
R
T
Data
A
C
K
N
O
A
C
K
1100
AAA1
Byte
210
24AA512/24LC512/24FC512
DS21754M-page 14 2010 Microchip Technology Inc.
FIGURE 8-2: RANDOM READ
FIGURE 8-3: SEQUENTIAL READ
Bus Activity
Master
SDA Line
Bus Activity
A
C
K
N
O
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
S
T
A
R
T
Control
Byte
Address
High Byte
Address
Low Byte
Control
Byte
Data
Byte
S
T
A
R
T
x = “don’t care” bit
S1010AAA0
210 S1010AAA
1
210 P
Bus Activity
Master
SDA Line
Bus Activity
Control
Byte Data (n) Data (n + 1) Data (n + 2) Data (n + x)
N
O
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
P
2010 Microchip Technology Inc. DS21754M-page 15
24AA512/24LC512/24FC512
9.0 PACKAGING INFORMATION
9.1 Package Marking Information
XXXXXXXX
T/XXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Lead SOIJ (5.28 mm) Example:
24LC512
0510017
I/SM
24AA512
I/P 017
0510
XXXXXXXX
YYWWNNN
T/XXXXXX
8-Lead DFN-S Example:
XXXXXXX
T/XXXXX
YYWW
24LC512
I/MF
0510
017
NNN
*Standard device marking consists of Microchip part number, year code, week code, and traceability code. For
device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.
Legend: XX...X Customer-specific information*
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
T Temperature
Blank Commercial
I Industrial
E Extended
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
3
e
3
e
3
e
24AA512/24LC512/24FC512
DS21754M-page 16 2010 Microchip Technology Inc.
Package Marking Information (Continued)
8-Lead SOIC (3.90 mm) Example:
24LC512I
0510
SNM
XXXXXXXT
NNN
XXXXYYWW
3
e
017
14-Lead TSSOP
XXXXXXXT
YYWW
NNN
Example
4L512I
0510
017
8-Lead Chip Scale
XXXXXXX
YYWWNNN
Example:
24AA512
0810017
First Line Marking Codes
Part No. 8- Lead TSSOP Package Codes
24AA512 4AE
24LC512 4LE
24FC512 4FE
2010 Microchip Technology Inc. DS21754M-page 17
24AA512/24LC512/24FC512
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DS21754M-page 18 2010 Microchip Technology Inc.
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2010 Microchip Technology Inc. DS21754M-page 19
24AA512/24LC512/24FC512
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DS21754M-page 20 2010 Microchip Technology Inc.
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2010 Microchip Technology Inc. DS21754M-page 21
24AA512/24LC512/24FC512
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA512/24LC512/24FC512
DS21754M-page 22 2010 Microchip Technology Inc.
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24AA512/24LC512/24FC512
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8QLWV 0,//,0(7(56
'LPHQVLRQ/LPLWV 0,1 120 0$;
1XPEHURI3LQV 1 
3LWFK H %6&
2YHUDOO+HLJKW $ ± ± 
0ROGHG3DFNDJH7KLFNQHVV $   
6WDQGRII $  ± 
2YHUDOO:LGWK ( %6&
0ROGHG3DFNDJH:LGWK (   
0ROGHG3DFNDJH/HQJWK '   
)RRW/HQJWK /   
)RRWSULQW / 5()
)RRW$QJOH  ± 
/HDG7KLFNQHVV F  ± 
/HDG:LGWK E  ± 
NOTE 1
D
N
E
E1
12
e
b
c
A
A1
A2
L1 L
φ
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%