IS62/65WV1288FALL
IS62/65WV1288FBLL
Integrated Silicon Solution, Inc.- www.issi.com 1
Rev. A1
03/16/2018
128Kx8 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
KEY FEATURES
High-speed access time: 45ns, 55ns
CMOS low power operation
– Operating Current: 26mA (max) at 125°C
– CMOS Standby Current: 3.0 uA (typ) at 25°C
TTL compatible interface levels
Single power supply
–1.65V-2.2V VDD (IS62/65WV1288FALL)
– 2.2V-3.6V VDD (IS62/65WV1288FBLL)
Three state outputs
Industrial and Automotive temperature support
Lead-free available
DESCRIPTION
The ISSI IS62/65WV1288FALL/BLL are high-speed,
1M bit static RAMs organized as 128K words by 8 bits.
It is fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-
performance and low power consumption devices.
When CS1# is HIGH (deselected) or when CS2 is
LOW (deselected), the device assumes a standby
mode at which the power dissipation can be reduced
down with CMOS input levels.
Easy memory expansion is provided by using Chip
Enable and Output Enable inputs. The active LOW
Write Enable (WE#) controls both writing and reading
of the memory.
The IS62/65WV1288FALL/BLL are packaged in the
JEDEC standard 32-pin TSOP (TYPE I), sTSOP
(TYPE I), SOP, and 36-pin mini BGA.
FUNCTIONAL BLOCK DIAGRAM
COLUMN I/O
CS1#
CS2
WE#
OE#CONTROL
CIRCUIT
I/O
DATA
CIRCUIT
128K x 8
MEMORY
ARRAY
DECODER
VDD
GND
A0 – A16
I/O0 – I/O7
Copyright © 2018 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
MARCH 2018
IS62/65WV1288FALL
IS62/65WV1288FBLL
Integrated Silicon Solution, Inc.- www.issi.com 2
Rev. A1
03/16/2018
PIN CONFIGURATIONS
36-Pin mini BGA (6mm x 8mm)
A0 CS2A1 A3 A6 A8
I/O4 WE#A2 A4 A7 I/O0
I/O5 NC A5 I/O1
GND VDD
VDD VSS
I/O6 NC NC I/O2
I/O7 CS1#OE# A16 A15 I/O3
A9 A11A10 A12 A13 A14
1 2 3 4 5 6
A
B
C
D
E
F
G
H
32-Pin TSOP (Type I), STSOP (Type I)
A11
A9
A8
A13
WE#
CS2
A15
VDD
NC
A16
A14
A12
A7
A6
A5
A4
OE#
A10
CS1#
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O0
I/O1
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
12
11
13
14
15
16
32
31
30
29
28
27
26
25
24
23
21
22
20
19
18
17
PIN DESCRIPTIONS
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
No Connection
Power
Ground
32-Pin SOP
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VDD
A15
CS2
WE#
A13
A8
A9
A11
OE#
A10
I/O7
CS1#
I/O6
I/O5
I/O4
I/O3
1
2
3
4
5
6
7
8
9
10
12
11
13
14
15
16
32
31
30
29
28
27
26
25
24
23
21
22
20
19
18
17
IS62/65WV1288FALL
IS62/65WV1288FBLL
Integrated Silicon Solution, Inc.- www.issi.com 3
Rev. A1
03/16/2018
FUNCTION DESCRIPTION
SRAM is one of random access memories. SRAM has three different modes supported. Each function is described
below with Truth Table.
STANDBY MODE
Device enters standby mode when deselected (CS1# HIGH or CS2 LOW). The input and output pins (I/O0-7) are
placed in a high impedance state. CMOS input in this mode will maximize saving power.
WRITE MODE
Write operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input LOW. The input
and output pins (I/O0-7) are in data input mode. Output buffers are closed during this time even if OE# is LOW.
READ MODE
Read operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input HIGH. When
OE# is LOW, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted.
In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as
READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used.
TRUTH TABLE
Mode
CS1#
CS2
WE#
OE#
I/O0-I/O7
VDD Current
Not Selected
H
X
X
X
High-Z
ISB2
X
L
X
X
High-Z
Output Disabled
L
H
H
H
High-Z
ICC
Read
L
H
H
L
DOUT
ICC
Write
L
H
L
X
DIN
ICC
IS62/65WV1288FALL
IS62/65WV1288FBLL
Integrated Silicon Solution, Inc.- www.issi.com 4
Rev. A1
03/16/2018
ABSOLUTE MAXIMUM RATINGS
AND OPERATING RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
Vterm
Terminal Voltage with Respect to GND
–0.2 to +3.9 (VDD+0.3V)
V
tBIAS
Temperature Under Bias
–55 to +125
C
VDD
VDD Related to GND
–0.2 to +3.9 (VDD+0.3V)
V
tStg
Storage Temperature
–65 to +150
C
IOUT(2)
DC Output Current (LOW)
20
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2.
This condition is not per pin. Total current of all pins must meet this value.
OPERATING RANGE (1)
Range
Ambient Temperature
Device Marking
VDD
Commercial
0C to +70C
IS62WV1288FALL
1.65V-2.2V
Industrial
-40C to +85C
IS62WV1288FALL
1.65V-2.2V
Commercial
0C to +70C
IS62WV1288FBLL
2.2V-3.6V
Industrial
-40C to +85C
IS62WV1288FBLL
2.2V-3.6V
Automotive
-40C to +125C
IS65WV1288FBLL
2.2V-3.6V
Note:
1. Full device AC operation assumes a 100 µs ramp time from 0 to VDD (min) and 200 µs wait time after VDD stabilization.
PIN CAPACITANCE (1)
Parameter
Symbol
Test Condition
Max
Units
Input capacitance
CIN
TA = 25°C, f = 1 MHz, VDD = VDD(typ)
10
pF
DQ capacitance (IO0–IO7)
CI/O
10
pF
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
THERMAL CHARACTERISTICS (1)
Parameter
Symbol
Rating
Units
Thermal resistance from junction to ambient (airflow = 1m/s)
RθJA
TBD
°C/W
Thermal resistance from junction to pins
RθJB
TBD
°C/W
Thermal resistance from junction to case
RθJC
TBD
°C/W
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
IS62/65WV1288FALL
IS62/65WV1288FBLL
Integrated Silicon Solution, Inc.- www.issi.com 5
Rev. A1
03/16/2018
ELECTRICAL CHARACTERISTICS
IS62WV1288FALL
DC ELECTRICAL CHARACTERISTICS-I
(OVER THE OPERATING RANGE)
VDD = 1.65V~2.2V
Symbol
Parameter
Test Conditions
Min
Max
Unit
VOH
Output HIGH Voltage
IOH = -0.1 mA
1.4
—
V
VOL
Output LOW Voltage
IOL = 0.1 mA
—
0.2
V
VIH
(1)
Input HIGH Voltage
1.4
VDD + 0.2
V
VIL
(1)
Input LOW Voltage
–0.2
0.4
V
ILI
Input Leakage
GND < VIN < VDD
–1
1
µA
ILO
Output Leakage
GND < VIN < VDD, Output Disabled
–1
1
µA
Notes:
1. VILL(min) = -1.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max) = VDD + 1.0V AC (pulse width < 10ns). Not 100% tested.
IS62 (5) WV1288FBLL
DC ELECTRICAL CHARACTERISTICS-I
(OVER THE OPERATING RANGE)
VDD = 2.2V~3.6V
Symbol
Parameter
Test Conditions
Min
Max
Unit
VOH
Output HIGH Voltage
2.2 ≤ VDD < 2.7, IOH = -0.1 mA
2.0
—
V
2.7 ≤ VDD ≤ 3.6, IOH = -1.0 mA
2.4
—
V
VOL
Output LOW Voltage
2.2 ≤ VDD < 2.7, IOL = 0.1 mA
—
0.4
V
2.7 ≤ VDD ≤ 3.6, IOL = 2.1 mA
—
0.4
V
VIH
(1)
Input HIGH Voltage
2.2 ≤ VDD < 2.7
1.8
VDD + 0.3
V
2.7 ≤ VDD ≤ 3.6
2.2
VDD + 0.3
V
VIL
(1)
Input LOW Voltage
2.2 ≤ VDD < 2.7
–0.3
0.6
V
2.7 ≤ VDD ≤ 3.6
–0.3
0.8
V
ILI
Input Leakage
GND < VIN < VDD
–1
1
µA
ILO
Output Leakage
GND < VIN < VDD, Output Disabled
–1
1
µA
Note:
1. VILL(min) = -2.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max) = VDD + 2.0V AC (pulse width < 10ns). Not 100% tested.
IS62/65WV1288FALL
IS62/65WV1288FBLL
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Rev. A1
03/16/2018
IS62WV1288FALL
DC ELECTRICAL CHARACTERISTICS-II FOR POWER
(OVER THE OPERATING RANGE)
Symbol
Parameter
Test Conditions
Grade
Typ(1)
Max
Unit
ICC
VDD Dynamic Operating
Supply Current
VDD = VDD(max), IOUT = 0mA, f = fmax
CS1# = VIL, CS2 = VIH
Com.
-
26
Com.
Ind.
Ind.
26
ICC1
VDD Static Operating
Supply Current
VDD = VDD(max), IOUT = 0mA, f = 0
CS1# = VIL, CS2 = VIH
Com.
-
5
Com.
Ind.
Ind.
5
ISB2
CMOS Standby Current
(CMOS Inputs)
VDD = VDD(max), f = 0,
CS1# ≥ VDD - 0.2V or
CS2 ≤ 0.2V,
VIN ≤ 0.2V or CS2 ≥ VDD - 0.2V
Com.
25°C
3.0
-
µA
45°C
3.5
-
70°C
4.0
5
Ind.
85°C
4.1
6
Note:
1. Typical values are measured at VDD = 1.8V, and not 100% tested.
IS62 (5) WV1288FBLL
DC ELECTRICAL CHARACTERISTICS-II FOR POWER
(OVER THE OPERATING RANGE)
Symbol
Parameter
Test Conditions
Grade
Typ(1)
Max
Unit
ICC
VDD Dynamic Operating
Supply Current
VDD = VDD(max), IOUT = 0mA, f = fmax
CS1# = VIL, CS2 = VIH
Com.
-
26
mA
Ind.
26
Auto.
26
ICC1
VDD Static Operating
Supply Current
VDD = VDD(max), IOUT = 0mA, f = 0
CS1# = VIL, CS2 = VIH
Com.
-
5
mA
Ind.
5
Auto.
5
ISB2
CMOS Standby Current
(CMOS Inputs)
VDD = VDD(max), f = 0,
CS1# ≥ VDD - 0.2V or
CS2 ≤ 0.2V,
VIN ≤ 0.2V or CS2 ≥ VDD - 0.2V
Com.
25°C
3.0
-
µA
45°C
3.5
-
70°C
4.0
5
Ind.
85°C
4.1
6
Auto.
125°C
9.0
18
Note:
1. Typical values are measured at VDD = 3.0V, and not 100% tested.
IS62/65WV1288FALL
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Integrated Silicon Solution, Inc.- www.issi.com 7
Rev. A1
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AC CHARACTERISTICS
(6)
(OVER OPERATING RANGE)
READ CYCLE AC CHARACTERISTICS
Parameter
Symbol
45ns
55ns
unit
notes
Min
Max
Min
Max
Read Cycle Time
tRC
45
-
55
-
ns
1,5
Address Access Time
tAA
-
45
-
55
ns
1
Output Hold Time
tOHA
10
-
10
-
ns
1
CS1#, CS2 Access Time
tACS1/ACS2
-
45
-
55
ns
1
OE# Access Time
tDOE
-
20
-
25
ns
1
OE# to High-Z Output
tHZOE
-
18
-
20
ns
2
OE# to Low-Z Output
tLZOE
5
-
5
-
ns
2
CS1#, CS2 to High-Z Output
tHZCS1/HZCS2
-
18
-
20
ns
2
CS1#, CS2 to Low-Z Output
tLZCS/LZCS2
10
-
10
-
ns
2
WRITE CYCLE AC CHARACTERISTICS
Parameter
Symbol
45ns
55ns
unit
notes
Min
Max
Min
Max
Write Cycle Time
tWC
45
-
55
-
ns
1,3,5
CS1#, CS2 to Write End
tSCS1/tSCS2
35
-
40
-
ns
1,3
Address Setup Time to Write End
tAW
35
-
40
-
ns
1,3
Address Hold from Write End
tHA
0
-
0
-
ns
1,3
Address Setup Time
tSA
0
-
0
-
ns
1,3
WE# Pulse Width
tPWE
35
-
40
-
ns
1,3,4
Data Setup to Write End
tSD
25
-
25
-
ns
1,3
Data Hold from Write End
tHD
0
-
0
-
ns
1,3
WE# LOW to High-Z Output
tHZWE
-
18
-
20
ns
2,3
WE# HIGH to Low-Z Output
tLZWE
10
-
10
-
ns
2,3
Notes:
1 Tested with the load in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. tHZOE, tHZCS, tHZB, and tHZWE transitions
are measured when the output enters a high impedance state. Not 100% tested.
3. The internal write time is defined by the overlap of CS1# = LOW, CS2=HIGH, and WE# = LOW. All four conditions must be in valid states
to initiate a Write, but any condition can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
4. tPWE > tHZWE + tSD when OE# is LOW.
5. Address inputs must meet VIH and VIL SPEC during this period. Any glitch or unknown inputs are not permitted. Unknown input with
standby mode is acceptable.
6. Data retention characteristics are defined later in DATA RETENTION CHARACTERISTICS.
IS62/65WV1288FALL
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Rev. A1
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AC TEST CONDITIONS (OVER THE OPERATING RANGE)
Parameter
Unit
(1.65V~2.2V)
Unit
(2.2V~3.6V)
Input Pulse Level
0V to VDD
0V to VDD
Input Rise and Fall Time
1V/ns
1V/ns
Output Timing Reference Level
0.9V
½ VDD
R1
13500
1005
R2
10800
820
VTM
1.8V
VDD
Output Load Conditions
Refer to Figure 1 and 2
OUTPUT LOAD CONDITIONS FIGURES
Figure1 Figure2
R1
R2
VTM
OUTPUT 30pF,
Including
jig
and scope
R1
R2
VTM
OUTPUT 5pF,
Including
jig
and scope
R1
R2
VTM
OUTPUT 5pF,
Including
jig
and scope
R1
R2
VTM
OUTPUT 5pF,
Including
jig
and scope
R1
R2
VTM
OUTPUT 5pF,
Including
jig
and scope
IS62/65WV1288FALL
IS62/65WV1288FBLL
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Rev. A1
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TIMING DIAGRAM
READ CYCLE NO. 1(1) (ADDRESS CONTROLLED) (CS1# = OE# = LOW, CS2 = WE# = HIGH)
Notes:
1. The device is continuously selected.
READ CYCLE NO. 2(1) (OE# CONTROLLED)
OE#
CS1#
DOUT
tAA
ADDRESS
tRC
tOHA
tDOE
tLZOE
tACS1/tACS2
tLZCS1/
tLZCS2
tHZOE
tHZCS1/
tHZCS2
HIGH-Z DATA VALID
CS2
LOW-Z
Notes: 1. Address is valid prior to or coincident with CS1# LOW and CS2 HIGH transition.
tRC
ADDRESS
I/O0-15
tAA
tOHA
tOHA
DATA VALID
PREVIOUS DATA VALID
Low-Z
Low-Z
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Rev. A1
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WRITE CYCLE 1(1, 2) (CS1#, CS2 Controlled, OE# = HIGH or LOW)
ADDRESS
CS1#
CS2
WE#
UB#, LB#
DOUT
DIN
tWC
tHA
tAW tPWE
tPWB
tSA
tHZWE tLZWE
tSD tHD
DATA IN VALID
DATA UNDEFINED HIGH-Z
DATA UNDEFINED
tSCS1
(1)
(2)
tSCS2
Notes: 1 tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if OE# goes high
before Write Cycle. tHZOE is the time DOUT goes to High-Z after OE# goes high
2. During this period the I/Os are in output state. Do not apply input signals.
WRITE CYCLE NO. 2(1, 2) (WE# Controlled: OE# is HIGH During Write Cycle)
ADDRESS
CS1#
CS2
WE#
UB#, LB#
DOUT
DIN
tWC
tHA
tAW tPWE
tPWB
tSA
tHZOE
tSD tHD
DATA IN VALID
DATA UNDEFINED HIGH-Z
DATA UNDEFINED
tSCS1
(1)
(2)
tSCS2
OE#
Notes:
1. tHZOE is the time DOUT goes to High-Z after OE# goes high.
2. During this period the I/Os are in output state. Do not apply input signals.
IS62/65WV1288FALL
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Rev. A1
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WRITE CYCLE NO. 3(1) (WE# CONTROLLED: OE# IS LOW DURING WRITE CYCLE)
ADDRESS
CS1#
CS2
WE#
UB#, LB#
DOUT
DIN
tWC
tHA
tAW tPWE
tPWB
tSA
tHZWE tLZWE
tSD tHD
DATA IN VALID
DATA UNDEFINED HIGH-Z
DATA UNDEFINED
tSCS1
(1)
(2)
tSCS2
Note:
1. If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the
previous READ operation will drive IO BUS.
IS62/65WV1288FALL
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Integrated Silicon Solution, Inc.- www.issi.com 12
Rev. A1
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DATA RETENTION CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
Typ.(1)
Max.
Unit
VDR
VDD for Data Retention
See Data Retention Waveform
1.5
-
-
V
IDR
Data Retention Current
VDD= VDR(min),
CS1# ≥ VDD – 0.2V
or CS2 ≤ 0.2V
VIN ≤ 0.2V or VIN ≥ VDD - 0.2V
25°C
-
3.0
5
uA
85°C
-
-
6
125°C
-
-
18
tSDR (2)
Data Retention Setup Time
See Data Retention Waveform
-
0
-
-
ns
tRDR
Recovery Time
See Data Retention Waveform
-
tRC
-
-
ns
Notes:
1. Typical values are measured at 25C, VDD = VDR (min.), and not 100% tested.
2. VDD power down slope must be longer than 100 us/volt when enter into Data Retention Mode.
DATA RETENTION WAVEFORM (CS1# CONTROLLED)
GND CS1#
VDR
VDD
CS1# > VDD – 0.2V
Data Retention Mode
tSDR tRDR
DATA RETENTION WAVEFORM (CS2 CONTROLLED)
GND
VDR
VDD
CS2 < 0.2V
Data Retention Mode
tSDR tRDR
CS2
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Rev. A1
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ORDERING INFORMATION
IS62WV1288FALL (1.65V - 2.2V)
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Package
55
IS62WV1288FALL-55TLI
TSOP (Type I, 8x20mm), Lead-free
55
IS62WV1288FALL-55BI
mini BGA (6mm x 8mm)
55
IS62WV1288FALL-55BLI
mini BGA (6mm x 8mm), Lead-free
55
IS62WV1288FALL-55HLI
sTSOP (Type I, 8x13.4mm), Lead-free
IS62WV1288FBLL (2.2V - 3.6V)
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Package
45
IS62WV1288FBLL-45TLI
TSOP (Type I, 8x20mm), Lead-free
45
IS62WV1288FBLL-45QLI
SOP, Lead-free
45
IS62WV1288FBLL-45BI
mini BGA (6mm x 8mm)
45
IS62WV1288FBLL-45BLI
mini BGA (6mm x 8mm), Lead-free
45
IS62WV1288FBLL-45HLI
sTSOP (Type I, 8x13.4mm), Lead-free
Automotive Range (A3): –40°C to +125°C
Speed (ns)
Order Part No.
Package
55
IS65WV1288FBLL-55CTLA3
TSOP (Type I, 8x20mm), Lead-free, Copper Leadframe
55
IS65WV1288FBLL-55HLA3
sTSOP (Type I, 8x13.4mm), Lead-free
55
IS65WV1288FBLL-55QLA3
SOP, Lead-free
IS62/65WV1288FALL
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Rev. A1
03/16/2018
PACKAGE INFORMATION
IS62/65WV1288FALL
IS62/65WV1288FBLL
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Rev. A1
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Integrated Silicon Solution, Inc.- www.issi.com 16
Rev. A1
03/16/2018
IS62/65WV1288FALL
IS62/65WV1288FBLL
Integrated Silicon Solution, Inc.- www.issi.com 17
Rev. A1
03/16/2018