0 QPro Virtex-E 1.8V QML High-Reliability FPGAs R DS098-1 (v1.1) July 29, 2004 0 0 Advance Product Specification Features * * * * * * * * Certified to MIL-PRF-38535 (Qualified Manufacturer Listing) Guaranteed over the full military temperature range (-55C to +125C) Ceramic and Plastic Packages Fast, High-Density 1.8V FPGA Family - Densities from 600K to 2M system gates - 130 MHz internal performance (four LUT levels) - Designed for low-power operation - PCI compliant 3.3V, 32-bit, 33 MHz Highly Flexible SelectIOTM+ Technology - Supports 20 high-performance interface standards - Up to 804 singled-ended I/Os or 344 differential I/O pairs for an aggregate bandwidth of > 100 Gb/s Differential Signalling Support - LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL - Differential I/O signals can be input, output, or I/O - Compatible with standard differential devices - LVPECL and LVDS clock inputs for 300+ MHz clocks Proprietary High-Performance SelectLink Technology - Double Data Rate (DDR) to VirtexTM-E link - Web-based HDL generation methodology Sophisticated SelectRAM+TM Memory Hierarchy - 600 Kb of internal configurable distributed RAM - Up to 640 Kb of synchronous internal block RAM - Dual port block RAM capability - Memory bandwidth up to 1.66 Tb/s (equivalent bandwidth of over 100 RAMBUS channels) - Designed for high-performance Interfaces to External Memories - 200 MHz ZBT* SRAMs * * * * * * * * - 200 Mb/s DDR SDRAMs - Supported by free Synthesizable reference design High-Performance Built-In Clock Management Circuitry - Eight fully digital Delay-Locked Loops (DLLs) - Digitally-Synthesized 50% duty cycle for Double Data Rate (DDR) Applications - Clock Multiply and Divide - Zero-delay conversion of high-speed LVPECL/LVDS clocks to any I/O standard Flexible Architecture Balances Speed and Density - Dedicated carry logic for high-speed arithmetic - Dedicated multiplier support - Cascade chain for wide-input function - Abundant registers/latches with clock enable, and dual synchronous/asynchronous set and reset - Internal 3-state bussing - IEEE 1149.1 boundary-scan logic - Die-temperature sensor diode Supported by Xilinx FoundationTM and Alliance SeriesTM Development Systems - Further compile time reduction of 50% - Internet Team Design (ITD) tool ideal for million-plus gate density designs - Wide selection of PC and workstation platforms SRAM-Based In-System Configuration - Unlimited reprogrammability Advanced Packaging Options - 1.0 mm BGA - 1.27 mm BGA 0.18 m 6-Layer Metal Process 100% Factory Tested 100% Factory Tested * ZBT is a trademark of Integrated Device Technology, Inc. Table 1: Virtex-E Field-Programmable Gate Array Family Members Device System Gates Logic Gates CLB Array Logic Cells Differential I/O Pairs User I/O Block RAM Bits Distributed RAM Bits XQV600E 985,882 186,624 48 x 72 15,552 247 316 294,912 221,184 XQV1000E 1,569,178 331,776 64 x 96 27,648 281 404 393,216 393,216 XQV2000E 2,541,952 518,400 80 x 120 43,200 344 804 655,360 614,400 (c) 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS098-1 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 1 of 4 1 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Virtex-E Compared to Virtex Devices The Virtex-E family offers up to 43,200 logic cells in devices up to 30% faster than the Virtex family. I/O performance is increased to 622 Mb/s using Source Synchronous data transmission architectures and synchronous system performance up to 240 MHz using singled-ended SelectIO technology. Additional I/O standards are supported, notably LVPECL, LVDS, and BLVDS, which use two pins per signal. Almost all signal pins can be used for these new standards. Virtex-E devices have up to 640 Kb of faster (250 MHz) block SelectRAM, but the individual RAMs are the same size and structure as in the Virtex family. They also have eight DLLs instead of the four in Virtex devices. Each individual DLL is slightly improved with easier clock mirroring and 4x frequency multiplication. VCCINT, the supply voltage for the internal logic and memory, is 1.8V, instead of 2.5V for Virtex devices. Advanced processing and 0.18 m design rules have resulted in smaller dice, faster speed, and lower power consumption. I/O pins are 3V tolerant, and can be 5V tolerant with an external 100 resistor. PCI 5V is not supported. With the addition of appropriate external resistors, any pin can tolerate any voltage desired. Banking rules are different. With Virtex devices, all input buffers are powered by VCCINT. With Virtex-E devices, the LVTTL, LVCMOS2, and PCI input buffers are powered by the I/O supply voltage VCCO. The Virtex-E family is not bitstream-compatible with the Virtex family, but Virtex designs can be compiled into equivalent Virtex-E devices. The same device in the same package for the Virtex-E and Virtex families are pin-compatible with some minor exceptions. See the data sheet pinout section for details. General Description The Virtex-E FPGA family delivers high-performance, high-capacity programmable logic solutions. Dramatic increases in silicon efficiency result from optimizing the new architecture for place-and-route efficiency and exploiting an aggressive 6-layer metal 0.18 m CMOS process. These advances make Virtex-E FPGAs powerful and flexible alter- Module 1 of 4 2 natives to mask-programmed gate arrays. The QPro Virtex-E family includes the three members in Table 1. Building on experience gained from Virtex FPGAs, the Virtex-E family is an evolutionary step forward in programmable logic design. Combining a wide variety of programmable system features, a rich hierarchy of fast, flexible interconnect resources, and advanced process technology, the Virtex-E family delivers a high-speed and high-capacity programmable logic solution that enhances design flexibility while reducing time-to-market. Virtex-E Architecture Virtex-E devices feature a flexible, regular architecture that comprises an array of configurable logic blocks (CLBs) surrounded by programmable input/output blocks (IOBs), all interconnected by a rich hierarchy of fast, versatile routing resources. The abundance of routing resources permits the Virtex-E family to accommodate even the largest and most complex designs. Virtex-E FPGAs are SRAM-based, and are customized by loading configuration data into internal memory cells. Configuration data can be read from an external SPROM (master serial mode), or can be written into the FPGA (SelectMAPTM, slave serial, and JTAG modes). The standard Xilinx Foundation Series and Alliance Series Development systems deliver complete design support for Virtex-E, covering every aspect from behavioral and schematic entry, through simulation, automatic design translation and implementation, to the creation and downloading of a configuration bit stream. Higher Performance Virtex-E devices provide better performance than previous generations of FPGAs. Designs can achieve synchronous system clock rates up to 240 MHz including I/O or 622 Mb/s using Source Synchronous data transmission architechtures. Virtex-E I/Os comply fully with 3.3V PCI specifications, and interfaces can be implemented that operate at 33 MHz or 66 MHz. While performance is design-dependent, many designs operate internally at speeds in excess of 133 MHz and can achieve over 311 MHz. www.xilinx.com 1-800-255-7778 DS098-1 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Virtex-E Device/Package Combinations and Maximum I/O Table 2: Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins) XQV600E XQV1000E XQV2000E BG432 316 - - BG560 - 404 404 CG560 - 404 - FG1156 - - 804 Virtex-E Ordering Information Example: XQV600E -6 BG 432 M Device Type Speed Temperature Range/Grade Grade(1) Number of Pins Package Type Device Ordering Options XQV600E BG432 432-ball Plastic BGA Package M Military Ceramic Temperature TC = -55C to +125C XQV1000E BG560 560-ball Plastic BGA Package N Military Plastic TJ = -55C to +125C XQV2000E FG1156 1156-ball Plastic Fine Pitch BGA Package CG560 560-column Ceramic Column Grid Package Device Type Package Grade Notes: 1. -6 only supported speed grade. Valid Ordering Combinations M Grade XQV1000E-6CG560M N Grade XQV600E-6BG432N XQV1000E-6BG560N XQV2000E-6BG560N XQV2000E-6FG1156N DS098-1 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 1 of 4 3 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Revision History The following table shows the revision history for this document. Date Version Revision 05/19/03 1.0 Initial Xilinx release. 07/29/04 1.1 * * * Module 1 of 4 4 Device/Package Availability and Ordering Information tables on page 3: Removed references to devices in CB228 and HQ240 packages (not offered). Device Ordering Options table on page 3: Removed Footnote (2) referring to Class Q order codes (not offered). Table 1: Corrected number of available User I/Os to conform to numbers in Table 2. www.xilinx.com 1-800-255-7778 DS098-1 (v1.1) July 29, 2004 Advance Product Specification 0 QPro Virtex-E 1.8V QML HighReliability FPGAs R DS098-2 (v1.1) July 29, 2004 0 0 Advance Product Specification Architectural Description Virtex-E Array The VirtexTM-E user-programmable gate array, shown in Figure 1, comprises two major configurable elements: configurable logic blocks (CLBs) and input/output blocks (IOBs). * * CLBs provide the functional elements for constructing logic IOBs provide the interface between the package pins and the CLBs CLBs interconnect through a general routing matrix (GRM). The GRM comprises an array of routing switches located at the intersections of horizontal and vertical routing channels. Each CLB nests into a VersaBlock that also provides local routing resources to connect the CLB to the GRM. Values stored in static memory cells control the configurable logic elements and interconnect resources. These values load into the memory cells on power-up, and can reload if necessary to change the function of the device. Input/Output Block The Virtex-E IOB, Figure 2, features SelectIOTM+ inputs and outputs that support a wide variety of I/O signalling standards, see Table 1. T TCE D Q CE Weak Keeper SR DLLDLL DLLDLL O OCE PAD D Q CE OBUFT VersaRing SR I CLBs BRAMs CLBs BRAMs CLBs CLBs BRAMs BRAMs Q D CE Programmable Delay IBUF IOBs IOBs IQ Vref SR SR CLK ICE ds022_02_091300 Figure 2: Virtex-E Input/Output Block (IOB) The three IOB storage elements function either as edgetriggered D-type flip-flops or as level-sensitive latches. Each IOB has a clock signal (CLK) shared by the three flip-flops and independent clock enable signals for each flip-flop. VersaRing DLLDLL DLLDLL ds022_01_121099 The VersaRingTM I/O interface provides additional routing resources around the periphery of the device. This routing improves I/O routability and facilitates pin locking. In addition to the CLK and CE control signals, the three flipflops share a Set/Reset (SR). For each flip-flop, this signal can be independently configured as a synchronous Set, a synchronous Reset, an asynchronous Preset, or an asynchronous Clear. The Virtex-E architecture also includes the following circuits that connect to the GRM. The output buffer and all of the IOB control signals have independent polarity controls. * * All pads are protected against damage from electrostatic discharge (ESD) and from over-voltage transients. After configuration, clamping diodes are connected to VCCO with the exception of LVCMOS18, LVCMOS25, GTL, GTL+, LVDS, and LVPECL. Figure 1: Virtex-E Architecture Overview * Dedicated block memories of 4096 bits each Clock DLLs for clock-distribution delay compensation and clock domain control 3-State buffers (BUFTs) associated with each CLB that drive dedicated segmentable horizontal routing resources (c) 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS098-2 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 2 of 4 1 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 1: Supported I/O Standards Each input buffer can be configured to conform to any of the low-voltage signalling standards supported. In some of these standards the input buffer utilizes a user-supplied threshold voltage, VREF. The need to supply VREF imposes constraints on which standards can be used in close proximity to each other. See "I/O Banking" on page 2. I/O Output Input Input Board Termination Standard VCCO VCCO VREF Voltage (VTT) LVTTL 3.3 3.3 N/A N/A LVCMOS2 2.5 2.5 N/A N/A LVCMOS18 1.8 1.8 N/A N/A There are optional pull-up and pull-down resistors at each user I/O input for use after configuration. Their value is in the range 50-100 k. SSTL3 I & II 3.3 N/A 1.50 1.50 Output Path SSTL2 I & II 2.5 N/A 1.25 1.25 GTL N/A N/A 0.80 1.20 GTL+ N/A N/A 1.0 1.50 The output path includes a 3-state output buffer that drives the output signal onto the pad. The output signal can be routed to the buffer directly from the internal logic or through an optional IOB output flip-flop. HSTL I 1.5 N/A 0.75 0.75 HSTL III & IV 1.5 N/A 0.90 1.50 CTT 3.3 N/A 1.50 1.50 AGP-2X 3.3 N/A 1.32 N/A PCI33_3 3.3 3.3 N/A N/A PCI66_3 3.3 3.3 N/A N/A BLVDS & LVDS 2.5 N/A N/A N/A LVPECL 3.3 N/A N/A N/A The 3-state control of the output can also be routed directly from the internal logic or through a flip-flip that provides synchronous enable and disable. Each output driver can be individually programmed for a wide range of low-voltage signalling standards. Each output buffer can source up to 24 mA and sink up to 48 mA. Drive strength and slew rate controls minimize bus transients. In most signalling standards, the output High voltage depends on an externally supplied VCCO voltage. The need to supply VCCO imposes constraints on which standards can be used in close proximity to each other. See "I/O Banking" on page 2. Optional pull-up, pull-down and weak-keeper circuits are attached to each pad. Prior to configuration all outputs not involved in configuration are forced into their high-impedance state. The pull-down resistors and the weak-keeper circuits are inactive, but I/Os can optionally be pulled up. The activation of pull-up resistors prior to configuration is controlled on a global basis by the configuration mode pins. If the pull-up resistors are not activated, all the pins are in a high-impedance state. Consequently, external pull-up or pull-down resistors must be provided on pins required to be at a well-defined logic level prior to configuration. All Virtex-E IOBs support IEEE 1149.1-compatible boundary scan testing. Input Path The Virtex-E IOB input path routes the input signal directly to internal logic and/ or through an optional input flip-flop. An optional delay element at the D-input of this flip-flop eliminates pad-to-pad hold time. The delay is matched to the internal clock-distribution delay of the FPGA, and when used, assures that the pad-to-pad hold time is zero. Module 2 of 4 2 An optional weak-keeper circuit is connected to each output. When selected, the circuit monitors the voltage on the pad and weakly drives the pin High or Low to match the input signal. If the pin is connected to a multiple-source signal, the weak keeper holds the signal in its last state if all drivers are disabled. Maintaining a valid logic level in this way eliminates bus chatter. Since the weak-keeper circuit uses the IOB input buffer to monitor the input level, an appropriate VREF voltage must be provided if the signalling standard requires one. The provision of this voltage must comply with the I/O banking rules. I/O Banking Some of the I/O standards described above require VCCO and/or VREF voltages. These voltages are externally supplied and connected to device pins that serve groups of IOBs, called banks. Consequently, restrictions exist about which I/O standards can be combined within a given bank. Eight I/O banks result from separating each edge of the FPGA into two banks, as shown in Figure 3. Each bank has multiple VCCO pins, all of which must be connected to the same voltage. This voltage is determined by the output standards in use. www.xilinx.com 1-800-255-7778 DS098-2 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Bank 1 GCLK3 GCLK2 Bank 2 Bank 7 Bank 0 VCCO rather than VCCINT. For these standards, only input and output buffers that have the same VCCO can be mixed together. The VCCO and VREF pins for each bank appear in the device pin-out tables and diagrams. The diagrams also show the bank affiliation of each I/O. GCLK1 GCLK0 Bank 5 Within a given package, the number of VREF and VCCO pins can vary depending on the size of device. In larger devices, more I/O pins convert to VREF pins. Since these are always a super set of the VREF pins used for smaller devices, it is possible to design a PCB that permits migration to a larger device if necessary. All the VREF pins for the largest device anticipated must be connected to the VREF voltage, and not used for I/O. Bank 3 Bank 6 VirtexE Device Bank 4 ds022_03_121799 Figure 3: Virtex-E I/O Banks Within a bank, output standards can be mixed only if they use the same VCCO. Compatible standards are shown in Table 2. GTL and GTL+ appear under all voltages because their open-drain outputs do not depend on VCCO. Configurable Logic Blocks Table 2: Compatible Output Standards VCCO Compatible Standards 3.3V PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL, GTL+, LVPECL 2.5V SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+, BLVDS, LVDS 1.8V LVCMOS18, GTL, GTL+ 1.5V HSTL I, HSTL III, HSTL IV, GTL, GTL+ Some input standards require a user-supplied threshold voltage, VREF. In this case, certain user-I/O pins are automatically configured as inputs for the VREF voltage. Approximately one in six of the I/O pins in the bank assume this role. The VREF pins within a bank are interconnected internally and consequently only one VREF voltage can be used within each bank. All VREF pins in the bank, however, must be connected to the external voltage source for correct operation. Within a bank, inputs that require VREF can be mixed with those that do not. However, only one VREF voltage can be used within a bank. In Virtex-E, input buffers with LVTTL, LVCMOS2, LVCMOS18, PCI33_3, PCI66_3 standards are supplied by DS098-2 (v1.1) July 29, 2004 Advance Product Specification In smaller devices, some VCCO pins used in larger devices do not connect within the package. These unconnected pins can be left unconnected externally, or can be connected to the VCCO voltage to permit migration to a larger device if necessary. The basic building block of the Virtex-E CLB is the logic cell (LC). An LC includes a 4-input function generator, carry logic, and a storage element. The output from the function generator in each LC drives both the CLB output and the D input of the flip-flop. Each Virtex-E CLB contains four LCs, organized in two similar slices, as shown in Figure 4. Figure 5 shows a more detailed view of a single slice. In addition to the four basic LCs, the Virtex-E CLB contains logic that combines function generators to provide functions of five or six inputs. Consequently, when estimating the number of system gates provided by a given device, each CLB counts as 4.5 LCs. Look-Up Tables Virtex-E function generators are implemented as 4-input look-up tables (LUTs). In addition to operating as a function generator, each LUT can provide a 16 x 1-bit synchronous RAM. Furthermore, the two LUTs within a slice can be combined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM, or a 16 x 1-bit dual-port synchronous RAM. The Virtex-E LUT can also provide a 16-bit shift register that is ideal for capturing high-speed or burst-mode data. This mode can also be used to store data in applications such as Digital Signal Processing. www.xilinx.com 1-800-255-7778 Module 2 of 4 3 R QPro Virtex-E 1.8V QML High-Reliability FPGAs COUT COUT YB Y G4 G3 G2 LUT SP D Q CE Carry & Control YB Y G4 G3 YQ G1 LUT G2 SP D Q CE Carry & Control YQ G1 RC BY RC BY XB X F4 F3 LUT F2 SP D Q CE Carry & Control F1 XB F3 XQ LUT F2 SP D Q CE Carry & Control XQ F1 RC BX X F4 RC BX Slice 1 Slice 0 CIN CIN ds022_04_121799 Figure 4: 2-Slice Virtex-E CLB COUT YB CY G4 G3 G2 G1 I3 I2 I1 I0 Y O LUT DI WE 0 INIT D Q CE 1 REV YQ BY XB F5IN F6 CY CK WE A4 WSO I3 I2 I1 I0 WE WSH BX X DI INIT DQ CE BX F4 F3 F2 F1 F5 F5 BY DG XQ DI REV O LUT 0 1 SR CLK CE CIN ds022_05_092000 Figure 5: Detailed View of Virtex-E Slice Storage Elements The storage elements in the Virtex-E slice can be configured either as edge-triggered D-type flip-flops or as levelsensitive latches. The D inputs can be driven either by the Module 2 of 4 4 function generators within the slice or directly from slice inputs, bypassing the function generators. In addition to Clock and Clock Enable signals, each Slice has synchronous set and reset signals (SR and BY). SR www.xilinx.com 1-800-255-7778 DS098-2 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs forces a storage element into the initialization state specified for it in the configuration. BY forces it into the opposite state. Alternatively, these signals can be configured to operate asynchronously. All of the control signals are independently invertible, and are shared by the two flip-flops within the slice. Additional Logic The F5 multiplexer in each slice combines the function generator outputs. This combination provides either a function generator that can implement any 5-input function, a 4:1 multiplexer, or selected functions of up to nine inputs. Similarly, the F6 multiplexer combines the outputs of all four function generators in the CLB by selecting one of the F5multiplexer outputs. This permits the implementation of any 6-input function, an 8:1 multiplexer, or selected functions of up to 19 inputs. Each CLB has four direct feedthrough paths, two per slice. These paths provide extra data input lines or additional local routing that does not consume logic resources. Arithmetic Logic Dedicated carry logic provides fast arithmetic carry capability for high-speed arithmetic functions. The Virtex-E CLB supports two separate carry chains, one per Slice. The height of the carry chains is two bits per CLB. Table 3: CLB/Block RAM Column Locations Column Number XQ Device 0 12 24 V600E V1000E V2000E 36 48 60 72 84 96 108 120 Table 4 shows the amount of block SelectRAM memory that is available in each Virtex-E device. Table 4: Virtex-E Block SelectRAM Amounts Virtex-E Device # of Blocks Block SelectRAM Bits XQV600E 72 294,912 XQV1000E 96 393,216 XQV2000E 160 655,360 As illustrated in Figure 6, each block SelectRAM cell is a fully synchronous dual-ported (True Dual Port) 4096-bit RAM with independent control signals for each port. The data widths of the two ports can be configured independently, providing built-in bus-width conversion. RAMB4_S#_S# The arithmetic logic includes an XOR gate that allows a 2bit full adder to be implemented within a slice. In addition, a dedicated AND gate improves the efficiency of multiplier implementation. The dedicated carry path can also be used to cascade function generators for implementing wide logic functions. WEA ENA RSTA CLKA ADDRA[#:0] DIA[#:0] BUFTs WEB ENB RSTB CLKB ADDRB[#:0] DIB[#:0] Each Virtex-E CLB contains two 3-state drivers (BUFTs) that can drive on-chip busses. See "Dedicated Routing" on page 6. Each Virtex-E BUFT has an independent 3-state control pin and an independent input pin. DOA[#:0] DOB[#:0] ds022_06_121699 Block SelectRAM Figure 6: Dual-Port Block SelectRAM Virtex-E FPGAs incorporate large block SelectRAM memories. These complement the Distributed SelectRAM memories that provide shallow RAM structures implemented in CLBs. Block SelectRAM memory blocks are organized in columns, starting at the left (column 0) and right outside edges and inserted every 12 CLB columns (see notes for smaller devices). Each memory block is four CLBs high, and each memory column extends the full height of the chip, immediately adjacent (to the right, except for column 0) of the CLB column locations indicated in Table 3. DS098-2 (v1.1) July 29, 2004 Advance Product Specification Table 5 shows the depth and width aspect ratios for the block SelectRAM. The Virtex-E block SelectRAM also includes dedicated routing to provide an efficient interface with both CLBs and other block SelectRAMs. Refer to XAPP130 for block SelectRAM timing waveforms. Table 5: Block SelectRAM Port Aspect Ratios Width Depth ADDR Bus Data Bus 1 4096 ADDR<11:0> DATA<0> 2 2048 ADDR<10:0> DATA<1:0> www.xilinx.com 1-800-255-7778 Module 2 of 4 5 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 5: Block SelectRAM Port Aspect Ratios Width Depth ADDR Bus Data Bus 4 1024 ADDR<9:0> DATA<3:0> resources are associated with this level of the routing hierarchy. General-purpose routing resources are located in horizontal and vertical routing channels associated with the CLB rows and columns and are as follows: 8 512 ADDR<8:0> DATA<7:0> * 16 256 ADDR<7:0> DATA<15:0> Programmable Routing Matrix It is the longest delay path that limits the speed of any worstcase design. Consequently, the Virtex-E routing architecture and its place-and-route software were defined in a joint optimization process. This joint optimization minimizes long-path delays, and consequently, yields the best system performance. The joint optimization also reduces design compilation times because the architecture is software-friendly. Design cycles are correspondingly reduced due to shorter design iteration times. Local Routing * * * The VersaBlock provides local routing resources (see Figure 7), providing three types of connections: * * * Interconnections among the LUTs, flip-flops, and GRM Internal CLB feedback paths that provide high-speed connections to LUTs within the same CLB, chaining them together with minimal routing delay Direct paths that provide high-speed connections between horizontally adjacent CLBs, eliminating the delay of the GRM. To Adjacent GRM To Adjacent GRM GRM I/O Routing Virtex-E devices have additional routing resources around their periphery that form an interface between the CLB array and the IOBs. This additional routing, called the VersaRing, facilitates pin-swapping and pin-locking, such that logic redesigns can adapt to existing PCB layouts. Time-to-market is reduced, since PCBs and other system components can be manufactured while the logic design is still in progress. Dedicated Routing To Adjacent GRM Some classes of signal require dedicated routing resources to maximize performance. In the Virtex-E architecture, dedicated routing resources are provided for two classes of signal. To Adjacent GRM Direct Connection To Adjacent CLB * CLB Direct Connection To Adjacent CLB XCVE_ds_007 Figure 7: Virtex-E Local Routing * General Purpose Routing Most Virtex-E signals are routed on the general purpose routing, and consequently, the majority of interconnect Module 2 of 4 6 Adjacent to each CLB is a General Routing Matrix (GRM). The GRM is the switch matrix through which horizontal and vertical routing resources connect, and is also the means by which the CLB gains access to the general purpose routing. 24 single-length lines route GRM signals to adjacent GRMs in each of the four directions. 72 buffered Hex lines route GRM signals to another GRMs six-blocks away in each one of the four directions. Organized in a staggered pattern, Hex lines are driven only at their endpoints. Hex-line signals can be accessed either at the endpoints or at the midpoint (three blocks from the source). One third of the Hex lines are bidirectional, while the remaining ones are uni-directional. 12 Longlines are buffered, bidirectional wires that distribute signals across the device quickly and efficiently. Vertical Longlines span the full height of the device, and horizontal ones span the full width of the device. * Horizontal routing resources are provided for on-chip 3state busses. Four partitionable bus lines are provided per CLB row, permitting multiple busses within a row, as shown in Figure 8. Two dedicated nets per CLB propagate carry signals vertically to the adjacent CLB.Global Clock Distribution Network DLL Location www.xilinx.com 1-800-255-7778 DS098-2 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Clock Routing Clock Routing resources distribute clocks and other signals with very high fanout throughout the device. Virtex-E devices include two tiers of clock routing resources referred to as global and local clock routing resources. * * The global routing resources are four dedicated global nets with dedicated input pins that are designed to distribute high-fanout clock signals with minimal skew. Each global clock net can drive all CLB, IOB, and block RAM clock pins. The global nets can be driven only by global buffers. There are four global buffers, one for each global net. The local clock routing resources consist of 24 backbone lines, 12 across the top of the chip and 12 across bottom. From these lines, up to 12 unique signals per column can be distributed via the 12 longlines in the column. These local resources are more flexible than the global resources since they are not restricted to routing only to clock pins. Tri-State Lines CLB CLB CLB CLB buft_c.eps Figure 8: BUFT Connections to Dedicated Horizontal Bus LInes Global Clock Distribution Virtex-E provides high-speed, low-skew clock distribution through the global routing resources described above. A typical clock distribution net is shown in Figure 9. GCLKPAD3 GCLKPAD2 GCLKBUF3 GCLKBUF2 Global Clock Column Global Clock Rows Global Clock Spine GCLKBUF1 GCLKBUF0 GCLKPAD1 GCLKPAD0 Digital Delay-Locked Loops There are eight DLLs (Delay-Locked Loops) per device, with four located at the top and four at the bottom, Figure 10. The DLLs can be used to eliminate skew between the clock input pad and the internal clock input pins throughout the device. Each DLL can drive two global clock networks.The DLL monitors the input clock and the distributed clock, and automatically adjusts a clock delay element. Additional delay is introduced such that clock edges arrive at internal flip-flops synchronized with clock edges arriving at the input. In addition to eliminating clock-distribution delay, the DLL provides advanced control of multiple clock domains. The DLL provides four quadrature phases of the source clock, and can double the clock or divide the clock by 1.5, 2, 2.5, 3, 4, 5, 8, or 16. The DLL also operates as a clock mirror. By driving the output from a DLL off-chip and then back on again, the DLL can be used to de-skew a board level clock among multiple devices. XCVE_009 Figure 9: Global Clock Distribution Network Four global buffers are provided, two at the top center of the device and two at the bottom center. These drive the four global nets that in turn drive any clock pin. Four dedicated clock pads are provided, one adjacent to each of the global buffers. The input to the global buffer is DS098-2 (v1.1) July 29, 2004 Advance Product Specification selected either from these pads or from signals in the general purpose routing. To guarantee that the system clock is operating correctly prior to the FPGA starting up after configuration, the DLL can delay the completion of the configuration process until after it has achieved lock. For more information about DLL functionality, see the Design Consideration section of the data sheet. www.xilinx.com 1-800-255-7778 Module 2 of 4 7 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Boundary-scan operation is independent of individual IOB configurations, and unaffected by package type. All IOBs, including un-bonded ones, are treated as independent 3state bidirectional pins in a single scan chain. Retention of the bidirectional test capability after configuration facilitates the testing of external interconnections. Secondary DLLs Secondary DLLs VCCO in bank 2, and for proper operation of LVTTL 3.3V levels, the bank should be supplied with 3.3V. DLLDLL DLLDLL Primary DLLs Table 6 lists the boundary-scan instructions supported in Virtex-E FPGAs. Internal signals can be captured during EXTEST by connecting them to un-bonded or unused IOBs. They can also be connected to the unused outputs of IOBs defined as unidirectional input pins. DLLDLL DLLDLL XCVE_0010 Before the device is configured, all instructions except USER1 and USER2 are available. After configuration, all instructions are available. During configuration, it is recommended that those operations using the boundary-scan register (SAMPLE/PRELOAD, INTEST, EXTEST) not be performed. Figure 10: DLL Locations Boundary Scan Virtex-E devices support all the mandatory boundary-scan instructions specified in the IEEE standard 1149.1. A Test Access Port (TAP) and registers are provided that implement the EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS, IDCODE, USERCODE, and HIGHZ instructions. The TAP also supports two internal scan chains and configuration/readback of the device. In addition to the test instructions outlined above, the boundary-scan circuitry can be used to configure the FPGA, and also to read back the configuration data. Figure 11 is a diagram of the Virtex-E Series boundary scan logic. It includes three bits of Data Register per IOB, the IEEE 1149.1 Test Access Port controller, and the Instruction Register with decodes. The JTAG input pins (TDI, TMS, TCK) do not have a VCCO requirement and operate with either 2.5V or 3.3V input signalling levels. The output pin (TDO) is sourced from the DATA IN IOB.T 0 1 0 IOB IOB IOB IOB sd D D Q Q 1 LE IOB IOB IOB IOB IOB IOB IOB IOB IOB 1 sd D Q D Q 0 LE 1 IOB.I 0 1 IOB IOB IOB IOB IOB BYPASS REGISTER 0 sd D Q D Q LE 1 0 IOB.Q IOB IOB.T TDI INSTRUCTION REGISTER M TDO U X 0 1 0 sd D Q D Q 1 LE 1 0 sd D Q D Q LE 1 IOB.I 0 DATAOUT SHIFT/ CLOCK DATA CAPTURE REGISTER UPDATE EXTEST X9016 Figure 11: Virtex-E Family Boundary Scan Logic Module 2 of 4 8 www.xilinx.com 1-800-255-7778 DS098-2 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Instruction Set The Virtex-E Series boundary scan instruction set also includes instructions to configure the device and read back configuration data (CFG_IN, CFG_OUT, and JSTART). The complete instruction set is coded as shown in Table 6.. Table 6: Boundary Scan Instructions Boundary-Scan Command Binary Code(4:0) Description EXTEST 00000 Enables boundary-scan EXTEST operation SAMPLE/ PRELOAD 00001 Enables boundary-scan SAMPLE/PRELOAD operation USER1 00010 Access user-defined register 1 USER2 00011 Access user-defined register 2 CFG_OUT 00100 Access the configuration bus for read operations. CFG_IN 00101 Access the configuration bus for write operations. INTEST 00111 Enables boundary-scan INTEST operation USERCODE 01000 Each EXTEST CAPTURED-OR state captures all In, Out, and 3-state pins. The other standard data register is the single flip-flop BYPASS register. It synchronizes data being passed through the FPGA to the next downstream boundary scan device. The FPGA supports up to two additional internal scan chains that can be specified using the BSCAN macro. The macro provides two user pins (SEL1 and SEL2) which are decodes of the USER1 and USER2 instructions respectively. For these instructions, two corresponding pins (T DO1 and TDO2) allow user scan data to be shifted out of TDO. Likewise, there are individual clock pins (DRCK1 and DRCK2) for each user register. There is a common input pin (TDI) and shared output pins that represent the state of the TAP controller (RESET, SHIFT, and UPDATE). Bit Sequence The order within each IOB is: In, Out, 3-State. The inputonly pins contribute only the In bit to the boundary scan I/O data register, while the output-only pins contributes all three bits. From a cavity-up view of the chip (as shown in EPIC), starting in the upper right chip corner, the boundary scan dataregister bits are ordered as shown in Figure 12. Bit 0 ( TDO end) Bit 1 Bit 2 Enables shifting out USER code Right half of top-edge IOBs (Right to Left) GCLK2 GCLK3 Left half of top-edge IOBs (Right to Left) Left-edge IOBs (Top to Bottom) IDCODE 01001 Enables shifting out of ID Code M1 M0 M2 HIGHZ 01010 3-states output pins while enabling the Bypass Register Left half of bottom-edge IOBs (Left to Right) GCLK1 GCLK0 Right half of bottom-edge IOBs (Left to Right) JSTART BYPASS RESERVED 01100 11111 All other codes Clock the start-up sequence when StartupClk is TCK DONE PROG Right-edge IOBs (Bottom to Top) (TDI end) Enables BYPASS 990602001 Xilinx reserved instructions Figure 12: Boundary Scan Bit Sequence Data Registers The primary data register is the boundary scan register. For each IOB pin in the FPGA, bonded or not, it includes three bits for In, Out, and 3-State Control. Non-IOB pins have appropriate partial bit population if input-only or output-only. DS098-2 (v1.1) July 29, 2004 Advance Product Specification CCLK BSDL (Boundary Scan Description Language) files for Virtex-E Series devices are available on the Xilinx web site in the File Download area. Identification Registers The IDCODE register is supported. By using the IDCODE, the device connected to the JTAG port can be determined. www.xilinx.com 1-800-255-7778 Module 2 of 4 9 R QPro Virtex-E 1.8V QML High-Reliability FPGAs The IDCODE register has the following binary format: vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1 For HDL design entry, the Xilinx FPGA Foundation development system provides interfaces to the following synthesis design environments. where v = the die version number f = the family code (05 for Virtex-E family) a = the number of CLB rows (ranges from 48 for XQV600E to 80 for XQV2000E) c = the company code (49h for Xilinx) * * * The USERCODE register is supported. By using the USERCODE, a user-programmable identification code can be loaded and shifted out for examination. The identification code (see Table 7) is embedded in the bitstream during bitstream generation and is valid only after configuration. IDCODE XCV600E v0A30093h XCV1000E v0A40093h XCV2000E v0A50093h For schematic design entry, the Xilinx FPGA Foundation and Alliance development system provides interfaces to the following schematic-capture design environments. * * Mentor Graphics V8 (Design Architect, QuickSim II) Viewlogic Systems (Viewdraw) A standard interface-file specification, Electronic Design Interchange Format (EDIF), simplifies file transfers into and out of the development system. Virtex-E FPGAs are supported by a unified library of standard functions. This library contains over 400 primitives and macros, ranging from 2-input AND gates to 16-bit accumulators, and includes arithmetic functions, comparators, counters, data registers, decoders, encoders, I/O functions, latches, Boolean functions, multiplexers, shift registers, and barrel shifters. Note: Attempting to load an incorrect bitstream causes configuration to fail and can damage the device. Including Boundary Scan in a Design Since the boundary scan pins are dedicated, no special element needs to be added to the design unless an internal data register (USER1 or USER2) is desired. If an internal data register is used, insert the boundary scan symbol and connect the necessary pins as appropriate. Development System Virtex-E FPGAs are supported by the Xilinx Foundation and Alliance Series CAE tools. The basic methodology for Virtex-E design consists of three interrelated steps: design entry, implementation, and verification. Industry-standard tools are used for design entry and simulation (for example, Synopsys FPGA Express), while Xilinx provides proprietary architecture-specific tools for implementation. The Xilinx development system is integrated under the Xilinx Design Manager (XDMTM) software, providing designers with a common user interface regardless of their choice of entry and verification tools. The XDM software simplifies the selection of implementation options with pull-down menus and on-line help. Application programs ranging from schematic capture to Placement and Routing (PAR) can be accessed through the XDM software. The program command sequence is generated prior to execution, and stored for documentation. Several advanced software features facilitate Virtex-E design. RPMs, for example, are schematic-based macros with relative Module 2 of 4 10 Synopsys (FPGA Compiler, FPGA Express) Exemplar (Spectrum) Synplicity (Synplify) Third-party vendors support many other environments. Table 7: IDCODEs Assigned to Virtex-E FPGAs FPGA location constraints to guide their placement. They help ensure optimal implementation of common functions. The "soft macro" portion of the library contains detailed descriptions of common logic functions, but does not contain any partitioning or placement information. The performance of these macros depends, therefore, on the partitioning and placement obtained during implementation. RPMs, on the other hand, do contain predetermined partitioning and placement information that permits optimal implementation of these functions. Users can create their own library of soft macros or RPMs based on the macros and primitives in the standard library. The design environment supports hierarchical design entry, with high-level schematics that comprise major functional blocks, while lower-level schematics define the logic in these blocks. These hierarchical design elements are automatically combined by the implementation tools. Different design entry tools can be combined within a hierarchical design, thus allowing the most convenient entry method to be used for each portion of the design. Design Implementation The place-and-route tools (PAR) automatically provide the implementation flow described in this section. The partitioner takes the EDIF net list for the design and maps the logic into the architectural resources of the FPGA (CLBs and IOBs, for example). The placer then determines the best locations for these blocks based on their interconnections and the desired performance. Finally, the router interconnects the blocks. www.xilinx.com 1-800-255-7778 DS098-2 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs The PAR algorithms support fully automatic implementation of most designs. For demanding applications, however, the user can exercise various degrees of control over the process. User partitioning, placement, and routing information is optionally specified during the design-entry process. The implementation of highly structured designs can benefit greatly from basic floor planning. Design Verification The implementation software incorporates Timing Wizard(R) timing-driven placement and routing. Designers specify timing requirements along entire paths during design entry. The timing path analysis routines in PAR then recognize these user-specified requirements and accommodate them. The development system supports both software simulation and in-circuit debugging techniques. For simulation, the system extracts the post-layout timing information from the design database, and back-annotates this information into the net list for use by the simulator. Alternatively, the user can verify timing-critical portions of the design using the TRCE(R) static timing analyzer. Timing requirements are entered on a schematic in a form directly relating to the system requirements, such as the targeted clock frequency, or the maximum allowable delay between two registers. In this way, the overall performance of the system along entire signal paths is automatically tailored to user-generated specifications. Specific timing information for individual nets is unnecessary. In addition to conventional software simulation, FPGA users can use in-circuit debugging techniques. Because Xilinx devices are infinitely reprogrammable, designs can be verified in real time without the need for extensive sets of software simulation vectors. For in-circuit debugging, an optional download and readback cable is available. This cable connects the FPGA in the target system to a PC or workstation. After downloading the design into the FPGA, the designer can single-step the logic, readback the contents of the flip-flops, and so observe the internal logic state. Simple modifications can be downloaded into the system in a matter of minutes. Configuration Virtex-E devices are configured by loading configuration data into the internal configuration memory. Note that attempting to load an incorrect bitstream causes configuration to fail and can damage the device. Some of the pins used for configuration are dedicated pins, while others can be re-used as general purpose inputs and outputs once configuration is complete. The following are dedicated pins: * * * * * Note that some configuration pins can act as outputs. For correct operation, these pins require a VCCO of 3.3 V or 2.5 V. At 3.3 V the pins operate as LVTTL, and at 2.5 V they operate as LVCMOS. All affected pins fall in banks 2 or 3. The configuration pins needed for SelectMap (CS, Write) are located in bank 1. Configuration Modes Virtex-E supports the following four configuration modes. Mode pins (M2, M1, M0) Configuration clock pin (CCLK) PROGRAM pin DONE pin Boundary-scan pins (TDI, TDO, TMS, TCK) * * * * Depending on the configuration mode chosen, CCLK can be an output generated by the FPGA, or can be generated externally and provided to the FPGA as an input. The PROGRAM pin must be pulled High prior to reconfiguration. Slave-serial mode Master-serial mode SelectMAP mode Boundary-scan mode (JTAG) The Configuration mode pins (M2, M1, M0) select among these configuration modes with the option in each case of having the IOB pins either pulled up or left floating prior to configuration. The selection codes are listed in Table 8. Table 8: Configuration Codes Configuration Mode M2 M1 M0 CCLK Direction Data Width Serial Dout Configuration Pull-ups Master-serial mode 0 0 0 Out 1 Yes No Boundary-scan mode 1 0 1 N/A 1 No No SelectMAP mode 1 1 0 In 8 No No Slave-serial mode 1 1 1 In 1 Yes No Master-serial mode 1 0 0 Out 1 Yes Yes Boundary-scan mode 0 0 1 N/A 1 No Yes SelectMAP mode 0 1 0 In 8 No Yes Slave-serial mode 0 1 1 In 1 Yes Yes DS098-2 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 2 of 4 11 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Configuration through the boundary-scan port is always available, independent of the mode selection. Selecting the boundary-scan mode simply turns off the other modes. The three mode pins have internal pull-up resistors, and default to a logic High if left unconnected. However, it is recommended to drive the configuration mode pins externally. Table 9 lists the total number of bits required to configure each device. Table 9: Virtex-E Bitstream Lengths Device # of Configuration Bits XQV600E 3,961,632 XQV1000E 6,587,520 XQV2000E 10,159,648 Multiple FPGAs can be daisy-chained for configuration from a single source. After a particular FPGA has been configured, the data for the next device is routed to the DOUT pin. The data on the DOUT pin changes on the rising edge of CCLK. The change of DOUT on the rising edge of CCLK differs from previous families, but does not cause a problem for mixed configuration chains. This change was made to improve serial configuration rates for Virtex and Virtex-E only chains. Figure 13 shows a full master/slave system. A Virtex-E device in slave-serial mode should be connected as shown in the right-most device. Slave-Serial Mode In slave-serial mode, the FPGA receives configuration data in bit-serial form from a serial PROM or other source of serial configuration data. The serial bitstream must be set up at the DIN input pin a short time before each rising edge of an externally generated CCLK. For more detailed information on serial PROMs, see the PROM data sheet at http://www.xilinx.com/bvdocs/publications/ds082.pdf. Slave-serial mode is selected by applying <111> or <011> to the mode pins (M2, M1, M0). A weak pull-up on the mode pins makes slave serial the default mode if the pins are left unconnected. However, it is recommended to drive the configuration mode pins externally. Figure 14 shows slaveserial mode programming switching characteristics. Table 10 provides more detail about the characteristics shown in Figure 14. Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High. Table 10: Master/Slave Serial Mode Programming Switching Symbol min max Units DIN setup/hold, slave mode 1/2 TDCC / TCCD 5.0 / 0.0 - ns DIN setup/hold, master mode 1/2 TDSCK / TCKDS 5.0 / 0.0 - ns DOUT 3 TCCO 12.0 ns High time 4 TCCH 5.0 - ns Low time 5 TCCL 5.0 - ns Maximum Frequency - FCC - 66 MHz Frequency Tolerance, master mode with respect to nominal - - -30 +45 % Description CCLK Values Figure References Module 2 of 4 12 www.xilinx.com 1-800-255-7778 DS098-2 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs . N/C 3.3V 330 M0 M1 M2 N/C DOUT XC1701L CCLK DIN PROGRAM DONE DOUT CCLK VIRTEX-E MASTER SERIAL Optional Pull-up 1 Resistor on Done M0 M1 M2 DIN CLK DATA CE INIT CEO RESET/OE VIRTEX-E, XC4000XL, SLAVE PROGRAM DONE INIT (Low Reset Option Used) PROGRAM Note 1: If none of the Virtex FPGAs have been selected to drive DONE, an external pull-up resistor of 330 should be added to the common DONE line. (For Spartan-XL devices, add a 4.7K pull-up resistor.) This pull-up is not needed if the DriveDONE attribute is set. If used, DriveDONE should be selected only for the last device in the configuration chain. XCVE_ds_013_050103 Figure 13: Master/Slave Serial Mode Circuit Diagram DIN 1 TDCC 2 TCCD 5 TCCL CCLK 4 TCCH 3 TCCO DOUT (Output) X5379_a Figure 14: Slave-Serial Mode Programming Switching Characteristics Master-Serial Mode In master-serial mode, the CCLK output of the FPGA drives a Xilinx Serial PROM that feeds bit-serial data to the DIN input. The FPGA accepts this data on each rising CCLK edge. After the FPGA has been loaded, the data for the next device in a daisy-chain is presented on the DOUT pin after the rising CCLK edge. The interface is identical to slave-serial except that an internal oscillator is used to generate the configuration clock (CCLK). A wide range of frequencies can be selected for CCLK, which always starts at a slow default frequency. Configuration bits then switch CCLK to a higher frequency for the remainder of the configuration. Switching to a lower frequency is prohibited. The CCLK frequency is set using the ConfigRate option in the bitstream generation software. The maximum CCLK fre- DS098-2 (v1.1) July 29, 2004 Advance Product Specification quency that can be selected is 60 MHz. When selecting a CCLK frequency, ensure that the serial PROM and any daisy-chained FPGAs are fast enough to support the clock rate. On power-up, the CCLK frequency is approximately 2.5 MHz. This frequency is used until the ConfigRate bits have been loaded when the frequency changes to the selected ConfigRate. Unless a different frequency is specified in the design, the default ConfigRate is 4 MHz. In a full master/slave system (Figure 13), the left-most device operates in master-serial mode. The remaining devices operate in slave-serial mode. The SPROM RESET pin is driven by INIT, and the CE input is driven by DONE. There is the potential for contention on the DONE pin, depending on the start-up sequence options chosen. www.xilinx.com 1-800-255-7778 Module 2 of 4 13 R QPro Virtex-E 1.8V QML High-Reliability FPGAs The sequence of operations necessary to configure a Virtex-E FPGA serially appears in Figure 15. Apply Power FPGA starts to clear configuration memory. Set PROGRAM = High FPGA makes a final clearing pass and releases INIT when finished. If used to delay configuration Release INIT INIT? Low High Load a Configuration Bit Once per bitstream, FPGA checks data using CRC and pulls INIT Low on error. If no CRC errors found, FPGA enters start-up phase causing DONE to go High. End of Bitstream? No Yes Configuration Completed ds009_15_111799 Figure 15: Serial Configuration Flowchart Figure 16 shows the timing of master-serial configuration. Master-serial mode is selected by a <000> or <100> on the mode pins (M2, M1, M0). Table 10 shows the timing information for Figure 16. CCLK (Output) TCKDS 2 1 TDSCK Serial Data In Serial DOUT (Output) DS022_44_071201 Figure 16: Master-Serial Mode Programming Switching Characteristics At power-up, VCC must rise from 1.0 V to VCC Min in less than 50 ms, otherwise delay configuration by pulling PROGRAM Low until VCC is valid. SelectMAP Mode The SelectMAP mode is the fastest configuration option. Byte-wide data is written into the FPGA with a BUSY flag controlling the flow of data. An external data source provides a byte stream, CCLK, a Chip Select (CS) signal and a Write signal (WRITE). If BUSY is asserted (High) by the FPGA, the data must be held until BUSY goes Low. Data can also be read using the SelectMAP mode. If WRITE is not asserted, configuration data is read out of the FPGA as part of a readback operation. After configuration, the pins of the SelectMAP port can be used as additional user I/O. Alternatively, the port can be retained to permit high-speed 8-bit readback. Module 2 of 4 14 Retention of the SelectMAP port is selectable on a designby-design basis when the bitstream is generated. If retention is selected, PROHIBIT constraints are required to prevent the SelectMAP-port pins from being used as user I/O. Multiple Virtex-E FPGAs can be configured using the SelectMAP mode, and be made to start-up simultaneously. To configure multiple devices in this way, wire the individual CCLK, Data, WRITE, and BUSY pins of all the devices in parallel. The individual devices are loaded separately by asserting the CS pin of each device in turn and writing the appropriate data. See Table 11 for SelectMAP Write Timing Characteristics. Write Write operations send packets of configuration data into the FPGA. The sequence of operations for a multi-cycle write operation is shown below. Note that a configuration packet can be split into many such sequences. The packet does www.xilinx.com 1-800-255-7778 DS098-2 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs not have to complete within one assertion of CS, illustrated in Figure 17. and WRITE is High. Similarly, while WRITE is High, no more that one CS should be asserted. 3. At the rising edge of CCLK: If BUSY is Low, the data is accepted on this clock. If BUSY is High (from a previous write), the data is not accepted. Acceptance instead occurs on the first clock after BUSY goes Low, and the data must be held until this has happened. 1. Assert WRITE and CS Low. Note that when CS is asserted on successive CCLKs, WRITE must remain either asserted or de-asserted. Otherwise, an abort is initiated, as described below. 2. Drive data onto D[7:0]. Note that to avoid contention, the data source should not be enabled while CS is Low 4. Repeat steps 2 and 3 until all the data has been sent. 5. De-assert CS and WRITE. Table 11: SelectMAP Write Timing Characteristics Description CCLK Symbol Units D0-7 Setup/Hold 1/2 TSMDCC/TSMCCD 5.0 / 1.7 ns, min CS Setup/Hold 3/4 TSMCSCC/TSMCCCS 7.0 / 1.7 ns, min WRITE Setup/Hold 5/6 TSMCCW/TSMWCC 7.0 / 1.7 ns, min 7 TSMCKBY 12.0 ns, max FCC 66 MHz, max FCCNH 50 MHz, max BUSY Propagation Delay Maximum Frequency Maximum Frequency with no handshake CCLK CS WRITE 3 4 5 6 1 2 DATA[0:7] 7 BUSY No Write Write No Write Write DS022_45_071702 Figure 17: Write Operations DS098-2 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 2 of 4 15 R QPro Virtex-E 1.8V QML High-Reliability FPGAs A flowchart for the write operation is shown in Figure 18. Note that if CCLK is slower than fCCNH, the FPGA never asserts BUSY, In this case, the above handshake is unnecessary, and data can simply be entered into the FPGA every CCLK cycle. Apply Power FPGA starts to clear configuration memory. PROGRAM from Low to High Abort FPGA makes a final clearing pass and releases INIT when finished. During a given assertion of CS, the user cannot switch from a write to a read, or vice-versa. This action causes the current packet command to be aborted. The device remains BUSY until the aborted operation has completed. Following an abort, data is assumed to be unaligned to word boundaries, and the FPGA requires a new synchronization word prior to accepting any new packets. No Yes If used to delay configuration Release INIT INIT? Low High Set WRITE = Low Enter Data Source Sequence A To initiate an abort during a write operation, de-assert WRITE. At the rising edge of CCLK, an abort is initiated, as shown in Figure 19. On first FPGA Set CS = Low Apply Configuration Byte Once per bitstream, FPGA checks data using CRC and pulls INIT Low on error. Busy? High Low End of Data? If no errors, first FPGAs enter start-up phase releasing DONE. If no errors, later FPGAs enter start-up phase releasing DONE. No Yes Set CS = High Repeat Sequence A On first FPGA For any other FPGAs Disable Data Source Set WRITE = High When all DONE pins are released, DONE goes High and start-up sequences complete. Configuration Completed ds003_17_090602 Figure 18: SelectMAP Flowchart for Write Operations CCLK CS WRITE DATA[0:7] BUSY Abort DS022_46_071702 Figure 19: SelectMAP Write Abort Waveforms Module 2 of 4 16 www.xilinx.com 1-800-255-7778 DS098-2 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Boundary-Scan Mode 7. Clock TCK through the startup sequence. In the boundary-scan mode, configuration is done through the IEEE 1149.1 Test Access Port. Note that the PROGRAM pin must be pulled High prior to reconfiguration. A Low on the PROGRAM pin resets the TAP controller and no JTAG operations can be performed. 8. Return to RTI. Configuration through the TAP uses the CFG_IN instruction. This instruction allows data input on TDI to be converted into data packets for the internal configuration bus. The following steps are required to configure the FPGA through the boundary-scan port (when using TCK as a start-up clock). 1. Load the CFG_IN instruction into the boundary-scan instruction register (IR). 2. Enter the Shift-DR (SDR) state. 3. Shift a configuration bitstream into TDI. 4. Return to Run-Test-Idle (RTI). 5. Load the JSTART instruction into IR. Configuration Sequence The configuration of Virtex-E devices is a three-phase process. First, the configuration memory is cleared. Next, configuration data is loaded into the memory, and finally, the logic is activated by a start-up process. Configuration is automatically initiated on power-up unless it is delayed by the user, as described below. The configuration process can also be initiated by asserting PROGRAM. The end of the memory-clearing phase is signalled by INIT going High, and the completion of the entire process is signalled by DONE going High. The power-up timing of configuration signals is shown in Figure 20. 6. Enter the SDR state. Vcc Configuration and readback via the TAP is always available. The boundary-scan mode is selected by a <101> or <001> on the mode pins (M2, M1, M0). For details on TAP characteristics, refer to XAPP139. TPOR PROGRAM TPL INIT TICCK CCLK OUTPUT or INPUT M0, M1, M2 (Required) VALI ds022_020_071201 Figure 20: Power-Up Timing Configuration Signals The corresponding timing characteristics are listed in Table 12. Table 12: Power-up Timing Characteristics Value Description Figure Reference Symbol min max Units Power-on Reset1 20 TPOR - 2.0 ms Program Latency 20 TPL - 100.0 s CCLK (output) Delay 20 TICCK 0.5 4.0 s Program Pulse Width - TPROGRAM 300 - ns Notes: 1. TPOR delay is the initialization time required after VCCINT and VCCO in Bank 2 reach the recommended operating voltage. DS098-2 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 2 of 4 17 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Delaying Configuration INIT can be held Low using an open-drain driver. An opendrain is required since INIT is a bidirectional open-drain pin that is held Low by the FPGA while the configuration memory is being cleared. Extending the time that the pin is Low causes the configuration sequencer to wait. Thus, configuration is delayed by preventing entry into the phase where data is loaded. Start-Up Sequence The default Start-up sequence is that one CCLK cycle after DONE goes High, the global 3-state signal (GTS) is released. This permits device outputs to turn on as necessary. One CCLK cycle later, the Global Set/Reset (GSR) and Global Write Enable (GWE) signals are released. This permits the internal storage elements to begin changing state in response to the logic and the user clock. The relative timing of these events can be changed. In addition, the GTS, GSR, and GWE events can be made dependent on the DONE pins of multiple devices all going High, forcing the devices to start synchronously. The sequence can also be paused at any stage until lock has been achieved on any or all DLLs. Readback The configuration data stored in the Virtex-E configuration memory can be readback for verification. Along with the configuration data it is possible to readback the contents all flip-flops/latches, LUT RAMs, and block RAMs. This capa- Module 2 of 4 18 bility is used for real-time debugging. For more detailed information, see application note XAPP138 "Virtex FPGA Series Configuration and Readback". www.xilinx.com 1-800-255-7778 DS098-2 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Design Considerations This section contains more detailed design information on the following features. * * * Delay-Locked Loop . . . see page 19 BlockRAM . . . see page 23 SelectIO . . . see page 30 In order to guarantee the system clock establishes prior to the device "waking up," the DLL can delay the completion of the device configuration process until after the DLL achieves lock. By taking advantage of the DLL to remove on-chip clock delay, the designer can greatly simplify and improve system level design involving high-fanout, high-performance clocks. Using DLLs The Virtex-E FPGA series provides up to eight fully digital dedicated on-chip Delay-Locked Loop (DLL) circuits which provide zero propagation delay, low clock skew between output clock signals distributed throughout the device, and advanced clock domain control. These dedicated DLLs can be used to implement several circuits which improve and simplify system level design. Introduction As FPGAs grow in size, quality on-chip clock distribution becomes increasingly important. Clock skew and clock delay impact device performance and the task of managing clock skew and clock delay with conventional clock trees becomes more difficult in large devices. The Virtex-E series of devices resolve this potential problem by providing up to eight fully digital dedicated on-chip DLL circuits, which provide zero propagation delay and low clock skew between output clock signals distributed throughout the device. Library DLL Symbols Figure 21 shows the simplified Xilinx library DLL macro symbol, BUFGDLL. This macro delivers a quick and efficient way to provide a system clock with zero propagation delay throughout the device. Figure 22 and Figure 23 show the two library DLL primitives. These symbols provide access to the complete set of DLL features when implementing more complex applications. I ds022_25_121099 Figure 21: Simplified DLL Macro Symbol BUFGDLL CLKDLL Each DLL can drive up to two global clock routing networks within the device. The global clock distribution network minimizes clock skews due to loading differences. By monitoring a sample of the DLL output clock, the DLL can compensate for the delay on the routing network, effectively eliminating the delay from the external input port to the individual clock loads within the device. CLKIN CLKFB CLKDV RST LOCKED ds022_26_121099 Figure 22: Standard DLL Symbol CLKDLL Clock multiplication gives the designer a number of design alternatives. For instance, a 50 MHz source clock doubled by the DLL can drive an FPGA design operating at 100 MHz. This technique can simplify board design because the clock path on the board no longer distributes such a highspeed signal. A multiplied clock also provides designers the option of time-domain-multiplexing, using one circuit twice per clock cycle, consuming less area than two copies of the same circuit. Two DLLs in can be connected in series to increase the effective clock multiplication factor to four. DS098-2 (v1.1) July 29, 2004 Advance Product Specification CLK0 CLK90 CLK180 CLK270 CLK2X In addition to providing zero delay with respect to a user source clock, the DLL can provide multiple phases of the source clock. The DLL can also act as a clock doubler or it can divide the user source clock by up to 16. The DLL can also act as a clock mirror. By driving the DLL output off-chip and then back in again, the DLL can be used to de-skew a board level clock between multiple devices. O 0ns CLKDLLHF CLKIN CLKFB CLK0 CLK180 CLKDV RST LOCKED ds022_027_121099 Figure 23: High Frequency DLL Symbol CLKDLLHF www.xilinx.com 1-800-255-7778 Module 2 of 4 19 R QPro Virtex-E 1.8V QML High-Reliability FPGAs BUFGDLL Pin Descriptions Use the BUFGDLL macro as the simplest way to provide zero propagation delay for a high-fanout on-chip clock from an external input. This macro uses the IBUFG, CLKDLL and BUFG primitives to implement the most basic DLL application as shown in Figure 24. IBUFG I O CLKDLL CLKIN CLKFB CLK0 CLK90 CLK180 CLK270 BUFG I O DLLs. This makes a total of eight usable input pins for DLLs in the Virtex-E family. Feedback Clock Input -- CLKFB The DLL requires a reference or feedback signal to provide the delay-compensated output. Connect only the CLK0 or CLK2X DLL outputs to the feedback clock input (CLKFB) pin to provide the necessary feedback to the DLL. The feedback clock input can also be provided through one of the following pins. IBUFG - Global Clock Input Pad CLK2X IO_LVDS_DLL - the pin adjacent to IBUF CLKDV RST LOCKED If an IBUFG sources the CLKFB pin, the following special rules apply. 1. An external input port must source the signal that drives the IBUFG I pin. ds022_28_121099 Figure 24: BUFGDLL Schematic This symbol does not provide access to the advanced clock domain controls or to the clock multiplication or clock division features of the DLL. This symbol also does not provide access to the RST, or LOCKED pins of the DLL. For access to these features, a designer must use the library DLL primitives described in the following sections. Source Clock Input -- I The I pin provides the user source clock, the clock signal on which the DLL operates, to the BUFGDLL. For the BUFGDLL macro the source clock frequency must fall in the low frequency range as specified in the data sheet. The BUFGDLL requires an external signal source clock. Therefore, only an external input port can source the signal that drives the BUFGDLL I pin. Clock Output -- O The clock output pin O represents a delay-compensated version of the source clock (I) signal. This signal, sourced by a global clock buffer BUFG symbol, takes advantage of the dedicated global clock routing resources of the device. The output clock has a 50-50 duty cycle unless you deactivate the duty cycle correction property. 2. The CLK2X output must feedback to the device if both the CLK0 and CLK2X outputs are driving off chip devices. 3. That signal must directly drive only OBUFs and nothing else. These rules enable the software determine which DLL clock output sources the CLKFB pin. Reset Input -- RST When the reset pin RST activates the LOCKED signal deactivates within four source clock cycles. The RST pin, active High, must either connect to a dynamic signal or tied to ground. As the DLL delay taps reset to zero, glitches can occur on the DLL clock output pins. Activation of the RST pin can also severely affect the duty cycle of the clock output pins. Furthermore, the DLL output clocks no longer deskew with respect to one another. For these reasons, rarely use the reset pin unless re-configuring the device or changing the input frequency. 2x Clock Output -- CLK2X The library CLKDLL primitives provide access to the complete set of DLL features needed when implementing more complex applications with the DLL. The output pin CLK2X provides a frequency-doubled clock with an automatic 50/50 duty-cycle correction. Until the CLKDLL has achieved lock, the CLK2X output appears as a 1x version of the input clock with a 25/75 duty cycle. This behavior allows the DLL to lock on the correct edge with respect to source clock. This pin is not available on the CLKDLLHF primitive. Source Clock Input -- CLKIN Clock Divide Output -- CLKDV The CLKIN pin provides the user source clock (the clock signal on which the DLL operates) to the DLL. The CLKIN frequency must fall in the ranges specified in the data sheet. A global clock buffer (BUFG) driven from another CLKDLL, one of the global clock input buffers (IBUFG), or an IO_LVDS_DLL pin on the same edge of the device (top or bottom) must source this clock signal. There are four IO_LVDS_DLL input pins that can be used as inputs to the The clock divide output pin CLKDV provides a lower frequency version of the source clock. The CLKDV_DIVIDE property controls CLKDV such that the source clock is divided by N where N is either 1.5, 2, 2.5, 3, 4, 5, 8, or 16. CLKDLL Primitive Pin Descriptions Module 2 of 4 20 This feature provides automatic duty cycle correction such that the CLKDV output pin always has a 50/50 duty cycle, with the exception of noninteger divides in HF mode, where the duty cycle is 1/3 for N=1.5 and 2/5 for N=2.5. www.xilinx.com 1-800-255-7778 DS098-2 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs 1x Clock Outputs -- CLK[0|90|180|270] The 1x clock output pin CLK0 represents a delay-compensated version of the source clock (CLKIN) signal. The CLKDLL primitive provides three phase-shifted versions of the CLK0 signal while CLKDLLHF provides only the 180 phase-shifted version. The relationship between phase shift and the corresponding period shift appears in Table 13. Table 13: Relationship of Phase-Shifted Output Clock to Period Shift Phase (degrees) Period Shift (percent) 0 0% 90 25% 180 50% 270 75% 90 180 270 0 90 180 270 t To achieve lock, the DLL might need to sample several thousand clock cycles. After the DLL achieves lock, the LOCKED signal activates. The DLL timing parameter section of the data sheet provides estimates for locking times. To guarantee that the system clock is established prior to the device "waking up," the DLL can delay the completion of the device configuration process until after the DLL locks. The STARTUP_WAIT property activates this feature. DLL Properties Properties provide access to some of the Virtex-E series DLL features, (for example, clock division and duty cycle correction). Duty Cycle Correction Property CLKIN The 1x clock outputs, CLK0, CLK90, CLK180, and CLK270, use the duty-cycle corrected default, exhibiting a 50/50 duty cycle. The DUTY_CYCLE_CORRECTION property (by default TRUE) controls this feature. To deactivate the DLL duty-cycle correction for the 1x clock outputs, attach the DUTY_CYCLE_CORRECTION=FALSE property to the DLL symbol. CLK2X CLKDV_DIVIDE=2 CLKDV DUTY_CYCLE_CORRECTION=FALSE CLK0 Clock Divide Property CLK90 The CLKDV_DIVIDE property specifies how the signal on the CLKDV pin is frequency divided with respect to the CLK0 pin. The values allowed for this property are 1.5, 2, 2.5, 3, 4, 5, 8, or 16; the default value is 2. CLK180 CLK270 DUTY_CYCLE_CORRECTION=TRUE Startup Delay Property CLK0 This property, STARTUP_WAIT, takes on a value of TRUE or FALSE (the default value). When TRUE the device configuration DONE signal waits until the DLL locks before going to High. CLK90 CLK180 CLK270 Virtex-E DLL Location Constraints ds022_29_121099 Figure 25: DLL Output Characteristics The DLL provides duty cycle correction on all 1x clock outputs such that all 1x clock outputs by default have a 50/50 duty cycle. The DUTY_CYCLE_CORRECTION property (TRUE by default), controls this feature. In order to deactivate the DLL duty cycle correction, attach the DUTY_CYCLE_CORRECTION=FALSE property to the DLL symbol. When duty cycle correction deactivates, the output clock has the same duty cycle as the source clock. DS098-2 (v1.1) July 29, 2004 Advance Product Specification Locked Output -- LOCKED Until the LOCKED signal activates, the DLL output clocks are not valid and can exhibit glitches, spikes, or other spurious movement. In particular the CLK2X output appears as a 1x clock with a 25/75 duty cycle. The timing diagrams in Figure 25 illustrate the DLL clock output characteristics. 0 The DLL clock outputs can drive an OBUF, a BUFG, or they can route directly to destination clock pins. The DLL clock outputs can only drive the BUFGs that reside on the same edge (top or bottom). As shown in Figure 26, there are four additional DLLs in the Virtex-E devices, for a total of eight per Virtex-E device. These DLLs are located in silicon, at the top and bottom of the two innermost block SelectRAM columns. The location constraint LOC, attached to the DLL symbol with the identifier DLL0S, DLL0P, DLL1S, DLL1P, DLL2S, DLL2P, DLL3S, or DLL3P, controls the DLL location. The LOC property uses the following form: LOC = DLL0P www.xilinx.com 1-800-255-7778 Module 2 of 4 21 R QPro Virtex-E 1.8V QML High-Reliability FPGAs DLL-3S DLL-3P DLL-2P DLL-2S B R A M B R A M B R A M B R A M DLL-1S DLL-1P DLL-0P DLL-0S In a similar manner, a phase shift of the input clock is also possible. The phase shift propagates to the output one to four clocks after the original shift, with no disruption to the CLKDLL control. Output Clocks Bottom Right Half Edge x132_14_100799 Figure 26: Virtex Series DLLs Design Factors Use the following design considerations to avoid pitfalls and improve success designing with Xilinx devices. Input Clock The output clock signal of a DLL, essentially a delayed version of the input clock signal, reflects any instability on the input clock in the output waveform. For this reason the quality of the DLL input clock relates directly to the quality of the output clock waveforms generated by the DLL. The DLL input clock requirements are specified in the data sheet. In most systems a crystal oscillator generates the system clock. The DLL can be used with any commercially available quartz crystal oscillator. For example, most crystal oscillators produce an output waveform with a frequency tolerance of 100 PPM, meaning 0.01 percent change in the clock period. The DLL operates reliably on an input waveform with a frequency drift of up to 1 ns -- orders of magnitude in excess of that needed to support any crystal oscillator in the industry. However, the cycle-to-cycle jitter must be kept to less than 300 ps in the low frequencies and 150 ps for the high frequencies. As mentioned earlier in the DLL pin descriptions, some restrictions apply regarding the connectivity of the output pins. The DLL clock outputs can drive an OBUF, a global clock buffer BUFG, or they can route directly to destination clock pins. The only BUFGs that the DLL clock outputs can drive are the two on the same edge of the device (top or bottom). In addition, the CLK2X output of the secondary DLL can connect directly to the CLKIN of the primary DLL in the same quadrant. Do not use the DLL output clock signals until after activation of the LOCKED signal. Prior to the activation of the LOCKED signal, the DLL output clocks are not valid and can exhibit glitches, spikes, or other spurious movement. Useful Application Examples The Virtex-E DLL can be used in a variety of creative and useful applications. The following examples show some of the more common applications. The Verilog and VHDL example files are available at: ftp://ftp.xilinx.com/pub/applications/xapp/xapp132.zip Standard Usage The circuit shown in Figure 27 resembles the BUFGDLL macro implemented to provide access to the RST and LOCKED pins of the CLKDLL. CLKDLL IBUFG CLKIN CLKFB BUFG CLK0 CLK90 CLK180 CLK270 Input Clock Changes CLK2X Changing the period of the input clock beyond the maximum drift amount requires a manual reset of the CLKDLL. Failure to reset the DLL produces an unreliable lock signal and output clock. It is possible to stop the input clock with little impact to the DLL. Stopping the clock should be limited to less than 100 s to keep device cooling to a minimum. The clock should be stopped during a Low phase, and when restored the full High period should be seen. During this time, LOCKED stays High and remains High when the clock is restored. When the clock is stopped, one to four more clocks are still observed as the delay line is flushed. When the clock is restarted, the output clocks are not observed for one to four clocks as the delay line is filled. The most common case is two or three clocks. Module 2 of 4 22 CLKDV OBUF IBUF RST LOCKED ds022_028_121099 Figure 27: Standard DLL Implementation Board Level De-skew of Multiple Non-Virtex-E Devices The circuit shown in Figure 28 can be used to de-skew a system clock between a Virtex-E chip and other non-VirtexE chips on the same board. This application is commonly used when the Virtex-E device is used in conjunction with other standard products such as SRAM or DRAM devices. While designing the board level route, ensure that the return net delay to the source equals the delay to the other chips involved. www.xilinx.com 1-800-255-7778 DS098-2 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Because any single DLL can access only two BUFGs at most, any additional output clock signals must be routed from the DLL in this example on the high speed backbone routing. Virtex-E Device CLKDLL IBUFG CLKIN OBUF CLK0 CLK90 CLK180 CLK270 CLKFB IBUFG The dll_2x files in the xapp132.zip file show the VHDL and Verilog implementation of this circuit. CLK2X Virtex-E 4x Clock CLKDV RST Two DLLs located in the same half-edge (top-left, top-right, bottom-right, bottom-left) can be connected together, without using a BUFG between the CLKDLLs, to generate a 4x clock as shown in Figure 30. Virtex-E devices, like the Virtex devices, have four clock networks that are available for internal de-skewing of the clock. Each of the eight DLLs have access to two of the four clock networks. Although all the DLLs can be used for internal de-skewing, the presence of two GCLKBUFs on the top and two on the bottom indicate that only two of the four DLLs on the top (and two of the four DLLs on the bottom) can be used for this purpose. LOCKED BUFG CLKDLL CLKIN CLK0 CLK90 CLK180 CLK270 CLKFB CLK2X CLKDV RST LOCKED Non-Virtex-E Chip CLKDLL-S IBUFG Non-Virtex-E Chip CLKIN CLKFB Other Non_Virtex-E Chips CLK0 CLK90 CLK180 CLK270 ds022_029_121099 CLK2X Figure 28: DLL De-skew of Board Level Clock CLKDV RST Board-level de-skew is not required for low-fanout clock networks. It is recommended for systems that have fanout limitations on the clock network, or if the clock distribution chip cannot handle the load. INV LOCKED CLKDLL-P CLKIN CLKFB Do not use the DLL output clock signals until after activation of the LOCKED signal. Prior to the activation of the LOCKED signal, the DLL output clocks are not valid and can exhibit glitches, spikes, or other spurious movement. CLK0 CLK90 CLK180 CLK270 BUFG CLK2X CLKDV RST OBUF LOCKED The dll_mirror_1 files in the xapp132.zip file show the VHDL and Verilog implementation of this circuit. ds022_031_041901 De-Skew of Clock and Its 2x Multiple The circuit shown in Figure 29 implements a 2x clock multiplier and also uses the CLK0 clock output with a zero ns skew between registers on the same chip. Alternatively, a clock divider circuit can be implemented using similar connections. CLKDLL IBUFG CLKIN CLKFB Figure 30: DLL Generation of 4x Clock in Virtex-E Devices The dll_4xe files in the xapp132.zip file show the DLL implementation in Verilog for Virtex-E devices. These files can be found at: ftp://ftp.xilinx.com/pub/applications/xapp/xapp132.zip BUFG CLK0 CLK90 CLK180 CLK270 Using Block SelectRAM+ Features BUFG CLK2X CLKDV IBUF RST OBUF LOCKED ds022_030_121099 Figure 29: DLL De-skew of Clock and 2x Multiple DS098-2 (v1.1) July 29, 2004 Advance Product Specification The Virtex FPGA Series provides dedicated blocks of onchip, true dual-read/write port synchronous RAM, with 4096 memory cells. Each port of the block SelectRAM+ memory can be independently configured as a read/write port, a read port, a write port, and can be configured to a specific data width. The block SelectRAM+ memory offers new capabilities allowing the FPGA designer to simplify designs. www.xilinx.com 1-800-255-7778 Module 2 of 4 23 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Operating Modes RAMB4_S#_S# VIrtex-E block SelectRAM+ memory supports two operating modes: * * WEA ENA RSTA CLKA ADDRA[#:0] DIA[#:0] Read Through Write Back Read Through (one clock edge) The read address is registered on the read port clock edge and data appears on the output after the RAM access time. Some memories might place the latch/register at the outputs, depending on whether a faster clock-to-out versus setup time is desired. This is generally considered to be an inferior solution, since it changes the read operation to an asynchronous function with the possibility of missing an address/control line transition during the generation of the read pulse clock. WEB ENB RSTB CLKB ADDRB[#:0] DIB[#:0] Figure 31: Dual-Port Block SelectRAM+ Memory RAMB4_S# The write address is registered on the write port clock edge and the data input is written to the memory and mirrored on the output. WE EN RST CLK * * * * All inputs are registered with the port clock and have a set-up to clock timing specification. All outputs have a read through or write back function depending on the state of the port WE pin. The outputs relative to the port clock are available after the clock-toout timing specification. The block SelectRAMs are true SRAM memories and do not have a combinatorial path from the address to the output. The LUT SelectRAM+ cells in the CLBs are still available with this function. The ports are completely independent from each other (i.e., clocking, control, address, read/write function, and data width) without arbitration. A write operation requires only one clock edge. A read operation requires only one clock edge. The output ports are latched with a self timed circuit to guarantee a glitch free read. The state of the output port does not change until the port executes another read or write operation. Library Primitives Figure 31 and Figure 32 show the two generic library block SelectRAM+ primitives. Table 14 describes all of the available primitives for synthesis and simulation. Module 2 of 4 24 DO[#:0] ADDR[#:0] DI[#:0] Block SelectRAM+ Characteristics * DOB[#:0] ds022_032_121399 Write Back (one clock edge) * DOA[#:0] ds022_033_121399 Figure 32: Single-Port Block SelectRAM+ Memory Table 14: Available Library Primitives Primitive Port A Width Port B Width 1 N/A 1 2 4 8 16 2 N/A 2 4 8 16 RAMB4_S4 RAMB4_S4_S4 RAMB4_S4_S8 RAMB4_S4_S16 4 N/A 4 8 16 RAMB4_S8 RAMB4_S8_S8 RAMB4_S8_S16 8 N/A 8 16 RAMB4_S16 RAMB4_S16_S16 16 N/A 16 RAMB4_S1 RAMB4_S1_S1 RAMB4_S1_S2 RAMB4_S1_S4 RAMB4_S1_S8 RAMB4_S1_S16 RAMB4_S2 RAMB4_S2_S2 RAMB4_S2_S4 RAMB4_S2_S8 RAMB4_S2_S16 www.xilinx.com 1-800-255-7778 DS098-2 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Port Signals Data Output Bus--DO[A|B]<#:0> Each block SelectRAM+ port operates independently of the others while accessing the same set of 4096 memory cells. The data out bus reflects the contents of the memory cells referenced by the address bus at the last active clock edge. During a write operation, the data out bus reflects the data in bus. The width of this bus equals the width of the port. The allowed widths appear in Table 15. Table 15 describes the depth and width aspect ratios for the block SelectRAM+ memory. Table 15: Block SelectRAM+ Port Aspect Ratios Inverting Control Pins Width Depth ADDR Bus Data Bus 1 4096 ADDR<11:0> DATA<0> 2 2048 ADDR<10:0> DATA<1:0> The four control pins (CLK, EN, WE and RST) for each port have independent inversion control as a configuration option. 4 1024 ADDR<9:0> DATA<3:0> Address Mapping 8 512 ADDR<8:0> DATA<7:0> 16 256 ADDR<7:0> DATA<15:0> Each port accesses the same set of 4096 memory cells using an addressing scheme dependent on the width of the port. Clock--CLK[A|B] Each port is fully synchronous with independent clock pins. All port input pins have setup time referenced to the port CLK pin. The data output bus has a clock-to-out time referenced to the CLK pin. Enable--EN[A|B] The enable pin affects the read, write and reset functionality of the port. Ports with an inactive enable pin keep the output pins in the previous state and do not write data to the memory cells. Write Enable--WE[A|B] Activating the write enable pin allows the port to write to the memory cells. When active, the contents of the data input bus are written to the RAM at the address pointed to by the address bus, and the new data also reflects on the data out bus. When inactive, a read operation occurs and the contents of the memory cells referenced by the address bus reflect on the data out bus. The physical RAM location addressed for a particular width are described in the following formula (of interest only when the two ports use different aspect ratios). Start = ((ADDRport +1) * Widthport) -1 End = ADDRport * Widthport Table 16 shows low order address mapping for each port width. Table 16: Port Address Mapping Port Port Width Addresses 1 4095... 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 2 2047... 07 4 1023... 8 511... 16 255... 06 05 03 04 03 02 02 01 01 01 00 00 00 00 Creating Larger RAM Structures Reset--RST[A|B] The reset pin forces the data output bus latches to zero synchronously. This does not affect the memory cells of the RAM and does not disturb a write operation on the other port. The block SelectRAM+ columns have specialized routing to allow cascading blocks together with minimal routing delays. This achieves wider or deeper RAM structures with a smaller timing penalty than when using normal routing channels. Address Bus--ADDR[A|B]<#:0> Location Constraints The address bus selects the memory cells for read or write. The width of the port determines the required width of this bus as shown in Table 15. Block SelectRAM+ instances can have LOC properties attached to them to constrain the placement. The block SelectRAM+ placement locations are separate from the CLB location naming convention, allowing the LOC properties to transfer easily from array to array. Data In Bus--DI[A|B]<#:0> The data in bus provides the new data value to be written into the RAM. This bus and the port have the same width, as shown in Table 15. DS098-2 (v1.1) July 29, 2004 Advance Product Specification The LOC properties use the following form. LOC = RAMB4_R#C# RAMB4_R0C0 is the upper left RAMB4 location on the device. www.xilinx.com 1-800-255-7778 Module 2 of 4 25 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Conflict Resolution Dual Port Timing The block SelectRAM+ memory is a true dual-read/write port RAM that allows simultaneous access of the same memory cell from both ports. When one port writes to a given memory cell, the other port must not address that memory cell (for a write or a read) within the clock-to-clock setup window. The following lists specifics of port and memory cell write conflict resolution. Figure 34 shows a timing diagram for a true dual-port read/write block SelectRAM+ memory. The clock on port A has a longer period than the clock on Port B. The timing parameter TBCCS, (clock-to-clock set-up) is shown on this diagram. The parameter, TBCCS is violated once in the diagram. All other timing parameters are identical to the single port version shown in Figure 33. * TBCCS is only of importance when the address of both ports are the same and at least one port is performing a write operation. When the clock-to-clock set-up parameter is violated for a WRITE-WRITE condition, the contents of the memory at that location are invalid. When the clock-to-clock set-up parameter is violated for a WRITE-READ condition, the contents of the memory are correct, but the read port has invalid data. * If both ports write to the same memory cell simultaneously, violating the clock-to-clock setup requirement, consider the data stored as invalid. If one port attempts a read of the same memory cell the other simultaneously writes, violating the clock-toclock setup requirement, the following occurs. - The write succeeds - The data out on the writing port accurately reflects the data written. - The data out on the reading port is invalid. Conflicts do not cause any physical damage. Single Port Timing Figure 33 shows a timing diagram for a single port of a block SelectRAM+ memory. The block SelectRAM+ AC switching characteristics are specified in the data sheet. The block SelectRAM+ memory is initially disabled. At the first rising edge of the CLK pin, the ADDR, DI, EN, WE, and RST pins are sampled. The EN pin is High and the WE pin is Low indicating a read operation. The DO bus contains the contents of the memory location, 0x00, as indicated by the ADDR bus. At the second rising edge of the CLK pin, the ADDR, DI, EN, WR, and RST pins are sampled again. The EN and WE pins are High indicating a write operation. The DO bus mirrors the DI bus. The DI bus is written to the memory location 0x0F. At the third rising edge of the CLK pin, the ADDR, DI, EN, WR, and RST pins are sampled again. The EN pin is High and the WE pin is Low indicating a read operation. The DO bus contains the contents of the memory location 0x7E as indicated by the ADDR bus. At the fourth rising edge of the CLK pin, the ADDR, DI, EN, WR, and RST pins are sampled again. The EN pin is Low indicating that the block SelectRAM+ memory is now disabled. The DO bus retains the last value. Module 2 of 4 26 At the first rising edge of the CLKA, memory location 0x00 is to be written with the value 0xAAAA and is mirrored on the DOA bus. The last operation of Port B was a read to the same memory location 0x00. The DOB bus of Port B does not change with the new value on Port A, and retains the last read value. A short time later, Port B executes another read to memory location 0x00, and the DOB bus now reflects the new memory value written by Port A. At the second rising edge of CLKA, memory location 0x7E is written with the value 0x9999 and is mirrored on the DOA bus. Port B then executes a read operation to the same memory location without violating the TBCCS parameter and the DOB reflects the new memory values written by Port A. At the third rising edge of CLKA, the TBCCS parameter is violated with two writes to memory location 0x0F. The DOA and DOB busses reflect the contents of the DIA and DIB busses, but the stored value at 0x0F is invalid. At the fourth rising edge of CLKA, a read operation is performed at memory location 0x0F and invalid data is present on the DOA bus. Port B also executes a read operation to memory location 0x0F and also reads invalid data. At the fifth rising edge of CLKA a read operation is performed that does not violate the TBCCS parameter to the previous write of 0x7E by Port B. THe DOA bus reflects the recently written value by Port B. www.xilinx.com 1-800-255-7778 DS098-2 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs TBPWH TBPWL CLK TBACK ADDR 00 0F 7E 8F CCCC BBBB 2222 TBDCK DDDD DIN TBCKO DOUT MEM (00) CCCC MEM (7E) TBECK EN RST TBWCK WE DISABLED READ WRITE READ DISABLED ds022_0343_121399 Figure 33: Timing Diagram for Single Port Block SelectRAM+ Memory TBCCS VIOLATION CLK_A PORT A ADDR_A 00 EN_A 7E 0F 0F 7E TBCCS TBCCS WE_A DI_A AAAA DO_A 9999 AAAA AAAA 1111 0000 9999 AAAA UNKNOWN 2222 CLK_B PORT B ADDR_B 00 00 7E 0F 0F 7E 1A 1111 1111 1111 BBBB 1111 2222 FFFF EN_B WE_B DI_B DO_B MEM (00) AAAA 9999 BBBB UNKNOWN 2222 FFFF ds022_035_121399 Figure 34: Timing Diagram for a True Dual-port Read/Write Block SelectRAM+ Memory Initialization The block SelectRAM+ memory can initialize during the device configuration sequence. The 16 initialization properties of 64 hex values each (a total of 4096 bits) set the initialization of each RAM. These properties appear in Table 17. Any initialization properties not explicitly set configure as zeros. Partial DS098-2 (v1.1) July 29, 2004 Advance Product Specification initialization strings pad with zeros. Initialization strings greater than 64 hex values generate an error. The RAMs can be simulated with the initialization values using generics in VHDL simulators and parameters in Verilog simulators. www.xilinx.com 1-800-255-7778 Module 2 of 4 27 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Initialization in VHDL and Synopsys The block SelectRAM+ structures can be initialized in VHDL for both simulation and synthesis for inclusion in the EDIF output file. The simulation of the VHDL code uses a generic to pass the initialization. Synopsys FPGA compiler does not presently support generics. The initialization values instead attach as attributes to the RAM by a built-in Synopsys dc_script. The translate_off statement stops synthesis translation of the generic statements. The following code illustrates a module that employs these techniques. bit wide RAM to be created using a single block SelectRAM+ cell as shown in Figure 35. RAMB4_S16_S16 Table 17: RAM Initialization Properties WE EN RST CLK ADDR[6:0], V CC DI[31:16] WEA ENA RSTA CLKA ADDRA[7:0] DIA[15:0] WE EN RST CLK ADDR[6:0], GND DI[15:0] WEB ENB RSTB CLKB ADDRB[7:0] DIB[15:0] DOA[15:0] DO[31:16] DOB[15:0] DO[15:0] Property Memory Cells INIT_00 255 to 0 INIT_01 511 to 256 INIT_02 767 to 512 INIT_03 1023 to 768 INIT_04 1279 to 1024 Interleaving the memory space, setting the LSB of the address bus of Port A to 1 (VCC), and the LSB of the address bus of Port B to 0 (GND), allows a 32-bit wide single port RAM to be created. INIT_05 1535 to 1280 Creating Two Single-Port RAMs INIT_06 1791 to 2047 INIT_07 2047 to 1792 INIT_08 2303 to 2048 The true dual-read/write port functionality of the block SelectRAM+ memory allows a single RAM to be split into two single port memories of 2K bits each as shown in Figure 36. INIT_09 2559 to 2304 INIT_0a 2815 to 2560 INIT_0b 3071 to 2816 INIT_0c 3327 to 3072 INIT_0d 3583 to 3328 INIT_0e 3839 to 3584 INIT_0f 4095 to 3840 ds022_036_121399 Figure 35: Single Port 128 x 32 RAM RAMB4_S4_S16 WE1 EN1 RST1 CLK1 V CC , ADDR1[8:0] DI1[3:0] WEA ENA RSTA CLKA ADDRA[9:0] DIA[3:0] WE2 EN2 RST2 CLK2 GND, ADDR2[6:0] DI2[15:0] WEB ENB RSTB CLKB ADDRB[7:0] DIB[15:0] Initialization in Verilog and Synopsys DO1[3:0] DOB[15:0] DO2[15:0] ds022_037_121399 The block SelectRAM+ structures can be initialized in Verilog for both simulation and synthesis for inclusion in the EDIF output file. The simulation of the Verilog code uses a defparam to pass the initialization. The Synopsys FPGA compiler does not presently support defparam. The initialization values instead attach as attributes to the RAM by a built-in Synopsys dc_script. The translate_off statement stops synthesis translation of the defparam statements. The following code illustrates a module that employs these techniques. Design Examples Creating a 32-bit Single-Port RAM The true dual-read/write port functionality of the block SelectRAM+ memory allows a single port, 128 deep by 32- Module 2 of 4 28 DOA[3:0] Figure 36: 512 x 4 RAM and 128 x 16 RAM In this example, a 512K x 4 RAM (Port A) and a 128 x 16 RAM (Port B) are created out of a single block SelectRAM+. The address space for the RAM is split by fixing the MSB of Port A to 1 (VCC) for the upper 2K bits and the MSB of Port B to 0 (GND) for the lower 2K bits. Block Memory Generation The CoreGen program generates memory structures using the block SelectRAM+ features. This program outputs VHDL or Verilog simulation code templates and an EDIF file for inclusion in a design. www.xilinx.com 1-800-255-7778 DS098-2 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs VHDL Initialization Example library IEEE; use IEEE.std_logic_1164.all; entity MYMEM is port (CLK, WE:in std_logic; ADDR: in std_logic_vector(8 downto 0); DIN: in std_logic_vector(7 downto 0); DOUT: out std_logic_vector(7 downto 0)); end MYMEM; architecture BEHAVE of MYMEM is signal logic0, logic1: std_logic; component RAMB4_S8 --synopsys translate_off generic( INIT_00,INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0a, INIT_0b, INIT_0c, INIT_0d, INIT_0e, INIT_0f : BIT_VECTOR(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"); --synopsys translate_on port (WE, EN, RST, CLK: in STD_LOGIC; ADDR: in STD_LOGIC_VECTOR(8 downto 0); DI: in STD_LOGIC_VECTOR(7 downto 0); DO: out STD_LOGIC_VECTOR(7 downto 0)); end component; --synopsys dc_script_begin --set_attribute ram0 INIT_00 "0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string --set_attribute ram0 INIT_01 "FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string --synopsys dc_script_end begin logic0 <='0'; logic1 <='1'; ram0: RAMB4_S8 --synopsys translate_off generic map ( INIT_00 => X"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF", INIT_01 => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210") --synopsys translate_on port map (WE=>WE, EN=>logic1, RST=>logic0, CLK=>CLK,ADDR=>ADDR, DI=>DIN, DO=>DOUT); end BEHAVE; DS098-2 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 2 of 4 29 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Verilog Initialization Example module MYMEM (CLK, WE, ADDR, DIN, DOUT); input CLK, WE; input [8:0] ADDR; input [7:0] DIN; output [7:0] DOUT; wire logic0, logic1; //synopsys dc_script_begin //set_attribute ram0 INIT_00 "0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string //set_attribute ram0 INIT_01 "FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string //synopsys dc_script_end assign logic0 = 1'b0; assign logic1 = 1'b1; RAMB4_S8 ram0 (.WE(WE), .EN(logic1), .RST(logic0), .CLK(CLK), .ADDR(ADDR), .DI(DIN), .DO(DOUT)); //synopsys translate_off defparam ram0.INIT_00 = 256h'0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF; defparam ram0.INIT_01 = 256h'FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210; //synopsys translate_on endmodule Using SelectIO The Virtex-E FPGA series includes a highly configurable, high-performance I/O resource, called SelectIO to provide support for a wide variety of I/O standards. The SelectIO resource is a robust set of features including programmable control of output drive strength, slew rate, and input delay and hold time. Taking advantage of the flexibility and SelectIO features and the design considerations described in this document can improve and simplify system level design. Introduction As FPGAs continue to grow in size and capacity, the larger and more complex systems designed for them demand an increased variety of I/O standards. Furthermore, as system clock speeds continue to increase, the need for high performance I/O becomes more important. While chip-to-chip delays have an increasingly substantial impact on overall system speed, the task of achieving the desired system performance becomes more difficult with the proliferation of low-voltage I/O standards. SelectIO, the revolutionary input/output resources of Virtex-E devices, resolve this potential problem by providing a highly configurable, high-performance alternative to the I/O resources of more conventional programmable devices. Virtex-E SelectIO features combine the flexibility and time-to-market advantages of programmable logic with the high performance previously available only with ASICs and custom ICs. Module 2 of 4 30 Each SelectIO block can support up to 20 I/O standards. Supporting such a variety of I/O standards allows the support of a wide variety of applications, from general purpose standard applications to high-speed low-voltage memory busses. SelectIO blocks also provide selectable output drive strengths and programmable slew rates for the LVTTL output buffers, as well as an optional, programmable weak pullup, weak pull-down, or weak "keeper" circuit ideal for use in external bussing applications. Each Input/Output Block (IOB) includes three registers, one each for the input, output, and 3-state signals within the IOB. These registers are optionally configurable as either a D-type flip-flop or as a level sensitive latch. The input buffer has an optional delay element used to guarantee a zero hold time requirement for input signals registered within the IOB. The Virtex-E SelectIO features also provide dedicated resources for input reference voltage (VREF) and output source voltage (VCCO), along with a convenient banking system that simplifies board design. By taking advantage of the built-in features and wide variety of I/O standards supported by the SelectIO features, system-level design and board design can be greatly simplified and improved. www.xilinx.com 1-800-255-7778 DS098-2 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Fundamentals Overview of Supported I/O Standards Modern bus applications, pioneered by the largest and most influential companies in the digital electronics industry, are commonly introduced with a new I/O standard tailored specifically to the needs of that application. The bus I/O standards provide specifications to other vendors who create products designed to interface with these applications. Each standard often has its own specifications for current, voltage, I/O buffering, and termination techniques. This section provides a brief overview of the I/O standards supported by all Virtex-E devices. The ability to provide the flexibility and time-to-market advantages of programmable logic is increasingly dependent on the capability of the programmable logic device to support an ever increasing variety of I/O standards LVTTL -- Low-Voltage TTL The SelectIO resources feature highly configurable input and output buffers which provide support for a wide variety of I/O standards. As shown in Table 18, each buffer type can support a variety of voltage requirements. Table 18: Virtex-E Supported I/O Standards While most I/O standards specify a range of allowed voltages, this document records typical voltage values only. Detailed information on each specification can be found on the Electronic Industry Alliance Jedec website at: http://www.jedec.org The Low-Voltage TTL, or LVTTL standard is a general purpose EIA/JESDSA standard for 3.3V applications that uses an LVTTL input buffer and a Push-Pull output buffer. This standard requires a 3.3V output source voltage (VCCO), but does not require the use of a reference voltage (VREF) or a termination voltage (VTT). LVCMOS2 -- Low-Voltage CMOS for 2.5V The Low-Voltage CMOS for 2.5V or lower, or LVCMOS2 standard is an extension of the LVCMOS standard (JESD 85) used for general purpose 2.5V applications. This standard requires a 2.5V output source voltage (VCCO), but does not require the use of a reference voltage (VREF) or a board termination voltage (VTT). Output VCCO Input VCCO Input VREF Board Termination Voltage (VTT) LVTTL 3.3 3.3 N/A N/A LVCMOS2 2.5 2.5 N/A N/A LVCMOS18 1.8 1.8 N/A N/A SSTL3 I & II 3.3 N/A 1.50 1.50 SSTL2 I & II 2.5 N/A 1.25 1.25 GTL N/A N/A 0.80 1.20 GTL+ N/A N/A 1.0 1.50 HSTL I 1.5 N/A 0.75 0.75 The Peripheral Component Interface, or PCI standard specifies support for both 33 MHz and 66 MHz PCI bus applications. It uses a LVTTL input buffer and a Push-Pull output buffer. This standard does not require the use of a reference voltage (VREF) or a board termination voltage (VTT), however, it does require a 3.3V output source voltage (VCCO). HSTL III & IV 1.5 N/A 0.90 1.50 GTL -- Gunning Transceiver Logic Terminated CTT 3.3 N/A 1.50 1.50 AGP-2X 3.3 N/A 1.32 N/A PCI33_3 3.3 3.3 N/A N/A PCI66_3 3.3 3.3 N/A N/A BLVDS & LVDS 2.5 N/A N/A N/A LVPECL 3.3 N/A N/A N/A I/O Standard LVCMOS18 -- 1.8V Low Voltage CMOS This standard is an extension of the LVCMOS standard. It is used in general purpose 1.8V applications. The use of a reference voltage (VREF) or a board termination voltage (VTT) is not required. PCI -- Peripheral Component Interface The Gunning Transceiver Logic, or GTL standard is a highspeed bus standard (JESD 8.3) invented by Xerox. Xilinx has implemented the terminated variation for this standard. This standard requires a differential amplifier input buffer and a Open Drain output buffer. GTL+ -- Gunning Transceiver Logic Plus The Gunning Transceiver Logic Plus, or GTL+ standard is a high-speed bus standard (JESD 8.3) first used by the Pentium Pro processor. HSTL -- High-Speed Transceiver Logic The High-Speed Transceiver Logic, or HSTL standard is a general purpose high-speed, 1.5V bus standard sponsored by IBM (EIA/JESD 8-6). This standard has four variations or classes. SelectIO devices support Class I, III, and IV. This DS098-2 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 2 of 4 31 R QPro Virtex-E 1.8V QML High-Reliability FPGAs standard requires a Differential Amplifier input buffer and a Push-Pull output buffer. SSTL3 -- Stub Series Terminated Logic for 3.3V The Stub Series Terminated Logic for 3.3V, or SSTL3 standard is a general purpose 3.3V memory bus standard also sponsored by Hitachi and IBM (JESD 8-8). This standard has two classes, I and II. SelectIO devices support both classes for the SSTL3 standard. This standard requires a Differential Amplifier input buffer and an Push-Pull output buffer. SSTL2 -- Stub Series Terminated Logic for 2.5V The Stub Series Terminated Logic for 2.5V, or SSTL2 standard is a general purpose 2.5V memory bus standard sponsored by Hitachi and IBM (JESD 8-9). This standard has two classes, I and II. SelectIO devices support both classes for the SSTL2 standard. This standard requires a Differential Amplifier input buffer and an Push-Pull output buffer. Library Symbols The Xilinx library includes an extensive list of symbols designed to provide support for the variety of SelectIO features. Most of these symbols represent variations of the five generic SelectIO symbols. * * * * * IBUF (input buffer) IBUFG (global clock input buffer) OBUF (output buffer) OBUFT (3-state output buffer) IOBUF (input/output buffer) IBUF Signals used as inputs to the Virtex-E device must source an input buffer (IBUF) via an external input port. The generic Virtex-E IBUF symbol appears in Figure 37. The extension IBUF I CTT -- Center Tap Terminated The Center Tap Terminated, or CTT standard is a 3.3V memory bus standard sponsored by Fujitsu (JESD 8-4). This standard requires a Differential Amplifier input buffer and a Push-Pull output buffer. AGP-2X -- Advanced Graphics Port The Intel AGP standard is a 3.3V Advanced Graphics Port2X bus standard used with the Pentium II processor for graphics applications. This standard requires a Push-Pull output buffer and a Differential Amplifier input buffer. LVDS -- Low Voltage Differential Signal LVDS is a differential I/O standard. It requires that one data bit is carried through two signal lines. As with all differential signaling standards, LVDS has an inherent noise immunity over single-ended I/O standards. The voltage swing between two signal lines is approximately 350 mV. The use of a reference voltage (VREF) or a board termination voltage (VTT) is not required. LVDS requires the use of two pins per input or output. LVDS requires external resistor termination. BLVDS -- Bus LVDS This standard allows for bidirectional LVDS communication between two or more devices. The external resistor termination is different than the one for standard LVDS. LVPECL -- Low Voltage Positive Emitter Coupled Logic LVPECL is another differential I/O standard. It requires two signal lines for transmitting one data bit. This standard specifies two pins per input or output. The voltage swing between these two signal lines is approximately 850 mV. The use of a reference voltage (VREF) or a board termination voltage (VTT) is not required. The LVPECL standard requires external resistor termination. Module 2 of 4 32 O x133_01_111699 Figure 37: Input Buffer (IBUF) Symbols to the base name defines which I/O standard the IBUF uses. The assumed standard is LVTTL when the generic IBUF has no specified extension. The following list details the variations of the IBUF symbol: * * * * * * * * * * * * * * * * * * IBUF IBUF_LVCMOS2 IBUF_PCI33_3 IBUF_PCI66_3 IBUF_GTL IBUF_GTLP IBUF_HSTL_I IBUF_HSTL_III IBUF_HSTL_IV IBUF_SSTL3_I IBUF_SSTL3_II IBUF_SSTL2_I IBUF_SSTL2_II IBUF_CTT IBUF_AGP IBUF_LVCMOS18 IBUF_LVDS IBUF_LVPECL When the IBUF symbol supports an I/O standard that requires a VREF, the IBUF automatically configures as a differential amplifier input buffer. The VREF voltage must be supplied on the VREF pins. In the case of LVDS, LVPECL, and BLVDS, VREF is not required. www.xilinx.com 1-800-255-7778 DS098-2 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs The voltage reference signal is "banked" within the Virtex-E device on a half-edge basis such that for all packages there are eight independent VREF banks internally. See Figure 38 for a representation of the Virtex-E I/O banks. Within each bank approximately one of every six I/O pins is automatically configured as a VREF input. After placing a differential amplifier input signal within a given VREF bank, the same external source must drive all I/O pins configured as a VREF input. IBUF placement restrictions require that any differential amplifier input signals within a bank be of the same standard. How to specify a specific location for the IBUF via the LOC property is described below. Table 19 summarizes the Virtex-E input standards compatibility requirements. An optional delay element is associated with each IBUF. When the IBUF drives a flip-flop within the IOB, the delay element by default activates to ensure a zero hold-time requirement. The NODELAY=TRUE property overrides this default. When the IBUF does not drive a flip-flop within the IOB, the delay element de-activates by default to provide higher performance. To delay the input signal, activate the delay element with the DELAY=TRUE property. Table 19: Xilinx Input Standards Compatibility Requirements Standards with the same input VCCO, output VCCO, and VREF can be placed within the same bank. Bank 7 Bank 0 Bank 1 GCLK3 GCLK2 Bank 2 Rule 1 GCLK1 Bank 5 GCLK0 Bank 4 ds022_42_012100 Figure 38: Virtex-E I/O Banks IBUFG Signals used as high fanout clock inputs to the Virtex-E device should drive a global clock input buffer (IBUFG) via an external input port in order to take advantage of one of the four dedicated global clock distribution networks. The output of the IBUFG symbol can drive only a CLKDLL, DS098-2 (v1.1) July 29, 2004 Advance Product Specification IBUFG I O x133_03_111699 Figure 39: Virtex-E Global Clock Input Buffer (IBUFG) Symbol The extension to the base name determines which I/O standard is used by the IBUFG. With no extension specified for the generic IBUFG symbol, the assumed standard is LVTTL. The following list details variations of the IBUFG symbol. * * * * * * * * * * * * * * * * * * IBUFG IBUFG_LVCMOS2 IBUFG_PCI33_3 IBUFG_PCI66_3 IBUFG_GTL IBUFG_GTLP IBUFG_HSTL_I IBUFG_HSTL_III IBUFG_HSTL_IV IBUFG_SSTL3_I IBUFG_SSTL3_II IBUFG_SSTL2_I IBUFG_SSTL2_II IBUFG_CTT IBUFG_AGP IBUFG_LVCMOS18 IBUFG_LVDS IBUFG_LVPECL When the IBUFG symbol supports an I/O standard that requires a differential amplifier input, the IBUFG automatically configures as a differential amplifier input buffer. The low-voltage I/O standards with a differential amplifier input require an external reference voltage input VREF. Bank 3 Bank 6 Virtex-E Device CLKDLLHF, or BUFG symbol. The generic Virtex-E IBUFG symbol appears in Figure 39. The voltage reference signal is "banked" within the Virtex-E device on a half-edge basis such that for all packages there are eight independent VREF banks internally. See Figure 38 for a representation of the Virtex-E I/O banks. Within each bank approximately one of every six I/O pins is automatically configured as a VREF input. After placing a differential amplifier input signal within a given VREF bank, the same external source must drive all I/O pins configured as a VREF input. IBUFG placement restrictions require any differential amplifier input signals within a bank be of the same standard. The LOC property can specify a location for the IBUFG. www.xilinx.com 1-800-255-7778 Module 2 of 4 33 R QPro Virtex-E 1.8V QML High-Reliability FPGAs As an added convenience, the BUFGP can be used to instantiate a high fanout clock input. The BUFGP symbol represents a combination of the LVTTL IBUFG and BUFG symbols, such that the output of the BUFGP can connect directly to the clock pins throughout the design. Unlike previous architectures, the Virtex-E BUFGP symbol can only be placed in a global clock pad location. The LOC property can specify a location for the BUFGP. OBUF An OBUF must drive outputs through an external output port. The generic output buffer (OBUF) symbol appears in Figure 40. The extension to the base name defines which I/O standard the OBUF uses. With no extension specified for the generic OBUF symbol, the assumed standard is slew rate limited LVTTL with 12 mA drive strength. OBUF I * * * * * * * * * * * * * * * * * OBUF_LVCMOS2 OBUF_PCI33_3 OBUF_PCI66_3 OBUF_GTL OBUF_GTLP OBUF_HSTL_I OBUF_HSTL_III OBUF_HSTL_IV OBUF_SSTL3_I OBUF_SSTL3_II OBUF_SSTL2_I OBUF_SSTL2_II OBUF_CTT OBUF_AGP OBUF_LVCMOS18 OBUF_LVDS OBUF_LVPECL The Virtex-E series supports eight banks for the HQ packages. The CB packages support one VCCO banks. O x133_04_111699 Figure 40: Virtex-E Output Buffer (OBUF) Symbol The LVTTL OBUF additionally can support one of two slew rate modes to minimize bus transients. By default, the slew rate for each output buffer is reduced to minimize power bus transients when switching non-critical signals. LVTTL output buffers have selectable drive strengths. The format for LVTTL OBUF symbol names is as follows: OBUF placement restrictions require that within a given VCCO bank each OBUF share the same output source drive voltage. Input buffers of any type and output buffers that do not require VCCO can be placed within any VCCO bank. Table 20 summarizes the Virtex-E output compatibility requirements. The LOC property can specify a location for the OBUF. Table 20: Output Standards Compatibility Requirements Rule 1 Only outputs with standards that share compatible VCCO can be used within the same bank. Rule 2 There are no placement restrictions for outputs with standards that do not require a VCCO. VCCO Compatible Standards 3.3 LVTTL, SSTL3_I, SSTL3_II, CTT, AGP, GTL, GTL+, PCI33_3, PCI66_3 2.5 SSTL2_I, SSTL2_II, LVCMOS2, GTL, GTL+ 1.5 HSTL_I, HSTL_III, HSTL_IV, GTL, GTL+ OBUF_<slew_rate>_<drive_strength> where <slew_rate> is either F (Fast) or S (Slow), and <drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16, or 24). The following list details variations of the OBUF symbol. * * * * * * * * * * * * * * * OBUF OBUF_S_2 OBUF_S_4 OBUF_S_6 OBUF_S_8 OBUF_S_12 OBUF_S_16 OBUF_S_24 OBUF_F_2 OBUF_F_4 OBUF_F_6 OBUF_F_8 OBUF_F_12 OBUF_F_16 OBUF_F_24 Module 2 of 4 34 OBUFT The generic 3-state output buffer OBUFT (see Figure 41) typically implements 3-state outputs or bidirectional I/O. The extension to the base name defines which I/O standard OBUFT uses. With no extension specified for the generic OBUFT symbol, the assumed standard is slew rate limited LVTTL with 12 mA drive strength. The LVTTL OBUFT additionally can support one of two slew rate modes to minimize bus transients. By default, the slew rate for each output buffer is reduced to minimize power bus transients when switching non-critical signals. www.xilinx.com 1-800-255-7778 DS098-2 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs LVTTL 3-state output buffers have selectable drive strengths. The Virtex-E series supports eight banks for the HQ package. The CB package supports one VCCO bank. The format for LVTTL OBUFT symbol names is as follows: The SelectIO OBUFT placement restrictions require that within a given VCCO bank each OBUFT share the same output source drive voltage. Input buffers of any type and output buffers that do not require VCCO can be placed within the same VCCO bank. OBUFT_<slew_rate>_<drive_strength> where <slew_rate> is either F (Fast) or S (Slow), and <drive_strength> is specified in mA (2, 4, 6, 8, 12, 16, 24). The LOC property can specify a location for the OBUFT. T 3-state output buffers and bidirectional buffers can have either a weak pull-up resistor, a weak pull-down resistor, or a weak "keeper" circuit. Control this feature by adding the appropriate symbol to the output net of the OBUFT (PULLUP, PULLDOWN, or KEEPER). OBUFT I O x133_05_111699 Figure 41: 3-State Output Buffer Symbol (OBUFT) The following list details variations of the OBUFT symbol. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * OBUFT OBUFT_S_2 OBUFT_S_4 OBUFT_S_6 OBUFT_S_8 OBUFT_S_12 OBUFT_S_16 OBUFT_S_24 OBUFT_F_2 OBUFT_F_4 OBUFT_F_6 OBUFT_F_8 OBUFT_F_12 OBUFT_F_16 OBUFT_F_24 OBUFT_LVCMOS2 OBUFT_PCI33_3 OBUFT_PCI66_3 OBUFT_GTL OBUFT_GTLP OBUFT_HSTL_I OBUFT_HSTL_III OBUFT_HSTL_IV OBUFT_SSTL3_I OBUFT_SSTL3_II OBUFT_SSTL2_I OBUFT_SSTL2_II OBUFT_CTT OBUFT_AGP OBUFT_LVCMOS18 OBUFT_LVDS OBUFT_LVPECL The weak "keeper" circuit requires the input buffer within the IOB to sample the I/O signal. So, OBUFTs programmed for an I/O standard that requires a VREF have automatic placement of a VREF in the bank with an OBUFT configured with a weak "keeper" circuit. This restriction does not affect most circuit design as applications using an OBUFT configured with a weak "keeper" typically implement a bidirectional I/O. In this case the IBUF (and the corresponding VREF) are explicitly placed. The LOC property can specify a location for the OBUFT. IOBUF Use the IOBUF symbol for bidirectional signals that require both an input buffer and a 3-state output buffer with an active high 3-state pin. The generic input/output buffer IOBUF appears in Figure 42. The extension to the base name defines which I/O standard the IOBUF uses. With no extension specified for the generic IOBUF symbol, the assumed standard is LVTTL input buffer and slew rate limited LVTTL with 12 mA drive strength for the output buffer. The LVTTL IOBUF additionally can support one of two slew rate modes to minimize bus transients. By default, the slew rate for each output buffer is reduced to minimize power bus transients when switching non-critical signals. LVTTL bidirectional buffers have selectable output drive strengths. The format for LVTTL IOBUF symbol names is as follows: IOBUF_<slew_rate>_<drive_strength> where <slew_rate> is either F (Fast) or S (Slow), and <drive_strength> is specified in mA (2, 4, 6, 8, 12, 16, 24). T I IOBUF IO O x133_06_111699 Figure 42: Input/Output Buffer Symbol (IOBUF) DS098-2 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 2 of 4 35 R QPro Virtex-E 1.8V QML High-Reliability FPGAs The following list details variations of the IOBUF symbol. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * IOBUF IOBUF_S_2 IOBUF_S_4 IOBUF_S_6 IOBUF_S_8 IOBUF_S_12 IOBUF_S_16 IOBUF_S_24 IOBUF_F_2 IOBUF_F_4 IOBUF_F_6 IOBUF_F_8 IOBUF_F_12 IOBUF_F_16 IOBUF_F_24 IOBUF_LVCMOS2 IOBUF_PCI33_3 IOBUF_PCI66_3 IOBUF_GTL IOBUF_GTLP IOBUF_HSTL_I IOBUF_HSTL_III IOBUF_HSTL_IV IOBUF_SSTL3_I IOBUF_SSTL3_II IOBUF_SSTL2_I IOBUF_SSTL2_II IOBUF_CTT IOBUF_AGP IOBUF_LVCMOS18 IOBUF_LVDS IOBUF_LVPECL Additional restrictions on the Virtex-E SelectIO IOBUF placement require that within a given VCCO bank each IOBUF must share the same output source drive voltage. Input buffers of any type and output buffers that do not require VCCO can be placed within the same VCCO bank. The LOC property can specify a location for the IOBUF. An optional delay element is associated with the input path in each IOBUF. When the IOBUF drives an input flip-flop within the IOB, the delay element activates by default to ensure a zero hold-time requirement. Override this default with the NODELAY=TRUE property. In the case when the IOBUF does not drive an input flip-flop within the IOB, the delay element de-activates by default to provide higher performance. To delay the input signal, activate the delay element with the DELAY=TRUE property. 3-state output buffers and bidirectional buffers can have either a weak pull-up resistor, a weak pull-down resistor, or a weak "keeper" circuit. Control this feature by adding the appropriate symbol to the output net of the IOBUF (PULLUP, PULLDOWN, or KEEPER). SelectIO Properties Access to some of the SelectIO features (for example, location constraints, input delay, output drive strength, and slew rate) is available through properties associated with these features. Input Delay Properties An optional delay element is associated with each IBUF. When the IBUF drives a flip-flop within the IOB, the delay element activates by default to ensure a zero hold-time requirement. Use the NODELAY=TRUE property to override this default. When the IOBUF symbol used supports an I/O standard that requires a differential amplifier input, the IOBUF automatically configures with a differential amplifier input buffer. The low-voltage I/O standards with a differential amplifier input require an external reference voltage input VREF. The voltage reference signal is "banked" within the Virtex-E device on a half-edge basis such that for all packages there are eight independent VREF banks internally. See Figure 38, page 33 for a representation of the Virtex-E I/O banks. Within each bank approximately one of every six I/O pins is automatically configured as a VREF input. After placing a differential amplifier input signal within a given VREF bank, the same external source must drive all I/O pins configured as a VREF input. IOBUF placement restrictions require any differential amplifier input signals within a bank be of the same standard. Module 2 of 4 36 The Virtex-E series supports eight banks for the HQ package. The CB package supports one VCCO bank. In the case when the IBUF does not drive a flip-flop within the IOB, the delay element by default de-activates to provide higher performance. To delay the input signal, activate the delay element with the DELAY=TRUE property. IOB Flip-Flop/Latch Property The Virtex-E series I/O Block (IOB) includes an optional register on the input path, an optional register on the output path, and an optional register on the 3-state control pin. The design implementation software automatically takes advantage of these registers when the following option for the Map program is specified. map -pr b <filename> Alternatively, the IOB = TRUE property can be placed on a register to force the mapper to place the register in an IOB. Location Constraints Specify the location of each SelectIO symbol with the location constraint LOC attached to the SelectIO symbol. The www.xilinx.com 1-800-255-7778 DS098-2 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs external port identifier indicates the value of the location constrain. The format of the port identifier depends on the package chosen for the specific design. figured as a VREF input. After placing a differential amplifier input signal within a given VREF bank, the same external source must drive all I/O pins configured as a VREF input. The LOC properties use the following form: Within each VREF bank, any input buffers that require a VREF signal must be of the same type. Output buffers of any type and input buffers can be placed without requiring a reference voltage within the same VREF bank. LOC=A42 LOC=P37 Output Slew Rate Property Output Drive Source Voltage (VCCO) Pins As mentioned above, a variety of symbol names provide the option of choosing the desired slew rate for the output buffers. In the case of the LVTTL output buffers (OBUF, OBUFT, and IOBUF), slew rate control can be alternatively programed with the SLEW= property. By default, the slew rate for each output buffer is reduced to minimize power bus transients when switching non-critical signals. The SLEW= property has one of the two following values. Many of the low voltage I/O standards supported by SelectIO devices require a different output drive source voltage (VCCO). As a result each device can often have to support multiple output drive source voltages. SLEW=SLOW SLEW=FAST The Virtex-E series supports eight banks for the HQ and PQ packages. The CS package supports four VCCO banks. Output buffers within a given VCCO bank must share the same output drive source voltage. Input buffers for LVTTL, LVCMOS2, LVCMOS18, PCI33_3, and PCI 66_3 use the VCCO voltage for Input VCCO voltage. Output Drive Strength Property Transmission Line Effects The desired output drive strength can be additionally specified by choosing the appropriate library symbol. The Xilinx library also provides an alternative method for specifying this feature. For the LVTTL output buffers (OBUF, OBUFT, and IOBUF, the desired drive strength can be specified with the DRIVE= property. This property could have one of the following seven values. The delay of an electrical signal along a wire is dominated by the rise and fall times when the signal travels a short distance. Transmission line delays vary with inductance and capacitance, but a well-designed board can experience delays of approximately 180 ps per inch. DRIVE=2 DRIVE=4 DRIVE=6 DRIVE=8 DRIVE=12 (Default) DRIVE=16 DRIVE=24 Termination Techniques A variety of termination techniques reduce the impact of transmission line effects. Design Considerations The following are output termination techniques: Reference Voltage (VREF) Pins Low-voltage I/O standards with a differential amplifier input buffer require an input reference voltage (VREF). Provide the VREF as an external signal to the device. The voltage reference signal is "banked" within the device on a half-edge basis such that for all packages there are eight independent VREF banks internally. See Figure 38 for a representation of the Virtex-E I/O banks. Within each bank approximately one of every six I/O pins is automatically con- DS098-2 (v1.1) July 29, 2004 Advance Product Specification Transmission line effects, or reflections, typically start at 1.5" for fast (1.5 ns) rise and fall times. Poor (or non-existent) termination or changes in the transmission line impedance cause these reflections and can cause additional delay in longer traces. As system speeds continue to increase, the effect of I/O delays can become a limiting factor and therefore transmission line termination becomes increasingly more important. * * * * None Series Parallel (Shunt) Series and Parallel (Series-Shunt) Input termination techniques include the following. * * None Parallel (Shunt) www.xilinx.com 1-800-255-7778 Module 2 of 4 37 R QPro Virtex-E 1.8V QML High-Reliability FPGAs These termination techniques can be applied in any combination. A generic example of each combination of termination methods appears in Figure 43. Table 21: Guidelines for Max Number of Simultaneously Switching Outputs per Power/Ground Pair (Continued) Standard Double Parallel Terminated Unterminated VTT VTT Outputs LVTTL Slow Slew Rate, 12 mA drive 17 LVTTL Slow Slew Rate, 16 mA drive 14 LVTTL Slow Slew Rate, 24 mA drive 9 LVTTL Fast Slew Rate, 2 mA drive 40 LVTTL Fast Slew Rate, 4 mA drive 24 LVTTL Fast Slew Rate, 6 mA drive 17 LVTTL Fast Slew Rate, 8 mA drive 13 LVTTL Fast Slew Rate, 12 mA drive 10 LVTTL Fast Slew Rate, 16 mA drive 8 LVTTL Fast Slew Rate, 24 mA drive 5 Simultaneous Switching Guidelines LVCMOS2 10 Ground bounce can occur with high-speed digital ICs when multiple outputs change states simultaneously, causing undesired transient behavior on an output, or in the internal logic. This problem is also referred to as the Simultaneous Switching Output (SSO) problem. PCI 8 GTL 4 GTL+ 4 HSTL Class I 18 HSTL Class III 9 HSTL Class IV 5 SSTL2 Class I 15 SSTL2 Class II 10 SSTL3 Class I 11 SSTL3 Class II 7 CTT 14 AGP 9 Z=50 Z=50 VREF Unterminated Output Driving a Parallel Terminated Input Series Terminated Output Driving a Parallel Terminated Input VTT VTT Z=50 Z=50 VREF VREF Series-Parallel Terminated Output Driving a Parallel Terminated Input Series Terminated Output VTT VTT Z=50 Z=50 VREF VREF x133_07_111699 Figure 43: Overview of Standard Input and Output Termination Methods Ground bounce is primarily due to current changes in the combined inductance of ground pins, bond wires, and ground metallization. The IC internal ground level deviates from the external system ground level for a short duration (a few nanoseconds) after multiple outputs change state simultaneously. Ground bounce affects stable Low outputs and all inputs because they interpret the incoming signal by comparing it to the internal ground. If the ground bounce amplitude exceeds the actual instantaneous noise margin, then a nonchanging input can be interpreted as a short pulse with a polarity opposite to the ground bounce. Table 21 provides guidelines for the maximum number of simultaneously switching outputs allowed per output power/ground pair to avoid the effects of ground bounce. See Table 22 for the number of effective output power/ground pairs for each Virtex-E device and package combination. Table 21: Guidelines for Max Number of Simultaneously Switching Outputs per Power/Ground Pair Standard Outputs Notes: 1. This analysis assumes a 35 pF load for each output. Table 22: Virtex-E Equivalent Power/Ground Pairs Pkg/Part XQV600E XQV1000E XQV2000E CB228 27 - - BG432 40 - - BG560 - 56 60 LVTTL Slow Slew Rate, 2 mA drive 68 LVTTL Slow Slew Rate, 4 mA drive 41 CG560 - 56 - LVTTL Slow Slew Rate, 6 mA drive 29 FG1156 - - 120 LVTTL Slow Slew Rate, 8 mA drive 22 Module 2 of 4 38 www.xilinx.com 1-800-255-7778 DS098-2 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Application Examples GTL+ Creating a design with the SelectIO features requires the instantiation of the desired library symbol within the design code. At the board level, designers need to know the termination techniques required for each I/O standard. A sample circuit illustrating a valid termination technique for GTL+ appears in Figure 45. DC voltage specifications appear in Table 24. GTL+ VTT = 1.5V VTT = 1.5V This section describes some common application examples illustrating the termination techniques recommended by each of the standards supported by the SelectIO features. 50 Termination Examples VCCO = N/A Circuit examples involving typical termination techniques for each of the SelectIO standards follow. For a full range of accepted values for the DC voltage specifications for each standard, refer to the table associated with each figure. The resistors used in each termination technique example and the transmission lines depicted represent board level components and are not meant to represent components on the device. GTL A sample circuit illustrating a valid termination technique for GTL is shown in Figure 44. GTL VTT = 1.2V VTT = 1.2V 50 50 VCCO = N/A Z = 50 VREF = 1.0V x133_09_012400 Figure 45: Terminated GTL+ Table 24: GTL+ Voltage Specifications Parameter Min Typ Max - - - 0.88 1.0 1.12 VTT 1.35 1.5 1.65 VCCO VREF = N x VTT(1) VIH = VREF + 0.1 0.98 1.1 - VIL = VREF - 0.1 - 0.9 1.02 VOH - - - VOL 0.3 0.45 0.6 IOH at VOH (mA) Z = 50 VREF = 0.8V 50 - - - IOLat VOL (mA) at 0.6V 36 - - IOLat VOL (mA) at 0.3V - - 48 Notes: 1. N must be greater than or equal to 0.653 and less than or equal to 0.68. x133_08_111699 Figure 44: Terminated GTL Table 23 lists DC voltage specifications. Table 23: GTL Voltage Specifications Parameter Min Typ Max - N/A - 0.74 0.8 0.86 VTT 1.14 1.2 1.26 VIH = VREF + 0.05 0.79 0.85 - VIL = VREF - 0.05 - 0.75 0.81 VOH - - - VOL - 0.2 0.4 IOH at VOH (mA) - - - IOLat VOL(mA) at 0.4V 32 - - IOLat VOL(mA) at 0.2V - - 40 VCCO VREF = N x VTT(1) Notes: 1. N must be greater than or equal to 0.653 and less than or equal to 0.68. DS098-2 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 2 of 4 39 R QPro Virtex-E 1.8V QML High-Reliability FPGAs HSTL A sample circuit illustrating a valid termination technique for HSTL_I appears in Figure 46. A sample circuit illustrating a valid termination technique for HSTL_III appears in Figure 47. HSTL Class III VTT= 1.5V VCCO = 1.5V 50 Table 25: HSTL Class I Voltage Specification Parameter Z = 50 Min Typ Max VCCO 1.40 1.50 1.60 VREF 0.68 0.75 0.90 VTT - VCCO x 0.5 - VIH VREF + 0.1 - - VIL - - VREF - 0.1 VOH VCCO - 0.4 - - VREF = 0.9V x133_11_111699 Figure 47: Terminated HSTL Class III A sample circuit illustrating a valid termination technique for HSTL_IV appears in Figure 48. Table 27: HSTL Class IV Voltage Specification Min Typ Max VCCO 1.40 1.50 1.60 VREF - 0.90 - VTT - VCCO - VIH VREF + 0.1 - - VIL - - VREF - 0.1 VOH VCCO - 0.4 - - VTT= 0.75V VOL - - 0.4 50 IOH at VOH (mA) -8 - - IOLat VOL (mA) 48 - - VOL 0.4 IOH at VOH (mA) -8 - - IOLat VOL (mA) 8 - - HSTL Class I VCCO = 1.5V Parameter Z = 50 VREF = 0.75V Notes: 1. Per EIA/JESD8-6, "The value of VREF is to be selected by the user to provide optimum noise margin in the use conditions specified by the user. x133_10_111699 Figure 46: Terminated HSTL Class I Table 26: HSTL Class III Voltage Specification Parameter Min Typ Max 1.40 1.50 1.60 VREF (1) - 0.90 - VTT - VCCO - VIH VREF + 0.1 - - VIL - - VREF - 0.1 VOH VCCO - 0.4 - - VOL - - 0.4 IOH at VOH (mA) -8 - - IOLat VOL (mA) 24 - - VCCO HSTL Class IV VCCO = 1.5V VTT= 1.5V VTT= 1.5V 50 50 Z = 50 VREF = 0.9V x133_12_111699 Figure 48: Terminated HSTL Class IV Notes: 1. Per EIA/JESD8-6, "The value of VREF is to be selected by the user to provide optimum noise margin in the use conditions specified by the user." Module 2 of 4 40 www.xilinx.com 1-800-255-7778 DS098-2 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs SSTL3_I A sample circuit illustrating a valid termination technique for SSTL3_I appears in Figure 49. DC voltage specifications appear in Table 28. SSTL3 Class I VTT= 1.5V VCCO = 3.3V 50 25 Z = 50 VREF = 1.5V x133_13_111699 Figure 49: Terminated SSTL3 Class I Table 28: SSTL3_I Voltage Specifications Table 29: SSTL3_II Voltage Specifications Parameter Min Typ Max VCCO 3.0 3.3 3.6 VREF = 0.45 x VCCO 1.3 1.5 1.7 VTT = VREF 1.3 1.5 1.7 VIH = VREF + 0.2 1.5 1.7 3.9(1) VIL= VREF - 0.2 -0.3(2) 1.3 1.5 VOH = VREF + 0.8 2.1 - - VOL= VREF - 0.8 - - 0.9 IOH at VOH (mA) -16 - - IOLat VOL (mA) 16 - - Min Typ Max VCCO 3.0 3.3 3.6 Notes: 1. VIH maximum is VCCO + 0.3 2. VIL minimum does not conform to the formula VREF = 0.45 x VCCO 1.3 1.5 1.7 SSTL2_I VTT = VREF 1.3 1.5 1.7 VIH = VREF + 0.2 1.5 1.7 3.9(1) VIL = VREF - 0.2 -0.3(2) A sample circuit illustrating a valid termination technique for SSTL2_I appears in Figure 51. DC voltage specifications appear in Table 30. 1.3 1.5 VOH = VREF + 0.6 1.9 - - VOL = VREF - 0.6 - - 1.1 IOH at VOH (mA) -8 - - Parameter SSTL2 Class I V CCO VTT= 1.25V = 2.5V 50 25 IOLat VOL (mA) 8 - Z = 50 V Notes: 1. VIH maximum is VCCO + 0.3 2. VIL minimum does not conform to the formula REF = 1.25V xap133_15_011000 Figure 51: Terminated SSTL2 Class I SSTL3_II Table 30: SSTL2_I Voltage Specifications A sample circuit illustrating a valid termination technique for SSTL3_II appears in Figure 50. DC voltage specifications appear in Table 29. Min Typ Max VCCO 2.3 2.5 2.7 VREF = 0.5 x VCCO 1.15 1.25 1.35 VTT = VREF + N(1) 1.11 1.25 1.39 VTT= 1.5V VTT= 1.5V VIH = VREF + 0.18 1.33 1.43 3.0(2) 50 VIL = VREF - 0.18 -0.3(3) 1.07 1.17 VOH = VREF + 0.61 1.76 - - VOL= VREF - 0.61 - - 0.74 SSTL3 Class II VCCO = 3.3V 25 50 Z = 50 VREF = 1.5V x133_14_111699 Parameter Figure 50: Terminated SSTL3 Class II DS098-2 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 2 of 4 41 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 30: SSTL2_I Voltage Specifications Parameter Min Typ Max IOH at VOH (mA) -7.6 - - IOLat VOL (mA) 7.6 - - CTT VCCO = 3.3V VTT = 1.5V 50 Notes: 1. N must be greater than or equal to -0.04 and less than or equal to 0.04. 2. VIH maximum is VCCO + 0.3. 3. VIL minimum does not conform to the formula. Z = 50 VREF= 1.5V x133_17_111699 Figure 53: Terminated CTT SSTL2_II A sample circuit illustrating a valid termination technique for SSTL2_II appears in Figure 52. DC voltage specifications appear in Table 31. SSTL2 Class II VCCO = 2.5V 25 VTT= 1.25V VTT= 1.25V 50 50 Z = 50 VREF = 1.25V Table 32: CTT Voltage Specifications Parameter Min Typ Max VCCO 2.05(1) 3.3 3.6 VREF 1.35 1.5 1.65 VTT 1.35 1.5 1.65 VIH = VREF + 0.2 1.55 1.7 - VIL = VREF - 0.2 - 1.3 1.45 VOH = VREF + 0.4 1.75 1.9 - VOL= VREF - 0.4 - 1.1 1.25 IOH at VOH (mA) -8 - - IOLat VOL (mA) 8 - - x133_16_111699 Figure 52: Terminated SSTL2 Class II Table 31: SSTL2_II Voltage Specifications Parameter Min Typ Max VCCO 2.3 2.5 2.7 VREF = 0.5 x VCCO 1.15 1.25 1.35 VTT = VREF + N(1) 1.11 1.25 1.39 VIH = VREF + 0.18 1.33 1.43 3.0(2) VIL = VREF - 0.18 -0.3(3) 1.07 1.17 VOH = VREF + 0.8 1.95 - - VOL = VREF - 0.8 - - 0.55 IOH at VOH (mA) -15.2 - - IOLat VOL (mA) 15.2 - - Notes: 1. N must be greater than or equal to -0.04 and less than or equal to 0.04. 2. VIH maximum is VCCO + 0.3. 3. VIL minimum does not conform to the formula. CTT A sample circuit illustrating a valid termination technique for CTT appear in Figure 53. DC voltage specifications appear in Table 32. Notes: 1. Timing delays are calculated based on VCCO min of 3.0V. PCI33_3 & PCI66_3 PCI33_3 or PCI66_3 require no termination. DC voltage specifications appear in Table 33. Table 33: PCI33_3 and PCI66_3 Voltage Specifications Parameter Min Typ Max VCCO 3.0 3.3 3.6 VREF - - - VTT - - - VIH = 0.5 x VCCO 1.5 1.65 VCCO + 0.5 VIL = 0.3 x VCCO -0.5 0.99 1.08 VOH = 0.9 x VCCO 2.7 - - VOL= 0.1 x VCCO - - 0.36 IOH at VOH (mA) Note 1 - - IOLat VOL (mA) Note 1 - - Notes: 1. Tested according to the relevant specification. Module 2 of 4 42 www.xilinx.com 1-800-255-7778 DS098-2 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs LVTTL LVCMOS18 LVTTL requires no termination. DC voltage specifications appears in Table 34. LVCMOS18 does not require termination. Table 36 lists DC voltage specifications. Table 34: LVTTL Voltage Specifications Table 36: LVCMOS18 Voltage Specifications Parameter Min Typ Max VCCO 3.0 3.3 3.6 VREF - - VTT - VIH Min Typ Max VCCO 1.70 1.80 1.90 - VREF - - - - - VTT - - - 2.0 - 3.6 VIH 0.65 x VCCO - 1.95 VIL -0.5 - 0.8 VIL - 0.5 - 0.2 x VCCO VOH 2.4 - - VOH VCCO - 0.4 - - VOL - - 0.4 VOL - - 0.4 IOH at VOH (mA) -24 - - IOH at VOH (mA) -8 - - IOLat VOL (mA) 24 - - IOLat VOL (mA) 8 - - Notes: 1. Note: VOLand VOH for lower drive currents sample tested. LVCMOS2 LVCMOS2 requires no termination. DC voltage specifications appear in Table 35. Parameter AGP-2X The specification for the AGP-2X standard does not document a recommended termination technique. DC voltage specifications appear in Table 37. Table 37: AGP-2X Voltage Specifications Parameter Table 35: LVCMOS2 Voltage Specifications Parameter Min Typ Max VCCO VREF = N x VCCO(1) Min Typ Max 3.0 3.3 3.6 1.17 1.32 1.48 - - - VCCO 2.3 2.5 2.7 VREF - - - VTT VTT - - - VIH = VREF + 0.2 1.37 1.52 - VIH 1.7 - 3.6 VIL = VREF - 0.2 - 1.12 1.28 VIL -0.5 - 0.7 VOH = 0.9 x VCCO 2.7 3.0 - VOH 1.9 - - VOL = 0.1 x VCCO - 0.33 0.36 VOL - - 0.4 IOH at VOH (mA) Note 2 - - IOH at VOH (mA) -12 - - IOLat VOL (mA) Note 2 - - IOLat VOL (mA) 12 - - DS098-2 (v1.1) July 29, 2004 Advance Product Specification Notes: 1. N must be greater than or equal to 0.39 and less than or equal to 0.41. 2. Tested according to the relevant specification. www.xilinx.com 1-800-255-7778 Module 2 of 4 43 R QPro Virtex-E 1.8V QML High-Reliability FPGAs LVDS LVPECL Depending on whether the device is transmitting an LVDS signal or receiving an LVDS signal, there are two different circuits used for LVDS termination. A sample circuit illustrating a valid termination technique for transmitting LVDS signals appears in Figure 54. A sample circuit illustrating a valid termination for receiving LVDS signals appears in Figure 55. Table 38 lists DC voltage specifications. Further information on the specific termination resistor packs shown can be found on Table 40. Depending on whether the device is transmitting or receiving an LVPECL signal, two different circuits are used for LVPECL termination. A sample circuit illustrating a valid termination technique for transmitting LVPECL signals appears in Figure 56. A sample circuit illustrating a valid termination for receiving LVPECL signals appears in Figure 57. Table 39 lists DC voltage specifications. Further information on the specific termination resistor packs shown can be found on Table 40. Table 39: LVPECL Voltage Specifications 1/4 of Bourns Part Number CAT16-LV4F12 Virtex-E FPGA Q 2.5V RS Parameter Z0 = 50 to LVDS Receiver 165 DATA Transmit RS Q RDIV 140 Z0 = 50 to LVDS Receiver 165 VCCO = 2.5V LVDS Output x133_19_122799 Figure 54: Transmitting LVDS Signal Circuit Q Z0 = 50 from LVDS Driver + RT 100 Z0 = 50 Q Typ Max VCCO 3.0 3.3 3.6 VREF - - - VTT - - - VIH 1.49 - 2.72 VIL 0.86 - 2.125 VOH 1.8 - - VOL - - 1.57 Notes: 1. For more detailed information, see LVPECL DC Specifications (Module 2). VIRTEX-E FPGA LVDS_IN Min DATA Receive - LVDS_IN 1/4 of Bourns Part Number CAT16-PC4F12 Virtex-E FPGA Q 3.3V x133_29_122799 DATA Transmit Figure 55: Receiving LVDS Signal Circuit RS Z0 = 50 LVPECL_OUT to LVPECL Receiver 100 RS Q RDIV 187 Z0 = 50 100 to LVPECL Receiver LVPECL_OUT Table 38: LVDS Voltage Specifications Parameter Min Typ Max 2.375 2.5 2.625 0.2 1.25 2.2 1.125 1.25 1.375 VIDIFF (1) 0.1 0.35 - VODIFF (1) 0.25 0.35 0.45 VOH(1) VOL(1) 1.25 - - - - 1.25 VCCO VICM(2) VOCM (1) x133_20_122799 Figure 56: Transmitting LVPECL Signal Circuit Q VIRTEX-E FPGA Z0 = 50 LVPECL_IN + from LVPECL Driver RT 100 Z0 = 50 Q - DATA Receive LVPECL_IN x133_21_122799 Figure 57: Receiving LVPECL Signal Circuit Notes: 1. Measured with a 100 resistor across Q and Q. 2. Measured with a differential input voltage = 350 mV. Module 2 of 4 44 www.xilinx.com 1-800-255-7778 DS098-2 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Termination Resistor Packs Creating LVDS Global Clock Input Buffers Resistor packs are available with the values and the configuration required for LVDS and LVPECL termination from Bourns, Inc., as listed in Table. For pricing and availability, please contact Bourns directly at http://www.bourns.com. Global clock input buffers can be combined with adjacent IOBs to form LVDS clock input buffers. P-side is the GCLKPAD location; N-side is the adjacent IO_LVDS_DLL site. Table 41: Global Clock Input Buffer Pair Locations Table 40: Bourns LVDS/LVPECL Resistor Packs I/O Standard Term. for: Pairs/ Pack Pins CAT16-LV2F6 LVDS Driver 2 8 CAT16-LV4F12 LVDS Driver 4 16 CAT16-PC2F6 LVPECL Driver 2 8 CAT16-PC4F12 LVPECL Driver 4 16 CAT16-PT2F2 LVDS/LVPECL Receiver 2 8 CAT16-PT4F4 LVDS/LVPECL Receiver 4 16 Part Number LVDS Design Guide The SelectIO library elements have been expanded for Virtex-E devices to include new LVDS variants. At this time all of the cells might not be included in the Synthesis libraries. The 2.1i-Service Pack 2 update for Alliance and Foundation software includes these cells in the VHDL and Verilog libraries. It is necessary to combine these cells to create the Pside (positive) and N-side (negative) as described in the input, output, 3-state and bidirectional sections. GCLK 3 GCLK 2 GCLK 1 GCLK 0 Pkg P N P N P N P N CB228 - - 199 198 - - 87 88 BG432 D17 C17 A16 B16 AK16 AL17 AL16 AH15 BG560 A17 C18 D17 E17 AJ17 AM18 AL17 AM17 CG560 A17 C18 D17 E17 AJ17 AM18 AL17 AM17 FG1156 E17 C17 D17 J18 Al19 AL17 AH18 AM18 HDL Instantiation Only one global clock input buffer is required to be instantiated in the design and placed on the correct GCLKPAD location. The N-side of the buffer is reserved and no other IOB is allowed to be placed on this location. In the physical device, a configuration option is enabled that routes the pad wire to the differential input buffer located in the GCLKIOB. The output of this buffer then drives the output of the GCLKIOB cell. In EPIC it appears that the second buffer is unused. Any attempt to use this location for another purpose leads to a DRC error in the software. VHDL Instantiation IBUF_LVDS I O OBUF_LVDS I O IOBUF_LVDS T I IBUFG_LVDS I O gclk0_p : IBUFG_LVDS port map (I=>clk_external, O=>clk_internal); IO Verilog Instantiation OBUFT_LVDS T I IBUFG_LVDS gclk0_p (.I(clk_external), .O(clk_internal)); O O x133_22_122299 Figure 58: LVDS elements Location constraints All LVDS buffers must be explicitly placed on a device. For the global clock input buffers this can be done with the following constraint in the .ucf or .ncf file. NET clk_external LOC = GCLKPAD3; GCLKPAD3 can also be replaced with the package pin name such as D17 for the BG432 package. Optional N-side Some designers might prefer to also instantiate the N-side buffer for the global clock buffer. This allows the top-level net list to include net connections for both PCB layout and system-level integration. In this case, only the output P-side IBUFG connection has a net connected to it. Since the Nside IBUFG does not have a connection in the EDIF net list, it is trimmed from the design in MAP. DS098-2 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 2 of 4 45 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Location Constraints VHDL Instantiation gclk0_p : IBUFG_LVDS port map (I=>clk_p_external, O=>clk_internal); gclk0_n : IBUFG_LVDS port map (I=>clk_n_external, O=>clk_internal); IBUFG_LVDS gclk0_p (.I(clk_p_external), .O(clk_internal)); IBUFG_LVDS gclk0_n (.I(clk_n_external), .O(clk_internal)); Location Constraints All LVDS buffers must be explicitly placed on a device. For the global clock input buffers this can be done with the following constraint in the .ucf or .ncf file. NET clk_p_external LOC = GCLKPAD3; GCLKPAD3 can also be replaced with the package pin name, such as D17 for the BG432 package. VHDL Instantiation data0_p : IBUF_LVDS port map (I=>data_p(0), O=>data_int(0)); Verilog Instantiation IBUF_LVDS data0_p (.I(data_p[0]), .O(data_int[0])); Creating LVDS Input Buffers An LVDS input buffer can be placed in a wide number of IOB locations. The exact location is dependent on the package that is used. The Virtex-E package information lists the possible locations as IO_L#P for the P-side and IO_L#N for the N-side where # is the pair number. HDL Instantiation Only one input buffer is required to be instantiated in the design and placed on the correct IO_L#P location. The Nside of the buffer is reserved and no other IOB is allowed to be placed on this location. In the physical device, a configuration option is enabled that routes the pad wire from the IO_L#N IOB to the differential input buffer located in the IO_L#P IOB. The output of this buffer then drives the output of the IO_L#P cell or the input register in the IO_L#P IOB. In EPIC it appears that the second buffer is unused. Any attempt to use this location for another purpose leads to a DRC error in the software. VHDL Instantiation data0_p : IBUF_LVDS port map (I=>data(0), O=>data_int(0)); Module 2 of 4 46 Some designers might prefer to also instantiate the N-side buffer for the input buffer. This allows the top-level net list to include net connections for both PCB layout and systemlevel integration. In this case, only the output P-side IBUF connection has a net connected to it. Since the N-side IBUF does not have a connection in the EDIF net list, it is trimmed from the design in MAP. data0_n : IBUF_LVDS port map (I=>data_n(0), O=>open); NET clk_n_external LOC = C17; IBUF_LVDS data0_p (.I(data[0]), .O(data_int[0])); NET data<0> LOC = D28; # IO_L0P Optional N-side Verilog Instantiation Verilog Instantiation All LVDS buffers must be explicitly placed on a device. For the input buffers this can be done with the following constraint in the .ucf or .ncf file. IBUF_LVDS data0_n (.I(data_n[0]), .O()); Location Constraints All LVDS buffers must be explicitly placed on a device. For the global clock input buffers this can be done with the following constraint in the .ucf or .ncf file. NET data_p<0> LOC = D28; # IO_L0P NET data_n<0> LOC = B29; # IO_L0N Adding an Input Register All LVDS buffers can have an input register in the IOB. The input register is in the P-side IOB only. All the normal IOB register options are available (FD, FDE, FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD, LDE, LDC, LDCE, LDP, LDPE). The register elements can be inferred or explicitly instantiated in the HDL code. The register elements can be packed in the IOB using the IOB property to TRUE on the register or by using the "map -pr [i|o|b]" where "i" is inputs only, "o" is outputs only and "b" is both inputs and outputs. To improve design coding times VHDL and Verilog synthesis macro libraries available to explicitly create these structures. The input library macros are listed in Table 42. The I and IB inputs to the macros are the external net connections. www.xilinx.com 1-800-255-7778 DS098-2 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Verilog Instantiation Table 42: Input Library Macros Name OBUF_LVDS data0_p .O(data_p[0])); (.I(data_int[0]), Inputs Outputs I, IB, C Q IBUFDS_FDE_LVDS I, IB, CE, C Q IBUFDS_FDC_LVDS I, IB, C, CLR Q I, IB, CE, C, CLR Q I, IB, C, PRE Q Location Constraints I, IB, CE, C, PRE Q I, IB, C, R Q All LVDS buffers must be explicitly placed on a device. For the output buffers this can be done with the following constraint in the .ucf or .ncf file. I, IB, CE, C, R Q NET data_p<0> LOC = D28; # IO_L0P I, IB, C, S Q NET data_n<0> LOC = B29; # IO_L0N I, IB, CE, C, S Q Synchronous vs. Asynchronous Outputs I, IB, G Q IBUFDS_LDE_LVDS I, IB, GE, G Q IBUFDS_LDC_LVDS I, IB, G, CLR Q I, IB, GE, G, CLR Q If the outputs are synchronous (registered in the IOB) then any IO_L#P|N pair can be used. If the outputs are asynchronous (no output register), then they must use one of the pairs that are part of the same IOB group at the end of a ROW or COLUMN in the device. I, IB, G, PRE Q I, IB, GE, G, PRE Q IBUFDS_FD_LVDS IBUFDS_FDCE_LVDS IBUFDS_FDP_LVDS IBUFDS_FDPE_LVDS IBUFDS_FDR_LVDS IBUFDS_FDRE_LVDS IBUFDS_FDS_LVDS IBUFDS_FDSE_LVDS IBUFDS_LD_LVDS IBUFDS_LDCE_LVDS IBUFDS_LDP_LVDS IBUFDS_LDPE_LVDS INV data0_inv (.I(data_int[0], .O(data_n_int[0]); OBUF_LVDS data0_n .O(data_n[0])); Creating LVDS Output Buffers LVDS output buffers can be placed in a wide number of IOB locations. The exact locations are dependent on the package used. The Virtex-E package information lists the possible locations as IO_L#P for the P-side and IO_L#N for the N-side, where # is the pair number. HDL Instantiation Both output buffers are required to be instantiated in the design and placed on the correct IO_L#P and IO_L#N locations. The IOB must have the same net source the following pins, clock (C), set/reset (SR), output (O), output clock enable (OCE). In addition, the output (O) pins must be inverted with respect to each other, and if output registers are used, the INIT states must be opposite values (one HIGH and one LOW). Failure to follow these rules leads to DRC errors in software. data0_p : OBUF_LVDS port map (I=>data_int(0), O=>data_p(0)); port map O=>data_n_int(0)); data0_n : OBUF_LVDS port map (I=>data_n_int(0), O=>data_n(0)); DS098-2 (v1.1) July 29, 2004 Advance Product Specification The LVDS pairs that can be used as asynchronous outputs are listed in the Virtex-E pinout tables. Some pairs are marked as asynchronous-capable for all devices in that package, and others are marked as available only for that device in the package. If the device size might change at some point in the product lifetime, then only the common pairs for all packages should be used. Adding an Output Register All LVDS buffers can have an output register in the IOB. The output registers must be in both the P-side and N-side IOBs. All the normal IOB register options are available (FD, FDE, FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD, LDE, LDC, LDCE, LDP, LDPE). The register elements can be inferred or explicitly instantiated in the HDL code. Special care must be taken to insure that the D pins of the registers are inverted and that the INIT states of the registers are opposite. The clock pin (C), clock enable (CE) and set/reset (CLR/PRE or S/R) pins must connect to the same source. Failure to do this leads to a DRC error in the software. The register elements can be packed in the IOB using the IOB property to TRUE on the register or by using the "map -pr [i|o|b]" where "i" is inputs only, "o" is outputs only and "b" is both inputs and outputs. VHDL Instantiation data0_inv: INV (I=>data_int(0), (.I(data_n_int[0]), To improve design coding times VHDL and Verilog synthesis macro libraries have been developed to explicitly create these structures. The output library macros are listed in Table 43. The O and OB inputs to the macros are the external net connections. www.xilinx.com 1-800-255-7778 Module 2 of 4 47 R QPro Virtex-E 1.8V QML High-Reliability FPGAs VHDL Instantiation Table 43: Output Library Macros Name data0_p: OBUFT_LVDS port map (I=>data_int(0), T=>data_tri, O=>data_p(0)); Inputs Outputs D, C O, OB OBUFDS_FDE_LVDS DD, CE, C O, OB OBUFDS_FDC_LVDS D, C, CLR O, OB D, CE, C, CLR O, OB D, C, PRE O, OB D, CE, C, PRE O, OB D, C, R O, OB D, CE, C, R O, OB D, C, S O, OB D, CE, C, S O, OB D, G O, OB Location Constraints OBUFDS_LDE_LVDS D, GE, G O, OB OBUFDS_LDC_LVDS D, G, CLR O, OB All LVDS buffers must be explicitly placed on a device. For the output buffers this can be done with the following constraint in the .ucf or .ncf file. D, GE, G, CLR O, OB NET data_p<0> LOC = D28; # IO_L0P D, G, PRE O, OB NET data_n<0> LOC = B29; # IO_L0N D, GE, G, PRE O, OB OBUFDS_FD_LVDS OBUFDS_FDCE_LVDS OBUFDS_FDP_LVDS OBUFDS_FDPE_LVDS OBUFDS_FDR_LVDS OBUFDS_FDRE_LVDS OBUFDS_FDS_LVDS OBUFDS_FDSE_LVDS OBUFDS_LD_LVDS OBUFDS_LDCE_LVDS OBUFDS_LDP_LVDS OBUFDS_LDPE_LVDS Creating LVDS Output 3-State Buffers LVDS output 3-state buffers can be placed in a wide number of IOB locations. The exact locations are dependent on the package used. The Virtex-E package information lists the possible locations as IO_L#P for the P-side and IO_L#N for the N-side, where # is the pair number. HDL Instantiation Both output 3-state buffers are required to be instantiated in the design and placed on the correct IO_L#P and IO_L#N locations. The IOB must have the same net source the following pins, clock (C), set/reset (SR), 3-state (T), 3-state clock enable (TCE), output (O), output clock enable (OCE). In addition, the output (O) pins must be inverted with respect to each other, and if output registers are used, the INIT states must be opposite values (one High and one Low). If 3-state registers are used, they must be initialized to the same state. Failure to follow these rules leads to DRC errors in the software. data0_inv: INV port map (I=>data_int(0), O=>data_n_int(0)); data0_n: OBUFT_LVDS port map (I=>data_n_int(0), T=>data_tri, O=>data_n(0)); Verilog Instantiation OBUFT_LVDS data0_p (.I(data_int[0]), .T(data_tri), .O(data_p[0])); INV data0_inv (.I(data_int[0], .O(data_n_int[0]); OBUFT_LVDS data0_n (.I(data_n_int[0]), .T(data_tri), .O(data_n[0])); Synchronous vs. Asynchronous 3-State Outputs If the outputs are synchronous (registered in the IOB), then any IO_L#P|N pair can be used. If the outputs are asynchronous (no output register), then they must use one of the pairs that are part of the same IOB group at the end of a ROW or COLUMN in the device. This applies for either the 3-state pin or the data out pin. LVDS pairs that can be used as asynchronous outputs are listed in the Virtex-E pinout tables. Some pairs are marked as "asynchronous capable" for all devices in that package, and others are marked as available only for that device in the package. If the device size might be changed at some point in the product lifetime, then only the common pairs for all packages should be used. Adding Output and 3-State Registers All LVDS buffers can have an output register in the IOB. The output registers must be in both the P-side and N-side IOBs. All the normal IOB register options are available (FD, FDE, FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD, LDE, LDC, LDCE, LDP, LDPE). The register elements can be inferred or explicitly instantiated in the HDL code. Special care must be taken to insure that the D pins of the registers are inverted and that the INIT states of the registers are opposite. The 3-state (T), 3-state clock enable (CE), clock pin (C), output clock enable (CE) and set/reset (CLR/PRE or S/R) pins must connect to the same source. Failure to do this leads to a DRC error in the software. Module 2 of 4 48 www.xilinx.com 1-800-255-7778 DS098-2 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs The register elements can be packed in the IOB using the IOB property to TRUE on the register or by using the "map -pr [i|o|b]" where "i" is inputs only, "o" is outputs only and "b" is both inputs and outputs. To improve design coding times VHDL and Verilog synthesis macro libraries have been developed to explicitly create these structures. The input library macros are listed below. The 3-state is configured to be 3-stated at GSR and when the PRE,CLR,S or R is asserted and shares its clock enable with the output register. If this is not desirable then the library can be updated by the user for the desired functionality. The O and OB inputs to the macros are the external net connections. Creating a LVDS Bidirectional Buffer LVDS bidirectional buffers can be placed in a wide number of IOB locations. The exact locations are dependent on the package used. The Virtex-E package information lists the possible locations as IO_L#P for the P-side and IO_L#N for the N-side, where # is the pair number. HDL Instantiation Both bidirectional buffers are required to be instantiated in the design and placed on the correct IO_L#P and IO_L#N locations. The IOB must have the same net source the following pins, clock (C), set/reset (SR), 3-state (T), 3-state clock enable (TCE), output (O), output clock enable (OCE). In addition, the output (O) pins must be inverted with respect to each other, and if output registers are used, the INIT states must be opposite values (one HIGH and one LOW). If 3-state registers are used, they must be initialized to the same state. Failure to follow these rules leads to DRC errors in the software. VHDL Instantiation data0_p: IOBUF_LVDS port map (I=>data_out(0), T=>data_tri, IO=>data_p(0), O=>data_int(0)); data0_inv: INV (I=>data_out(0), port map O=>data_n_out(0)); data0_n : IOBUF_LVDS port map (I=>data_n_out(0), T=>data_tri, IO=>data_n(0), O=>open); Verilog Instantiation IOBUF_LVDS data0_p(.I(data_out[0]), .T(data_tri), .IO(data_p[0]), .O(data_int[0]); INV data0_inv (.I(data_out[0], .O(data_n_out[0]); IOBUF_LVDS data0_n(.I(data_n_out[0]),.T(data_tri),. IO(data_n[0]).O()); DS098-2 (v1.1) July 29, 2004 Advance Product Specification Location Constraints All LVDS buffers must be explicitly placed on a device. For the output buffers this can be done with the following constraint in the .ucf or .ncf file. NET data_p<0> LOC = D28; # IO_L0P NET data_n<0> LOC = B29; # IO_L0N Synchronous vs. Asynchronous Bidirectional Buffers If the output side of the bidirectional buffers are synchronous (registered in the IOB), then any IO_L#P|N pair can be used. If the output side of the bidirectional buffers are asynchronous (no output register), then they must use one of the pairs that is a part of the asynchronous LVDS IOB group. This applies for either the 3-state pin or the data out pin. The LVDS pairs that can be used as asynchronous bidirectional buffers are listed in the Virtex-E pinout tables. Some pairs are marked as asynchronous capable for all devices in that package, and others are marked as available only for that device in the package. If the device size might change at some point in the product's lifetime, then only the common pairs for all packages should be used. Adding Output and 3-State Registers All LVDS buffers can have an output and input registers in the IOB. The output registers must be in both the P-side and N-side IOBs, the input register is only in the P-side. All the normal IOB register options are available (FD, FDE, FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD, LDE, LDC, LDCE, LDP, LDPE). The register elements can be inferred or explicitly instantiated in the HDL code. Special care must be taken to insure that the D pins of the registers are inverted and that the INIT states of the registers are opposite. The 3-state (T), 3-state clock enable (CE), clock pin (C), output clock enable (CE), and set/reset (CLR/PRE or S/R) pins must connect to the same source. Failure to do this leads to a DRC error in the software. The register elements can be packed in the IOB using the IOB property to TRUE on the register or by using the "map -pr [i|o|b]" where "i" is inputs only, "o" is outputs only and "b" is both inputs and outputs. To improve design coding times VHDL and Verilog synthesis macro libraries have been developed to explicitly create these structures. The bidirectional I/O library macros are listed in Table 44. The 3-state is configured to be 3-stated at GSR and when the PRE,CLR,S or R is asserted and shares its clock enable with the output and input register. If this is not desirable then the library can be updated be the user for the desired functionality. The I/O and IOB inputs to the macros are the external net connections. www.xilinx.com 1-800-255-7778 Module 2 of 4 49 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 44: Bidirectional I/O Library Macros Name Inputs Bidirectional Outputs D, T, C IO, IOB Q IOBUFDS_FDE_LVDS D, T, CE, C IO, IOB Q IOBUFDS_FDC_LVDS D, T, C, CLR IO, IOB Q D, T, CE, C, CLR IO, IOB Q D, T, C, PRE IO, IOB Q D, T, CE, C, PRE IO, IOB Q D, T, C, R IO, IOB Q D, T, CE, C, R IO, IOB Q D, T, C, S IO, IOB Q D, T, CE, C, S IO, IOB Q D, T, G IO, IOB Q IOBUFDS_LDE_LVDS D, T, GE, G IO, IOB Q IOBUFDS_LDC_LVDS D, T, G, CLR IO, IOB Q D, T, GE, G, CLR IO, IOB Q D, T, G, PRE IO, IOB Q D, T, GE, G, PRE IO, IOB Q IOBUFDS_FD_LVDS IOBUFDS_FDCE_LVDS IOBUFDS_FDP_LVDS IOBUFDS_FDPE_LVDS IOBUFDS_FDR_LVDS IOBUFDS_FDRE_LVDS IOBUFDS_FDS_LVDS IOBUFDS_FDSE_LVDS IOBUFDS_LD_LVDS IOBUFDS_LDCE_LVDS IOBUFDS_LDP_LVDS IOBUFDS_LDPE_LVDS Revision History The following table shows the revision history for this document. Date Version Revision 05/19/03 1.0 Initial Xilinx release. 07/29/04 1.1 * * * * * * * * * Module 2 of 4 50 Section Input/Output Block, page 1: Last paragraph, excepted certain I/O standards from automatic addition of clamping diodes at the inputs. Section Input Path, page 2: Last paragraph, qualified the presence of optional pullup/pull-down resistors on all inputs to "all user I/O inputs." Section Block SelectRAM, page 5: Last paragraph, added reference to XAPP130. Section Configuration, page 11: Added updated information regarding the optional special use of certain pins. Section Configuration Modes: On page 12 (two places), added recommendation to actively drive configuration mode pins rather than leave tem floating. Figure 18, page 16: Updated flowchart. Section Boundary-Scan Mode, page 17: Added information about required control of PROGRAM pin, and added a reference to XAPP139. Section Duty Cycle Correction Property, page 21: Removed the statement that when duty-cycle correction deactivates, the output clock has the same duty cycle as the source clock. Table 36, page 43: Correct VIH Min from 0.7 x VCCO to 0.65 x VCCO. www.xilinx.com 1-800-255-7778 DS098-2 (v1.1) July 29, 2004 Advance Product Specification 0 QPro Virtex-E 1.8V QML High-Reliability FPGAs R DS098-3 (v1.1) July 29, 2004 0 0 Advance Product Specification QPro Virtex-E Electrical Characteristics Based on preliminary characterization. Further changes are not expected. All guaranteed specifications are representative of worst-case supply voltage and junction temperature conditions. Some specifications also include best-case timing predictions. Best-case timing specifications are for design guidance and are not guaranteed. DC Characteristics Absolute Maximum Ratings Description(1) Symbol VCCINT Units Internal Supply voltage relative to GND -0.5 to 2.0 V VCCO Supply voltage relative to GND -0.5 to 4.0 V VREF Input Reference Voltage -0.5 to 4.0 V VIN(3) Input voltage relative to GND -0.5 to VCCO + 0.5 V -0.5 to 4.0 V 50 ms -65 to +150 C Plastic packages +125 C Ceramic packages +150 C VTS Voltage applied to 3-state output VCC Longest Supply Voltage Rise Time from 0 V - 1.71 V TSTG Storage temperature (ambient) TJ Junction temperature(2) Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time can affect device reliability. 2. For soldering guidelines and thermal considerations, see the Device Packaging infomation on the Xilinx website. 3. Inputs configured as PCI are fully PCI compliant. This statement takes precedence over any specification that would imply that the device is not PCI compliant. Recommended Operating Conditions Symbol VCCINT VCCO Description Min Max Units Internal Supply voltage relative to GND, TJ = -55C to +125C Military 1.71 1.89 V Supply voltage relative to GND, TJ = -55C to +125C Military 1.2 3.6 V - 250 ns XQV600E -55 +125 C XQV1000E -55 +125 C XQV2000E -40 +125 C TIN Input signal transition time TC Operating Temperature Range (c) 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS098-3 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 1 R QPro Virtex-E 1.8V QML High-Reliability FPGAs DC Characteristics Over Recommended Operating Conditions Symbol Device Min Max Units All 1.5 - V All 1.2 - V XQV600E - 400 mA XQV1000E - 500 mA XQV2000E - 1100 mA Quiescent VCCO supply current(1) All - 2 mA Input or output leakage current All -10 +10 A CIN Input capacitance (sample tested) All - 8 pF IRPU Pad pull-up (when selected) @ Vin = 0V, VCCO = 3.3V (sample tested) All Note 2 0.25 mA IRPD Pad pull-down (when selected) @ Vin = 3.6V (sample tested) - Note 2 0.25 mA VDRINT Description Data Retention VCCINT Voltage (below which configuration data might be lost) VDRIO Data Retention VCCO Voltage (below which configuration data might be lost) ICCINTQ ICCOQ IL Quiescent VCCINT supply current(1) Notes: 1. With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating. 2. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors do not guarantee valid logic levels when input pins are connected to other circuits. Power-On Power Supply Requirements Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device operation. The actual current consumed depends on the power-on ramp rate of the power supply. This is the time required to reach the nominal power supply voltage of the device1 from 0 V. The fastest ramp rate is 0V to nominal voltage in 2 ms, and the slowest allowed ramp rate is 0V to nominal voltage in 50 ms. For more details on power supply requirements, see XAPP158. Description2 Minimum required current supply Temperature Min3 Units TJ = 0C to +125 C 1 A TJ = -40C to 0C 2 A TJ = -55C to -40C 2.5 A Notes: 1. Ramp rate used for this specification is from 0-1.8V DC. Peak current occurs on or near the internal power-on reset threshold and lasts for less than 3 ms. 2. Devices are guaranteed to initialize properly with the minimum current available from the power supply as noted above. 3. Larger currents might result if ramp rates are forced to be faster. Module 3 of 4 2 www.xilinx.com 1-800-255-7778 DS098-3 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs DC Input and Output Levels Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested. Input/Output Standard VIL VIH VOL VOH IOL IOH V, Min V, Max V, Min V, Max V, Max V, Min mA mA LVTTL(1) - 0.5 0.8 2.0 3.6 0.4 2.4 24 - 24 LVCMOS2 - 0.5 0.7 1.7 2.7 0.4 1.9 12 - 12 LVCMOS18 - 0.5 35% VCCO 65% VCCO 1.95 0.4 VCCO - 0.4 8 -8 PCI, 3.3V - 0.5 30% VCCO 50% VCCO VCCO + 0.5 10% VCCO 90% VCCO Note 2 Note 2 GTL - 0.5 VREF - 0.05 VREF + 0.05 3.6 0.4 n/a 40 n/a GTL+ - 0.5 VREF - 0.1 VREF + 0.1 3.6 0.6 n/a 36 n/a HSTL I - 0.5 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCO - 0.4 8 -8 HSTL III - 0.5 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCO - 0.4 24 -8 HSTL IV - 0.5 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCO - 0.4 48 -8 SSTL3 I - 0.5 VREF - 0.2 VREF + 0.2 3.6 VREF - 0.6 VREF + 0.6 8 -8 SSTL3 II - 0.5 VREF - 0.2 VREF + 0.2 3.6 VREF - 0.8 VREF + 0.8 16 -16 SSTL2 I - 0.5 VREF - 0.2 VREF + 0.2 3.6 VREF - 0.61 VREF + 0.61 7.6 -7.6 SSTL2 II - 0.5 VREF - 0.2 VREF + 0.2 3.6 VREF - 0.80 VREF + 0.80 15.2 -15.2 CTT - 0.5 VREF - 0.2 VREF + 0.2 3.6 VREF - 0.4 VREF + 0.4 8 -8 AGP - 0.5 VREF - 0.2 VREF + 0.2 3.6 10% VCCO 90% VCCO Note 2 Note 2 Notes: 1. VOL and VOH for lower drive currents are sample tested. 2. Tested according to the relevant specifications. DS098-3 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 3 R QPro Virtex-E 1.8V QML High-Reliability FPGAs LVDS DC Specifications Symbol DC Parameter VCCO Conditions Supply Voltage Min Typ Max Units 2.375 2.5 2.625 V VOH Output High Voltage for Q and Q RT = 100 across Q and Q signals 1.25 1.425 1.6 V VOL Output Low Voltage for Q and Q RT = 100 across Q and Q signals 0.9 1.075 1.25 V RT = 100 across Q and Q signals 250 350 450 mV RT = 100 across Q and Q signals 1.125 1.25 1.375 V Common-mode input voltage = 1.25V 100 350 NA mV Differential input voltage = 350 mV 0.2 1.25 2.2 V Differential Output Voltage (Q - Q), VODIFF Q = High (Q - Q), Q = High VOCM Output Common-Mode Voltage Differential Input Voltage (Q - Q), VIDIFF Q = High (Q - Q), Q = High VICM Input Common-Mode Voltage Notes: 1. Refer to the Design Consideration section for termination schematics. LVPECL DC Specifications These values are valid at the output of the source termination pack shown under LVPECL (Module 2), with a 100 differential load only. The VOH levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower common-mode ranges. The following table summarizes the DC output specifications of LVPECL. DC Parameter Min VCCO Max Min 3.0 Max Min 3.3 Max 3.6 Units V VOH 1.8 2.11 1.92 2.28 2.13 2.41 V VOL 0.96 1.27 1.06 1.43 1.30 1.57 V VIH 1.49 2.72 1.49 2.72 1.49 2.72 V VIL 0.86 2.125 0.86 2.125 0.86 2.125 V Differential Input Voltage 0.3 - 0.3 - 0.3 - V Module 3 of 4 4 www.xilinx.com 1-800-255-7778 DS098-3 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Virtex-E Switching Characteristics Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Virtex-E devices unless otherwise noted. IOB Input Switching Characteristics Input delays associated with the pad are specified below for LVTTL levels. For other standards, adjust the delays with the values shown in IOB Input Switching Characteristics Standard Adjustments, page 6. Description(2) Symbol Best Case(3) Worst Case Device Min Max Min Max All 0.43 - - 0.8 ns XQV600E 0.51 - - 1.0 ns XQV1000E 0.55 - - 1.1 ns XQV2000E 0.55 - - 1.1 ns All 0.8 - - XQV600E 1.55 - - 3.7 ns XQV1000E 1.55 - - 3.7 ns XQV2000E 1.59 - - 3.8 ns 0.56 1.4 ns 0.56 1.4 ns ns Units Propagation Delays TIOPI Pad to I output, no delay TIOPID Pad to I output, with delay TIOPLI Pad to output IQ via transparent latch, no delay TIOPLID Pad to output IQ via transparent latch, with delay 1.6 ns Sequential Delays, Clock CLK TCH Minimum Pulse Width, High TCL Minimum Pulse Width, Low TIOCKIQ All Clock CLK to output IQ 0.18 - - 0.7 All 0.69 / 0 - 1.5 / 0 - XQV600E 1.49 / 0 - 3.5 / 0 - ns XQV1000E 1.49 / 0 - 3.5 / 0 - ns XQV2000E 1.53 / 0 - 3.6 / 0 - ns Setup and Hold Times with respect to Clock at IOB Input Register TIOPICK/ TIOICKP Pad, no delay TIOPICKD/ TIOICKPD Pad, with delay ns TIOICECK/ TIOCKICE ICE input All 0.28 / 0.01 - 0.7 / 0.01 - ns TIOSRCKI SR input (IFF, synchronous) All 0.38 - 1.0 - ns Set/Reset Delays TIOSRIQ SR input to IQ (asynchronous) All 0.54 - - 1.4 ns TGSRQ GSR to output IQ All 3.88 - - 9.7 ns Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. 2. Input timing i for LVTTL is measured at 1.4V. For other I/O standards, see Table 2. 3. Best Case numbers are Advance specification numbers. See DC Characteristics, page 1 for a description. DS098-3 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 5 R QPro Virtex-E 1.8V QML High-Reliability FPGAs IOB Input Switching Characteristics Standard Adjustments Standard(1) Min(2) Max Units LVTTL 0.0 0.0 ns LVCMOS2 -0.02 0.0 ns TILVCMOS18 LVCMOS18 0.12 +0.20 ns TILVDS LVDS 0.00 +0.15 ns TILVPECL LVPECL 0.00 +0.15 ns TIPCI33_3 PCI, 33 MHz, 3.3V -0.05 +0.08 ns TIPCI66_3 PCI, 66 MHz, 3.3V -0.05 -0.11 ns TIGTL GTL +0.10 +0.14 ns TIGTLPLUS GTL+ +0.06 +0.14 ns TIHSTL HSTL +0.02 +0.04 ns TISSTL2 SSTL2 -0.04 +0.04 ns TISSTL3 SSTL3 -0.02 +0.04 ns TICTT CTT +0.01 +0.10 ns TIAGP AGP -0.03 +0.04 ns Symbol Description Data Input Delay Adjustments TILVTTL Standard-specific data input delay adjustments TILVCMOS2 Notes: 1. Input timing i for LVTTL is measured at 1.4V. For other I/O standards, see Table 2. 2. Best Case Numbers are Advance product specification numbers. See DC Characteristics, page 1 for a description. T TCE D Q CE Weak Keeper SR O OCE PAD D Q CE OBUFT SR I IQ Q D CE Programmable Delay IBUF Vref SR SR CLK ICE ds022_02_091300 Figure 1: Virtex-E Input/Output Block (IOB) Module 3 of 4 6 www.xilinx.com 1-800-255-7778 DS098-3 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs IOB Output Switching Characteristics, Figure 1 Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 8. Best Case Description (2) Symbol Worst Case (1) Min (3) Max Min Max Units Propagation Delays TIOOP O input to Pad 1.04 - - 2.9 ns TIOOLP O input to Pad via transparent latch 1.24 - - 3.4 ns 3-State Delays TIOTHZ T input to Pad high-impedance(2) 0.73 - - 1.9 ns TIOTON T input to valid data on Pad 1.13 - - 3.1 ns TIOTLPHZ T input to Pad high-impedance via transparent latch (2) 0.86 - - 2.2 ns TIOTLPON T input to valid data on Pad via transparent latch 1.26 - - 3.4 ns TGTS impedance(2) 1.94 - - 4.9 ns GTS to Pad high Sequential Delays, Clock CLK TCH Minimum Pulse Width, High 0.56 1.4 ns TCL Minimum Pulse Width, Low 0.56 1.4 ns TIOCKP Clock CLK to Pad 0.97 - - 2.9 ns TIOCKHZ Clock CLK to Pad high-impedance (synchronous)(2) 0.77 - - 2.2 ns TIOCKON Clock CLK to valid data on Pad (synchronous) 1.17 - - 3.4 ns 0.43 / 0 - 1.1 / 0 - ns 0.28 / 0 - 0.7 / 0 - ns 0.40 / 0 - 1.0 / 0 - ns 0.26 / 0 - 0.7 / 0 - ns Setup and Hold Times before/after Clock CLK TIOOCK / TIOCKO O input TIOOCECK / TIOCKOCE OCE input TIOSRCKO / TIOCKOSR SR input (OFF) TIOTCK / TIOCKT 3-State Setup Times, T input TIOTCECK / TIOCKTCE 3-State Setup Times, TCE input 0.30 / 0 - 0.8 / 0 - ns TIOSRCKT / TIOCKTSR 3-State Setup Times, SR input (TFF) 0.38 / 0 - 1.0 / 0 - ns 1.30 - - 3.5 ns 1.08 - - 2.7 ns Set/Reset Delays TIOSRP SR input to Pad (asynchronous) (asynchronous)(2) TIOSRHZ SR input to Pad high-impedance TIOSRON SR input to valid data on Pad (asynchronous) 1.48 - - 3.9 ns TIOGSRQ GSR to Pad 3.88 - - 9.7 ns Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. 2. 3-state turn-off delays should not be adjusted. 3. Best Case Numbers are Advance product specification numbers. See DC Characteristics, page 1 for a description. DS098-3 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 7 R QPro Virtex-E 1.8V QML High-Reliability FPGAs IOB Output Switching Characteristics Standard Adjustments Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays by the values shown. Description Standard Min(1) Max Units Standard-specific adjustments for output delays terminating at pads (based on standard capacitive load, Csl) LVTTL, Slow, 2 mA 4.2 +14.7 ns 4 mA 2.5 +7.5 ns TOLVTTL_S6 6 mA 1.8 +4.8 ns TOLVTTL_S8 8 mA 1.2 +3.0 ns TOLVTTL_S12 12 mA 1.0 +1.9 ns TOLVTTL_S16 16 mA 0.9 +1.7 ns TOLVTTL_S24 24 mA 0.8 +1.3 ns TOLVTTL_F2 LVTTL, Fast, 2 mA 1.9 +13.1 ns TOLVTTL_F4 4 mA 0.7 +5.3 ns TOLVTTL_F6 6 mA 0.20 +3.1 ns TOLVTTL_F8 8 mA 0.10 +1.0 ns TOLVTTL_F12 12 mA 0.0 0.0 ns TOLVTTL_F16 16 mA -0.10 -0.05 ns TOLVTTL_F24 24 mA -0.10 -0.20 ns TOLVCMOS_2 LVCMOS2 0.10 +0.09 ns TOLVCMOS_18 LVCMOS18 0.10 +0.7 ns TOLVDS LVDS -0.39 -1.2 ns TOLVPECL LVPECL -0.20 -0.41 ns TOPCI33_3 PCI, 33 MHz, 3.3V 0.50 +2.3 ns TOPCI66_3 PCI, 66 MHz, 3.3V 0.10 -0.41 ns TOGTL GTL 0.6 +0.49 ns TOGTLP GTL+ 0.7 +0.8 ns TOHSTL_I HSTL I 0.10 -0.51 ns TOHSTL_III HSTL III -0.10 -0.91 ns TOHSTL_IV HSTL IV -0.20 -1.01 ns TOSSTL2_I SSTL2 I -0.10 -0.51 ns TOSSTL2_II SSTL2 II -0.20 -0.91 ns TOSSTL3_I SSTL3 I -0.20 -0.51 ns TOSSTL3_II SSTL3 II -0.30 -1.01 ns TOCTT CTT 0.0 -0.61 ns TOAGP AGP -0.1 -0.91 ns Symbol Output Delay Adjustments TOLVTTL_S2 TOLVTTL_S4 Notes: 1. The numbers for Min are Best Case Advance product specification numbers. See DC Characteristics, page 1 for a description. Module 3 of 4 8 www.xilinx.com 1-800-255-7778 DS098-3 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Calculation of Tioop as a Function of Capacitance Tioop is the propagation delay from the O Input of the IOB to the pad. The values for Tioop are based on the standard capacitive load (Csl) for each I/O standard as listed in Table 1. For other capacitive loads, use the formulas below to calculate the corresponding Tioop: Tioop = Tioop + Topadjust + (Cload - Csl) * fl where: Table 1: Constants for Use in Calculation of Tioop Standard Csl (pF) fl (ns/pF) LVTTL Fast Slew Rate, 2 mA drive 35 0.41 LVTTL Fast Slew Rate, 4 mA drive 35 0.20 LVTTL Fast Slew Rate, 6 mA drive 35 0.13 LVTTL Fast Slew Rate, 8 mA drive 35 0.079 LVTTL Fast Slew Rate, 12 mA drive 35 0.044 LVTTL Fast Slew Rate, 16 mA drive 35 LVTTL Fast Slew Rate, 24 mA drive Topadjust is reported above in the Output Delay Adjustment section. Cload is the capacitive load for the design. Table 2: Delay Measurement Methodology VL(1) VH(1) Meas. Point VREF (Typ)(2) LVTTL 0 3 1.4 - 0.043 LVCMOS2 0 2.5 1.125 - 35 0.033 PCI33_3 Per PCI Spec - LVTTL Slow Slew Rate, 2 mA drive 35 0.41 PCI66_3 Per PCI Spec - LVTTL Slow Slew Rate, 4 mA drive 35 0.20 GTL VREF - 0.2 VREF + 0.2 VREF 0.80 LVTTL Slow Slew Rate, 6 mA drive 35 0.10 GTL+ VREF - 0.2 VREF + 0.2 VREF 1.0 LVTTL Slow Slew Rate, 8 mA drive 35 0.086 HSTL Class I VREF - 0.5 VREF + 0.5 VREF 0.75 LVTTL Slow Slew Rate, 12 mA drive 35 0.058 HSTL Class III VREF - 0.5 VREF + 0.5 VREF 0.90 LVTTL Slow Slew Rate, 16 mA drive 35 0.050 HSTL Class IV VREF - 0.5 VREF + 0.5 VREF 0.90 LVTTL Slow Slew Rate, 24 mA drive 35 0.048 SSTL3 I & II VREF - 1.0 VREF + 1.0 VREF 1.5 LVCMOS2 35 0.041 SSTL2 I & II VREF - 0.75 VREF + 0.75 VREF 1.25 LVCMOS18 35 0.050 VREF + 0.2 VREF 1.5 PCI 33 MHZ 3.3V 10 0.050 PCI 66 MHz 3.3V 10 0.033 VREF GTL 0 0.014 Per AGP Spec GTL+ 0 0.017 HSTL Class I 20 0.022 HSTL Class III 20 0.016 HSTL Class IV 20 0.014 SSTL2 Class I 30 0.028 SSTL2 Class II 30 0.016 SSTL3 Class I 30 0.029 SSTL3 Class II 30 0.016 CTT 20 0.035 AGP 10 0.037 Standard CTT VREF - 0.2 AGP VREF - VREF + (0.2xVCCO) (0.2xVCCO) 1.2 - 0.125 1.2 + 0.125 1.2 1.6 - 0.3 1.6 + 0.3 1.6 LVDS LVPECL Notes: 1. Input waveform switches between VLand VH. 2. Measurements are made at VREF (Typ), Maximum, and Minimum. Worst-case values are reported. I/O parameter measurements are made with the capacitance values shown in Table 14. See the Application Examples (Module 2) for appropriate terminations. I/O standard measurements are reflected in the IBIS model information except where the IBIS format precludes it. Notes: 1. I/O parameter measurements are made with the capacitance values shown above. See the Application Examples (Module 2) for appropriate terminations. 2. I/O standard measurements are reflected in the IBIS model information except where the IBIS format precludes it. DS098-3 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 9 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Clock Distribution Switching Characteristics Symbol Description Min(1) Max Units GCLK IOB and Buffer TGPIO Global Clock PAD to output. 0.38 0.7 ns TGIO Global Clock Buffer I input to O output 0.11 0.50 ns Notes: 1. The numbers for Min are Best Case Advance product specification numbers. See DC Characteristics, page 1 for a description. I/O Standard Global Clock Input Adjustments Symbol(1) Standard Min(2) Max Units LVTTL 0.0 0.0 ns LVCMOS2 -0.02 0.0 ns TGPLVCMOS18 LVCMOS18 0.12 0.20 ns TGLVDS LVDS 0.23 0.38 ns TGLVPECL LVPECL 0.23 0.38 ns TGPPCI33_3 PCI, 33 MHz, 3.3V -0.05 0.08 ns TGPPCI66_3 PCI, 66 MHz, 3.3V -0.05 -0.11 ns TGPGTL GTL 0.20 0.37 ns TGPGTLP GTL+ 0.20 0.37 ns TGPHSTL HSTL 0.18 0.27 ns TGPSSTL2 SSTL2 0.21 0.27 ns TGPSSTL3 SSTL3 0.18 0.27 ns TGPCTT CTT 0.22 0.33 ns TGPAGP AGP 0.21 0.27 ns Description Data Input Delay Adjustments TGPLVTTL TGPLVCMOS2 Standard-specific global clock input delay adjustments Notes: 1. Input timing for GPLVTTL is measured at 1.4V. For other I/O standards, see Table 2. 2. The numbers for Min are Best Case Advance product specification numbers. See DC Characteristics, page 1 for a description. Module 3 of 4 10 www.xilinx.com 1-800-255-7778 DS098-3 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs CLB Switching Characteristics Delays originating at F/G inputs vary slightly according to the input used, see Figure 2. The values listed below are worst-case. Precise values are provided by the timing analyzer. Best Case (1) Description Symbol Worst Case (2) Min Max Min Max Units Combinatorial Delays TILO 4-input function: F/G inputs to X/Y outputs 0.19 - - 0.47 ns TIF5 5-input function: F/G inputs to F5 output 0.36 - - 0.9 ns TIF5X 5-input function: F/G inputs to X output 0.35 - - 0.9 ns TIF6Y 6-input function: F/G inputs to Y output via F6 MUX 0.35 - - 1.0 ns TF5INY 6-input function: F5IN input to Y output 0.04 - - 0.22 ns TIFNCTL Incremental delay routing through transparent latch to XQ/YQ outputs 0.27 - - 0.8 ns BY input to YB output 0.19 - - 0.51 ns TBYYB Sequential Delays TCKO FF Clock CLK to XQ/YQ outputs 0.34 - - 1.0 ns TCKLO Latch Clock CLK to XQ/YQ outputs 0.40 - - 1.0 ns 0.39 / 0 - 1.1 / 0 - ns 0.55 / 0 - 1.5 / 0 - ns 0.27 / 0 - 0.8 / 0 - ns 0.58 / 0 - 1.6 / 0 - ns 0.25 / 0 - 0.8 / 0 - ns 0.28 / 0 - 0.7 / 0 - ns 0.24 / 0 - 0.6 / 0 - ns Setup and Hold Times before/after Clock CLK TICK / TCKI 4-input function: F/G Inputs TIF5CK / TCKIF5 5-input function: F/G inputs TF5INCK / TCKF5IN 6-input function: F5IN input TIF6CK / TCKIF6 6-input function: F/G inputs via F6 MUX TDICK / TCKDI BX/BY inputs TCECK / TCKCE CE input TRCK / TCKR SR/BY inputs (synchronous) Clock CLK TCH Minimum Pulse Width, High 1.4 - 1.4 - ns TCL Minimum Pulse Width, Low 1.4 - 1.4 - ns Minimum Pulse Width, SR/BY inputs 0.94 - 2.4 - ns TRQ Delay from SR/BY inputs to XQ/YQ outputs (asynchronous) 0.39 - - 1.0 ns FTOG Toggle Frequency (MHz) (for export control) - - - 357.2 MHz Set/Reset TRPW Notes: 1. Best Case Numbers are Advance product specification numbers. See DC Characteristics, page 1 for a description. 2. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. DS098-3 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 11 R QPro Virtex-E 1.8V QML High-Reliability FPGAs COUT YB CY G4 G3 G2 G1 I3 I2 I1 I0 Y O LUT DI WE 0 INIT D Q CE 1 REV YQ BY XB F5IN F6 CY CK WE A4 BY DG WSO WSH BX X DI INIT DQ CE BX F4 F3 F2 F1 I3 I2 I1 I0 F5 F5 WE XQ DI REV O LUT 0 1 SR CLK CE CIN ds022_05_092000 Figure 2: Detailed View of Virtex-E Slice Module 3 of 4 12 www.xilinx.com 1-800-255-7778 DS098-3 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs CLB Arithmetic Switching Characteristics Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment listed. Precise values are provided by the timing analyzer. Best Case(1) Symbol Description Worst Case(2) Min Max Min Max Units Combinatorial Delays TOPX F operand inputs to X via XOR 0.32 - - 0.8 ns TOPXB F operand input to XB output 0.35 - - 0.9 ns TOPY F operand input to Y via XOR 0.59 - - 1.5 ns TOPYB F operand input to YB output 0.48 - - 1.3 ns TOPCYF F operand input to COUT output 0.37 - - 1.0 ns TOPGY G operand inputs to Y via XOR 0.34 - - 0.9 ns TOPGYB G operand input to YB output 0.47 - - 1.3 ns TOPCYG G operand input to COUT output 0.36 - - 1.0 ns TBXCY BX initialization input to COUT 0.19 - - 0.57 ns TCINX CIN input to X output via XOR 0.27 - - 0.7 ns TCINXB CIN input to XB 0.02 - - 0.08 ns TCINY CIN input to Y via XOR 0.26 - - 0.7 ns TCINYB CIN input to YB 0.16 - - 0.43 ns CIN input to COUT output 0.05 - - 0.15 ns TBYP Multiplier Operation TFANDXB F1/2 operand inputs to XB output via AND 0.10 - - 0.39 ns TFANDYB F1/2 operand inputs to YB output via AND 0.28 - - 0.8 ns TFANDCY F1/2 operand inputs to COUT output via AND 0.17 - - 0.51 ns TGANDYB G1/2 operand inputs to YB output via AND 0.20 - - 0.7 ns TGANDCY G1/2 operand inputs to COUT output via AND 0.09 - - 0.34 ns Setup and Hold Times before/after Clock CLK TCCKX/TCKCX CIN input to FFX 0.47 / 0 - 1.3 / 0 - ns TCCKY/TCKCY CIN input to FFY 0.49 / 0 - 1.3 / 0 - ns Notes: 1. Best Case Numbers are Advance product specification numbers. See DC Characteristics, page 1 for a description. 2. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. DS098-3 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 13 R QPro Virtex-E 1.8V QML High-Reliability FPGAs CLB Distributed RAM Switching Characteristics Worst Case(1) Best Case Description Symbol Min(2) Max Min Max Units Sequential Delays TSHCKO16 Clock CLK to X/Y outputs (WE active) 16 x 1 mode 0.67 - - 1.7 ns TSHCKO32 Clock CLK to X/Y outputs (WE active) 32 x 1 mode 0.84 - - 2.1 ns 1.25 - - 3.2 ns Shift-Register Mode TREG Clock CLK to X/Y outputs Setup and Hold Times before/after Clock CLK TAS/TAH F/G address inputs 0.19 / 0 - 0.47 / 0 - ns TDS/TDH BX/BY data inputs (DIN) 0.24 / 0 - 0.6 / 0 - ns TWS/TWH CE input (WE) 0.29 / 0 - 0.8 / 0 - ns Shift-Register Mode TSHDICK BX/BY data inputs (DIN) 0.24 / 0 - 0.6 / 0 - ns TSHCECK CE input (WS) 0.29 / 0 - 0.8 / 0 - ns Clock CLK TWPH Minimum Pulse Width, High 0.96 - 2.4 - ns TWPL Minimum Pulse Width, Low 0.96 - 2.4 - ns TWC Minimum clock period to meet address write cycle time 1.92 - 4.8 - ns Shift-Register Mode TSRPH Minimum Pulse Width, High 1.0 - 2.4 - ns TSRPL Minimum Pulse Width, Low 1.0 - 2.4 - ns Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. 2. The numbers for Min are Advance product specification numbers. See DC Characteristics, page 1 for a description. RAMB4_S#_S# WEA ENA RSTA CLKA ADDRA[#:0] DIA[#:0] WEB ENB RSTB CLKB ADDRB[#:0] DIB[#:0] DOA[#:0] DOB[#:0] ds022_06_121699 Figure 3: Dual-Port Block SelectRAM Module 3 of 4 14 www.xilinx.com 1-800-255-7778 DS098-3 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Block RAM Switching Characteristics Worst Case(1) Best Case Description Symbol Min(2) Max Min Max Units 0.63 - - 3.5 ns Sequential Delays TBCKO Clock CLK to DOUT output Setup and Hold Times before Clock CLK TBACK/TBCKA ADDR inputs 0.42 / 0 - 1.1 / 0 - ns TBDCK/TBCKD DIN inputs 0.42 / 0 - 1.1 / 0 - ns TBECK/TBCKE EN input 0.97 / 0 - 2.5 / 0 - ns TBRCK/TBCKR RST input 0.9 / 0 - 2.3 / 0 - ns TBWCK/TBCKW WEN input 0.86 / 0 - 2.2 / 0 - ns Clock CLK TBPWH Minimum Pulse Width, High 0.6 - 1.5 - ns TBPWL Minimum Pulse Width, Low 0.6 - 1.5 - ns TBCCS CLKA -> CLKB setup time for different ports 1.2 - 3.0 - ns Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. 2. The numbers for Min are Advance product specification numbers. See DC Characteristics, page 1 for a description. TBUF Switching Characteristics Best Case Description Worst Case Min(1) Max Min Max Units IN input to OUT output 0.0 - - 0 .0 ns TOFF TRI input to OUT output high-impedance 0.05 - - 0.11 ns TON TRI input to valid data on OUT output 0.05 - - 0.11 ns Symbol Combinatorial Delays TIO Notes: 1. The numbers for Min are Advance product specification numbers. See DC Characteristics, page 1 for a description. JTAG Test Access Port Switching Characteristics Symbol Description Min Max Units TTAPTK TMS and TDI Setup times before TCK 4.0 - ns TTCKTAP TMS and TDI Hold times after TCK 2.0 - ns TTCKTDO Output delay from clock TCK to output TDO - 11.0 ns Maximum TCK clock frequency - 33 MHz FTCK DS098-3 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 15 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Virtex-E Pin-to-Pin Output Parameter Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are expressed in nanoseconds unless otherwise noted. Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DLL Best Case Worst Case Symbol Description(1) Device Min(4) Max Min Max Units TICKOFDLL LVTTL Global Clock Input to Output Delay using Output Flip-flop, 12 mA, Fast Slew Rate, with DLL. For data output with different standards, adjust the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 8. XQV600E 1.0 - - 3.1 ns XQV1000E 1.0 - - 3.1 ns XQV2000E 1.0 - - 3.1 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at 50% VCC threshold with 35 pF external capacitive load. For other I/O standards and different loads, see Table 1 and Table 2. 3. DLL output jitter is already included in the timing calculation. 4. The numbers for Min are Advance product specification numbers. See DC Characteristics, page 1 for a description. Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DLL Best Case Worst Case Symbol Description1 Device Min(4) Max Min Max Units TICKOF LVTTL Global Clock Input to Output Delay using Output Flip-flop, 12 mA, Fast Slew Rate, without DLL. For data output with different standards, adjust the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 8. XQV600E 1.6 - - 4.9 ns XQV1000E 1.7 - - 5.0 ns XQV2000E 1.8 - - 5.2 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at 50% VCC threshold with 35 pF external capacitive load. For other I/O standards and different loads, see Table 1 and Table 2. 3. The numbers for Min are Advance product specification numbers. See DC Characteristics, page 1 for a description. Module 3 of 4 16 www.xilinx.com 1-800-255-7778 DS098-3 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Virtex-E Pin-to-Pin Input Parameter Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are expressed in nanoseconds unless otherwise noted. Global Clock Set-Up and Hold for LVTTL Standard, with DLL Best Case Description(1) Symbol TPSDLL/TPHDLL No Delay. Global Clock and IFF, with DLL. Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. For data input with different standards, adjust the setup time delay by the values shown in IOB Input Switching Characteristics Standard Adjustments, page 6. Worst Case Device Min(4) Max Min Max Units XQV600E 1.5 / -0.4 - - 1.7 / -0.4 ns XQV1000E 1.5 / -0.4 - - 1.7 / -0.4 ns XQV2000E 1.5 / -0.4 - - 1.7 / -0.4 ns Notes: 1. IFF = Input Flip-Flop or Latch. 2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. 3. DLL output jitter is already included in the timing calculation. 4. The numbers for Min are Advance product specification numbers. See DC Characteristics, page 1 for a description. Global Clock Set-Up and Hold for LVTTL Standard, without DLL Best Case Description(1) Device Min(4) Max Min Max Units Full Delay XQV600E 2.1 / 0 - - 2.1 / 0 ns Global Clock and IFF, without DLL XQV1000E 2.3 / 0 - - 2.3 / 0 ns Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. For data input with different standards, adjust the setup time delay by the values shown in IOB Input Switching Characteristics Standard Adjustments, page 6. XQV2000E 2.5 / 0 - - 2.5 / 0 ns Symbol TPSFD/TPHFD Worst Case Notes: 1. IFF = Input Flip-Flop or Latch. 2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. 3. DLL output jitter is already included in the timing calculation. 4. The numbers for Min are Advance product specification numbers. See DC Characteristics, page 1 for a description. DS098-3 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 17 R QPro Virtex-E 1.8V QML High-Reliability FPGAs DLL Timing Parameters Switching parameters testing is modeled after testing methods specified by MIL-M-38510/605; all devices are 100 percent functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those parameters are derived from benchmark timing patterns. The following guidelines reflect worst-case values across the recommended operating conditions. Min Max Units FCLKINHF 60 275 MHz Input Clock Frequency (CLKDLL) FCLKINLF 25 135 MHz Input Clock Low/High Pulse Width TDLLPW 25 MHz 5.0 - ns 50 MHz 3.0 - ns 100 MHz 2.4 - ns 150 MHz 2.0 - ns 200 MHz 1.8 - ns 250 MHz 1.5 - ns 300 MHz NA - ns Description Symbol Input Clock Frequency (CLKDLLHF) FCLKIN Notes: 1. All specifications correspond to Military Operating Temperatures (-55C to +125C). Period Tolerance: the allowed input clock period change in nanoseconds. TCLKIN + _ TIPTOL TCLKIN Output Jitter: the difference between an ideal reference clock edge and the actual design. Phase Offset and Maximum Phase Difference Ideal Period Actual Period + Jitter +/- Jitter + Maximum Phase Difference + Phase Offset ds022_24_091200 Figure 4: DLL Timing Waveforms Module 3 of 4 18 www.xilinx.com 1-800-255-7778 DS098-3 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs DLL Clock Tolerance, Jitter, and Phase Information All DLL output jitter and phase specifications determined through statistical measurement at the package pins using a clock mirror configuration and matched drivers. CLKDLLHF Symbol Description FCLKIN CLKDLL Min Max Min Max Units TIPTOL Input Clock Period Tolerance - 1.0 - 1.0 ns TIJITCC Input Clock Jitter Tolerance (Cycle to Cycle) - 150 - 300 ps TLOCK Time Required for DLL to Acquire Lock > 60 MHz - 20 - 20 s 50 - 60 MHz - - - 25 s 40 - 50 MHz - - - 50 s 30 - 40 MHz - - - 90 s 25 - 30 MHz - - - 120 s Output Jitter (cycle-to-cycle) for any DLL Clock Output(1) - 60 - 60 ps Phase Offset between CLKIN and CLKO(2) - 100 - 100 ps - 140 - 140 ps - 160 - 160 ps - 200 - 200 ps TOJITCC TPHIO TPHOO TPHIOM TPHOOM Phase Offset between Clock Outputs on the DLL(3) Maximum Phase Difference between CLKIN and CLKO(4) Maximum Phase Difference between Clock Outputs on the DLL(5) Notes: 1. Output Jitter is cycle-to-cycle jitter measured on the DLL output clock, excluding input clock jitter. 2. Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO, excluding Output Jitter and input clock jitter. 3. Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL outputs, excluding Output Jitter and input clock jitter. 4. Maximum Phase Difference between CLKIN an CLKO is the sum of Output Jitter and Phase Offset between CLKIN and CLKO, or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter). 5. Maximum Phase DIfference between Clock Outputs on the DLL is the sum of Output JItter and Phase Offset between any DLL clock outputs, or the greatest difference between any two DLL output rising edges sue to DLL alone (excluding input clock jitter). 6. All specifications correspond to Military Operating Temperatures (-55C to +125C). Revision History The following table shows the revision history for this document. Date Version Revision 05/19/03 1.0 Initial Xilinx release. 07/29/04 1.1 * * * * DS098-3 (v1.1) July 29, 2004 Advance Product Specification Table Absolute Maximum Ratings, page 1: - Revised VIN from "-0.5 to 4.0" to "-0.5 to VCCO + 0.5". - Removed Footnote (2) regarding power-up sequencing. Former Footnote (3) is now Footnote (2). - Added new Footnote (3) regarding PCI standard compliance. Table DC Characteristics Over Recommended Operating Conditions, page 2: Revised ICCINTQ for XQV2000E device from 500 mA to 1100 mA. Section Power-On Power Supply Requirements, page 2: Added reference to XAPP158 regarding power supply requirements. Table IOB Input Switching Characteristics, page 5, and IOB Output Switching Characteristics, Figure 1, page 7: Added TCH and TCL pulse width parameters for clock CLK. www.xilinx.com 1-800-255-7778 Module 3 of 4 19 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Module 3 of 4 20 www.xilinx.com 1-800-255-7778 DS098-3 (v1.1) July 29, 2004 Advance Product Specification 0 QPro Virtex-E 1.8V QML High-Reliability FPGAs R DS096-4 (v1.1) July 29, 2004 0 0 Advance Product Specification Virtex-E Pin Definitions Pin Name Dedicated Pin Direction Description GCK0, GCK1, GCK2, GCK3 Yes Input Clock input pins that connect to Global Clock Buffers. M0, M1, M2 Yes Input Mode pins are used to specify the configuration mode. CCLK Yes Input or Output PROGRAM Yes Input DONE Yes Bidirectional Indicates that configuration loading is complete, and that the start-up sequence is in progress. The output can be open drain. INIT No Bidirectional (Open-drain) When Low, indicates that the configuration memory is being cleared. The pin becomes a user I/O after configuration. BUSY/DOUT No Output In SelectMAP mode, BUSY controls the rate at which configuration data is loaded. The pin becomes a user I/O after configuration unless the SelectMAP port is retained. The configuration Clock I/O pin: it is an input for SelectMAP and slave-serial modes, and output in master-serial mode. After configuration, it is input only, logic level = Don't Care. Initiates a configuration sequence when asserted Low. In bit-serial modes, DOUT provides preamble and configuration data to downstream devices in a daisy-chain. The pin becomes a user I/O after configuration. D0/DIN, D1, D2, D3, D4, D5, D6, D7 No Input or Output In SelectMAP mode, D0-D7 are configuration data pins. These pins become user I/Os after configuration unless the SelectMAP port is retained. In bit-serial modes, DIN is the single data input. This pin becomes a user I/O after configuration. WRITE No Input In SelectMAP mode, the active-low Write Enable signal. The pin becomes a user I/O after configuration unless the SelectMAP port is retained. CS No Input In SelectMAP mode, the active-low Chip Select signal. The pin becomes a user I/O after configuration unless the SelectMAP port is retained. TDI, TDO, TMS, TCK Yes Mixed Boundary-scan Test-Access-Port pins, as defined in IEEE1149.1. DXN, DXP Yes N/A Temperature-sensing diode pins. (Anode: DXP, cathode: DXN) VCCINT Yes Input Power-supply pins for the internal core logic. VCCO Yes Input Power-supply pins for the output drivers (subject to banking rules) VREF No Input Input threshold voltage pins. Become user I/Os when an external threshold voltage is not needed (subject to banking rules). GND Yes Input Ground (c) 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS096-4 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 1 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Low Voltage Differential Signals The Virtex-E family incorporates low-voltage signalling (LVDS and LVPECL). Two pins are utilized for these signals to be connected to a Virtex-E device. These are known as differential pin pairs. Each differential pin pair has a Positive (P) and a Negative (N) pin. These pairs are labeled in the following manner. an additional table summarizing information specific to differential pin pairs for all devices provided in that package. Table 1: LVDS Pin Pairs Pin Name IO_L#[P/N] IO_L#[P/N] where Example: IO_L22N L = LVDS or LVPECL pin # = Pin Pair Number P = Positive N = Negative IO_L#[P/N]_Y I/O pins for differential signals can either be synchronous or asynchronous, input or output. The pin pairs can be used for synchronous input and output signals as well as asynchronous input signals. However, only some of the low-voltage pairs can be used for asynchronous output signals. DIfferential signals require the pins of a pair to switch almost simultaneously. If the signals driving the pins are from IOB flip-flops, they are synchronous. If the signals driving the pins are from internal logic, they are asynchronous. Table 1 defines the names and function of the different types of low-voltage pin pairs in the Virtex-E family. IO_L#[P/N]_YY Example: O_L22N_YY IO_LVDS_DLL_L#[P/N] Example: Virtex-E Package Pinouts The QPro Virtex-E family of FPGAs is available in three popular packages, including plastic ball grid, fine-pitch plastic ball grid, and hermetic ceramic column grid arrays. Family members have footprint compatibility across devices provided in the same package. The pinout tables in this section indicate function, pin, and bank information for each package/device combination. Following each pinout table is Module 4 of 4 2 Example: IO_L22N_Y IO_LVDS_DLL_L16N www.xilinx.com 1-800-255-7778 Description Represents a general IO or a synchronous input/output differential signal. When used as a differential signal, N means Negative I/O and P means Positive I/O. Represents a general IO or a synchronous input/output differential signal, or a part-dependent asynchronous output differential signal. Represents a general IO or a synchronous input/output differential signal, or an asynchronous output differential signal. Represents a general IO or a synchronous input/output differential signal, a differential clock input signal, or a DLL input. When used as a differential clock input, this pin is paired with the adjacent GCK pin. The GCK pin is always the positive input in the differential clock input configuration. DS096-4 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs BG432 Ball Grid Array Packages Table 2: BG432 -- XQV600E XQV600E devices are available in the BG432 Ball Grid Array package and supports output banking. See Table 2 for pinout information. Immediately following Table 2, see Table 3 for Differential Pair information. Table 2: BG432 -- XQV600E Bank Pin Description Pin # 0 IO_VREF_L13N_YY B19 0 IO_L13P_YY A19 0 IO_L14N_Y B18 Bank Pin Description Pin # 0 IO_L14P_Y D18 0 GCK3 D17 0 IO_VREF_L15N_Y C18 0 IO A22 0 IO_L15P_Y B17 0 IO A26 0 IO_LVDS_DLL_L16N C17 0 IO B20 0 IO C23 1 GCK2 A16 0 IO C28 1 IO A12 0 IO_L0N_Y B29 1 IO B9 0 IO_L0P_Y D27 1 IO B11 0 IO_L1N_YY B28 1 IO C16 0 IO_L1P_YY C27 1 IO D9 0 IO_VREF_L2N_YY D26 1 IO_LVDS_DLL_L16P B16 0 IO_L2P_YY A28 1 IO_L17N_Y A15 0 IO_L3N_Y B27 1 IO_VREF_L17P_Y B15 0 IO_L3P_Y C26 1 IO_L18N_Y C15 0 IO_L4N_YY D25 1 IO_L18P_Y D15 0 IO_L4P_YY A27 1 IO_L19N_YY B14 0 IO_VREF_L5N_YY D24 1 IO_VREF_L19P_YY A13 0 IO_L5P_YY C25 1 IO_L20N_YY B13 0 IO_L6N_Y B25 1 IO_L20P_YY D14 0 IO_L6P_Y D23 1 IO_L21N_YY C13 0 IO_VREF_L7N_Y C24 1 IO_L21P_YY B12 0 IO_L7P_Y B24 1 IO_L22N_YY D13 0 IO_VREF_L8N_YY D22 1 IO_L22P_YY C12 0 IO_L8P_YY A24 1 IO_L23N_YY D12 0 IO_L9N_YY C22 1 IO_L23P_YY C11 0 IO_L9P_YY B22 1 IO_L24N_YY B10 0 IO_L10N_YY C21 1 IO_VREF_L24P_YY C10 0 IO_L10P_YY D20 1 IO_L25N_Y C9 0 IO_L11N_YY B21 1 IO_VREF_L25P_Y D10 0 IO_L11P_YY C20 1 IO_L26N_Y A8 0 IO_L12N_YY A20 1 IO_L26P_Y B8 0 IO_L12P_YY D19 1 IO_L27N_YY C8 DS096-4 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 3 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 2: BG432 -- XQV600E Table 2: BG432 -- XQV600E Bank Pin Description Pin # Bank Pin Description Pin # 1 IO_VREF_L27P_YY B7 2 IO_L42N_Y J4 1 IO_L28N_YY D8 2 IO_VREF_L43P_YY J2 1 IO_L28P_YY A6 2 IO_D1_L43N_YY K4 1 IO_L29N_Y B6 2 IO_D2_L44P_YY K2 1 IO_L29P_Y D7 2 IO_L44N_YY K1 1 IO_L30N_YY A5 2 IO_L45P_Y L2 1 IO_VREF_L30P_YY C6 2 IO_L45N_Y M4 1 IO_L31N_YY B5 2 IO_L46P_Y M3 1 IO_L31P_YY D6 2 IO_L46N_Y M2 1 IO_L32N_Y A4 2 IO_L47P_Y N4 1 IO_L32P_Y C5 2 IO_L47N_Y N3 1 IO_WRITE_L33N_YY B4 2 IO_VREF_L48P_YY N1 1 IO_CS_L33P_YY D5 2 IO_D3_L48N_YY P4 2 IO_L49P_Y P3 2 IO H4 2 IO_L49N_Y P2 2 IO J3 2 IO_VREF_L50P_Y R3 2 IO L3 2 IO_L50N_Y R4 2 IO M1 2 IO_L51P_YY R1 2 IO R2 2 IO_L51N_YY T3 2 IO_DOUT_BUSY_L34P_YY D3 2 IO_DIN_D0_L34N_YY C2 3 IO AA2 2 IO_L35P D2 3 IO AC2 2 IO_L35N E4 3 IO AE2 2 IO_L36P_Y D1 3 IO U3 2 IO_L36N_Y E3 3 IO W1 2 IO_VREF_L37P_Y E2 3 IO_L52P_Y U4 2 IO_L37N_Y F4 3 IO_VREF_L52N_Y U22 2 IO_L38P E1 3 IO_L53P_Y U1 2 IO_L38N F3 3 IO_L53N_Y V3 2 IO_L39P_Y F2 3 IO_D4_L54P_YY V4 2 IO_L39N_Y G4 3 IO_VREF_L54N_YY V2 2 IO_VREF_L40P_YY G3 3 IO_L55P_Y W3 2 IO_L40N_YY G2 3 IO_L55N_Y W4 2 IO_L41P_Y H3 3 IO_L56P_Y Y1 2 IO_L41N_Y H2 3 IO_L56N_Y Y3 2 IO_VREF_L42P_Y H1 3 IO_L57P_Y Y4 Module 4 of 4 4 www.xilinx.com 1-800-255-7778 DS096-4 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 2: BG432 -- XQV600E Table 2: BG432 -- XQV600E Bank Pin Description Pin # Bank Pin Description Pin # 3 IO_L57N_Y Y2 4 IO_L71N_YY AH6 3 IO_L58P_YY AA3 4 IO_VREF_L72P_YY AL4 3 IO_D5_L58N_YY AB1 4 IO_L72N_YY AK5 3 IO_D6_L59P_YY AB3 4 IO_L73P_Y AJ6 3 IO_VREF_L59N_YY AB4 4 IO_L73N_Y AH7 3 IO_L60P_Y AD1 4 IO_L74P_YY AL5 3 IO_VREF_L60N_Y AC3 4 IO_L74N_YY AK6 3 IO_L61P_Y AC4 4 IO_VREF_L75P_YY AJ7 3 IO_L61N_Y AD2 4 IO_L75N_YY AL6 3 IO_L62P_YY AD3 4 IO_L76P_Y AH9 3 IO_VREF_L62N_YY AD4 4 IO_L76N_Y AJ8 3 IO_L63P_Y AF2 4 IO_VREF_L77P_Y AK81 3 IO_L63N_Y AE3 4 IO_L77N_Y AJ9 3 IO_L64P AE4 4 IO_VREF_L78P_YY AL8 3 IO_L64N AG1 4 IO_L78N_YY AK9 3 IO_L65P_Y AG2 4 IO_L79P_YY AK10 3 IO_VREF_L65N_Y AF3 4 IO_L79N_YY AL10 3 IO_L66P_Y AF4 4 IO_L80P_YY AH12 3 IO_L66N_Y AH1 4 IO_L80N_YY AK11 3 IO_L67P AH2 4 IO_L81P_YY AJ12 3 IO_L67N AG3 4 IO_L81N_YY AK12 3 IO_D7_L68P_YY AG4 4 IO_L82P_YY AH13 3 IO_INIT_L68N_YY AJ2 4 IO_L82N_YY AJ13 3 IO T2 4 IO_VREF_L83P_YY AL13 4 IO_L83N_YY AK14 4 GCK0 AL16 4 IO_L84P_Y AH14 4 IO AH10 4 IO_L84N_Y AJ14 4 IO AJ11 4 IO_VREF_L85P_Y AK152 4 IO AK7 4 IO_L85N_Y AJ15 4 IO AL12 4 IO_LVDS_DLL_L86P AH15 4 IO AL15 4 IO_L69P_YY AJ4 5 GCK1 AK16 4 IO_L69N_YY AK3 5 IO AH20 4 IO_L70P_Y AH5 5 IO AJ19 4 IO_L70N_Y AK4 5 IO AJ23 4 IO_L71P_YY AJ5 5 IO AJ24 DS096-4 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 5 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 2: BG432 -- XQV600E Table 2: BG432 -- XQV600E Bank Pin Description Pin # Bank Pin Description Pin # 5 IO_LVDS_DLL_L86N AL17 6 IO AD29 5 IO_L87P_Y AK17 6 IO U31 5 IO_VREF_L87N_Y AJ172 6 IO W28 5 IO_L88P_Y AH17 6 IO_L103N_YY AJ30 5 IO_L88N_Y AK18 6 IO_L103P_YY AH30 5 IO_L89P_YY AL19 6 IO_L104N AG28 5 IO_VREF_L89N_YY AJ18 6 IO_L104P AH31 5 IO_L90P_YY AH18 6 IO_L105N_Y AG29 5 IO_L90N_YY AL20 6 IO_L105P_Y AG30 5 IO_L91P_YY AK20 6 IO_VREF_L106N_Y AF28 5 IO_L91N_YY AH19 6 IO_L106P_Y AG31 5 IO_L92P_YY AJ20 6 IO_L107N AF29 5 IO_L92N_YY AK21 6 IO_L107P AF30 5 IO_L93P_YY AJ21 6 IO_L108N_Y AE28 5 IO_L93N_YY AL22 6 IO_L108P_Y AF31 5 IO_L94P_YY AJ22 6 IO_VREF_L109N_YY AE30 5 IO_VREF_L94N_YY AK23 6 IO_L109P_YY AD28 5 IO_L95P_Y AH22 6 IO_L110N_Y AD30 5 IO_VREF_L95N_Y AL241 6 IO_L110P_Y AD31 5 IO_L96P_Y AK24 6 IO_VREF_L111N_Y AC281 5 IO_L96N_Y AH23 6 IO_L111P_Y AC29 5 IO_L97P_YY AK25 6 IO_VREF_L112N_YY AB28 5 IO_VREF_L97N_YY AJ25 6 IO_L112P_YY AB29 5 IO_L98P_YY AL26 6 IO_L113N_YY AB31 5 IO_L98N_YY AK26 6 IO_L113P_YY AA29 5 IO_L99P_Y AH25 6 IO_L114N_Y Y28 5 IO_L99N_Y AL27 6 IO_L114P_Y Y29 5 IO_L100P_YY AJ26 6 IO_L115N_Y Y30 5 IO_VREF_L100N_YY AK27 6 IO_L115P_Y Y31 5 IO_L101P_YY AH26 6 IO_L116N_Y W29 5 IO_L101N_YY AL28 6 IO_L116P_Y W30 5 IO_L102P_Y AJ27 6 IO_VREF_L117N_YY V28 5 IO_L102N_Y AK28 6 IO_L117P_YY V29 6 IO_L118N_Y V30 6 IO AA30 6 IO_L118P_Y U29 6 IO AC30 6 IO_VREF_L119N_Y U28 Module 4 of 4 6 www.xilinx.com 1-800-255-7778 DS096-4 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 2: BG432 -- XQV600E Table 2: BG432 -- XQV600E Bank Pin Description Pin # Bank Pin Description Pin # 6 IO_L119P_Y U30 7 IO_L133P E30 6 IO T30 7 IO_L134N_Y F29 7 IO_VREF_L134P_Y F28 7 IO C30 7 IO_L135N_Y D31 7 IO H29 7 IO_L135P_Y D30 7 IO H31 7 IO_L136N E29 7 IO L29 7 IO_L136P E28 7 IO M31 7 IO R28 2 CCLK D4 7 IO_L120N_YY T31 3 DONE AH4 7 IO_L120P_YY R29 NA DXN AH27 7 IO_L121N_Y R30 NA DXP AK29 7 IO_VREF_L121P_Y R31 NA M0 AH28 7 IO_L122N_Y P29 NA M1 AH29 7 IO_L122P_Y P28 NA M2 AJ28 7 IO_L123N_YY P30 NA PROGRAM AH3 7 IO_VREF_L123P_YY N30 NA TCK D28 7 IO_L124N_Y N28 NA TDI B3 7 IO_L124P_Y N31 2 TDO C4 7 IO_L125N_Y M29 NA TMS D29 7 IO_L125P_Y M28 7 IO_L126N_Y M30 NA VCCINT A10 7 IO_L126P_Y L30 NA VCCINT A17 7 IO_L127N_YY K31 NA VCCINT B23 7 IO_L127P_YY K30 NA VCCINT B26 7 IO_L128N_YY K28 NA VCCINT C7 7 IO_VREF_L128P_YY J30 NA VCCINT C14 7 IO_L129N_Y J29 NA VCCINT C19 7 IO_VREF_L129P_Y J281 NA VCCINT F1 7 IO_L130N_Y H30 NA VCCINT F30 7 IO_L130P_Y G30 NA VCCINT K3 7 IO_L131N_YY H28 NA VCCINT K29 7 IO_VREF_L131P_YY F31 NA VCCINT N2 7 IO_L132N_Y G29 NA VCCINT N29 7 IO_L132P_Y G28 NA VCCINT T1 7 IO_L133N E31 NA VCCINT T29 DS096-4 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 7 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 2: BG432 -- XQV600E Table 2: BG432 -- XQV600E Bank Pin Description Pin # Bank Pin Description Pin # NA VCCINT W2 7 VCCO L28 NA VCCINT W31 7 VCCO L31 NA VCCINT AB2 NA VCCINT AB30 NA GND A2 NA VCCINT AE29 NA GND A3 NA VCCINT AF1 NA GND A7 NA VCCINT AH8 NA GND A9 NA VCCINT AH24 NA GND A14 NA VCCINT AJ10 NA GND A18 NA VCCINT AJ16 NA GND A23 NA VCCINT AK22 NA GND A25 NA VCCINT AK13 NA GND A29 NA VCCINT AK19 NA GND A30 NA GND B1 0 VCCO A21 NA GND B2 0 VCCO C29 NA GND B30 0 VCCO D21 NA GND B31 1 VCCO A1 NA GND C1 1 VCCO A11 NA GND C31 1 VCCO D11 NA GND D16 2 VCCO C3 NA GND G1 2 VCCO L4 NA GND G31 2 VCCO L1 NA GND J1 3 VCCO AA1 NA GND J31 3 VCCO AA4 NA GND P1 3 VCCO AJ3 NA GND P31 4 VCCO AH11 NA GND T4 4 VCCO AL1 NA GND T28 4 VCCO AL11 NA GND V1 5 VCCO AH21 NA GND V31 5 VCCO AL21 NA GND AC1 5 VCCO AJ29 NA GND AC31 6 VCCO AA28 NA GND AE1 6 VCCO AA31 NA GND AE31 6 VCCO AL31 NA GND AH16 7 VCCO A31 NA GND AJ1 Module 4 of 4 8 www.xilinx.com 1-800-255-7778 DS096-4 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 2: BG432 -- XQV600E Bank Pin Description Pin # NA GND AJ31 NA GND AK1 NA GND AK2 NA GND AK30 NA GND AK31 NA GND NA Table 3: BG432 Differential Pin Pair Summary XQV600E Pair Bank P N Pin Pin AO Other Functions 3 0 C26 B27 NA - 4 0 A27 D25 - 5 0 C25 D24 VREF AL2 6 0 D23 B25 - GND AL3 7 0 B24 C24 VREF NA GND AL7 8 0 A24 D22 VREF NA GND AL9 9 0 B22 C22 - NA GND AL14 10 0 D20 C21 - NA GND AL18 11 0 C20 B21 - NA GND AL23 12 0 D19 A20 - NA GND AL25 13 0 A19 B19 VREF NA GND AL29 14 0 D18 B18 - NA GND AL30 15 0 B17 C18 VREF BG432 Differential Pin Pairs 16 1 B16 C17 NA IO_LVDS_DLL Virtex-E devices have differential pin pairs that can also Virtex-E devices have differential pin pairs that can also provide other functions when not used as a differential pair. A in the AO column indicates that the pin pair can be used as an asynchronous output. The Other Functions column indicates alternative function(s) not available when the pair is used as a differential pair or differential clock. 17 1 B15 A15 VREF 18 1 D15 C15 - 19 1 A13 B14 VREF 20 1 D14 B13 - 21 1 B12 C13 - 22 1 C12 D13 - 23 1 C11 D12 - 24 1 C10 B10 VREF 25 1 D10 C9 VREF 26 1 B8 A8 - 27 1 B7 C8 VREF 28 1 A6 D8 - 29 1 D7 B6 NA - 30 1 C6 A5 VREF 31 1 D6 B5 - 32 1 C5 A4 - 33 1 D5 B4 CS, WRITE 34 2 D3 C2 DIN, D0, BUSY Table 3: BG432 Differential Pin Pair Summary XQV600E Pair Bank P N Pin Pin AO Other Functions Global Differential Clock 0 4 AL16 AH15 NA IO_DLL_L86P 1 5 AK16 AL17 NA IO_DLL_L86N 2 1 A16 B16 NA IO_DLL_L16P 3 0 D17 C17 NA IO_DLL_L16N IO LVDS Total Outputs: 137, Asynchronous Output Pairs: 63 0 0 D27 B29 - 1 0 C27 B28 - 2 0 A28 D26 VREF DS096-4 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 9 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 3: BG432 Differential Pin Pair Summary XQV600E Pair Bank P N Pin Pin AO Table 3: BG432 Differential Pin Pair Summary XQV600E Other Pair Bank Functions P N Pin Pin AO Other Functions 35 2 D2 E4 - 67 3 AH2 AG3 - 36 2 D1 E3 NA - 68 3 AG4 AJ2 INIT 37 2 E2 F4 VREF 69 4 AJ4 AK3 - 38 2 E1 F3 - 70 4 AH5 AK4 - 39 2 F2 G4 - 71 4 AJ5 AH6 - 40 2 G3 G2 VREF 72 4 AL4 AK5 VREF 41 2 H3 H2 NA - 73 4 AJ6 AH7 NA - 42 2 H1 J4 VREF 74 4 AL5 AK6 - 43 2 J2 K4 D1 75 4 AJ7 AL6 VREF 44 2 K2 K1 D2 76 4 AH9 AJ8 - 45 2 L2 M4 4 - 77 4 AK8 AJ9 VREF 46 2 M3 M2 - 78 4 AL8 AK9 VREF 47 2 N4 N3 - 79 4 AK10 AL10 - 48 2 N1 P4 D3 80 4 AH12 AK11 - 49 2 P3 P2 NA - 81 4 AJ12 AK12 - 50 2 R3 R4 VREF 82 4 AH13 AJ13 - 51 2 R1 T3 - 83 4 AL13 AK14 VREF 52 3 U4 U2 VREF 84 4 AH14 AJ14 - 53 3 U1 V3 NA - 85 4 AK15 AJ15 VREF 54 3 V4 V2 VREF 86 5 AH15 AL17 NA IO_LVDS_DLL 55 3 W3 W4 - 87 5 AK17 AJ17 VREF 56 3 Y1 Y3 - 88 5 AH17 AK18 - 57 3 Y4 Y2 NA - 89 5 AL19 AJ18 VREF 58 3 AA3 AB1 D5 90 5 AH18 AL20 - 59 3 AB3 AB4 VREF 91 5 AK20 AH19 - 60 3 AD1 AC3 VREF 92 5 AJ20 AK21 - 61 3 AC4 AD2 NA - 93 5 AJ21 AL22 - 62 3 AD3 AD4 VREF 94 5 AJ22 AK23 VREF 63 3 AF2 AE3 - 95 5 AH22 AL24 VREF 64 3 AE4 AG1 - 96 5 AK24 AH23 - 65 3 AG2 AF3 VREF 97 5 AK25 AJ25 VREF 66 3 AF4 AH1 NA - 98 5 AL26 AK26 - Module 4 of 4 10 www.xilinx.com 1-800-255-7778 DS096-4 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 3: BG432 Differential Pin Pair Summary XQV600E Pair Bank P N Pin Pin AO Table 3: BG432 Differential Pin Pair Summary XQV600E Other Pair Bank Functions P N Pin Pin AO Other Functions 99 5 AH25 AL27 NA - 131 7 F31 H28 VREF 100 5 AJ26 AK27 VREF 132 7 G28 G29 - 101 5 AH26 AL28 - 133 7 E30 E31 - 102 5 AJ27 AK28 - 134 7 F28 F29 VREF 103 6 AH30 AJ30 - 135 7 D30 D31 NA - 104 6 AH31 AG28 - 136 7 E28 E29 - 105 6 AG30 AG29 NA - 106 6 AG31 AF28 VREF 107 6 AF30 AF29 - 108 6 AF31 AE28 - 109 6 AD28 AE30 VREF 110 6 AD31 AD30 NA - 111 6 AC29 AC28 VREF 112 6 AB29 AB28 VREF 113 6 AA29 AB31 - 114 6 Y29 Y28 NA - 115 6 Y31 Y30 - 116 6 W30 W29 - 117 6 V29 V28 VREF 118 6 U29 V30 NA - 119 6 U30 U28 VREF 120 7 R29 T31 - 121 7 R31 R30 VREF 122 7 P28 P29 NA - 123 7 N30 P30 VREF 124 7 N31 N28 - 125 7 M28 M29 - 126 7 L30 M30 NA - 127 7 K30 K31 - 128 7 J30 K28 VREF 129 7 J28 J29 VREF 130 7 G30 H30 NA - DS096-4 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 11 R QPro Virtex-E 1.8V QML High-Reliability FPGAs BG560 Plastic Ball Grid and CG560 Ceramic Column Grid Array Packages XQV1000E is the only Virtex-E device available in the CG560 Hermetic Ceramic Column Grid Array package. XQV1000E and XQV2000E devices are both available in BG560 Ball Grid Array packages and have footprint compatibility. Pins labeled I0_VREF can be used as either in all parts unless device-dependent as indicated in the footnotes. If the pin is not used as VREF, it can be used as general I/O. Immediately following Table 4, see Table 5 for Differential Pair information. Table 4: BG560/CG560 -- XQV1000E, XQV2000E Bank Pin Description Pin# 0 GCK3 A17 0 IO A27 0 IO B25 0 IO C28 0 IO C30 0 IO D30 0 IO_L0N E28 0 IO_VREF_L0P D29 0 IO_L1N_YY D28 0 IO_L1P_YY A31 0 IO_VREF_L2N_YY E27 0 IO_L2P_YY C29 0 IO_L3N_Y B30 0 IO_L3P_Y D27 0 IO_L4N_YY E26 0 IO_L4P_YY B29 0 IO_VREF_L5N_YY D26 0 IO_L5P_YY C27 0 IO_L6N_Y E25 0 IO_VREF_L6P_Y A28 0 IO_L7N_Y D25 0 IO_L7P_Y C26 0 IO_VREF_L8N_Y E24 0 IO_L8P_Y B26 0 IO_L9N_Y C25 0 IO_L9P_Y D24 0 IO_VREF_L10N_YY E23 Module 4 of 4 12 See Note 1 Table 4: BG560/CG560 -- XQV1000E, XQV2000E Bank Pin Description Pin# 0 IO_L10P_YY A25 0 IO_L11N_YY D23 0 IO_L11P_YY B24 0 IO_L12N_Y E22 0 IO_L12P_Y C23 0 IO_L13N_YY A23 0 IO_L13P_YY D22 0 IO_VREF_L14N_YY E21 0 IO_L14P_YY B22 0 IO_L15N_Y D21 0 IO_L15P_Y C21 0 IO_L16N_YY B21 0 IO_L16P_YY E20 0 IO_VREF_L17N_YY D20 0 IO_L17P_YY C20 0 IO_L18N_Y B20 0 IO_L18P_Y E19 0 IO_L19N_Y D19 0 IO_L19P_Y C19 0 IO_VREF_L20N_Y A19 0 IO_L20P_Y D18 0 IO_LVDS_DLL_L21N C18 0 IO_VREF E18 1 GCK2 D17 1 IO A3 1 IO D9 1 IO E8 1 IO E11 1 IO_LVDS_DLL_L21P E17 1 IO_VREF_L22N_Y C17 1 IO_L22P_Y B17 1 IO_L23N_Y B16 1 IO_VREF_L23P_Y D16 1 IO_L24N_Y E16 1 IO_L24P_Y C16 www.xilinx.com 1-800-255-7778 See Note 1 1 DS096-4 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 4: BG560/CG560 -- XQV1000E, XQV2000E Bank Pin Description Pin# 1 IO_L25N_Y 1 Table 4: BG560/CG560 -- XQV1000E, XQV2000E Bank Pin Description Pin# A15 1 IO_L43N_Y C5 IO_L25P_Y C15 1 IO_VREF_L43P_Y E7 1 IO_L26N_YY D15 1 IO_WRITE_L44N_YY D6 1 IO_VREF_L26P_YY E15 1 IO_CS_L44P_YY A2 1 IO_L27N_YY C14 1 IO_L27P_YY D14 2 IO D3 1 IO_L28N_Y A13 2 IO F3 1 IO_L28P_Y E14 2 IO G1 1 IO_L29N_YY C13 2 IO J2 1 IO_VREF_L29P_YY D13 2 IO_DOUT_BUSY_L45P_YY D4 1 IO_L30N_YY C12 2 IO_DIN_D0_L45N_YY E4 1 IO_L30P_YY E13 2 IO_L46P_Y F5 1 IO_L31N_Y A11 2 IO_VREF_L46N_Y B3 1 IO_L31P_Y D12 2 IO_L47P_Y F4 1 IO_L32N_YY B11 2 IO_L47N_Y C1 1 IO_L32P_YY C11 2 IO_VREF_L48P_Y G5 1 IO_L33N_YY B10 2 IO_L48N_Y E3 1 IO_VREF_L33P_YY D11 2 IO_L49P_Y D2 1 IO_L34N_Y C10 2 IO_L49N_Y G4 1 IO_L34P_Y A9 2 IO_L50P_Y H5 1 IO_L35N_Y C9 2 IO_L50N_Y E2 1 IO_VREF_L35P_Y D10 2 IO_VREF_L51P_YY H4 1 IO_L36N_Y A8 2 IO_L51N_YY G3 1 IO_L36P_Y B8 2 IO_L52P_Y J5 1 IO_L37N_Y E10 2 IO_VREF_L52N_Y F1 1 IO_VREF_L37P_Y C8 2 IO_L53P_Y J4 1 IO_L38N_YY B7 2 IO_L53N_Y H3 1 IO_VREF_L38P_YY A6 2 IO_VREF_L54P_Y K5 1 IO_L39N_YY C7 2 IO_L54N_Y H2 1 IO_L39P_YY D8 2 IO_L55P_Y J3 1 IO_L40N_Y A5 2 IO_L55N_Y K4 1 IO_L40P_Y B5 2 IO_VREF_L56P_YY L5 1 IO_L41N_YY C6 2 IO_D1_L56N_YY K3 1 IO_VREF_L41P_YY D7 2 IO_D2_L57P_YY L4 1 IO_L42N_YY A4 2 IO_L57N_YY K2 1 IO_L42P_YY B4 2 IO_L58P_Y M5 DS096-4 (v1.1) July 29, 2004 Advance Product Specification See Note 1 www.xilinx.com 1-800-255-7778 See Note 1 Module 4 of 4 13 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 4: BG560/CG560 -- XQV1000E, XQV2000E Table 4: BG560/CG560 -- XQV1000E, XQV2000E Bank Pin Description Pin# 2 IO_L58N_Y 2 See Note Bank Pin Description Pin# L3 3 IO_L74P_Y Y3 IO_L59P_Y L1 3 IO_L74N_Y Y4 2 IO_L59N_Y M4 3 IO_L75P_Y AA1 2 IO_VREF_L60P_Y N5 3 IO_L75N_Y Y5 2 IO_L60N_Y M2 3 IO_L76P_Y AA3 2 IO_L61P_Y N4 3 IO_VREF_L76N_Y AA4 2 IO_L61N_Y N3 3 IO_L77P_Y AB3 2 IO_L62P_Y N2 3 IO_L77N_Y AA5 2 IO_L62N_Y P5 3 IO_L78P_Y AC1 2 IO_VREF_L63P_YY P4 3 IO_L78N_Y AB4 2 IO_D3_L63N_YY P3 3 IO_L79P_YY AC3 2 IO_L64P_Y P2 3 IO_D5_L79N_YY AB5 2 IO_L64N_Y R5 3 IO_D6_L80P_YY AC4 2 IO_L65P_Y R4 3 IO_VREF_L80N_YY AD3 2 IO_L65N_Y R3 3 IO_L81P_Y AE1 2 IO_VREF_L66P_Y R1 3 IO_L81N_Y AC5 2 IO_L66N_Y T4 3 IO_L82P_Y AD4 2 IO_L67P_Y T5 3 IO_VREF_L82N_Y AF1 2 IO_VREF_L67N_Y T3 3 IO_L83P_Y AF2 2 IO_L68P_YY T2 3 IO_L83N_Y AD5 2 IO_L68N_YY U3 3 IO_L84P_Y AG2 3 IO_VREF_L84N_Y AE4 1 3 IO AE3 3 IO_L85P_YY AH1 3 IO AF3 3 IO_VREF_L85N_YY AE5 3 IO AH3 3 IO_L86P_Y AF4 3 IO AK3 3 IO_L86N_Y AJ1 3 IO_VREF_L69P_Y U1 3 IO_L87P_Y AJ2 3 IO_L69N_Y U2 3 IO_L87N_Y AF5 3 IO_L70P_Y V2 3 IO_L88P_Y AG4 3 IO_VREF_L70N_Y V4 3 IO_VREF_L88N_Y AK2 3 IO_L71P_Y V5 3 IO_L89P_Y AJ3 3 IO_L71N_Y V3 3 IO_L89N_Y AG5 3 IO_L72P_Y W1 3 IO_L90P_Y AL1 3 IO_L72N_Y W3 3 IO_VREF_L90N_Y AH4 3 IO_D4_L73P_YY W4 3 IO_D7_L91P_YY AJ4 3 IO_VREF_L73N_YY W5 3 IO_INIT_L91N_YY AH5 Module 4 of 4 14 1 www.xilinx.com 1-800-255-7778 See Note 1 DS096-4 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 4: BG560/CG560 -- XQV1000E, XQV2000E Bank Pin Description Pin# 3 IO U4 Table 4: BG560/CG560 -- XQV1000E, XQV2000E See Note Bank Pin Description Pin# 4 IO_L106N_YY AM12 4 IO_VREF_L107P_YY AK13 4 GCK0 AL17 4 IO_L107N_YY AL13 4 IO AJ8 4 IO_L108P_Y AM13 4 IO AJ11 4 IO_L108N_Y AN13 4 IO AK6 4 IO_L109P_YY AJ14 4 IO AK9 4 IO_L109N_YY AK14 4 IO_L92P_YY AL4 4 IO_VREF_L110P_YY AM14 4 IO_L92N_YY AJ6 4 IO_L110N_YY AN15 4 IO_L93P_Y AK5 4 IO_L111P_Y AJ15 4 IO_VREF_L93N_Y AN3 4 IO_L111N_Y AK15 4 IO_L94P_YY AL5 4 IO_L112P_Y AL15 4 IO_L94N_YY AJ7 4 IO_L112N_Y AM16 4 IO_VREF_L95P_YY AM4 4 IO_VREF_L113P_Y AL16 4 IO_L95N_YY AM5 4 IO_L113N_Y AJ16 4 IO_L96P_Y AK7 4 IO_L114P_Y AK16 4 IO_L96N_Y AL6 4 IO_VREF_L114N_Y AN17 4 IO_L97P_YY AM6 4 IO_LVDS_DLL_L115P AM17 4 IO_L97N_YY AN6 4 IO_VREF_L98P_YY AL7 5 GCK1 AJ17 4 IO_L98N_YY AJ9 5 IO AL25 4 IO_L99P_Y AN7 5 IO AL28 4 IO_VREF_L99N_Y AL8 5 IO AL30 4 IO_L100P_Y AM8 5 IO AN28 4 IO_L100N_Y AJ10 5 IO_LVDS_DLL_L115N AM18 4 IO_VREF_L101P_Y AL9 5 IO_VREF AL18 4 IO_L101N_Y AM9 5 IO_L116P_Y AK18 4 IO_L102P_Y AK10 5 IO_VREF_L116N_Y AJ18 4 IO_L102N_Y AN9 5 IO_L117P_Y AN19 4 IO_VREF_L103P_YY AL10 5 IO_L117N_Y AL19 4 IO_L103N_YY AM10 5 IO_L118P_Y AK19 4 IO_L104P_YY AL11 5 IO_L118N_Y AM20 4 IO_L104N_YY AJ12 5 IO_L119P_YY AJ19 4 IO_L105P_Y AN11 5 IO_VREF_L119N_YY AL20 4 IO_L105N_Y AK12 5 IO_L120P_YY AN21 4 IO_L106P_YY AL12 5 IO_L120N_YY AL21 DS096-4 (v1.1) July 29, 2004 Advance Product Specification 1 www.xilinx.com 1-800-255-7778 See Note 1 1 Module 4 of 4 15 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 4: BG560/CG560 -- XQV1000E, XQV2000E Table 4: BG560/CG560 -- XQV1000E, XQV2000E Bank Pin Description Pin# 5 IO_L121P_Y 5 See Note Bank Pin Description Pin# AJ20 6 IO AL33 IO_L121N_Y AM22 6 IO_L137N_YY AH29 5 IO_L122P_YY AK21 6 IO_L137P_YY AJ30 5 IO_VREF_L122N_YY AN23 6 IO_L138N_Y AK31 5 IO_L123P_YY AJ21 6 IO_VREF_L138P_Y AH30 5 IO_L123N_YY AM23 6 IO_L139N_Y AG29 5 IO_L124P_Y AK22 6 IO_L139P_Y AJ31 5 IO_L124N_Y AM24 6 IO_VREF_L140N_Y AK32 5 IO_L125P_YY AL23 6 IO_L140P_Y AG30 5 IO_L125N_YY AJ22 6 IO_L141N_Y AH31 5 IO_L126P_YY AK23 6 IO_L141P_Y AF29 5 IO_VREF_L126N_YY AL24 6 IO_L142N_Y AH32 5 IO_L127P_Y AN26 6 IO_L142P_Y AF30 5 IO_L127N_Y AJ23 6 IO_VREF_L143N_YY AE29 5 IO_L128P_Y AK24 6 IO_L143P_YY AH33 5 IO_VREF_L128N_Y AM26 6 IO_L144N_Y AG33 5 IO_L129P_Y AM27 6 IO_VREF_L144P_Y AE30 5 IO_L129N_Y AJ24 6 IO_L145N_Y AD29 5 IO_L130P_Y AL26 6 IO_L145P_Y AF32 5 IO_VREF_L130N_Y AK25 6 IO_VREF_L146N_Y AE31 5 IO_L131P_YY AN29 6 IO_L146P_Y AD30 5 IO_VREF_L131N_YY AJ25 6 IO_L147N_Y AE32 5 IO_L132P_YY AK26 6 IO_L147P_Y AC29 5 IO_L132N_YY AM29 6 IO_VREF_L148N_YY AD31 5 IO_L133P_Y AM30 6 IO_L148P_YY AC30 5 IO_L133N_Y AJ26 6 IO_L149N_YY AB29 5 IO_L134P_YY AK27 6 IO_L149P_YY AC31 5 IO_VREF_L134N_YY AL29 6 IO_L150N_Y AC33 5 IO_L135P_YY AN31 6 IO_L150P_Y AB30 5 IO_L135N_YY AJ27 6 IO_L151N_Y AB31 5 IO_L136P_Y AM31 6 IO_L151P_Y AA29 5 IO_VREF_L136N_Y AK28 6 IO_VREF_L152N_Y AA30 6 IO_L152P_Y AA31 1 6 IO AE33 6 IO_L153N_Y AA32 6 IO AF31 6 IO_L153P_Y Y29 6 IO AJ32 6 IO_L154N_Y AA33 Module 4 of 4 16 www.xilinx.com 1-800-255-7778 See Note 1 DS096-4 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 4: BG560/CG560 -- XQV1000E, XQV2000E Bank Pin Description Pin# 6 IO_L154P_Y 6 Table 4: BG560/CG560 -- XQV1000E, XQV2000E See Note Bank Pin Description Pin# Y30 7 IO_L169N_Y M31 IO_VREF_L155N_YY Y32 7 IO_L169P_Y L32 6 IO_L155P_YY W29 7 IO_L170N_Y M30 6 IO_L156N_Y W30 7 IO_L170P_Y L31 6 IO_L156P_Y W31 7 IO_L171N_YY M29 6 IO_L157N_Y W33 7 IO_L171P_YY J33 6 IO_L157P_Y V30 7 IO_L172N_YY L30 6 IO_VREF_L158N_Y V29 7 IO_VREF_L172P_YY K31 6 IO_L158P_Y V31 7 IO_L173N_Y L29 6 IO_L159N_Y V32 7 IO_L173P_Y H33 6 IO_VREF_L159P_Y U33 7 IO_L174N_Y J31 6 IO U29 7 IO_VREF_L174P_Y H32 7 IO_L175N_Y K29 1 7 IO E30 7 IO_L175P_Y H31 7 IO F29 7 IO_L176N_Y J30 7 IO F33 7 IO_VREF_L176P_Y G32 7 IO G30 7 IO_L177N_YY J29 7 IO K30 7 IO_VREF_L177P_YY G31 7 IO_L160N_YY U31 7 IO_L178N_Y E33 7 IO_L160P_YY U32 7 IO_L178P_Y E32 7 IO_VREF_L161N_Y T32 7 IO_L179N_Y H29 7 IO_L161P_Y T30 7 IO_L179P_Y F31 7 IO_L162N_Y T29 7 IO_L180N_Y D32 7 IO_VREF_L162P_Y T31 7 IO_VREF_L180P_Y E31 7 IO_L163N_Y R33 7 IO_L181N_Y G29 7 IO_L163P_Y R31 7 IO_L181P_Y C33 7 IO_L164N_Y R30 7 IO_L182N_Y F30 7 IO_L164P_Y R29 7 IO_VREF_L182P_Y D31 7 IO_L165N_YY P32 7 IO_VREF_L165P_YY P31 2 CCLK C4 7 IO_L166N_Y P30 3 DONE AJ5 7 IO_L166P_Y P29 NA DXN AK29 7 IO_L167N_Y M32 NA DXP AJ28 7 IO_L167P_Y N31 NA M0 AJ29 7 IO_L168N_Y N30 NA M1 AK30 7 IO_VREF_L168P_Y L33 NA M2 AN32 DS096-4 (v1.1) July 29, 2004 Advance Product Specification 1 www.xilinx.com 1-800-255-7778 See Note 1 Module 4 of 4 17 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 4: BG560/CG560 -- XQV1000E, XQV2000E Bank Pin Description Pin# NA PROGRAM NA Table 4: BG560/CG560 -- XQV1000E, XQV2000E See Note Bank Pin Description Pin# AM1 NA VCCINT AG3 TCK E29 NA VCCINT AG31 NA TDI D5 NA VCCINT AJ13 2 TDO E6 NA VCCINT AK8 NA TMS B33 NA VCCINT AK11 NA VCCINT AK17 NA NC C31 NA VCCINT AK20 NA NC AC2 NA VCCINT AL14 NA NC AK4 NA VCCINT AL22 NA NC AL3 NA VCCINT AL27 NA VCCINT AN25 NA VCCINT A21 NA VCCINT B12 0 VCCO A22 NA VCCINT B14 0 VCCO A26 NA VCCINT B18 0 VCCO A30 NA VCCINT B28 0 VCCO B19 NA VCCINT C22 0 VCCO B32 NA VCCINT C24 1 VCCO A10 NA VCCINT E9 1 VCCO A16 NA VCCINT E12 1 VCCO B13 NA VCCINT F2 1 VCCO C3 NA VCCINT H30 1 VCCO E5 NA VCCINT J1 2 VCCO B2 NA VCCINT K32 2 VCCO D1 NA VCCINT M3 2 VCCO H1 NA VCCINT N1 2 VCCO M1 NA VCCINT N29 2 VCCO R2 NA VCCINT N33 3 VCCO V1 NA VCCINT U5 3 VCCO AA2 NA VCCINT U30 3 VCCO AD1 NA VCCINT Y2 3 VCCO AK1 NA VCCINT Y31 3 VCCO AL2 NA VCCINT AB2 4 VCCO AN4 NA VCCINT AB32 4 VCCO AN8 NA VCCINT AD2 4 VCCO AN12 NA VCCINT AD32 4 VCCO AM2 Module 4 of 4 18 www.xilinx.com 1-800-255-7778 See Note DS096-4 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 4: BG560/CG560 -- XQV1000E, XQV2000E Table 4: BG560/CG560 -- XQV1000E, XQV2000E Bank Pin Description Pin# 4 VCCO 5 See Note Bank Pin Description Pin# AM15 NA GND F32 VCCO AL31 NA GND G2 5 VCCO AM21 NA GND G33 5 VCCO AN18 NA GND J32 5 VCCO AN24 NA GND K1 5 VCCO AN30 NA GND L2 6 VCCO W32 NA GND M33 6 VCCO AB33 NA GND P1 6 VCCO AF33 NA GND P33 6 VCCO AK33 NA GND R32 6 VCCO AM32 NA GND T1 7 VCCO C32 NA GND V33 7 VCCO D33 NA GND W2 7 VCCO K33 NA GND Y1 7 VCCO N32 NA GND Y33 7 VCCO T33 NA GND AB1 NA GND AC32 NA GND A1 NA GND AD33 NA GND A7 NA GND AE2 NA GND A12 NA GND AG1 NA GND A14 NA GND AG32 NA GND A18 NA GND AH2 NA GND A20 NA GND AJ33 NA GND A24 NA GND AL32 NA GND A29 NA GND AM3 NA GND A32 NA GND AM7 NA GND A33 NA GND AM11 NA GND B1 NA GND AM19 NA GND B6 NA GND AM25 NA GND B9 NA GND AM28 NA GND B15 NA GND AM33 NA GND B23 NA GND AN1 NA GND B27 NA GND AN2 NA GND B31 NA GND AN5 NA GND C2 NA GND AN10 NA GND E1 NA GND AN14 DS096-4 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 See Note Module 4 of 4 19 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 4: BG560/CG560 -- XQV1000E, XQV2000E Bank Pin Description Pin# NA GND AN16 NA GND AN20 NA GND AN22 NA GND NA GND See Note Pin AO Functions 7 0 C26 D25 - AN27 8 0 B26 E24 VREF AN33 9 0 D24 C25 2 - 10 0 A25 E23 VREF 11 0 B24 D23 - 12 0 C23 E22 NA - 13 0 D22 A23 - 14 0 B22 E21 VREF 15 0 C21 D21 2 - 16 0 E20 B21 - 17 0 C20 D20 VREF 18 0 E19 B20 NA - 19 0 C19 D19 - 20 0 D18 A19 VREF 21 1 E17 C18 NA IO_LVDS_DLL 22 1 B17 C17 2 VREF 23 1 D16 B16 VREF 24 1 C16 E16 - 25 1 C15 A15 NA - 26 1 E15 D15 VREF 27 1 D14 C14 - 28 1 E14 A13 2 - 29 1 D13 C13 VREF 30 1 E13 C12 - 31 1 D12 A11 NA - 32 1 C11 B11 - 33 1 D11 B10 VREF 34 1 A9 C10 - 35 1 D10 C9 VREF 36 1 B8 A8 - 37 1 C8 E10 VREF Table 5: BG560/CG560 Differential Pin Pair Summary XQV1000E, XQV2000E Bank Pin Pin Other Pin Virtex-E devices have differential pin pairs that can also provide other functions when not used as a differential pair. A in the AO column indicates that the pin pair can be used as an asynchronous output for all devices provided in this package. Pairs with a note number in the AO column are device dependent. They can have asynchronous outputs if the pin pair are in the same CLB row and column in the device. Numbers in this column refer to footnotes that indicate which devices have pin pairs than can be asynchronous outputs. The Other Functions column indicates alternative function(s) not available when the pair is used as a differential pair or differential clock. Pair N Bank BG560 and CG560 Differential Pin Pairs N P Pair Notes: 1. VREF or I/O option only in the XQV2000E; otherwise, I/O option only. P Table 5: BG560/CG560 Differential Pin Pair Summary XQV1000E, XQV2000E Other AO Functions Global Differential Clock 0 4 AL17 AM17 NA IO_DLL_L15P 1 5 AJ17 AM18 NA IO_DLL_L15N 2 1 D17 E17 NA IO_DLL_L21P 3 0 A17 C18 NA IO_DLL_L21N IO LVDS Total Outputs: 183, Asynchronous Outputs: 87 0 0 D29 E28 NA VREF 1 0 A31 D28 - 2 0 C29 E27 VREF 3 0 D27 B30 2 - 4 0 B29 E26 - 5 0 C27 D26 VREF 6 0 A28 E25 NA VREF Module 4 of 4 20 www.xilinx.com 1-800-255-7778 DS096-4 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 5: BG560/CG560 Differential Pin Pair Summary XQV1000E, XQV2000E P N Table 5: BG560/CG560 Differential Pin Pair Summary XQV1000E, XQV2000E Other P N Other Pair Bank Pin Pin AO Functions Pair Bank Pin Pin AO Functions 38 1 A6 B7 VREF 69 3 U1 U2 2 VREF 39 1 D8 C7 - 70 3 V2 V4 VREF 40 1 B5 A5 1 - 71 3 V5 V3 1 - 41 1 D7 C6 VREF 72 3 W1 W3 2 - 42 1 B4 A4 - 73 3 W4 W5 VREF 43 1 E7 C5 VREF 74 3 Y3 Y4 - 44 1 A2 D6 CS 75 3 AA1 Y5 2 - 45 2 D4 E4 DIN, D0 76 3 AA3 AA4 VREF 46 2 F5 B3 2 VREF 77 3 AB3 AA5 1 - 47 2 F4 C1 1 - 78 3 AC1 AB4 2 - 48 2 G5 E3 VREF 79 3 AC3 AB5 D5 49 2 D2 G4 2 - 80 3 AC4 AD3 VREF 50 2 H5 E2 - 81 3 AE1 AC5 1 - 51 2 H4 G3 VREF 82 3 AD4 AF1 VREF 52 2 J5 F1 2 VREF 83 3 AF2 AD5 1 - 53 2 J4 H3 1 - 84 3 AG2 AE4 1 VREF 54 2 K5 H2 VREF 85 3 AH1 AE5 VREF 55 2 J3 K4 2 - 86 3 AF4 AJ1 - 56 2 L5 K3 D1 87 3 AJ2 AF5 1 - 57 2 L4 K2 D2 88 3 AG4 AK2 VREF 58 2 M5 L3 2 - 89 3 AJ3 AG5 1 - 59 2 L1 M4 1 - 90 3 AL1 AH4 1 VREF 60 2 N5 M2 VREF 91 3 AJ4 AH5 INIT 61 2 N4 N3 2 - 92 4 AL4 AJ6 - 62 2 N2 P5 - 93 4 AK5 AN3 NA VREF 63 2 P4 P3 D3 94 4 AL5 AJ7 - 64 2 P2 R5 2 - 95 4 AM4 AM5 VREF 65 2 R4 R3 1 - 96 4 AK7 AL6 2 - 66 2 R1 T4 VREF 97 4 AM6 AN6 - 67 2 T5 T3 2 VREF 98 4 AL7 AJ9 VREF 68 2 T2 U3 - 99 4 AN7 AL8 NA VREF DS096-4 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 21 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 5: BG560/CG560 Differential Pin Pair Summary XQV1000E, XQV2000E P N Table 5: BG560/CG560 Differential Pin Pair Summary XQV1000E, XQV2000E Other P N Other Pair Bank Pin Pin AO Functions Pair Bank Pin Pin AO Functions 100 4 AM8 AJ10 - 131 5 AN29 AJ25 VREF 101 4 AL9 AM9 VREF 132 5 AK26 AM29 - 102 4 AK10 AN9 2 - 133 5 AM30 AJ26 1 - 103 4 AL10 AM10 VREF 134 5 AK27 AL29 VREF 104 4 AL11 AJ12 - 135 5 AN31 AJ27 - 105 4 AN11 AK12 NA - 136 5 AM31 AK28 VREF 106 4 AL12 AM12 - 137 6 AJ30 AH29 - 107 4 AK13 AL13 VREF 138 6 AH30 AK31 2 VREF 108 4 AM13 AN13 2 - 139 6 AJ31 AG29 1 - 109 4 AJ14 AK14 - 140 6 AG30 AK32 VREF 110 4 AM14 AN15 VREF 141 6 AF29 AH31 2 - 111 4 AJ15 AK15 NA - 142 6 AF30 AH32 - 112 4 AL15 AM16 - 143 6 AH33 AE29 VREF 113 4 AL16 AJ16 VREF 144 6 AE30 AG33 2 VREF 114 4 AK16 AN17 2 VREF 145 6 AF32 AD29 1 - 115 5 AM17 AM18 NA IO_LVDS_DLL 146 6 AD30 AE31 VREF 116 5 AK18 AJ18 VREF 147 6 AC29 AE32 2 - 117 5 AN19 AL19 - 148 6 AC30 AD31 VREF 118 5 AK19 AM20 NA - 149 6 AC31 AB29 - 119 5 AJ19 AL20 VREF 150 6 AB30 AC33 2 - 120 5 AN21 AL21 - 151 6 AA29 AB31 1 - 121 5 AJ20 AM22 2 - 152 6 AA31 AA30 VREF 122 5 AK21 AN23 VREF 153 6 Y29 AA32 2 - 123 5 AJ21 AM23 - 154 6 Y30 AA33 - 124 5 AK22 AM24 NA - 155 6 W29 Y32 VREF 125 5 AL23 AJ22 - 156 6 W31 W30 2 - 126 5 AK23 AL24 VREF 157 6 V30 W33 1 - 127 5 AN26 AJ23 1 - 158 6 V31 V29 VREF 128 5 AK24 AM26 VREF 159 6 U33 V32 2 VREF 129 5 AM27 AJ24 - 160 7 U32 U31 - 130 5 AL26 AK25 VREF 161 7 T30 T32 2 VREF Module 4 of 4 22 www.xilinx.com 1-800-255-7778 DS096-4 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 5: BG560/CG560 Differential Pin Pair Summary XQV1000E, XQV2000E P N Other Pair Bank Pin Pin AO Functions 162 7 T31 T29 VREF 163 7 R31 R33 1 - 164 7 R29 R30 2 - 165 7 P31 P32 VREF 166 7 P29 P30 - 167 7 N31 M32 2 - 168 7 L33 N30 VREF 169 7 L32 M31 1 - 170 7 L31 M30 2 - 171 7 J33 M29 - 172 7 K31 L30 VREF 173 7 H33 L29 1 - 174 7 H32 J31 VREF 175 7 H31 K29 1 - 176 7 G32 J30 1 VREF 177 7 G31 J29 VREF 178 7 E32 E33 - 179 7 F31 H29 1 - 180 7 E31 D32 VREF 181 7 C33 G29 1 - 182 7 D31 F30 1 VREF Notes: 1. AO in the XQV1000E. 2. AO in the XQV2000E. DS096-4 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 23 R QPro Virtex-E 1.8V QML High-Reliability FPGAs FG1156 Fine-Pitch Ball Grid Array Package XQV2000E devices only are available in the FG1156 fine-pitch Ball Grid Array package. See Table 6 for pinout information. Immediately following Table 6, see Table 7 for Differential Pair information. Table 6: FG1156 -- XQV2000E Table 6: FG1156 -- XQV2000E Bank Pin Description Pin # 0 IO_L8N_Y K12 0 IO_L8P_Y E8 0 IO_L9N B6 Bank Pin Description Pin # 0 IO_L9P F9 0 GCK3 E17 0 IO_L10N_YY G10 0 IO B4 0 IO_L10P_YY C7 0 IO B9 0 IO_VREF_L11N_YY D8 0 IO B10 0 IO_L11P_YY B7 0 IO D9 0 IO_L12N H11 0 IO D16 0 IO_L12P C85 0 IO E7 0 IO_L13N_Y E9 0 IO E11 0 IO_L13P_Y B8 0 IO E13 0 IO_VREF_L14N_Y K13 0 IO E16 0 IO_L14P_Y G11 0 IO F17 0 IO_L15N A8 0 IO J12 0 IO_L15P F10 0 IO J13 0 IO_L16N_YY C9 0 IO J14 0 IO_L16P_YY H12 0 IO K11 0 IO_VREF_L17N_YY D10 0 IO_L0N_Y F7 0 IO_L17P_YY A9 0 IO_L0P_Y H9 0 IO_L18N_Y F11 0 IO_L1N_Y C5 0 IO_L18P_Y A10 0 IO_L1P_Y J10 0 IO_L19N_Y K14 0 IO_VREF_L2N_Y E6 0 IO_L19P_Y C10 0 IO_L2P_Y D6 0 IO_VREF_L20N_YY H13 0 IO_L3N_Y A4 0 IO_L20P_YY G12 0 IO_L3P_Y G8 0 IO_L21N_YY A11 0 IO_L4N_YY C6 0 IO_L21P_YY B11 0 IO_L4P_YY J11 0 IO_L22N_Y E12 0 IO_VREF_L5N_YY G9 0 IO_L22P_Y D11 0 IO_L5P_YY F8 0 IO_L23N_Y G13 0 IO_L6N_YY A5 0 IO_L23P_Y C12 0 IO_L6P_YY H10 0 IO_L24N_Y K15 0 IO_L7N_Y D7 0 IO_L24P_Y A12 0 IO_L7P_Y B5 0 IO_L25N_Y B12 Module 4 of 4 24 www.xilinx.com 1-800-255-7778 DS096-4 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 6: FG1156 -- XQV2000E Table 6: FG1156 -- XQV2000E Bank Pin Description Pin # Bank Pin Description Pin # 0 IO_L25P_Y H14 1 GCK2 D17 0 IO_L26N_YY D12 1 IO A18 0 IO_L26P_YY F13 1 IO B18 0 IO_VREF_L27N_YY A13 1 IO B24 0 IO_L27P_YY B13 1 IO B25 0 IO_L28N_YY J15 1 IO E22 0 IO_L28P_YY G14 1 IO E23 0 IO_L29N_Y C13 1 IO D18 0 IO_L29P_Y F14 1 IO D19 0 IO_L30N_Y H15 1 IO D25 0 IO_L30P_Y D13 1 IO D26 0 IO_L31N A14 1 IO D28 0 IO_L31P K16 1 IO D29 0 IO_L32N_YY E14 1 IO G23 0 IO_L32P_YY B14 1 IO J23 0 IO_VREF_L33N_YY G15 1 IO_LVDS_DLL_L42P J18 0 IO_L33P_YY D14 1 IO_L43N_Y G18 0 IO_L34N J16 1 IO_VREF_L43P_Y C18 0 IO_L34P D15 1 IO_L44N_Y H18 0 IO_L35N_Y F15 1 IO_L44P_Y F18 0 IO_L35P_Y B15 1 IO_L45N_YY B19 0 IO_L36N_Y A15 1 IO_VREF_L45P_YY A19 0 IO_L36P_Y E15 1 IO_L46N_YY K19 0 IO_L37N G16 1 IO_L46P_YY C19 0 IO_L37P A16 1 IO_L47N F19 0 IO_L38N_YY F16 1 IO_L47P E19 0 IO_L38P_YY J17 1 IO_L48N_Y G19 0 IO_VREF_L39N_YY C16 1 IO_L48P_Y J19 0 IO_L39P_YY B16 1 IO_L49N_Y A20 0 IO_L40N_Y H17 1 IO_L49P_Y G20 0 IO_L40P_Y A17 1 IO_L50N B20 0 IO_VREF_L41N_Y G17 1 IO_L50P F20 0 IO_L41P_Y B17 1 IO_L51N_YY D20 0 IO_LVDS_DLL_L42N C17 1 IO_VREF_L51P_YY E20 1 IO_L52N_YY H20 DS096-4 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 25 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 6: FG1156 -- XQV2000E Table 6: FG1156 -- XQV2000E Bank Pin Description Pin # Bank Pin Description Pin # 1 IO_L52P_YY A21 1 IO_L70N_Y C26 1 IO_L53N E21 1 IO_VREF_L70P_Y H24 1 IO_L53P J20 1 IO_L71N_Y G24 1 IO_L54N_Y D21 1 IO_L71P_Y A27 1 IO_L54P_Y K20 1 IO_L72N B27 1 IO_L55N_Y B21 1 IO_L72P G25 1 IO_L55P_Y H21 1 IO_L73N_YY E26 1 IO_L56N_YY G21 1 IO_VREF_L73P_YY C27 1 IO_L56P_YY F21 1 IO_L74N_YY J24 1 IO_L57N_YY A22 1 IO_L74P_YY B28 1 IO_VREF_L57P_YY B22 1 IO_L75N K24 1 IO_L58N_YY J21 1 IO_L75P H25 1 IO_L58P_YY C22 1 IO_L76N_Y D27 1 IO_L59N_Y D22 1 IO_L76P_Y F26 1 IO_L59P_Y G22 1 IO_L77N_Y G26 1 IO_L60N_Y K21 1 IO_L77P_Y C28 1 IO_L60P_Y A23 1 IO_L78N_YY E27 1 IO_L61N_Y F22 1 IO_L78P_YY J25 1 IO_L61P_Y B23 1 IO_L79N_YY A30 1 IO_L62N_Y C23 1 IO_VREF_L79P_YY H26 1 IO_L62P_Y H22 1 IO_L80N_YY G27 1 IO_L63N_YY D23 1 IO_L80P_YY B29 1 IO_L63P_YY K22 1 IO_L81N_Y F27 1 IO_L64N_YY A24 1 IO_L81P_Y C29 1 IO_VREF_L64P_YY J22 1 IO_L82N_Y E28 1 IO_L65N_Y H23 1 IO_VREF_L82P_Y F28 1 IO_L65P_Y D24 1 IO_L83N_Y L25 1 IO_L66N_Y A25 1 IO_L83P_Y B30 1 IO_L66P_Y E24 1 IO_L84N B31 1 IO_L67N_YY A26 1 IO_L84P E29 1 IO_VREF_L67P_YY C25 1 IO_WRITE_L85N_YY A31 1 IO_L68N_YY F24 1 IO_CS_L85P_YY D30 1 IO_L68P_YY B26 1 IO_L69N K23 2 IO F31 1 IO_L69P F25 2 IO J32 Module 4 of 4 26 www.xilinx.com 1-800-255-7778 DS096-4 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 6: FG1156 -- XQV2000E Table 6: FG1156 -- XQV2000E Bank Pin Description Pin # Bank Pin Description Pin # 2 IO K27 2 IO_L97P_Y M26 2 IO K31 2 IO_L97N_Y E34 2 IO L28 2 IO_VREF_L98P_YY H31 2 IO L30 2 IO_L98N_YY G32 2 IO M32 2 IO_L99P_YY N25 2 IO N26 2 IO_L99N_YY J31 2 IO N28 2 IO_L100P_YY J30 2 IO P25 2 IO_L100N_YY G33 2 IO U26 2 IO_VREF_L101P_Y H34 2 IO U30 2 IO_L101N_Y J29 2 IO U32 2 IO_L102P M27 2 IO U34 2 IO_L102N H33 2 IO_D2 M30 2 IO_L103P_Y K29 2 IO_DOUT_BUSY_L86P_YY D32 2 IO_L103N_Y J34 2 IO_DIN_D0_L86N_YY J27 2 IO_VREF_L104P_YY L29 2 IO_L87P_Y E31 2 IO_L104N_YY J33 2 IO_L87N_Y F30 2 IO_L105P_YY M28 2 IO_L88P_Y G29 2 IO_L105N_YY K34 2 IO_L88N_Y F32 2 IO_L106P_Y N27 2 IO_VREF_L89P_Y E32 2 IO_L106N_Y L34 2 IO_L89N_Y G30 2 IO_VREF_L107P_YY K33 2 IO_L90P M25 2 IO_D1_L107N_YY P26 2 IO_L90N G31 2 IO_L108P_Y R25 2 IO_L91P_Y L26 2 IO_L108N_Y M34 2 IO_L91N_Y D33 2 IO_L109P_Y L31 2 IO_VREF_L92P_Y D34 2 IO_L109N_Y L33 2 IO_L92N_Y H29 2 IO_L110P_Y P27 2 IO_L93P_YY J28 2 IO_L110N_Y M33 2 IO_L93N_YY E33 2 IO_L111P M31 2 IO_L94P_YY H28 2 IO_L111N R26 2 IO_L94N_YY H30 2 IO_L112P_Y N30 2 IO_L95P_Y H32 2 IO_L112N_Y P28 2 IO_L95N_Y K28 2 IO_VREF_L113P_Y N29 2 IO_L96P_Y L27 2 IO_L113N_Y N33 2 IO_L96N_Y F33 2 IO_L114P_YY T25 DS096-4 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 27 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 6: FG1156 -- XQV2000E Table 6: FG1156 -- XQV2000E Bank Pin Description Pin # Bank Pin Description Pin # 2 IO_L114N_YY N34 3 IO AB26 2 IO_L115P_YY P34 3 IO AB31 2 IO_L115N_YY R27 3 IO AC31 2 IO_L116P_Y P29 3 IO AF34 2 IO_L116N_Y P31 3 IO AG31 2 IO_L117P_Y P33 3 IO AG33 2 IO_L117N_Y T26 3 IO AG34 2 IO_L118P_Y R34 3 IO AH29 2 IO_L118N_Y R28 3 IO AJ30 2 IO_VREF_L119P_YY N31 3 IO_L129P_Y V26 2 IO_D3_L119N_YY N32 3 IO_VREF_L129N_Y V30 2 IO_L120P_YY P30 3 IO_L130P_YY W34 2 IO_L120N_YY R33 3 IO_L130N_YY V28 2 IO_L121P_YY R29 3 IO_L131P_YY W32 2 IO_L121N_YY T34 3 IO_VREF_L131N_YY W30 2 IO_L122P_Y R30 3 IO_L132P_Y V29 2 IO_L122N_Y T30 3 IO_L132N_Y Y34 2 IO_L123P T28 3 IO_L133P W29 2 IO_L123N R31 3 IO_L133N Y33 2 IO_L124P_Y T29 3 IO_L134P_Y W26 2 IO_L124N_Y U27 3 IO_L134N_Y W28 2 IO_VREF_L125P_YY T31 3 IO_L135P_YY Y31 2 IO_L125N_YY T33 3 IO_L135N_YY Y30 2 IO_L126P_YY U28 3 IO_L136P_YY AA34 2 IO_L126N_YY T32 3 IO_L136N_YY W31 2 IO_VREF_L127P_Y U29 3 IO_D4_L137P_YY AA33 2 IO_L127N_Y U33 3 IO_VREF_L137N_YY Y29 2 IO_L128P_YY V33 3 IO_L138P_Y W25 2 IO_L128N_YY U31 3 IO_L138N_Y AB34 3 IO_L139P_Y Y28 3 IO V27 3 IO_L139N_Y AB33 3 IO V31 3 IO_L140P_Y AA30 3 IO V32 3 IO_L140N_Y Y26 3 IO W33 3 IO_L141P_YY Y27 3 IO AB25 3 IO_L141N_YY AA31 Module 4 of 4 28 www.xilinx.com 1-800-255-7778 DS096-4 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 6: FG1156 -- XQV2000E Table 6: FG1156 -- XQV2000E Bank Pin Description Pin # Bank Pin Description Pin # 3 IO_L142P_YY AA27 3 IO_VREF_L159N_YY AF30 3 IO_L142N_YY AA29 3 IO_L160P_Y AC25 3 IO_L143P_Y AB32 3 IO_L160N_Y AH32 3 IO_VREF_L143N_Y AB29 3 IO_L161P_Y AE28 3 IO_L144P_Y AA28 3 IO_L161N_Y AL34 3 IO_L144N_Y AC34 3 IO_L162P_Y AG30 3 IO_L145P Y25 3 IO_L162N_Y AD27 3 IO_L145N AD34 3 IO_L163P_YY AF29 3 IO_L146P_Y AB30 3 IO_L163N_YY AK34 3 IO_L146N_Y AC33 3 IO_L164P_YY AD25 3 IO_L147P_Y AA26 3 IO_L164N_YY AE27 3 IO_L147N_Y AC32 3 IO_L165P_Y AJ33 3 IO_L148P_Y AD33 3 IO_VREF_L165N_Y AH31 3 IO_L148N_Y AB28 3 IO_L166P_Y AE26 3 IO_L149P_YY AE34 3 IO_L166N_Y AL33 3 IO_D5_L149N_YY AB27 3 IO_L167P AF28 3 IO_D6_L150P_YY AE33 3 IO_L167N AL32 3 IO_VREF_L150N_YY AC30 3 IO_L168P_Y AJ31 3 IO_L151P_Y AA25 3 IO_VREF_L168N_Y AF27 3 IO_L151N_Y AE32 3 IO_L169P_Y AG29 3 IO_L152P_YY AE31 3 IO_L169N_Y AJ32 3 IO_L152N_YY AD29 3 IO_L170P_Y AK33 3 IO_L153P_YY AD31 3 IO_L170N_Y AH30 3 IO_VREF_L153N_YY AF33 3 IO_D7_L171P_YY AK32 3 IO_L154P_Y AC28 3 IO_INIT_L171N_YY AK31 3 IO_L154N_Y AF31 3 IO V34 3 IO_L155P_Y AC27 3 IO_L155N_Y AF32 4 GCK0 AH18 3 IO_L156P_Y AE29 4 IO AE21 3 IO_VREF_L156N_Y AD28 4 IO AG18 3 IO_L157P_YY AD30 4 IO AG23 3 IO_L157N_YY AG32 4 IO AH24 3 IO_L158P_YY AC26 4 IO AH25 3 IO_L158N_YY AH33 4 IO AJ28 3 IO_L159P_YY AD26 4 IO AK18 DS096-4 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 29 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 6: FG1156 -- XQV2000E Table 6: FG1156 -- XQV2000E Bank Pin Description Pin # Bank Pin Description Pin # 4 IO AK19 4 IO_L186P_Y AL26 4 IO AL25 4 IO_L186N_Y AP26 4 IO AL27 4 IO_VREF_L187P_Y AN26 4 IO AL30 4 IO_L187N_Y AJ25 4 IO AN18 4 IO_L188P AG24 4 IO AN22 4 IO_L188N AP25 4 IO AN24 4 IO_L189P_YY AF23 4 IO_L172P_YY AP31 4 IO_L189N_YY AM26 4 IO_L172N_YY AK29 4 IO_VREF_L190P_YY AJ24 4 IO_L173P_Y AP30 4 IO_L190N_YY AN25 4 IO_L173N_Y AN31 4 IO_L191P_Y AE22 4 IO_L174P_Y AH27 4 IO_L191N_Y AM25 4 IO_L174N_Y AN30 4 IO_L192P_Y AK24 4 IO_VREF_L175P_Y AM30 4 IO_L192N_Y AH23 4 IO_L175N_Y AK28 4 IO_VREF_L193P_YY AF22 4 IO_L176P_Y AG26 4 IO_L193N_YY AP24 4 IO_L176N_Y AN29 4 IO_L194P_YY AL24 4 IO_L177P_YY AF25 4 IO_L194N_YY AK23 4 IO_L177N_YY AM29 4 IO_L195P_Y AG22 4 IO_VREF_L178P_YY AL29 4 IO_L195N_Y AN23 4 IO_L178N_YY AL28 4 IO_L196P_Y AP23 4 IO_L179P_YY AE24 4 IO_L196N_Y AM23 4 IO_L179N_YY AN28 4 IO_L197P_Y AH22 4 IO_L180P_Y AJ27 4 IO_L197N_Y AP22 4 IO_L180N_Y AH26 4 IO_L198P_Y AL23 4 IO_L181P_Y AG25 4 IO_L198N_Y AF21 4 IO_L181N_Y AK27 4 IO_L199P_YY AL22 4 IO_L182P AM28 4 IO_L199N_YY AJ22 4 IO_L182N AF24 4 IO_VREF_L200P_YY AK22 4 IO_L183P_YY AJ26 4 IO_L200N_YY AM22 4 IO_L183N_YY AP27 4 IO_L201P_YY AG21 4 IO_VREF_L184P_YY AK26 4 IO_L201N_YY AJ21 4 IO_L184N_YY AN27 4 IO_L202P_Y AP21 4 IO_L185P AE23 4 IO_L202N_Y AE20 4 IO_L185N AM27 4 IO_L203P_Y AH21 Module 4 of 4 30 www.xilinx.com 1-800-255-7778 DS096-4 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 6: FG1156 -- XQV2000E Table 6: FG1156 -- XQV2000E Bank Pin Description Pin # Bank Pin Description Pin # 4 IO_L203N_Y AL21 5 IO AN9 4 IO_L204P AN21 5 IO AN10 4 IO_L204N AF20 5 IO AN16 4 IO_L205P_YY AK21 5 IO AN17 4 IO_L205N_YY AP20 5 IO_LVDS_DLL_L215N AL17 4 IO_VREF_L206P_YY AE19 5 IO_L216P_Y AH17 4 IO_L206N_YY AN20 5 IO_VREF_L216N_Y AM17 4 IO_L207P_Y AG20 5 IO_L217P_Y AJ17 4 IO_L207N_Y AL20 5 IO_L217N_Y AG17 4 IO_L208P_Y AH20 5 IO_L218P_YY AP16 4 IO_L208N_Y AK20 5 IO_VREF_L218N_YY AL16 4 IO_L209P_Y AN19 5 IO_L219P_YY AJ16 4 IO_L209N_Y AJ20 5 IO_L219N_YY AM16 4 IO_L210P AF19 5 IO_L220P AK16 4 IO_L210N AP19 5 IO_L220N AP15 4 IO_L211P_YY AM19 5 IO_L221P_Y AL15 4 IO_L211N_YY AH19 5 IO_L221N_Y AH16 4 IO_VREF_L212P_YY AJ19 5 IO_L222P_Y AN15 4 IO_L212N_YY AP18 5 IO_L222N_Y AF16 4 IO_L213P_Y AF18 5 IO_L223P_Y AP14 4 IO_L213N_Y AP17 5 IO_L223N_Y AE16 4 IO_VREF_L214P_Y AJ18 5 IO_L224P_YY AK15 4 IO_L214N_Y AL18 5 IO_VREF_L224N_YY AJ15 4 IO_LVDS_DLL_L215P AM18 5 IO_L225P_YY AH15 5 IO_L225N_YY AN14 5 GCK1 AL19 5 IO_L226P AK14 5 IO AF17 5 IO_L226N AG15 5 IO AG12 5 IO_L227P_Y AM13 5 IO AH12 5 IO_L227N_Y AF15 5 IO AJ10 5 IO_L228P_Y AG14 5 IO AJ11 5 IO_L228N_Y AP13 5 IO AK7 5 IO_L229P_YY AE14 5 IO AK13 5 IO_L229N_YY AE15 5 IO AL13 5 IO_L230P_YY AN13 5 IO AM4 5 IO_VREF_L230N_YY AG13 DS096-4 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 31 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 6: FG1156 -- XQV2000E Table 6: FG1156 -- XQV2000E Bank Pin Description Pin # Bank Pin Description Pin # 5 IO_L231P_YY AH14 5 IO_L248N AJ9 5 IO_L231N_YY AP12 5 IO_L249P_Y AM7 5 IO_L232P_Y AJ14 5 IO_L249N_Y AL7 5 IO_L232N_Y AL14 5 IO_L250P_Y AG10 5 IO_L233P_Y AF13 5 IO_L250N_Y AN6 5 IO_L233N_Y AN12 5 IO_L251P_YY AK8 5 IO_L234P_Y AF14 5 IO_L251N_YY AH9 5 IO_L234N_Y AP11 5 IO_L252P_YY AP5 5 IO_L235P_Y AN11 5 IO_VREF_L252N_YY AJ8 5 IO_L235N_Y AH13 5 IO_L253P_YY AE11 5 IO_L236P_YY AM12 5 IO_L253N_YY AN5 5 IO_L236N_YY AL12 5 IO_L254P_Y AF10 5 IO_L237P_YY AJ13 5 IO_L254N_Y AM6 5 IO_VREF_L237N_YY AP10 5 IO_L255P_Y AL6 5 IO_L238P_Y AK12 5 IO_VREF_L255N_Y AG9 5 IO_L238N_Y AM10 5 IO_L256P_Y AH8 5 IO_L239P_Y AP9 5 IO_L256N_Y AP4 5 IO_L239N_Y AK11 5 IO_L257P_Y AN4 5 IO_L240P_YY AL11 5 IO_L257N_Y AJ7 5 IO_VREF_L240N_YY AL10 5 IO_L258P_YY AM5 5 IO_L241P_YY AE13 5 IO_L258N_YY AK6 5 IO_L241N_YY AM9 5 IO_L242P AF12 6 IO T1 5 IO_L242N AP8 6 IO V2 5 IO_L243P_Y AL9 6 IO V3 5 IO_VREF_L243N_Y AH11 6 IO V5 5 IO_L244P_Y AF11 6 IO V8 5 IO_L244N_Y AN8 6 IO AA10 5 IO_L245P_Y AM8 6 IO AB5 5 IO_L245N_Y AG11 6 IO AB7 5 IO_L246P_YY AL8 6 IO AB9 5 IO_VREF_L246N_YY AK9 6 IO AD7 5 IO_L247P_YY AH10 6 IO AD8 5 IO_L247N_YY AN7 6 IO AE2 5 IO_L248P AE12 6 IO AE4 Module 4 of 4 32 www.xilinx.com 1-800-255-7778 DS096-4 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 6: FG1156 -- XQV2000E Table 6: FG1156 -- XQV2000E Bank Pin Description Pin # Bank Pin Description Pin # 6 IO AJ4 6 IO_L275P AF2 6 IO AH5 6 IO_L276N_Y AC8 6 IO_L259N_YY AH6 6 IO_L276P_Y AE1 6 IO_L259P_YY AF8 6 IO_VREF_L277N_YY AD5 6 IO_L260N_Y AE9 6 IO_L277P_YY AE3 6 IO_L260P_Y AK3 6 IO_L278N_YY AC7 6 IO_L261N_Y AD10 6 IO_L278P_YY AD1 6 IO_L261P_Y AL2 6 IO_L279N_Y AD6 6 IO_VREF_L262N_Y AL1 6 IO_L279P_Y AD2 6 IO_L262P_Y AH4 6 IO_VREF_L280N_YY AB8 6 IO_L263N AG6 6 IO_L280P_YY AC1 6 IO_L263P AK1 6 IO_L281N_YY AC5 6 IO_L264N_Y AF7 6 IO_L281P_YY AC2 6 IO_L264P_Y AK2 6 IO_L282N_Y AA9 6 IO_VREF_L265N_Y AJ3 6 IO_L282P_Y AC3 6 IO_L265P_Y AG5 6 IO_L283N_Y AC4 6 IO_L266N_YY AD9 6 IO_L283P_Y AD4 6 IO_L266P_YY AJ2 6 IO_L284N_Y AA8 6 IO_L267N_YY AC10 6 IO_L284P_Y AB6 6 IO_L267P_YY AH2 6 IO_L285N AB1 6 IO_L268N_Y AH3 6 IO_L285P Y10 6 IO_L268P_Y AF5 6 IO_L286N_Y AB2 6 IO_L269N_Y AE8 6 IO_L286P_Y AA7 6 IO_L269P_Y AG3 6 IO_VREF_L287N_Y AA4 6 IO_L270N_Y AE7 6 IO_L287P_Y AA1 6 IO_L270P_Y AG2 6 IO_L288N_YY Y9 6 IO_VREF_L271N_YY AF6 6 IO_L288P_YY AB4 6 IO_L271P_YY AG1 6 IO_L289N_YY AA2 6 IO_L272N_YY AC9 6 IO_L289P_YY Y8 6 IO_L272P_YY AG4 6 IO_L290N_Y AA6 6 IO_L273N_YY AE6 6 IO_L290P_Y AA5 6 IO_L273P_YY AF3 6 IO_L291N_Y AB3 6 IO_VREF_L274N_Y AF1 6 IO_L291P_Y Y7 6 IO_L274P_Y AF4 6 IO_L292N_Y Y1 6 IO_L275N AB10 6 IO_L292P_Y W10 DS096-4 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 33 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 6: FG1156 -- XQV2000E Table 6: FG1156 -- XQV2000E Bank Pin Description Pin # Bank Pin Description Pin # 6 IO_VREF_L293N_YY Y5 7 IO_L302N_YY U9 6 IO_L293P_YY Y2 7 IO_L302P_YY U4 6 IO_L294N_YY W9 7 IO_L303N_Y U7 6 IO_L294P_YY W2 7 IO_VREF_L303P_Y U5 6 IO_L295N_YY W7 7 IO_L304N_YY U3 6 IO_L295P_YY Y4 7 IO_L304P_YY U6 6 IO_L296N_Y W1 7 IO_L305N_YY T3 6 IO_L296P_Y Y6 7 IO_VREF_L305P_YY T6 6 IO_L297N_Y W6 7 IO_L306N_Y T9 6 IO_L297P_Y W3 7 IO_L306P_Y T4 6 IO_L298N_Y V9 7 IO_L307N_Y T5 6 IO_L298P_Y W4 7 IO_L307P_Y R1 6 IO_VREF_L299N_YY W5 7 IO_L308N_Y R6 6 IO_L299P_YY V1 7 IO_L308P_Y T10 6 IO_L300N_YY V7 7 IO_L309N_YY R2 6 IO_L300P_YY U2 7 IO_L309P_YY R5 6 IO_VREF_L301N_Y V6 7 IO_L310N_YY P1 6 IO_L301P_Y U1 7 IO_VREF_L310P_YY P5 7 IO_L311N_Y R8 7 IO F5 7 IO_L311P_Y P2 7 IO G6 7 IO_L312N_Y R9 7 IO H1 7 IO_L312P_Y N1 7 IO H7 7 IO_L313N_Y P4 7 IO K2 7 IO_L313P_Y R10 7 IO K4 7 IO_L314N_YY P8 7 IO L6 7 IO_L314P_YY N2 7 IO M5 7 IO_L315N_YY P6 7 IO M10 7 IO_L315P_YY P7 7 IO N5 7 IO_L316N_Y M1 7 IO N10 7 IO_VREF_L316P_Y N4 7 IO R7 7 IO_L317N_Y N6 7 IO T2 7 IO_L317P_Y N3 7 IO T7 7 IO_L318N P9 7 IO U8 7 IO_L318P M2 7 IO V43 7 IO_L319N_Y N7 Module 4 of 4 34 www.xilinx.com 1-800-255-7778 DS096-4 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 6: FG1156 -- XQV2000E Table 6: FG1156 -- XQV2000E Bank Pin Description Pin # Bank Pin Description Pin # 7 IO_L319P_Y M3 7 IO_L337N_YY F3 7 IO_L320N_Y P10 7 IO_L337P_YY L10 7 IO_L320P_Y M4 7 IO_L338N_Y E1 7 IO_L321N_Y L1 7 IO_VREF_L338P_Y_Y H6 7 IO_L321P_Y N8 7 IO_L339N_Y G5 7 IO_L322N_YY L2 7 IO_L339P_Y E2 7 IO_L322P_YY N9 7 IO_L340N K9 7 IO_L323N_YY M7 7 IO_L340P D1 7 IO_VREF_L323P_YY K1 7 IO_L341N_Y E3 7 IO_L324N_Y M8 7 IO_VREF_L341P_Y J8 7 IO_L324P_Y L4 7 IO_L342N_Y E4 7 IO_L325N_YY J1 7 IO_L342P_Y D2 7 IO_L325P_YY L5 7 IO_L343N_Y F4 7 IO_L326N_YY J2 7 IO_L343P_Y D3 7 IO_VREF_L326P_YY K3 7 IO_L327N_Y L7 2 CCLK C31 7 IO_L327P_Y J3 3 DONE AM31 7 IO_L328N_Y M9 NA DXN AJ5 7 IO_L328P_Y H24 NA DXP AL5 7 IO_L329N_Y J4 NA M0 AK4 7 IO_VREF_L329P_Y K6 NA M1 AG7 7 IO_L330N_YY L8 NA M2 AL3 7 IO_L330P_YY G2 NA PROGRAM AG28 7 IO_L331N_YY H3 NA TCK D5 7 IO_L331P_YY K7 NA TDI C30 7 IO_L332N_YY G3 2 TDO K26 7 IO_VREF_L332P_YY J5 NA TMS C4 7 IO_L333N_Y L9 7 IO_L333P_Y H5 NA VCCINT K10 7 IO_L334N_Y J6 NA VCCINT K17 7 IO_L334P_Y H4 NA VCCINT K18 7 IO_L335N_Y G4 NA VCCINT K25 7 IO_L335P_Y K8 NA VCCINT L11 7 IO_L336N_YY J7 NA VCCINT L24 7 IO_L336P_YY F2 NA VCCINT M12 DS096-4 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 35 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 6: FG1156 -- XQV2000E Table 6: FG1156 -- XQV2000E Bank Pin Description Pin # Bank Pin Description Pin # NA VCCINT M23 NA VCCINT AD24 NA VCCINT N13 NA VCCINT AD11 NA VCCINT N14 NA VCCINT AE10 NA VCCINT N15 NA VCCINT AE17 NA VCCINT N16 NA VCCINT AE18 NA VCCINT N19 NA VCCINT AE25 NA VCCINT N20 NA VCCINT N21 NA VCCO_0 M17 NA VCCINT N22 NA VCCO_0 L17 NA VCCINT P13 NA VCCO_0 L16 NA VCCINT P22 NA VCCO_0 E10 NA VCCINT R13 NA VCCO_0 C14 NA VCCINT R22 NA VCCO_0 A6 NA VCCINT T13 NA VCCO_0 M13 NA VCCINT T22 NA VCCO_0 M14 NA VCCINT U10 NA VCCO_0 M15 NA VCCINT U25 NA VCCO_0 M16 NA VCCINT V10 NA VCCO_0 L12 NA VCCINT V25 NA VCCO_0 L13 NA VCCINT W13 NA VCCO_0 L14 NA VCCINT W22 NA VCCO_0 L15 NA VCCINT Y13 NA VCCO_1 M18 NA VCCINT Y22 NA VCCO_1 L18 NA VCCINT AA13 NA VCCO_1 L23 NA VCCINT AA22 NA VCCO_1 E25 NA VCCINT AB13 NA VCCO_1 C21 NA VCCINT AB14 NA VCCO_1 A29 NA VCCINT AB15 NA VCCO_1 M19 NA VCCINT AB16 NA VCCO_1 M20 NA VCCINT AB19 NA VCCO_1 M21 NA VCCINT AB20 NA VCCO_1 M22 NA VCCINT AB21 NA VCCO_1 L19 NA VCCINT AB22 NA VCCO_1 L20 NA VCCINT AC12 NA VCCO_1 L21 NA VCCINT AC23 NA VCCO_1 L22 Module 4 of 4 36 www.xilinx.com 1-800-255-7778 DS096-4 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 6: FG1156 -- XQV2000E Table 6: FG1156 -- XQV2000E Bank Pin Description Pin # Bank Pin Description Pin # NA VCCO_2 U24 NA VCCO_4 AM21 NA VCCO_2 U23 NA VCCO_4 AK25 NA VCCO_2 N24 NA VCCO_4 AD19 NA VCCO_2 M24 NA VCCO_4 AD20 NA VCCO_2 K30 NA VCCO_4 AD21 NA VCCO_2 F34 NA VCCO_4 AD22 NA VCCO_2 T23 NA VCCO_4 AD23 NA VCCO_2 T24 NA VCCO_5 AC17 NA VCCO_2 R23 NA VCCO_5 AD17 NA VCCO_2 R24 NA VCCO_5 AC13 NA VCCO_2 P23 NA VCCO_5 AC14 NA VCCO_2 P24 NA VCCO_5 AC15 NA VCCO_2 P32 NA VCCO_5 AC16 NA VCCO_2 N23 NA VCCO_5 AP6 NA VCCO_3 V23 NA VCCO_5 AM14 NA VCCO_3 V24 NA VCCO_5 AK10 NA VCCO_3 Y23 NA VCCO_5 AD12 NA VCCO_3 Y24 NA VCCO_5 AD13 NA VCCO_3 W23 NA VCCO_5 AD14 NA VCCO_3 W24 NA VCCO_5 AD15 NA VCCO_3 AJ34 NA VCCO_5 AD16 NA VCCO_3 AE30 NA VCCO_6 V11 NA VCCO_3 AC24 NA VCCO_6 V12 NA VCCO_3 AB23 NA VCCO_6 Y11 NA VCCO_3 AB24 NA VCCO_6 Y12 NA VCCO_3 AA23 NA VCCO_6 W11 NA VCCO_3 AA24 NA VCCO_6 W12 NA VCCO_3 AA32 NA VCCO_6 AJ1 NA VCCO_4 AD18 NA VCCO_6 AE5 NA VCCO_4 AC18 NA VCCO_6 AC11 NA VCCO_4 AC19 NA VCCO_6 AB11 NA VCCO_4 AC20 NA VCCO_6 AB12 NA VCCO_4 AC21 NA VCCO_6 AA3 NA VCCO_4 AC22 NA VCCO_6 AA11 NA VCCO_4 AP29 NA VCCO_6 AA12 DS096-4 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 37 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 6: FG1156 -- XQV2000E Table 6: FG1156 -- XQV2000E Bank Pin Description Pin # Bank Pin Description Pin # NA VCCO_7 U11 NA GND AP1 NA VCCO_7 U12 NA GND AN2 NA VCCO_7 N12 NA GND AM15 NA VCCO_7 M11 NA GND AK17 NA VCCO_7 K5 NA GND AH34 NA VCCO_7 F1 NA GND AC6 NA VCCO_7 T11 NA GND AA21 NA VCCO_7 T12 NA GND Y21 NA VCCO_7 R11 NA GND W20 NA VCCO_7 R12 NA GND V20 NA VCCO_7 P3 NA GND U21 NA VCCO_7 P11 NA GND T21 NA VCCO_7 P12 NA GND R20 NA VCCO_7 N11 NA GND P20 NA GND H16 NA GND K32 NA GND F23 NA GND R4 NA GND C3 NA GND AN1 NA GND B2 NA GND AM11 NA GND A28 NA GND AK5 NA GND AP34 NA GND AH28 NA GND AM3 NA GND AD32 NA GND AL31 NA GND AA20 NA GND AH7 NA GND Y20 NA GND AD3 NA GND W19 NA GND AA19 NA GND V19 NA GND Y19 NA GND U20 NA GND W18 NA GND T20 NA GND V18 NA GND R19 NA GND U19 NA GND P19 NA GND T19 NA GND H8 NA GND R18 NA GND F12 NA GND P18 NA GND C2 NA GND J26 NA GND B1 NA GND F6 NA GND A7 NA GND C1 Module 4 of 4 38 www.xilinx.com 1-800-255-7778 DS096-4 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 6: FG1156 -- XQV2000E Table 6: FG1156 -- XQV2000E Bank Pin Description Pin # Bank Pin Description Pin # NA GND C34 NA GND H27 NA GND A3 NA GND E5 NA GND AP2 NA GND C15 NA GND AN3 NA GND B32 NA GND AM20 NA GND A33 NA GND AK30 NA GND AP7 NA GND AG8 NA GND AN33 NA GND AC29 NA GND AM32 NA GND Y3 NA GND AJ12 NA GND Y32 NA GND AG19 NA GND W21 NA GND AA15 NA GND V21 NA GND Y15 NA GND T8 NA GND W14 NA GND T27 NA GND V14 NA GND R21 NA GND U15 NA GND P21 NA GND T15 NA GND H19 NA GND R14 NA GND F29 NA GND P14 NA GND C11 NA GND M29 NA GND B3 NA GND G1 NA GND A32 NA GND E18 NA GND AP3 NA GND C20 NA GND AN32 NA GND B33 NA GND AM24 NA GND A34 NA GND AJ6 NA GND AP28 NA GND AG16 NA GND AN34 NA GND AA14 NA GND AM33 NA GND Y14 NA GND AJ23 NA GND W8 NA GND AG27 NA GND W27 NA GND AA16 NA GND U14 NA GND Y16 NA GND T14 NA GND W15 NA GND R3 NA GND V15 NA GND R32 NA GND U16 NA GND M6 NA GND T16 DS096-4 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 39 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 6: FG1156 -- XQV2000E Table 6: FG1156 -- XQV2000E Bank Pin Description Pin # Bank Pin Description Pin # NA GND R15 NA GND T18 NA GND P15 NA GND R17 NA GND L3 NA GND P17 NA GND G7 NA GND J9 NA GND E30 NA GND G34 NA GND C24 NA GND D31 NA GND B34 NA GND C33 NA GND AP32 NA GND A2 NA GND AM1 NA GND AB17 NA GND AM34 NA GND AB18 NA GND AJ29 NA GND N17 NA GND AF9 NA GND N18 NA GND AA17 NA GND U13 NA GND Y17 NA GND V13 NA GND W16 NA GND U22 NA GND V16 NA GND V22 NA GND U17 NA GND T17 NA GND R16 NA GND P16 NA GND L32 NA GND G28 NA GND D4 NA GND C32 NA GND A1 NA GND AP33 NA GND AM2 NA GND AL4 NA GND AH1 NA GND AF26 NA GND AA18 NA GND Y18 NA GND W17 NA GND V17 NA GND U18 Module 4 of 4 40 FG1156 Differential Pin Pairs Virtex-E devices have differential pin pairs that can also provide other functions when not used as a differential pair. The AO column in Table 7 indicates which pin pairs may be used as an asynchronous output with a "." The "Other Functions" column indicates alternative function(s) that are not available when the pair is used as a differential pair or differential clock. Table 7: FG1156 Differential Pin Pair Summary: XQV2000E Pair Bank P N Other Pin Pin AO Functions GCLK LVDS 3 0 E17 C17 NA IO_DLL_L 42N 2 1 D17 J18 NA IO_DLL_L 42P 1 5 AL19 AL17 NA IO_DLL_L 215N 0 4 AH18 AM18 NA IO_DLL_L 215P IO LVDS Total Pairs: 344, Asynchronous Output Pairs: 134 0 0 H9 F7 NA - 1 0 J10 C5 - www.xilinx.com 1-800-255-7778 DS096-4 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 7: FG1156 Differential Pin Pair Summary: XQV2000E P N Table 7: FG1156 Differential Pin Pair Summary: XQV2000E Other P N Other Pair Bank Pin Pin AO Functions Pair Bank Pin Pin AO Functions 2 0 D6 E6 VREF 36 0 E15 A15 - 3 0 G8 A4 NA - 37 0 A16 G16 NA - 4 0 J11 C6 - 38 0 J17 F16 - 5 0 F8 G9 VREF 39 0 B16 C16 VREF 6 0 H10 A5 - 40 0 A17 H17 NA - 7 0 B5 D7 NA - 41 0 B17 G17 NA VREF 8 0 E8 K12 NA - 42 1 J18 C17 None IO_LVDS_DLL 9 0 F9 B6 NA - 43 1 C18 G18 NA VREF 10 0 C7 G10 - 44 1 F18 H18 NA - 11 0 B7 D8 VREF 45 1 A19 B19 VREF 12 0 C8 H11 NA - 46 1 C19 K19 - 13 0 B8 E9 - 47 1 E19 F19 - 14 0 G11 K13 VREF 48 1 J19 G19 - 15 0 F10 A8 NA - 49 1 G20 A20 - 16 0 H12 C9 - 50 1 F20 B20 NA - 17 0 A9 D10 VREF 51 1 E20 D20 VREF 18 0 A10 F11 NA - 52 1 A21 H20 - 19 0 C10 K14 NA - 53 1 J20 E21 NA - 20 0 G12 H13 VREF 54 1 K20 D21 NA - 21 0 B11 A11 - 55 1 H21 B21 NA - 22 0 D11 E12 NA - 56 1 F21 G21 - 23 0 C12 G13 - 57 1 B22 A22 VREF 24 0 A12 K15 - 58 1 C22 J21 - 25 0 H14 B12 NA - 59 1 G22 D22 NA - 26 0 F13 D12 - 60 1 A23 K21 - 27 0 B13 A13 VREF 61 1 B23 F22 - 28 0 G14 J15 - 62 1 H22 C23 NA - 29 0 F14 C13 NA - 63 1 K22 D23 - 30 0 D13 H15 NA - 64 1 J22 A24 VREF 31 0 K16 A14 NA - 65 1 D24 H23 NA - 32 0 B14 E14 - 66 1 E24 A25 NA - 33 0 D14 G15 VREF 67 1 C25 A26 VREF 34 0 D15 J16 NA - 68 1 B26 F24 - 35 0 B15 F15 - 69 1 F25 K23 NA - DS096-4 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 41 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 7: FG1156 Differential Pin Pair Summary: XQV2000E P N Table 7: FG1156 Differential Pin Pair Summary: XQV2000E Other P N Other Pair Bank Pin Pin AO Functions Pair Bank Pin Pin AO Functions 70 1 H24 C26 VREF 104 2 L29 J33 VREF 71 1 A27 G24 - 105 2 M28 K34 - 72 1 G25 B27 NA - 106 2 N27 L34 NA - 73 1 C27 E26 VREF 107 2 K33 P26 D1 74 1 B28 J24 - 108 2 R25 M34 - 75 1 H25 K24 NA - 109 2 L31 L33 - 76 1 F26 D27 NA - 110 2 P27 M33 NA - 77 1 C28 G26 NA - 111 2 M31 R26 NA - 78 1 J25 E27 - 112 2 N30 P28 NA - 79 1 H26 A30 VREF 113 2 N29 N33 VREF 80 1 B29 G27 - 114 2 T25 N34 - 81 1 C29 F27 NA - 115 2 P34 R27 - 82 1 F28 E28 VREF 116 2 P29 P31 NA - 83 1 B30 L25 - 117 2 P33 T26 - 84 1 E29 B31 NA - 118 2 R34 R28 - 85 1 D30 A31 CS 119 2 N31 N32 D3 86 2 D32 J27 DIN, D0 120 2 P30 R33 - 87 2 E31 F30 - 121 2 R29 T34 - 88 2 G29 F32 - 122 2 R30 T30 NA - 89 2 E32 G30 NA VREF 123 2 T28 R31 NA - 90 2 M25 G31 NA - 124 2 T29 U27 NA - 91 2 L26 D33 NA - 125 2 T31 T33 VREF 92 2 D34 H29 VREF 126 2 U28 T32 - 93 2 J28 E33 - 127 2 U29 U33 NA VREF 94 2 H28 H30 - 128 2 V33 U31 - 95 2 H32 K28 NA - 129 3 V26 V30 NA VREF 96 2 L27 F33 - 130 3 W34 V28 - 97 2 M26 E34 - 131 3 W32 W30 VREF 98 2 H31 G32 VREF 132 3 V29 Y34 NA - 99 2 N25 J31 - 133 3 W29 Y33 NA - 100 2 J30 G33 - 134 3 W26 W28 NA - 101 2 H34 J29 NA VREF 135 3 Y31 Y30 - 102 2 M27 H33 NA - 136 3 AA34 W31 - 103 2 K29 J34 NA - 137 3 AA33 Y29 VREF Module 4 of 4 42 www.xilinx.com 1-800-255-7778 DS096-4 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 7: FG1156 Differential Pin Pair Summary: XQV2000E P N Table 7: FG1156 Differential Pin Pair Summary: XQV2000E Other P N Other Pair Bank Pin Pin AO Functions Pair Bank Pin Pin AO Functions 138 3 W25 AB34 - 172 4 AP31 AK29 - 139 3 Y28 AB33 - 173 4 AP30 AN31 NA - 140 3 AA30 Y26 NA - 174 4 AH27 AN30 - 141 3 Y27 AA31 - 175 4 AM30 AK28 VREF 142 3 AA27 AA29 - 176 4 AG26 AN29 NA - 143 3 AB32 AB29 VREF 177 4 AF25 AM29 - 144 3 AA28 AC34 NA - 178 4 AL29 AL28 VREF 145 3 Y25 AD34 NA - 179 4 AE24 AN28 - 146 3 AB30 AC33 NA - 180 4 AJ27 AH26 NA - 147 3 AA26 AC32 - 181 4 AG25 AK27 NA - 148 3 AD33 AB28 - 182 4 AM28 AF24 NA - 149 3 AE34 AB27 D5 183 4 AJ26 AP27 - 150 3 AE33 AC30 VREF 184 4 AK26 AN27 VREF 151 3 AA25 AE32 NA - 185 4 AE23 AM27 NA - 152 3 AE31 AD29 - 186 4 AL26 AP26 - 153 3 AD31 AF33 VREF 187 4 AN26 AJ25 VREF 154 3 AC28 AF31 NA - 188 4 AG24 AP25 NA - 155 3 AC27 AF32 NA - 189 4 AF23 AM26 - 156 3 AE29 AD28 NA VREF 190 4 AJ24 AN25 VREF 157 3 AD30 AG32 - 191 4 AE22 AM25 NA - 158 3 AC26 AH33 - 192 4 AK24 AH23 NA - 159 3 AD26 AF30 VREF 193 4 AF22 AP24 VREF 160 3 AC25 AH32 - 194 4 AL24 AK23 - 161 3 AE28 AL34 - 195 4 AG22 AN23 NA - 162 3 AG30 AD27 NA - 196 4 AP23 AM23 - 163 3 AF29 AK34 - 197 4 AH22 AP22 - 164 3 AD25 AE27 - 198 4 AL23 AF21 NA - 165 3 AJ33 AH31 VREF 199 4 AL22 AJ22 - 166 3 AE26 AL33 NA - 200 4 AK22 AM22 VREF 167 3 AF28 AL32 NA - 201 4 AG21 AJ21 - 168 3 AJ31 AF27 NA VREF 202 4 AP21 AE20 NA - 169 3 AG29 AJ32 - 203 4 AH21 AL21 NA - 170 3 AK33 AH30 - 204 4 AN21 AF20 NA - 171 3 AK32 AK31 INIT 205 4 AK21 AP20 - DS096-4 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 43 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 7: FG1156 Differential Pin Pair Summary: XQV2000E P N Table 7: FG1156 Differential Pin Pair Summary: XQV2000E Other P N Other Pair Bank Pin Pin AO Functions Pair Bank Pin Pin AO Functions 206 4 AE19 AN20 VREF 240 5 AL11 AL10 VREF 207 4 AG20 AL20 NA - 241 5 AE13 AM9 - 208 4 AH20 AK20 - 242 5 AF12 AP8 NA - 209 4 AN19 AJ20 - 243 5 AL9 AH11 VREF 210 4 AF19 AP19 NA - 244 5 AF11 AN8 - 211 4 AM19 AH19 - 245 5 AM8 AG11 NA - 212 4 AJ19 AP18 VREF 246 5 AL8 AK9 VREF 213 4 AF18 AP17 NA - 247 5 AH10 AN7 - 214 4 AJ18 AL18 NA VREF 248 5 AE12 AJ9 NA - 215 5 AM18 AL17 None IO_LVDS_DLL 249 5 AM7 AL7 NA - 216 5 AH17 AM17 NA VREF 250 5 AG10 AN6 NA - 217 5 AJ17 AG17 NA - 251 5 AK8 AH9 - 218 5 AP16 AL16 VREF 252 5 AP5 AJ8 VREF 219 5 AJ16 AM16 - 253 5 AE11 AN5 - 220 5 AK16 AP15 NA - 254 5 AF10 AM6 NA - 221 5 AL15 AH16 - 255 5 AL6 AG9 VREF 222 5 AN15 AF16 - 256 5 AH8 AP4 - 223 5 AP14 AE16 NA - 257 5 AN4 AJ7 NA - 224 5 AK15 AJ15 VREF 258 5 AM5 AK6 - 225 5 AH15 AN14 - 259 6 AF8 AH6 - 226 5 AK14 AG15 NA - 260 6 AK3 AE9 - 227 5 AM13 AF15 NA - 261 6 AL2 AD10 - 228 5 AG14 AP13 NA - 262 6 AH4 AL1 NA VREF 229 5 AE14 AE15 - 263 6 AK1 AG6 NA - 230 5 AN13 AG13 VREF 264 6 AK2 AF7 NA - 231 5 AH14 AP12 - 265 6 AG5 AJ3 VREF 232 5 AJ14 AL14 NA - 266 6 AJ2 AD9 - 233 5 AF13 AN12 - 267 6 AH2 AC10 - 234 5 AF14 AP11 - 268 6 AF5 AH3 NA - 235 5 AN11 AH13 NA - 269 6 AG3 AE8 - 236 5 AM12 AL12 - 270 6 AG2 AE7 - 237 5 AJ13 AP10 VREF 271 6 AG1 AF6 VREF 238 5 AK12 AM10 NA - 272 6 AG4 AC9 - 239 5 AP9 AK11 NA - 273 6 AF3 AE6 - Module 4 of 4 44 www.xilinx.com 1-800-255-7778 DS096-4 (v1.1) July 29, 2004 Advance Product Specification R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 7: FG1156 Differential Pin Pair Summary: XQV2000E P N Table 7: FG1156 Differential Pin Pair Summary: XQV2000E Other P N Other Pair Bank Pin Pin AO Functions Pair Bank Pin Pin AO Functions 274 6 AF4 AF1 NA VREF 308 7 T10 R6 NA - 275 6 AF2 AB10 NA - 309 7 R5 R2 - 276 6 AE1 AC8 NA - 310 7 P5 P1 VREF 277 6 AE3 AD5 VREF 311 7 P2 R8 - 278 6 AD1 AC7 - 312 7 N1 R9 - 279 6 AD2 AD6 NA - 313 7 R10 P4 NA - 280 6 AC1 AB8 VREF 314 7 N2 P8 - 281 6 AC2 AC5 - 315 7 P7 P6 - 282 6 AC3 AA9 - 316 7 N4 M1 VREF 283 6 AD4 AC4 - 317 7 N3 N6 NA - 284 6 AB6 AA8 NA - 318 7 M2 P9 NA - 285 6 Y10 AB1 NA - 319 7 M3 N7 NA - 286 6 AA7 AB2 NA - 320 7 M4 P10 - 287 6 AA1 AA4 VREF 321 7 N8 L1 - 288 6 AB4 Y9 - 322 7 N9 L2 - 289 6 Y8 AA2 - 323 7 K1 M7 VREF 290 6 AA5 AA6 NA - 324 7 L4 M8 NA - 291 6 Y7 AB3 - 325 7 L5 J1 - 292 6 W10 Y1 - 326 7 K3 J2 VREF 293 6 Y2 Y5 VREF 327 7 J3 L7 NA - 294 6 W2 W9 - 328 7 H2 M9 NA - 295 6 Y4 W7 - 329 7 K6 J4 NA VREF 296 6 Y6 W1 NA - 330 7 G2 L8 - 297 6 W3 W6 NA - 331 7 K7 H3 - 298 6 W4 V9 NA - 332 7 J5 G3 VREF 299 6 V1 W5 VREF 333 7 H5 L9 - 300 6 U2 V7 - 334 7 H4 J6 - 301 6 U1 V6 NA VREF 335 7 K8 G4 NA - 302 7 U4 U9 - 336 7 F2 J7 - 303 7 U5 U7 NA VREF 337 7 L10 F3 - 304 7 U6 U3 - 338 7 H6 E1 VREF 305 7 T6 T3 VREF 339 7 E2 G5 NA - 306 7 T4 T9 NA - 340 7 D1 K9 NA - 307 7 R1 T5 NA - DS096-4 (v1.1) July 29, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 45 R QPro Virtex-E 1.8V QML High-Reliability FPGAs Table 7: FG1156 Differential Pin Pair Summary: XQV2000E P N Other Pair Bank Pin Pin AO Functions 341 7 J8 E3 NA VREF 342 7 D2 E4 - 343 7 D3 F4 - Revision History The following table shows the revision history for this document. Date Version 05/19/03 1.0 Initial Xilinx release. 07/29/04 1.1 * * Module 4 of 4 46 Revision Removed CB228 and HQ240 package pinout information (not offered). Added "VREF" to pin description of pin B15 in package BG432 (XQV600E). www.xilinx.com 1-800-255-7778 DS096-4 (v1.1) July 29, 2004 Advance Product Specification