25
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51336/72V51346/72V51356 3.3V, MULTI-QUEUE FIFO (8 QUEUES)
36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
PACKET READY FLAG
The Multi-Queue FIFO provides the user with a Packet Ready feature.
During a Master Reset the state of the PKT input (packet ready mode select),
determines whether the device will operate in packet ready mode. A discrete
flag output PR, provides a packet ready status of the active queue, selected on
the read port. A packet ready status is maintained for all queues, however only
the queue selected on the read port has its packet ready status output to the active
PR flag. The PR output flag for the active queue on the read port, is LOW
whenever the active queue has one or more full packets of data within its queue,
available for reading. If less than a full packet is available then the PR flag will
be HIGH, packet not ready. In Packet mode, words cannot be read from a queue
until a complete packet has been written into that queue, regardless of REN.
When packet ready mode is selected the Programmable Almost Empty bus,
PAEn, actually becomes the Packet Ready bus, PRn. The PRn bus now
providing packet ready status for all queues including those not currently
selected on the read port. Both Polled and Direct modes of operation are
available and selectable during a Master Reset.
When the Multi-Queue is selected for packet ready mode the device must also
be configured with a 36 bit write port and 36 bit read port. The two most significant
bits of the 36 bit data bus can now be used as “packet markers”. On the write
port these are bits D34, D35 and on the read port Q34, Q35. All four bits are
monitored by the packet control logic as data is written into and read out from
the FIFO queues. The packet ready status for individual queues is then
determined by the packet ready logic.
On the write port D34 is used to “mark” the word currently being written into
the selected FIFO queue as a “Transmit Start of Packet”, TSOP. When the user
requires a word being written in to be marked as the start of a packet, the TSOP
input must be HIGH for the same WCLK rising edge as the word that is written
in. This marker is effectively a “tag” on the end of the word to be marked as it
is being written in to its respective queue. This TSOP marker will remain stored
in the FIFO queue along with the data it was written in with until the word in turn
is read out of the queue via the read port. This marker will be read out on Q34
and is now denoted with the name, “Receive Start of Packet”, RSOP.
The second marker that is used on the write port is D35 and is used to “mark”
the word currently being written into the selected FIFO queue as a “Transmit
End of Packet”, TEOP. When the user requires a word being written in to be
marked as the end of a packet, the TEOP input must be HIGH for the same WCLK
rising edge as the word that is written in. This marker is effectively a “tag” on the
end of the word to be marked as it is being written in to its respective queue. This
TEOP marker will remain stored in the FIFO queue along with the data it was
written in with until the word in turn is read out of the queue via the read port.
This marker will be read out on Q35 and is now denoted with the name, “Receive
End of Packet”, REOP.
The packet ready logic monitors all start and end of packet markers both as
they enter respective queues via the write port and as they exit queues via the
read port. The logic both increments and decrements a packet counter, which
is provided for each queue. This functionality of the packet ready logic means
that status is provided as to whether or not at least one full packet of data is
available within a respective queue. For example, if a TSOP has been received
and some time later a TEOP is received a full packet of data is deemed to be
available, and the PR flag will go active LOW. Consequently if reads begin from
that queue and the RSOP is detected on the output port as data is being read
out, then there is no longer deemed to be a full packet of data available and PR
will go inactive HIGH provided, that no other full packets are available.
Essentially, a partial packet in a queue is regarded as a packet not being ready
and PR will be HIGH. In Packet mode, words cannot be read from a queue until
a complete packet has been written into that queue, regardless of REN. In Packet
mode the Multi-Queue device will prevent reads from a selected queue until a
TSOP marker followed (at some later time), by a TEOP marker has been written.
The PR flag will go active LOW to indicate that a complete packet is available
within the queue. Once the RSOP marker is read out, the PR flag will go HIGH,
indicating that a complete packet is no longer present, (assuming that there are
no more packets in the queue). The user may proceed with the reading
operation until the current packet has been read out and no further complete
packets are available. If during that time another complete packet has been
written into the queue and the PR flag has again gone active, then reads from
the new packet may follow after the current packet has been completely read
out.
The packet counters therefore look for start of packet markers followed by end
of packet markers and regard data in between the TSOP and TEOP as a full
packet of data. The packet monitoring has no limitation as to how many packets
are written into a FIFO queue, the only constraint of course being the depth of
the queue. Note, that there is a minimum allowable packet size of four writes, that
is within a TSOP marker and TEOP marker there must be two other write
operations.
The packet logic does expect a TSOP marker to be followed by a TEOP
marker.
If a second TSOP marker is read after a first, then it is ignored and the logic
regards data between the first TSOP and the first subsequent TEOP as the full
packet. The same is true for TEOP, a second consecutive TEOP mark is ignored.
On the write side the 2nd consecutive TSOP and TEOP is ignored. On the read
side the user should regard a packet as being between the first RSOP and the
first subsequent REOP.
The user may also wish to implement the use of an “Almost End of Packet”
marker, AEOP. For example, the AEOP can be set on input D33, and this will
pass straight through the FIFO queue, remaining attached as a “tag” to the 36
bit long word it was written with, being read out on Q33. The purpose of this AEOP
marker is to provide the entity reading data from the Multi-Queue device that the
end of packet is a fixed (known) number of reads away from the end of packet.
This is a useful feature when due to latencies within the system, monitoring the
REOP marker alone does not prevent “over reading” of the data from the queue
selected. For example, an AEOP marker set 4 writes before the TEOP marker
provides the device connected to the read port with and “almost end of packet”
indication 4 cycles before the end of packet.
The AEOP can be set any number of words before the end of packet
determined by the user requirements or latencies involved in the system.
Ideally a switch should be performed one cycle before the TEOP is read out.
So on the next cycle the last word of a packet (TEOP) is read, and on the following
cycle the next word of the new queue is read out. Once a packet is being read
out it must be read to completion. That is, the user cannot switch to a new queue
in the middle of a packet being read out. For example, when the RSOP marker
is read out of a queue, marking the start of Packet, that packet must be read to
completion, until its associated REOP, (End of Packet Marker) has been read
out, again the queue switch taking place one cycle before the "End of Packet"
is read out.
See Figure 26, Data Input (Transmit) Packet Ready Mode of Operation and
Figure 27, Data Output (Receive) Packet Ready Mode of Operation.
PACKET READY – MODULO OPERATION
When utilizing the Multi-Queue FIFO device in Packet Ready mode, the user
may also want to consider the implementation of “Modulo” operation or “valid
byte marking”. This may be a requirement when the packets being transferred
through a FIFO queue are in a byte arrangement even though the data bus
width is 36 bits. Here the user may actually be concatenating bytes to form a 36
bit data bus through the Multi-Queue device. In this situation only a limited number
of bytes may actually be part of the packet. This will only occur when the first