SN65LBC180A SN75LBC180A www.ti.com............................................................................................................................................................... SLLS378D - MAY 2000 - REVISED APRIL 2009 LOW-POWER DIFFERENTIAL LINE DRIVER AND RECEIVER PAIRS FEATURES 1 * High-Speed Low-Power LinBICMOSTM Circuitry Designed for Signaling Rates(1) of up to 30 Mbps * Bus-Pin ESD Protection 15 kV HBM * Low Disabled Supply-Current Requirements: 700 A Maximum * Designed for High-Speed Multipoint Data Transmission Over Long Cables * Common-Mode Voltage Range of -7 V to 12 V * Low Supply Current: 15 mA Max * Compatible With ANSI Standard TIA/EIA-485-A and ISO 8482:1987(E) * Positive and Negative Output Current Limiting * Driver Thermal Shutdown Protection SN65LBC180AD (Marked as BL180A) SN65LBC180AN (Marked as 65LBC180A) SN75LBC180AD (Marked as LB180A) SN75LBC180AN (Marked as 75LBC180A) (TOP VIEW) 2 (1) NC R RE DE D GND GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC VCC A B Z Y NC NC -No internal connection Pins 6 and 7 are connected together internally Pins 13 and 14 are connected together internally Signaling rate by TIA/EIA-485-A definition restrict transition times to 30% of the bit duration, and much higher signaling rates may be achieved without this requirement as displayed in the TYPICAL CHARACTERISTICS of this device. DESCRIPTION The SN65LBC180A and SN75LBC180A differential driver and receiver pairs are monolithic integrated circuits designed for bidirectional data communication over long cables that take on the characteristics of transmission lines. They are balanced, or differential, voltage mode devices that are compatible with ANSI standard TIA/EIA-485-A and ISO 8482:1987(E). The A version offers improved switching performance over its predecessors without sacrificing significantly more power. These devices combine a differential line driver and differential input line receiver and operate from a single 5-V power supply. The driver differential outputs and the receiver differential inputs are connected to separate terminals for full-duplex operation and are designed to present minimum loading to the bus when powered off (VCC = 0). These parts feature wide positive and negative common-mode voltage ranges, making them suitable for point-to-point or multipoint data bus applications. The devices also provide positive and negative current limiting for protection from line fault conditions. The SN65LBC180A is characterized for operation from -40C to 85C, and the SN75LBC180A is characterized for operation from 0C to 70C. FUNCTION TABLE (1) DRIVER (1) RECEIVER DIFFERENTIAL INPUTS A-B ENABLE RE OUTPUT R Z VID 0.2 V L H H L -0.2 V < VID < 0.2 V L ? L H VID -0.2 V L L L Z Z X H Z H H L Open circuit L H INPUT D ENABLE DE H H L H X OPEN OUTPUTS Y H = high level, L = low level, ? = indeterminate, X = irrelevant, Z = high impedance (off) 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinBICMOS is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2000-2009, Texas Instruments Incorporated SN65LBC180A SN75LBC180A SLLS378D - MAY 2000 - REVISED APRIL 2009............................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. LOGIC SYMBOL(1) DE 4 EN1 5 R 9 1 10 3 12 EN2 2 11 2 9 Z D A RE B R (1) This symbol is in accordance ANSI/IEEE Std 91-1984 and Publication 617-12. 4 DE Y 1 D RE LOGIC DIAGRAM (POSITIVE LOGIC) 5 10 3 2 with IEC 12 11 Y Z A B AVAILABLE OPTIONS (1) PACKAGE (1) (2) 2 TA SMALL OUTLINE (2) (D) PLASTIC DUAL-IN-LINE (N) 0C to 70C SN75LBC180AD SN75LBC180AN -40C to 85C SN65LBC180AD SN65LBC180AN For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. The D package is available taped and reeled. Add an R suffix to the part number (i.e., SN65LBC180ADR). Submit Documentation Feedback Copyright (c) 2000-2009, Texas Instruments Incorporated Product Folder Link(s): SN65LBC180A SN75LBC180A SN65LBC180A SN75LBC180A www.ti.com............................................................................................................................................................... SLLS378D - MAY 2000 - REVISED APRIL 2009 SCHEMATICS OF INPUTS AND OUTPUTS D, DE, and RE Inputs VCC 100 k 1 k Input 8V A Input B Input VCC 16 V 100 k VCC 4 k 4 k 16 V 18 k Input 18 k Input 100 k 16 V 16 V 4 k 4 k Y AND Z Outputs VCC R Output VCC 16 V 40 Output Output 8V 16 V Copyright (c) 2000-2009, Texas Instruments Incorporated Product Folder Link(s): SN65LBC180A SN75LBC180A Submit Documentation Feedback 3 SN65LBC180A SN75LBC180A SLLS378D - MAY 2000 - REVISED APRIL 2009............................................................................................................................................................... www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) UNIT VCC Supply voltage range (2) VI Input voltage range A, B Voltage range D, R, DE, RE IO -0.3 V to 6 V -10 V to 15 V -0.3 V to VCC + 0.5 V Receiver output current 10 mA Continuous total power dissipation (3) Internally limited Total power dissipation ESD (1) (2) (3) (4) See Dissipation Rating Table Bus terminals and GND HBM (Human Body Model) EIA/JESD22-A114 (4) 15 kV All pins HBM (Human Body Model) EIA/JESD22-A114 (4) 3 kV MM (Machine Model) EIA/JESD22-A115 400 V CDM (Charge Device Model) EIA/JESD22-C101 1.5 kV Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND except for differential input or output voltages. The maximum operating junction temperature is internally limited. Use the dissipation rating table to operate below this temperature. Tested in accordance with MIL-STD-883C, Method 3015.7. DISSIPATION RATINGS (1) PACKAGE TA 25C POWER RATING DERATING FACTOR (1) ABOVE TA = 25C TA = 70C POWER RATING TA = 85C POWER RATING D 950 mW 7.6 mW/C 608 mW 494 mW N 1150 mW 9.2 mW/C 736 mW 598 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. RECOMMENDED OPERATING CONDITIONS VCC Supply voltage VIH High-level input voltage D, DE, and RE VIL Low-level input voltage D, DE, and RE VID Differential input voltage (1) MIN NOM MAX UNIT 4.75 5 5.25 V 2 VCC V 0 0.8 V (2) 12 V -7 12 V -12 VO VI Voltage at any bus terminal (separately or common mode) A, B, Y, or Z VIC IOH High-level output current IOL Low-level output current TA Operating free-air temperature (1) (2) 4 Y or Z -60 R mA -8 Y or Z 60 R 8 SN65LBC180A -40 85 SN75LBC180A 0 70 mA C Differential input/output bus voltage is measured at the noninverting terminal with respect to the inverting terminal. The algebraic convention, where the least positive (more negative) limit is designated minimum, is used in this data sheet. Submit Documentation Feedback Copyright (c) 2000-2009, Texas Instruments Incorporated Product Folder Link(s): SN65LBC180A SN75LBC180A SN65LBC180A SN75LBC180A www.ti.com............................................................................................................................................................... SLLS378D - MAY 2000 - REVISED APRIL 2009 DRIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER VIK Input clamp voltage |VOD| MIN TYP (1) TEST CONDITIONS II = -18 mA -0.8 RL = 54 , See Figure 1 SN65LBC180A 1 1.5 3 SN75LBC180A 1.1 1.5 3 RL = 60 , See Figure 2 SN65LBC180A 1 1.5 3 SN75LBC180A 1.1 1.5 3 Differential output voltage magnitude | VOD | Change in magnitude of differential output See Figure 1 and Figure 2 voltage (2) VOC(ss) Steady-state common-mode output voltage VOC Change in steady-state common-mode output voltage (2) IO Output current with power off VCC = 0 , IIH High-level input current VI = 2 V -100 IIL Low-level input current VI = 0.8 V -100 IOS Short-circuit output current -7 V VO 12 V -250 ICC (1) (2) -0.2 1.8 2.4 VO = -7 V to 12 V UNIT V V V 0.2 V 2.8 V See Figure 1 VI = 0 or VCC, No load Supply current MAX -1.5 -0.1 0.1 -10 10 V A A A 70 250 Receiver disabled and driver enabled 5.5 9 Receiver disabled and driver disabled 0.5 1 Receiver enabled and driver enabled 8.5 15 mA mA All typical values are at VCC = 5 V, TA = 25C. | VOD | and | VOC | are the changes in the steady-state magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a low level. DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low-to-high-level output 2 6 12 ns tPHL Propagation delay time, high-to-low-level output 2 6 12 ns tsk(p) Pulse skew ( | tPLH - tPHL | ) 0.3 1 ns tr Differential output signal rise time 4 7.5 11 ns tf Differential output signal fall time 4 7.5 11 ns tPZH Propagation delay time, high-impedance-to-high-level output RL = 110 , See Figure 4 12 22 ns tPZL Propagation delay time, high-impedance-to-low-level output RL = 110 , See Figure 5 12 22 ns tPHZ Propagation delay time, high-level-to-high-impedance output RL = 110 , See Figure 4 12 22 ns tPLZ Propagation delay time, low-level-to-high-impedance output RL = 110 , See Figure 5 12 22 ns RL = 54 , CL = 50 pF, See Figure 3 Copyright (c) 2000-2009, Texas Instruments Incorporated Product Folder Link(s): SN65LBC180A SN75LBC180A Submit Documentation Feedback 5 SN65LBC180A SN75LBC180A SLLS378D - MAY 2000 - REVISED APRIL 2009............................................................................................................................................................... www.ti.com RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX 0.2 UNIT VIT+ Positive-going input threshold voltage IO = -8 mA VIT- Negative-going input threshold voltage IO = 8 mA -0.2 Vhys Hysteresis voltage ( VIT+ - VIT-) VIK Enable-input clamp voltage II = -18 mA -1.5 -0.8 V VOH High-level output voltage VID = 200 mV, IOH = -8 mA 4 4.9 V VOL Low-level output voltage VID = -200 mV, IOL = 8 mA IOZ High-impedance-state output current VO = 0 V to VCC IIH High-level enable-input current VIH = 2.4 V -100 A IIL Low-level enable-input current VIL = 0.4 V -100 A V 50 0.1 II Bus input current (1) V 1 A 0.4 1 0.5 1 mA -0.8 -0.8 -0.4 -0.3 Receiver enabled and driver disabled VI = 0 or VCC, Receiver disabled and driver disabled No load Receiver enabled and driver enabled Supply current 0.8 Other input at 0 V VI = -7 V, VCC = 5 V VI = -7 V, VCC = 0 ICC mV -1 VI = 12 V, VCC = 5 V VI = 12 V, VCC = 0 V 4.5 7.5 0.5 1 8.5 15 mA All typical values are at VCC = 5 V and TA = 25C. RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tsk(p) Pulse skew ( | tPHL - tPLH | ) tr Output signal rise time tf Output signal fall time tPZH Output enable time to high level tPZL Output enable time to low level tPHZ Output disable time from high level tPLZ Output disable time from low level VID = -1.5 V to 1.5 V, See Figure 7 See Figure 7 CL = 10 pF, See Figure 8 MIN TYP MAX 7 13 20 ns 7 UNIT 13 20 ns 0.5 1.5 ns 2.1 3.3 ns 2.1 3.3 ns 30 45 ns 30 45 ns 20 40 ns 20 40 ns PARAMETER MEASUREMENT INFORMATION 27 0 or 3 V VOD 27 VOC Figure 1. Driver VOD and VOC 6 Submit Documentation Feedback Copyright (c) 2000-2009, Texas Instruments Incorporated Product Folder Link(s): SN65LBC180A SN75LBC180A SN65LBC180A SN75LBC180A www.ti.com............................................................................................................................................................... SLLS378D - MAY 2000 - REVISED APRIL 2009 PARAMETER MEASUREMENT INFORMATION (continued) Vtest R1 375 Y D RL = 60 0 V or 3 V VOD Z R2 375 -7 V < Vtest < 12 V Vtest Figure 2. Driver VOD 3V Input Generator (see Note A) RL = 54 50 1.5 V CL = 50 pF (see Note B) 0V tPLH VO Output 3V 1.5 V tPHL 90% 50% 10% - 1.5 V tf tr TEST CIRCUIT 1.5 V VOLTAGE WAVEFORMS A. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, 50% duty cycle, tr 6 ns, tf 6 ns, ZO = 50 . B. CL includes probe and jig capacitance. Figure 3. Driver Test Circuit and Voltage Waveforms Output S1 3V Input 1.5 V 1.5 V 3V Generator (see Note A) 50 CL = 50 pF (see Note B) tPZH RL = 110 0V 0.5 V VOH Output TEST CIRCUIT 2.3 V tPHZ Voff 0 V VOLTAGE WAVEFORMS A. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, 50% duty cycle, tr 6 ns, tf 6 ns, ZO = 50 . B. CL includes probe and jig capacitance. Figure 4. Driver Test Circuit and Voltage Waveforms Copyright (c) 2000-2009, Texas Instruments Incorporated Product Folder Link(s): SN65LBC180A SN75LBC180A Submit Documentation Feedback 7 SN65LBC180A SN75LBC180A SLLS378D - MAY 2000 - REVISED APRIL 2009............................................................................................................................................................... www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) 5V 3V Input RL = 110 S1 1.5 V 1.5 V 0V Output 0V tPZL tPLZ Generator (see Note A) CL = 50 pF (see Note B) 50 5V 0.5 V 2.3 V Output VOL TEST CIRCUIT VOLTAGE WAVEFORMS A. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, 50% duty cycle, tr 6 ns, tf 6 ns, ZO = 50 . B. CL includes probe and jig capacitance. Figure 5. Driver Test Circuit and Voltage Waveforms IO VID VO Figure 6. Receiver VOH and VOL 3V Input Input Generator (see Note A) 1.5 V 1.5 V Output 50 1.5 V CL = 10 pF (see Note B) 0V 1.3 V 10% 1.3 V tr TEST CIRCUIT VOH 90% Output 0V tPHL tPLH VOL tf VOLTAGE WAVEFORMS A. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, 50% duty cycle, tr 6 ns, tf 6 ns, ZO = 50 . B. CL includes probe and jig capacitance. Figure 7. Receiver Test Circuit and Voltage Waveforms 8 Submit Documentation Feedback Copyright (c) 2000-2009, Texas Instruments Incorporated Product Folder Link(s): SN65LBC180A SN75LBC180A SN65LBC180A SN75LBC180A www.ti.com............................................................................................................................................................... SLLS378D - MAY 2000 - REVISED APRIL 2009 PARAMETER MEASUREMENT INFORMATION (continued) S1 1.5 V 2 k -1.5 V S2 5V CL = 10 pF (see Note B) Input Generator (see Note A) 5 k 50 S3 TEST CIRCUIT Input 1.5 V 3V S1 to 1.5 V S2 Open S3 Closed 0V Input 1.5 V tPZH 3V S1 to -1.5 V S2 Closed S3 Open 0V tPZL VOH 4.5 V 1.5 V Output Output 1.5 V 0V VOL 3V S1 to 1.5 V S2 Closed S3 Closed 0V 1.5 V Input Input tPHZ 3V S1 to -1.5 V S2 Closed S3 Closed 0V 1.5 V tPLZ 1.3 V VOH Output 0.5 V Output 0.5 V 1.3 V VOL VOLTAGE WAVEFORMS A. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, 50% duty cycle, tr 6 ns, tf 6 ns, ZO = 50 . B. CL includes probe and jig capacitance. Figure 8. Receiver Output Enable and Disable Times Copyright (c) 2000-2009, Texas Instruments Incorporated Product Folder Link(s): SN65LBC180A SN75LBC180A Submit Documentation Feedback 9 SN65LBC180A SN75LBC180A SLLS378D - MAY 2000 - REVISED APRIL 2009............................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS Receiver Output Driver Input 120 120 Driver Input Receiver Output Figure 9. Typical Waveform of Nonreturn-to-Zero (NRZ), Pseudorandom Binary Sequence (PRBS) Data at 100 Mbps Through 15m, of CAT 5 Unshielded Twisted Pair (UTP) Cable TIA/EIA-485-A defines a maximum signaling rate as that in which the transition time of the voltage transition of a logic-state change remains less than or equal to 30% of the bit length. Transition times of greater length perform quite well even though they do not meet the standard by definition. 10 Submit Documentation Feedback Copyright (c) 2000-2009, Texas Instruments Incorporated Product Folder Link(s): SN65LBC180A SN75LBC180A SN65LBC180A SN75LBC180A www.ti.com............................................................................................................................................................... SLLS378D - MAY 2000 - REVISED APRIL 2009 TYPICAL CHARACTERISTICS (continued) AVERAGE SUPPLY CURRENT vs FREQUENCY LOGIC INPUT CURRENT vs INPUT VOLTAGE -30 40 I I - Logic Input Current - A I CC - Average Supply Current - mA 30 VCC = 5 V TA = 25C Driver 35 RL = 54 CL = 50 pF 25 VCC = 5 V TA = 25C 50% Duty Cycle 20 15 10 5 0 0.05 Receiver CL = 10 pF 0.5 1 2 5 -25 -20 -15 -10 -5 10 20 0 30 0 1 2 BUS INPUT CURRENT vs INPUT VOLTAGE DRIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT VOL - Driver Low-Level Output Voltage - V I I - Bus Input Current - A 5 Figure 11. VCC = 5 V TA = 25C 400 200 0 -200 -400 -600 -8 4 Figure 10. 800 600 3 VI - Input Voltage - V f - Frequency - MHz 2 VCC = 5 V TA = 25C 1.75 1.50 1.25 1 0.75 0.50 0.25 0 -6 -4 -2 0 2 4 6 VI - Input Voltage - V 8 10 12 0 10 20 30 40 50 60 70 80 IOL - Low-Level Output Current - mA Figure 12. Copyright (c) 2000-2009, Texas Instruments Incorporated Product Folder Link(s): SN65LBC180A SN75LBC180A Figure 13. Submit Documentation Feedback 11 SN65LBC180A SN75LBC180A SLLS378D - MAY 2000 - REVISED APRIL 2009............................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) PROPAGATION DELAY TIME vs CASE TEMPERATURE 14 5 TA = 25C Receiver 4.5 13 4 VCC = 5.25 V Propagation Delay Time - ns VOH - Driver High-Level Output Voltage - V DRIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 3.5 3 2.5 VCC = 5 V 2 VCC = 4.75 V 1.5 12 11 10 9 8 1 7 0.5 6 0 0 -10 -20 -30 -40 -50 -60 -70 IOH - High-Level Output Current - mA -80 VCC = 5 V Driver Tested Per Figure 3 Receiver Tested Per Figure 7 Square Wave Input at 50% Duty Cycle 5 -50 Driver 0 50 Case Temperature - C Figure 14. 12 Submit Documentation Feedback 100 Figure 15. Copyright (c) 2000-2009, Texas Instruments Incorporated Product Folder Link(s): SN65LBC180A SN75LBC180A SN65LBC180A SN75LBC180A www.ti.com............................................................................................................................................................... SLLS378D - MAY 2000 - REVISED APRIL 2009 APPLICATION INFORMATION SN65LBC180A SN75LBC180A SN65LBC180A SN75LBC180A RT RT Up to 32 Unit Loads A. The line should be terminated at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept as short as possible. One SN65LBC180A typically represents less than one unit load. Figure 16. Typical Application Circuit Revision History Copyright (c) 2000-2009, Texas Instruments Incorporated Product Folder Link(s): SN65LBC180A SN75LBC180A Submit Documentation Feedback 13 PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65LBC180AD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LBC180ADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LBC180ADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LBC180ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LBC180AN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN65LBC180ANE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN75LBC180AD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LBC180ADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LBC180ADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LBC180ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LBC180AN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN75LBC180ANE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Apr-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LBC180ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN75LBC180ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Apr-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LBC180ADR SOIC D 14 2500 333.2 345.9 28.6 SN75LBC180ADR SOIC D 14 2500 333.2 345.9 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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