1
FEATURES
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC
R
RE
DE
D
GND
GND
VCC
VCC
A
B
Z
Y
NC
SN65LBC180AD(MarkedasBL180A)
SN65LBC180AN(Markedas65LBC180A)
SN75LBC180AD(MarkedasLB180A)
SN75LBC180AN(Markedas75LBC180A)
(TOP VIEW)
NC −Nointernalconnection
Pins6and7areconnectedtogetherinternally
Pins13and14areconnectedtogetherinternally
DESCRIPTION
SN65LBC180A
SN75LBC180A
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............................................................................................................................................................... SLLS378D – MAY 2000 – REVISED APRIL 2009
LOW-POWER DIFFERENTIAL LINE DRIVER AND RECEIVER PAIRS
2
•High-Speed Low-Power LinBICMOS™ CircuitryDesigned for Signaling Rates
(1)
of up to30 Mbps•Bus-Pin ESD Protection 15 kV HBM•Low Disabled Supply-Current Requirements:700 µA Maximum•Designed for High-Speed Multipoint DataTransmission Over Long Cables•Common-Mode Voltage Range of – 7 V to 12 V•Low Supply Current: 15 mA Max•Compatible With ANSI Standard TIA/EIA-485-Aand ISO 8482:1987(E)
•Positive and Negative Output Current Limiting•Driver Thermal Shutdown Protection(1)
Signaling rate by TIA/EIA-485-A definition restrict transitiontimes to 30% of the bit duration, and much higher signalingrates may be achieved without this requirement as displayedin the TYPICAL CHARACTERISTICS of this device.
The SN65LBC180A and SN75LBC180A differential driver and receiver pairs are monolithic integrated circuitsdesigned for bidirectional data communication over long cables that take on the characteristics of transmissionlines. They are balanced, or differential, voltage mode devices that are compatible with ANSI standardTIA/EIA-485-A and ISO 8482:1987(E). The A version offers improved switching performance over itspredecessors without sacrificing significantly more power.
These devices combine a differential line driver and differential input line receiver and operate from a single 5-Vpower supply. The driver differential outputs and the receiver differential inputs are connected to separateterminals for full-duplex operation and are designed to present minimum loading to the bus when powered off(V
CC
= 0). These parts feature wide positive and negative common-mode voltage ranges, making them suitablefor point-to-point or multipoint data bus applications. The devices also provide positive and negative currentlimiting for protection from line fault conditions. The SN65LBC180A is characterized for operation from – 40 ° C to85 ° C, and the SN75LBC180A is characterized for operation from 0 ° C to 70 ° C.
FUNCTION TABLE
(1)
DRIVER RECEIVER
DIFFERENTIAL INPUTS ENABLE OUTPUTOUTPUTSINPUT ENABLE
A – B RE RD DE
Y Z V
ID
≥0.2 V L HH H H L -0.2 V < V
ID
< 0.2 V L ?L H L H V
ID
≤-0.2 V L LX L Z Z X H ZOPEN H H L Open circuit L H
(1) H = high level, L = low level, ? = indeterminate, X = irrelevant, Z = high impedance (off)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2LinBICMOS is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000 – 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
EN2
EN1
B
A
Z
Y
R
RE
D
DE
11
12
10
9
2
3
5
4
2
1
1
R
RE
DE
D
B
A
Z
Y
11
12
10
9
2
3
4
5
SN65LBC180A
SN75LBC180A
SLLS378D – MAY 2000 – REVISED APRIL 2009 ...............................................................................................................................................................
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
LOGIC SYMBOL
(1)
LOGIC DIAGRAM (POSITIVE LOGIC)
(1) This symbol is in accordance withANSI/IEEE Std 91-1984 and IECPublication 617-12.
AVAILABLE OPTIONS
(1)
PACKAGE
PLASTICT
A
SMALL OUTLINE
(2)
DUAL-IN-LINE(D)
(N)
0 ° C to 70 ° C SN75LBC180AD SN75LBC180AN– 40 ° C to 85 ° C SN65LBC180AD SN65LBC180AN
(1) For the most current package and ordering information, see the Package Option Addendum at the endof this document, or see the TI website at www.ti.com .(2) The D package is available taped and reeled. Add an R suffix to the part number (i.e.,SN65LBC180ADR).
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Product Folder Link(s): SN65LBC180A SN75LBC180A
SCHEMATICS OF INPUTS AND OUTPUTS
Input
100 kΩ4 kΩ
18 kΩ
4 kΩ
16 V
16 V
Input
100 kΩ
4 kΩ
18 kΩ
4 kΩ
16 V
16 V
VCC VCC
Output
VCC
A Input B Input
R Output
40 Ω
8 V
1 kΩ
8 V
Input
VCC
D, DE, and RE Inputs
100 kΩ
16 V
16 V
Output
VCC
Y AND Z Outputs
SN65LBC180A
SN75LBC180A
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............................................................................................................................................................... SLLS378D – MAY 2000 – REVISED APRIL 2009
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ABSOLUTE MAXIMUM RATINGS
(1)
DISSIPATION RATINGS
RECOMMENDED OPERATING CONDITIONS
SN65LBC180A
SN75LBC180A
SLLS378D – MAY 2000 – REVISED APRIL 2009 ...............................................................................................................................................................
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over operating free-air temperature range (unless otherwise noted)
UNIT
V
CC
Supply voltage range
(2)
– 0.3 V to 6 VV
I
Input voltage range A, B – 10 V to 15 VVoltage range D, R, DE, RE – 0.3 V to V
CC
+ 0.5 VI
O
Receiver output current ± 10 mAContinuous total power dissipation
(3)
Internally limitedTotal power dissipation See Dissipation Rating TableBus terminals and GND HBM (Human Body Model) EIA/JESD22-A114
(4)
± 15 kVAll pins HBM (Human Body Model) EIA/JESD22-A114
(4)
± 3 kVESD
MM (Machine Model) EIA/JESD22-A115 ± 400 VCDM (Charge Device Model) EIA/JESD22-C101 ± 1.5 kV
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values are with respect to GND except for differential input or output voltages.(3) The maximum operating junction temperature is internally limited. Use the dissipation rating table to operate below this temperature.(4) Tested in accordance with MIL-STD-883C, Method 3015.7.
T
A
≤25 ° C DERATING FACTOR
(1)
T
A
= 70 ° C T
A
= 85 ° CPACKAGE
POWER RATING ABOVE T
A
= 25 ° C POWER RATING POWER RATING
D 950 mW 7.6 mW/ ° C 608 mW 494 mWN 1150 mW 9.2 mW/ ° C 736 mW 598 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
MIN NOM MAX UNIT
V
CC
Supply voltage 4.75 5 5.25 VV
IH
High-level input voltage D, DE, and RE 2 V
CC
VV
IL
Low-level input voltage D, DE, and RE 0 0.8 VV
ID
Differential input voltage
(1)
– 12
(2)
12 VV
O
V
I
Voltage at any bus terminal (separately or common mode) A, B, Y, or Z – 7 12 VV
IC
Y or Z – 60I
OH
High-level output current mAR – 8Y or Z 60I
OL
Low-level output current mAR 8SN65LBC180A – 40 85T
A
Operating free-air temperature ° CSN75LBC180A 0 70
(1) Differential input/output bus voltage is measured at the noninverting terminal with respect to the inverting terminal.(2) The algebraic convention, where the least positive (more negative) limit is designated minimum, is used in this data sheet.
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DRIVER ELECTRICAL CHARACTERISTICS
DRIVER SWITCHING CHARACTERISTICS
SN65LBC180A
SN75LBC180A
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............................................................................................................................................................... SLLS378D – MAY 2000 – REVISED APRIL 2009
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
IK
Input clamp voltage I
I
= – 18 mA – 1.5 – 0.8 VSN65LBC180A 1 1.5 3R
L
= 54 Ω,
VSee Figure 1
SN75LBC180A 1.1 1.5 3|V
OD
| Differential output voltage magnitude
SN65LBC180A 1 1.5 3R
L
= 60 Ω,
VSee Figure 2
SN75LBC180A 1.1 1.5 3Change in magnitude of differential outputΔ| V
OD
| See Figure 1 and Figure 2 – 0.2 0.2 Vvoltage
(2)
Steady-state common-mode output 1.8 2.4 2.8 VV
OC(ss)
voltage
See Figure 1Change in steady-state common-mode VΔV
OC
– 0.1 0.1output voltage
(2)
I
O
Output current with power off V
CC
= 0 , V
O
= – 7 V to 12 V – 10 10 µAI
IH
High-level input current V
I
= 2 V – 100 µAI
IL
Low-level input current V
I
= 0.8 V – 100 µAI
OS
Short-circuit output current – 7 V ≤V
O
≤12 V – 250 ± 70 250 mAReceiver disabled and
5.5 9driver enabledV
I
= 0 or V
CC
, Receiver disabled andI
CC
Supply current 0.5 1 mANo load driver disabled
Receiver enabled and
8.5 15driver enabled
(1) All typical values are at V
CC
= 5 V, T
A
= 25 ° C.(2) Δ| V
OD
| and Δ| V
OC
| are the changes in the steady-state magnitude of V
OD
and V
OC
, respectively, that occur when the input ischanged from a high level to a low level.
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output 2 6 12 nst
PHL
Propagation delay time, high-to-low-level output 2 6 12 nsR
L
= 54 Ω, C
L
= 50 pF,t
sk(p)
Pulse skew ( | t
PLH
– t
PHL
| ) 0.3 1 nsSee Figure 3t
r
Differential output signal rise time 4 7.5 11 nst
f
Differential output signal fall time 4 7.5 11 nst
PZH
Propagation delay time, high-impedance-to-high-level output R
L
= 110 Ω, See Figure 4 12 22 nst
PZL
Propagation delay time, high-impedance-to-low-level output R
L
= 110 Ω, See Figure 5 12 22 nst
PHZ
Propagation delay time, high-level-to-high-impedance output R
L
= 110 Ω, See Figure 4 12 22 nst
PLZ
Propagation delay time, low-level-to-high-impedance output R
L
= 110 Ω, See Figure 5 12 22 ns
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RECEIVER ELECTRICAL CHARACTERISTICS
RECEIVER SWITCHING CHARACTERISTICS
PARAMETER MEASUREMENT INFORMATION
VOC
VOD
27 Ω
27 Ω
0 or 3 V
SN65LBC180A
SN75LBC180A
SLLS378D – MAY 2000 – REVISED APRIL 2009 ...............................................................................................................................................................
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over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
IT+
Positive-going input threshold voltage I
O
= – 8 mA 0.2 VV
IT –
Negative-going input threshold voltage I
O
= 8 mA – 0.2 VV
hys
Hysteresis voltage ( V
IT+
– V
IT –
) 50 mVV
IK
Enable-input clamp voltage I
I
= – 18 mA – 1.5 – 0.8 VV
OH
High-level output voltage V
ID
= 200 mV, I
OH
= – 8 mA 4 4.9 VV
OL
Low-level output voltage V
ID
= – 200 mV, I
OL
= 8 mA 0.1 0.8 VI
OZ
High-impedance-state output current V
O
= 0 V to V
CC
– 1 1 µAI
IH
High-level enable-input current V
IH
= 2.4 V – 100 µAI
IL
Low-level enable-input current V
IL
= 0.4 V – 100 µAV
I
= 12 V,
0.4 1V
CC
= 5 VV
I
= 12 V, 0.5 1V
CC
= 0I
I
Bus input current Other input at 0 V mAV
I
= – 7 V,
– 0.8 – 0.4V
CC
= 5 VV
I
= – 7 V, – 0.8
– 0.3V
CC
= 0
Receiver enabled and driver disabled 4.5 7.5V
I
= 0 or V
CC
,I
CC
Supply current Receiver disabled and driver disabled 0.5 1 mANo load
Receiver enabled and driver enabled 8.5 15
(1) All typical values are at V
CC
= 5 V and T
A
= 25 ° C.
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output 7 13 20 nst
PHL
Propagation delay time, high-to-low-level output 7 13 20 nsV
ID
= – 1.5 V to 1.5 V, See Figure 7t
sk(p)
Pulse skew ( | t
PHL
– t
PLH
| ) 0.5 1.5 nst
r
Output signal rise time 2.1 3.3 nst
f
Output signal fall time See Figure 7 2.1 3.3 nst
PZH
Output enable time to high level 30 45 nst
PZL
Output enable time to low level 30 45 nsC
L
= 10 pF, See Figure 8t
PHZ
Output disable time from high level 20 40 nst
PLZ
Output disable time from low level 20 40 ns
Figure 1. Driver V
OD
and V
OC
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VOD
Vtest
R1
375 Ω
0 V or 3 V
Z
D
R2
375 Ω
Vtest
Y
RL = 60 Ω
−7 V < Vtest < 12 V
VOLTAGE WAVEFORMS
10%
tf
tPHL
tr
≈ 1.5 V
≈ − 1.5 V
90%
50%
Output
tPLH
0 V
3 V
1.5 V
Input
TEST CIRCUIT
VO
CL = 50 pF
(see Note B)
RL = 54 Ω
50 Ω
3 V
Generator
(see Note A)
1.5 V
VOLTAGE WAVEFORMS
tPHZ
1.5 V
2.3 V
0.5 V
0 V
3 V
tPZH
Output
Input 1.5 V
S1
3 V
Output
TEST CIRCUIT
50 Ω
VOH
Voff ≈ 0 V
RL = 110 Ω
Generator
(see Note A)
CL = 50 pF
(see Note B)
SN65LBC180A
SN75LBC180A
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............................................................................................................................................................... SLLS378D – MAY 2000 – REVISED APRIL 2009
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 2. Driver V
OD
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤1 MHz, 50% duty cycle, t
r
≤6ns, t
f
≤6 ns, Z
O
= 50 Ω.B. C
L
includes probe and jig capacitance.
Figure 3. Driver Test Circuit and Voltage Waveforms
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤1 MHz, 50% duty cycle, t
r
≤6ns, t
f
≤6 ns, Z
O
= 50 Ω.B. C
L
includes probe and jig capacitance.
Figure 4. Driver Test Circuit and Voltage Waveforms
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VO
VID IO
50 Ω
CL = 10 pF
(see Note B)
Output
1.5 V
0 V
TEST CIRCUIT VOLTAGE WAVEFORMS
1.5 V
3 V
0 V
Input
Output 1.3 V
VOH
VOL
tPHL
tPLH
Input
Generator
(see Note A)
1.5 V
1.3 V
tf
tr
90%
10%
SN65LBC180A
SN75LBC180A
SLLS378D – MAY 2000 – REVISED APRIL 2009 ...............................................................................................................................................................
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PARAMETER MEASUREMENT INFORMATION (continued)
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤1 MHz, 50% duty cycle, t
r
≤6ns, t
f
≤6 ns, Z
O
= 50 Ω.B. C
L
includes probe and jig capacitance.
Figure 5. Driver Test Circuit and Voltage Waveforms
Figure 6. Receiver V
OH
and V
OL
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤1 MHz, 50% duty cycle, t
r
≤6ns, t
f
≤6 ns, Z
O
= 50 Ω.B. C
L
includes probe and jig capacitance.
Figure 7. Receiver Test Circuit and Voltage Waveforms
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Input
3 V
tPZH
1.5 V
1.5 V
0 V
VOH
0 V
0 V
1.5 V
3 V
Input
≈ 1.3 V
VOH
0.5 V
Output
tPHZ
Output
0 V
1.5 V
3 V
Input
tPLZ
Input
3 V
1.5 V
0 V
Output 1.5 V
Output
VOL
≈ 1.3 V
tPZL ≈ 4.5 V
VOL
0.5 V
S1 to 1.5 V
S2 Open
S3 Closed S3 Open
S2 Closed
S1 to −1.5 V
S1 to 1.5 V
S2 Closed
S3 Closed S3 Closed
S2 Closed
S1 to −1.5 V
VOLTAGE WAVEFORMS
TEST CIRCUIT
50 Ω
S3
5 V
S2
2 kΩ
5 kΩ
S1
−1.5 V
1.5 V
Input
Generator
(see Note A)
CL = 10 pF
(see Note B)
SN65LBC180A
SN75LBC180A
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............................................................................................................................................................... SLLS378D – MAY 2000 – REVISED APRIL 2009
PARAMETER MEASUREMENT INFORMATION (continued)
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤1 MHz, 50% duty cycle, t
r
≤6ns, t
f
≤6 ns, Z
O
= 50 Ω.B. C
L
includes probe and jig capacitance.
Figure 8. Receiver Output Enable and Disable Times
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TYPICAL CHARACTERISTICS
Driver Input Receiver Output
120 Ω120 Ω
Receiver Output
Driver Input
SN65LBC180A
SN75LBC180A
SLLS378D – MAY 2000 – REVISED APRIL 2009 ...............................................................................................................................................................
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Figure 9. Typical Waveform of Nonreturn-to-Zero (NRZ), Pseudorandom Binary Sequence (PRBS) Data at100 Mbps Through 15m, of CAT 5 Unshielded Twisted Pair (UTP) Cable
TIA/EIA-485-A defines a maximum signaling rate as that in which the transition time of the voltage transition of alogic-state change remains less than or equal to 30% of the bit length. Transition times of greater length performquite well even though they do not meet the standard by definition.
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Product Folder Link(s): SN65LBC180A SN75LBC180A
−15
−10
−5
00 1 2 3
−20
−25
V − Input Voltage − V
−30
4 5
II− Logic Input Current − Aµ
I
VCC = 5 V
TA = 25°C
0
5
10
15
20
25
30
35
40
Driver
Receiver
0.05 0.5 1 2 5 10 20
− Average Supply Current − mA
f − Frequency − MHz 30
ICC
CL = 10 pF
VCC = 5 V
TA = 25°C
50% Duty Cycle
RL = 54 Ω
CL = 50 pF
IOL − Low-Level Output Current − mA
− Driver Low-Level Output Voltage − VVOL
2
1.75
1.50
1.25
1
0.75
0.50
0.25
00 10 20 30 40 50 60 70 80
VCC = 5 V
TA = 25°C
VI − Input Voltage − V
−600
−400
−200
0
200
400
600
800
−8 −6 −4 −2 0 2 4 6 8 10 12
− Bus Input Current −IIAµ
VCC = 5 V
TA = 25°C
SN65LBC180A
SN75LBC180A
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............................................................................................................................................................... SLLS378D – MAY 2000 – REVISED APRIL 2009
TYPICAL CHARACTERISTICS (continued)
AVERAGE SUPPLY CURRENT LOGIC INPUT CURRENTvs vsFREQUENCY INPUT VOLTAGE
Figure 10. Figure 11.
BUS INPUT CURRENT DRIVER LOW-LEVEL OUTPUT VOLTAGEvs vsINPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT
Figure 12. Figure 13.
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11
10
9
8
−50 0 50
Propagation Delay T ime − ns
12
13
Case Temperature − C
14
100
°
7
6
5
Receiver
Driver
VCC = 5 V
Driver Tested Per Figure 3
Receiver Tested Per Figure 7
Square Wave Input at 50%
Duty Cycle
3.5
3
2.5
2
0 −10 −20 −30 −40 −50 −60
4
4.5
I − High-Level Output Current − mA
5
−70 −80
OH
VOH− Driver High-Level Output Voltage − V
1.5
1
0.5
0
VCC = 4.75 V
VCC = 5 V
VCC = 5.25 V
TA = 25°C
SN65LBC180A
SN75LBC180A
SLLS378D – MAY 2000 – REVISED APRIL 2009 ...............................................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)
DRIVER HIGH-LEVEL OUTPUT VOLTAGE PROPAGATION DELAY TIMEvs vsHIGH-LEVEL OUTPUT CURRENT CASE TEMPERATURE
Figure 14. Figure 15.
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APPLICATION INFORMATION
Up to 32
Unit Loads
RT
RT
SN65LBC180A
SN75LBC180A
SN65LBC180A
SN75LBC180A
SN65LBC180A
SN75LBC180A
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............................................................................................................................................................... SLLS378D – MAY 2000 – REVISED APRIL 2009
A. The line should be terminated at both ends in its characteristic impedance (R
T
= Z
O
). Stub lengths off the main lineshould be kept as short as possible. One SN65LBC180A typically represents less than one unit load.
Figure 16. Typical Application Circuit
Revision History
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN65LBC180AD ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC180ADG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC180ADR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC180ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC180AN ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN65LBC180ANE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN75LBC180AD ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC180ADG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC180ADR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC180ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC180AN ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN75LBC180ANE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Jul-2006
Addendum-Page 1
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Jul-2006
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65LBC180ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN75LBC180ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Apr-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LBC180ADR SOIC D 14 2500 333.2 345.9 28.6
SN75LBC180ADR SOIC D 14 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Apr-2009
Pack Materials-Page 2
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