1
A1
A2
VSS
A1
A2
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
A0 VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
VSS
A0
DESCRIPTION
The CAT24AC128 is a 128kbit Serial CMOS EEPROM
internally organized as 16,384 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements. The CAT24AC128
features a 64-byte page write buffer. The device operates
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
■Commercial, industrial and extended
automotive temperature ranges
■Write protect feature
– Entire array protected when WP at VIH
■1,000,000 program/erase cycles
■100 year data retention
■8-Pin DIP, 8-Pin SOIC (JEDEC/EIAJ) or
14-pin TSSOP
via the I2C bus serial interface and is available in 8-pin
DIP, 8-pin SOIC or 14-pin TSSOP packages. Three
device address inputs allows up to 8 devices to share a
common 2-wire I2C bus.
PIN CONFIGURATION BLOCK DIAGRAM
CAT24AC128
128kbit I2C Serial CMOS EEPROM With Three Chip Address Input Pins
■1MHz (5V), 400kHz (2.5V) and 100kHz (1.8V) I2C
bus comatibility
■1.8 to 6 volt operation
■Low power CMOS technology
■Schmitt trigger filtered inputs for noise
suppression
■64-Byte page write buffer
■Self-timed write cycle with auto-clear
FEATURES
DIP Package (P, L) SOIC Package (J, K, W, X)
© 2003 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
DOUT
ACK
SENSE AMPS
SHIFT REGISTERS
CONTROL
LOGIC
WORD ADDRESS
BUFFERS
START/STOP
LOGIC
STATE COUNTERS
E
2
PROM
256X512
VCC
EXTERNAL LOAD
COLUMN
DECODERS
XDEC
DATA IN STORAGE
HIGH V OL TAGE/
TIMING CONTROL
VSS
WP
SCL
SDA
256
512
SLAVE
ADDRESS
COMPARATORS
A0
A1
A2
Doc. No. 1028, Rev. F
TSSOP Package (U14, Y14)
PIN FUNCTIONS
Pin Name Function
SDA Serial Data/Address
SCL Serial Clock
WP Write Protect
VCC +1.8V to +6V Power Supply
VSS Ground
A0 - A2 Device Address Inputs
H
A
L
O
G
E
N
F
R
E
E
TM
L
E
A
D
F
R
E
E
A1
NC
NC
A2
A0
SDA
WP
NC
NC
NC
SCL
NC
VSS
VCC
14
13
12
11
1
2
3
4
5
6
7
10
9
8
CAT24AC128
2
Doc. No. 1028, Rev. F
Symbol Parameter Test Conditions Min Typ Max Units
ICC1 Power Supply Current - Read fSCL = 100 KHz 1 mA
VCC = 5V
ICC2 Power Supply Current - Write fSCL = 100 KHz 3 mA
VCC = 5V
ISB(5) Standby Current VIN = GND or VCC 0µA
VCC = 5V
ILI Input Leakage Current VIN = GND to VCC 3µA
ILO Output Leakage Current VOUT = GND to VCC 3µA
VIL Input Low Voltage –1V
CC x 0.3 V
VIH Input High Voltage VCC x 0.7 VCC + 0.5 V
VOL1 Output Low Voltage (VCC = +3.0V) IOL = 3.0 mA 0.4 V
VOL2 Output Low Voltage (VCC = +1.8V) IOL = 1.5 mA 0.5 V
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
RELIABILITY CHARACTERISTICS
Symbol Parameter Reference Test Method Min Typ Max Units
NEND(3) Endurance MIL-STD-883, Test Method 1,000,000 Cycles/Byte
TDR(3) Data Retention MIL-STD-883, Test Method 1008 100 Years
VZAP(3) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts
ILTH(3)(4) Latch-up JEDEC Standard 17 100 mA
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol Test Conditions Min Typ Max Units
CI/O(3) Input/Output Capacitance (SDA) VI/O = 0V 8 pF
CIN(3) Input Capacitance (SCL, WP, A0, A1, A2) VIN = 0V 6 pF
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) Standby current (ISB ) = 0 µA (<900 nA).
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
CAT24AC128
3Doc. No. 1028, Rev. F
Power-Up Timing (1)(2)
Symbol Parameter Min Typ Max Units
tPUR Power-Up to Read Operation 1 ms
tPUW Power-Up to Write Operation 1 m s
A.C. CHARACTERISTICS
VCC = +1.8V to +6V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol Parameter VCC=1.8V - 6.0V VCC=2.5V - 6.0V VCC=3.0V - 5.5V
Min Max Min Max Min Max Units
FSCL Clock Frequency 100 400 1000 kHz
tAA SCL Low to SDA Data Out 0.1 3.5 0.05 0.9 0.05 0.55 µs
and ACK Out
tBUF(1) Time the Bus Must be Free Before 4.7 1.2 0.5 µs
a New Transmission Can Start
tHD:STA Start Condition Hold Time 4.0 0.6 0.25 µs
tLOW Clock Low Period 4.7 1.2 0.6 µs
tHIGH Clock High Period 4.0 0.6 0.4 µs
tSU:STA Start Condition Setup Time 4.0 0.6 0.25 µs
(for a Repeated Start Condition)
tHD:DAT Data In Hold Time 0 0 0 ns
tSU:DAT Data In Setup Time 100 100 100 ns
tR(1) SDA and SCL Rise Time 1.0 0.3 0.3 µs
tF(1) SDA and SCL Fall Time 300 300 100 ns
tSU:STO Stop Condition Setup Time 4.7 0.6 0.25 µs
tDH Data Out Hold Time 100 50 50 ns
tWR Write Cycle Time 5 5 5 ms
tSP Input Suppression (SDA, SCL) 100 100 100 ns
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During
the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave
address.
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
FUNCTIONAL DESCRIPTION
The CAT24AC128 supports the I2C Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24AC128
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or receiver,
but the Master device controls which mode is activated.
CAT24AC128
4
Doc. No. 1028, Rev. F
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. When this pin is tied to Vcc, the
entire memory is write protected. When left floating,
memory is unprotected.
A0, A1, A2: Device Address Inputs
These inputs set the device address when cascading
multiple devices. When these pins are left floating the
default values are zeroes. A maximum of eight devices
can be cascaded.
Figure 3. Start/Stop Timing
Figure 2. Write Cycle Timing
Figure 1. Bus Timing
I2C BUS PROTOCOL
The features of the I2C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus
is not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24AC128 monitors
the SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
PIN DESCRIPTIONS
SCL: Serial Clock
The serial clock input clocks all data transferred into or
out of the device.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with
other open drain or open collector outputs.
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tFtLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA tDH
tWR
STOP
CONDITION START
CONDITION ADDRESS
ACK8TH BIT
BYTE n
SCL
SDA
START BIT
SDA
STOP BIT
SCL
CAT24AC128
5Doc. No. 1028, Rev. F
10 1 0 A2 A1 A0 R/W
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 (Fig. 5). The next three significant bits (A2, A1, A0)
are the device address bits and define which device the
master is accessing. Up to eight CAT24AC128 devices
may be individually addressed by the system. The last
bit of the slave address specifies whether a Read or
Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a
Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24AC128 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24AC128 then performs a Read or Write operation
depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
The CAT24AC128 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
Figure 4. Acknowledge Timing
Figure 5. Slave Address Bits
When the CAT24AC128 begins a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT24AC128 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
two 8-bit address words that are to be written into the
address pointers of the CAT24AC128. After receiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the addressed
memory location. The CAT24AC128 acknowledges once
more and the Master generates the STOP condition. At
this time, the device begins an internal programming
cycle to nonvolatile memory. While the cycle is in
progress, the device will not respond to any request from
the Master device.
Page Write
The CAT24AC128 writes up to 64 bytes of data, in a
single write cycle, using the Page Write operation. The
page write operation is initiated in the same manner as
the byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
A2 A1 A0
*A0, A1 and A2 must compare to its corresonding hard wired inputs (pins 1, 2 and 3).
ACKNOWLEDGE
1
START
SCL FROM
MASTER 89
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
CAT24AC128
6
Doc. No. 1028, Rev. F
to send up to 63 additional bytes. After each byte has
been transmitted, CAT24AC128 will respond with an
acknowledge, and internally increment the six low order
address bits by one. The high order bits remain
unchanged.
If the Master transmits more than 64 bytes before sending
the STOP condition, the address counter ‘wraps around’,
and previously transmitted data will be overwritten.
When all 64 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT24AC128 in a single write cycle.
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
CAT24AC128 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issu-
ing the start condition followed by the slave address for
a write operation. If CAT24AC128 is still busy with the
write operation, no ACK will be returned. If
CAT24AC128 has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the entire memory array is
protected and becomes read only. The CAT24AC128
will accept both slave and byte addresses, but the
memory location accessed is protected from
programming by the device’s failure to send an
acknowledge after the first byte of data is received.
READ OPERATIONS
The READ operation for the CAT24AC128 is initiated in
the same manner as the write operation with one
exception, that R/W bit is set to one. Three different
READ operations are possible: Immediate/Current
Address READ, Selective/Random READ and
Sequential READ.
Immediate/Current Address Read
The CAT24AC128’s address counter contains the
address of the last byte accessed, incremented by one.
In other words, if the last READ or WRITE access was
to address N, the READ immediately following would
access data from address N+1. If N=E (where E=16383),
then the counter will ‘wrap around’ to address 0 and
continue to clock out data. After the CAT24AC128
receives its slave address information (with the R/W bit
set to one), it issues an acknowledge, then transmits the
8 bit byte requested. The master device does not send
an acknowledge, but will generate a STOP condition.
Selective/Random Read
Selective/Random READ operations allow the Master
Figure 7. Page Write Timing
Figure 6. Byte Write Timing
A15–A8
SLAVE
ADDRESS
S
A
C
K
A
C
K
DATA
A
C
K
S
T
O
P
P
BUS A CTIVITY :
MASTER
SDA LINE
S
T
A
R
TA7–A0
BYTE ADDRESS
A
C
K
*
*
A15–A8
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
BUS A CTIVITY :
MASTER
SDA LINE
S
T
A
R
TA7–A0
BYTE ADDRESS DATA n+63DATA
A
C
K
S
T
O
P
A
C
K
DATA n
A
C
K
P
A
C
K
*
*
*=Don't Care Bit
*=Don't Care Bit
CAT24AC128
7Doc. No. 1028, Rev. F
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condition,
slave address and byte addresses of the location it
wishes to read. After CAT24AC128 acknowledges, the
Master device sends the START condition and the slave
address again, this time with the R/W bit set to one. The
CAT24AC128 then responds with its acknowledge and
sends the 8-bit byte requested. The master device does
not send an acknowledge but will generate a STOP
condition.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24AC128 sends the initial 8-bit
byte requested, the Master will respond with an
acknowledge which tells the device it requires more
Figure 8. Immediate Address Read Timing
data. The CAT24AC128 will continue to output an 8-bit
byte for each acknowledge sent by the Master. The
operation will terminate when the Master fails to respond
with an acknowledge, thus sending the STOP condition.
The data being transmitted from CAT24AC128 is
outputted sequentially with data from address N followed
by data from address N+1. The READ operation address
counter increments all of the CAT24AC128 address bits
so that the entire memory array can be read during one
operation. If more than E (where E=16383) bytes are
read out, the counter will ‘wrap around’ and continue to
clock out data bytes.
Figure 9. Selective Read Timing
*=Don't Care Bit
24WC128 F10
SCL
SDA 8TH BIT
STOPNO ACKDATA OUT
89
SLAVE
ADDRESS
S
A
C
K
BUS A CTIVITY :
MASTER
SDA LINE
S
T
A
R
T
N
O
A
C
K
DATA
S
T
O
P
P
A15–A8
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
BUS A CTIVITY :
MASTER
SDA LINE
S
T
A
R
TA7–A0
BYTE ADDRESS SLAVE
ADDRESS
S
A
C
K
N
O
A
C
K
S
T
A
R
TDATA
P
S
T
O
P
**
CAT24AC128
8
Doc. No. 1028, Rev. F
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a 24AC128KI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating
Voltage, Tape & Reel)
Figure 10. Sequential Read Timing
BUS A CTIVITY :
MASTER
SDA LINE
DATA n+xDATA n
A
C
K
A
C
K
DATA n+1
A
C
K
S
T
O
P
N
O
A
C
K
DATA n+2
A
C
K
P
SLAVE
ADDRESS
24AC128
L: PDIP (Lead free, Halogen free)
X: SOIC, EIAJ (Lead free, Halogen free)
W: SOIC, JEDEC (Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)
CAT24AC128
9Doc. No. 1028, Rev. F
Notes:
1. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent.
2. All linear dimensions are in inches and parenthetically in millimeters.
0.180 (4.57) MAX
0.015 (0.38)
0.100 (2.54)
BSC
0.014 (0.36)
0.022 (0.56)
0.245 (6.17)
0.295 (7.49)
0.045 (1.14)
0.060 (1.52)
0.110 (2.79)
0.150 (3.81)
0.120 (3.05)
0.150 (3.81)
0.300 (7.62)
0.325 (8.26)
0.310 (7.87)
0.380 (9.65)
0.355 (9.02)
0.400 (10.16)
8-LEAD 300 MIL WIDE PLASTIC DIP (P)
8-LEAD 150 MIL WIDE SOIC (J)
Notes:
1. Complies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent.
2. All linear dimensions are in inches and parenthetically in millimeters.
0.1497 (3.80)
0.1574 (4.00) 0.2284 (5.80)
0.2440 (6.20)
0.0532 (1.35)
0.0688 (1.75)
0.0040 (0.10)
0.0098 (0.25)
0.050 (1.27) BSC
0.013 (0.33)
0.020 (0.51)
0—8
0.0075 (0.19)
0.0098 (0.25)
0.0099 (0.25)
0.0196 (0.50) X 45
0.016 (0.40)
0.050 (1.27)
0.1890 (4.80)
0.1968 (5.00)
CAT24AC128
10
Doc. No. 1028, Rev. F
Note:
1. All linear dimensions are in inches and parenthetically in millimeters.
0.205 (5.20)
0.213 (5.40) 0.303 (7.70)
0.318 (8.10)
4 REF
0.008 (0.20)
0.025 (0.65)
0.0137 (0.35)
0.0177 (0.45)
0.080 (2.03)
MAX
0.205 (5.15)
0.210 (5.35)
0.0267 (0.68)
0.0303 (0.77)
0.046 (1.17)
0.054 (1.37)
8-LEAD 210 MIL WIDE SOIC (K)
14-LEAD TSSOP (U)
7.72 TYP
4.16 TYP
(1.78 TYP)
0.42 TYP
0.65 TYP
LAND PATTERN RECOMMENDATION
-B-
3.2
6.4
ABC0.2
14 8
4.4 + 0.1
ALL LEAD TIPS
PIN #1 IDENT.
17
ALL LEAD TIPS
1.1 MAX TYP 0.1 C
(0.9)
0.10 + 0.05 TYP
0.19 - 0.30 TYP
0.3 M AB S C S
0.65 TYP
SEE DETAIL A
0.09 - 0.20 TYP
0.6+0.1 SEATING PLANE
GAGE PLANE
0.25
0
o
- 8
o
DETAIL A
-C-
-D-
Dimension D
Pkg Min Max
14 4.9 5.1
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catalyst-semiconductor.com
Publication #: 1028
Revison: F
Issue date: 7/24/03
Type: Final
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™ AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
