1PS8450D 03/06/08
Features
• All output pair skew <100ps typical (250 Max.)
• 3.75 MHz to 80 MHz output operation
• User-selectable output functions
— Selectable skew to 18ns
— Inverted and Non-Inverted
— Operation at ½ and ¼ input frequency
— Operation at 2X and 4X input frequency
(input as low as 3.75 MHz, x4 operation)
• Zero input-to-output delay
• 50% duty-cycle outputs
• LVTTL outputs drive 50-ohm terminated lines
• Operates from a single 3.3V supply
• Low operating current
• Available in 32-pin PLCC (J) package
• Jitter < 200ps peak-to-peak (< 25ps RMS)
Description
PI6C3991 offers selectable control over system clock functions.
These multiple-output clock drivers provide the system integrator
with functions necessary to optimize the timing of high-perfor-
mance computer systems. Eight individual drivers, arranged as four
pairs of user-controllable outputs, can each drive terminated trans-
mission lines with impedances as low as 50 ohms while delivering
minimal and specified output skews and full-swing logic levels
(LVTTL).
Each output can be hardwired to one of nine skews or function
configurations. Delay increments of 0.7ns to 1.5ns are determined
by the operating frequency with outputs able to skew up to ±6 time
units from their nominal “zero” skew position. The completely
integrated PLL allows external load and transmission line delay
effects to be canceled. The user can create output-to-output skew
up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems. When
combined with the internal PLL, these divide functions allow
distribution of a low-frequency clock that can be multiplied by
two or four at the clock destination. This feature allows flexibility
and simplifies system timing distribution design for complex
high-speed systems.
Logic Block Diagram Pin Configuration
1Q
0
1Q
1
1F0
1F1
2Q
0
2Q
1
2F0
2F1
3Q
0
3Q
1
3F0
3F1
4Q
0
4Q
1
4F0
4F1 Select Inputs
(three level)
Matrix
Select
Skew
Test
Filter
Phase
Freq.
DET
FB
R
EF
VCO and
Time Unit
Generator
FS
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PI6C3991
3.3V High-Speed, Low-Voltage
Programmable Skew Clock Buffer
SuperClock®
2F0
GND
1F1
1F0
VCC
N
1Q0
1Q1
GND
GND
3F1
4F0
4F1
V
CCQ
VCCN
4Q1
4Q0
GND
GND
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
3Q1
3Q0
V
CCN
FB
V
CCN
2Q1
2Q0
3F0
FS
VCC
Q
REF
GND
TES
T
2F1
4321323130
14 15 16 17 18 19 20
32-Pin
J
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2PS8450D 1 1/12 /08
PI6C3991
3.3V High-Speed, Low-V oltage Programmable
Skew Clock Buffer - SuperClock®
Pin Descriptions
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hT
1F2,0F2I .2elbaTeeS.)1Q2,0Q2(2riaptuptuorofstupnitcelesnoitcnuflevel-eerhT
1F3,0F3I .2elbaTeeS.)1Q3,0Q3(3r
iaptuptuorofstupnitcelesnoitcnuflevel-eerhT
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uflevel-eerhT
TSETI snoitpircsedmargaidkcolbehtrednunoitcesedomtseteeS.tceleslevel-eerhT
1Q1,0Q1O 2elbaTeeS.1
riaptuptuO
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1Q3,0Q3O 2elbaTeeS.3riaptuptuO
1Q4,0Q4O 2elbaTeeS.4riaptuptuO
V
NCC
RWPsrevirdtuptuorofylppusrewoP
V
QCC
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.niM.xaM
WOL5103447.22
DIM5205625.83
HGIH0408615.26
Table 1. Frequency Range Select and tU Calculation(1)
1
fNOM × N
stceleSnoitcnuFsnoitcnuFtuptuO
,1F2,1F1 1F4,1F3 ,0F2,0F1 0F4,0F3 ,1Q1,0Q1 1Q2,0Q2 1Q3,0Q31Q4,0Q4
WOLWOLt4– U2ybediviD2ybediviD
WOLDIMt3– Ut6– Ut6– U
WOLHGIHt2– Ut4– Ut4– U
DIMWOLt1– Ut2– Ut2– U
DIMDIMt0Ut0 Ut0 U
DIMHGIHt1+ Ut2+ Ut2+ U
HGIHWOLt2+ Ut4+ Ut4+ U
HGIHDIMt3+ Ut6+ Ut6+ U
HGIHHGIHt4+ U4ybediviDdetrevnI
Table 2. Programmable Skew Configurations(1)
Notes:
1. For all three-state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an
open connection. Internal termination circuitry holds an unconnected input to VCC/2.
2. The level to be set on FS is determined by the “normal” operating frequency (fNOM) and Time Unit Generator
(see Logic Block Diagram). Nominal frequency (fNOM) always appears at 1Q0 and the other outputs when they are operated in
their undivided modes (see Table 2). The frequency appearing at the REF and FB inputs will be f NOM when the output connected
to FB is undivided. The frequency of the REF and FB inputs will be fNOM/2 or fNOM/4 when the part is configured for a frequency
multiplication by using a divided output as the FB input.
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PI6C3991
3.3V High-Speed, Low-V oltage Programmable
Skew Clock Buffer - SuperClock®
3PS8450D 1 1/12/08
t
0
–6
t
U
t
0
–5
t
U
t
0
–4
t
U
t
0
–3
t
U
t
0
–2
t
U
t
0
–1
t
U
t
0
t
0
+1
t
U
t
0
+2
t
U
t
0
+3
t
U
t
0
+4
t
U
t
0
+5
t
U
t
0
+6
t
U
FB Input
REF Input
(N/A) HH Invert
(N/A) LL/HH Divided
(
N/A) LM –6t
U
LL LH –4t
U
LM (N/A) –3t
U
LH ML –2t
U
ML (N/A) –1t
U
MM MM 0t
U
MH (N/A) +1t
U
HL MH +2t
U
HM (N/A) +3t
U
HH HL +4t
U
(
N/A) HM +6t
U
1Fx
2Fx 3Fx
4Fx
Figure 1. Typical Outputs with FB Connected to a
Zero-Skew Output(3)
Note:
3. FB connected to an output selected for "zero" skew
(ie., xF1 = xF0 = MID).
Block Diagram Description
Phase Frequency Detector and Filter
These two blocks accept input signals from the reference frequency
(REF) input and the feedback (FB) input and generate correction
information to control the frequency of the Voltage-Controlled
Oscillator (VCO). These blocks, along with the VCO, form a Phase-
Locked Loop (PLL) that tracks the incoming REF signal.
VCO and Time Unit Generator
The VCO accepts analog control inputs from the PLL filter block
and generates a frequency that is used by the time unit generator
to create discrete time units that are selected in the skew mix matrix.
The operational range of the VCO is determined by the FS control
pin. The time unit (tU) is determined by the operating frequency of
the device and the level of the FS pin as shown in Table 1.
Skew Select Matrix
The skew select matrix is comprised of four independent sections.
Each section has two low-skew, high-fanout drivers (xQ0, xQ1),
and two corresponding three-level function select (xF0, xF1)
inputs. Table 2 shows the nine possible output functions for each
section as determined by the function select inputs. All times are
measured with respect to the REF input assuming that the output
connected to the FB input has 0tU selected.
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CC
laicremmoCC°07+otC°0%01±V3.3
lairtsudnIC°58+otC°04–%01±V3.3
Test Mode
The TEST input is a three-level input. In normal system operation,
this pin is connected to ground, allowing the PI6C3991 to operate
as explained briefly above (for testing purposes, any of the three
level inputs can have a removable jumper to ground, or be tied LOW
through a 100 Ohm resistor. This will allow an external tester to
change the state of these pins.)
If the TEST input is forced to its MID or HIGH state, the device will
operate with its internal phase locked loop disconnected, and input
levels supplied to REF will directly control all outputs. Relative
output to output functions are the same as in normal mode.
In contrast with normal operation (TEST tied LOW). All outputs
will function based only on the connection of their own function
select inputs (xF0 and xF1) and the waveform characteristics of
the REF input.
Storage Temperature ...................................... –65°C to +150°C
Ambient Temperature with
Power Applied ................................................. –55°C to +125°C
Supply Voltage to Ground Potential .................. –0.5V to +7.0V
DC Input Voltage ...............................................–0.5V to +7.0V
Output Current into Outputs (LOW) ............................... 64mA
Static Discharge Voltage ............................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .........................................................>200mA
Maximum Ratings
Operating Range
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4PS8450D 1 1/12 /08
PI6C3991
3.3V High-Speed, Low-V oltage Programmable
Skew Clock Buffer - SuperClock®
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V
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401Wm
Electrical Characteristics (Over the Operating Range)
Notes:
4. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal
termination resistors hold unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch
and the PLL may require an additional tLOCK time before all data sheet limits are achieved.
5. PI6C3991 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle.
Room temperature only.
6. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.
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Capacitance(6)
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PI6C3991
3.3V High-Speed, Low-V oltage Programmable
Skew Clock Buffer - SuperClock®
5PS8450D 1 1/12/08
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Switching Characteristics PI6C3991 (Over the Operating Range)(2,7)
Notes:
7. Test measurement levels for the PI6C3991 are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2ns or less
and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified.
8. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
9. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has
been selected when all are loaded with 30pF and terminated with 50 Ohm to VCC/2.
10. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU.
11. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted.
12. CL = 0pF. For CL = 30pF, tSKEW0 = 0.35ns.
13. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided
(3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode).
14. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow,
etc.)
15. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4
specifications.
16. Specified with outputs loaded with 30pF for the PI6C3991 and PI6C3991-5 devices. Devices are terminated through 50 Ohm to VCC/
2. tPWH is measured at 2.0V. tPWL is measured at 0.8V.
17. tORISE and tOFALL measured between 0.8V and 2.0V.
18. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within
normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within
specified limits.
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6PS8450D 1 1/12 /08
PI6C3991
3.3V High-Speed, Low-V oltage Programmable
Skew Clock Buffer - SuperClock®
AC Timing Diagrams
t
REF
t
RPWH
t
ODCV
tSKEWPR
tSKEW0, 1
tSKEW3,4 tSKEW3,4 tSKEW3,4
tSKEW2,4
tSKEW1,3,4
tSKEWPR
tSKEW0, 1
t
PD
t
ODCV
t
RPWL
t
J
R
REF
FB
Q
Other Q
Inverted Q
R
EF Divided by 2
R
EF Divided by 4
t
SKEW2
t
SKEW2
VCC
≤1ns ≤1ns
3.0V
2.0V
Vth=1.5V
0.8V
0V
R1
R1=100
R2=100
C
L
=30pF
(Includes fixture and probe capacitance)
R2
C
L
TTL Input Test WaveformTTL AC Test Load
AC Test Loads and Waveforms
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PI6C3991
3.3V High-Speed, Low-V oltage Programmable
Skew Clock Buffer - SuperClock®
7PS8450D 1 1/12/08
Operational Mode Descriptions
Figure 2. Zero-Skew and/or Zero-Delay Clock Driver
Figure 2 shows the SuperClock configured as a zero-skew clock
buffer. In this mode the PI6C3991 can be used as the basis for a low-
skew clock distribution tree. When all of the function select inputs
(xF0, xF1) are left open, the outputs are aligned and may each drive
a terminated transmission line to an independent load. The FB input
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
S
ystem Clock
REF
LOAD
LOAD
LOAD
LOAD
L1
L2
L3
L4
Z0
Z0
Z0
Z0
LENGTH: L1 = L2 = L3 = L4
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
System Clock
REF
LOAD
LOAD
LOAD
LOAD
L1
L2
L3
L4
Z
0
Z
0
Z
0
Z
0
LENGTH: L1 = L2, L3 < L2 by 6", L4 > L2 by 6"
Figure 3. Programmable Skew Clock Driver
can be tied to any output in this configuration and the operating
frequency range is selected with the FS pin. The low-skew specifi-
cation, coupled with the ability to drive terminated transmission lines
(with impedances as low as 50 Ohm), allows efficient printed circuit
board design.
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8PS8450D 1 1/12 /08
PI6C3991
3.3V High-Speed, Low-V oltage Programmable
Skew Clock Buffer - SuperClock®
Figure 3 shows a configuration to equalize skew between metal
traces of different lengths. In addition to low skew between outputs,
the SuperClock can be programmed to stagger the timing of its
outputs. The four groups of output pairs can each be programmed
to different output timing. Skew timing can be adjusted over a wide
range in small increments with the appropriate strapping of the
function select pins. In this configuration the 4Q0 output is fed back
to FB and configured for zero skew.
The other three pairs of outputs are programmed to yield different
skews relative to the feedback. By advancing the clock signal on the
longer traces or retarding the clock signal on shorter traces, all loads
can receive the clock pulse at the same time.
In this illustration the FB input is connected to an output with 0ns
skew (xF1, xF0 = MID) selected. The internal PLL synchronizes the
FB and REF inputs and aligns their rising edges to insure that all
outputs have precise phase alignment.
Clock skews can be advanced by ±6 time units (tU) when using an
output selected for zero skew as the feedback. A wider range of
delays is possible if the output connected to FB is also skewed. Since
“Zero Skew”, +tU, and –tU are defined relative to output groups, and
since the PLL aligns the rising edges of REF and FB, it is possible to
create wider output skews by proper selection of the xFn inputs. For
example a +10 tU between REF and 3Qx can be achieved by connect-
ing 1Q0 to FB and setting 1F0 = 1F1 = GND, 3F0 = MID, and 3F1 =
High. (Since FB aligns at –4 tU and 3Qx skews to +6 tU , a total of +10
tU skew is realized). Many other configurations can be realized by
skewing both the output used as the FB input and skewing the other
outputs.
Figure 4. Inverted Output Connections
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
REF
Figure 4 shows an example of the invert function of the SuperClock.
In this example the 4Q0 output used as the FB input is programmed
for invert (4F0 = 4F1 = HIGH) while the other three pairs of outputs
are programmed for zero skew. When 4F0 and 4F1 are tied HIGH, 4Q0
and 4Q1 become inverted zero phase outputs. The PLL aligns the
rising edge of the FB input with the rising edge of the REF. This
causes the 1Q, 2Q, and 3Q outputs to become the “inverted” outputs
with respect to the REF input. By selecting which output is connect
to FB, it is possible to have 2 inverted and 6 non-inverted outputs
or 6 inverted and 2 non-inverted outputs. The correct configura-tion
would be determined by the need for more (or fewer) inverted
outputs. 1Q, 2Q, and 3Q outputs can also be skewed to compensate
for varying trace delays independent of inver-sion on 4Q.
Figure 5. Frequency Multiplier with Skew Connections
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
REF
20 MHz
40 MHz
20 MHz
80 MHz
Figure 5 illustrates the SuperClock configured as a clock multiplier.
The 3Q0 output is programmed to divide by four and is fed back to
FB. This causes the PLL to increase its frequency until the 3Q0 and
3Q1 outputs are locked at 20 MHz while the 1Qx and 2Qx outputs run
at 80 MHz. The 4Q0 and 4Q1 outputs are programmed to divide by
two, which results in a 40 MHz waveform at these outputs. Note that
the rising edges of 4Qx and 3Qx outputs are aligned. The 2Q0, 2Q1,
1Q0, and 1Q1 outputs run at 80 MHz and are skewed by programming
their select inputs accordingly. Note that the FS pin is wired for 80
MHz operation because that is the frequency of the fastest output.
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PI6C3991
3.3V High-Speed, Low-V oltage Programmable
Skew Clock Buffer - SuperClock®
9PS8450D 1 1/12/08
Figure 6. Frequency Divider Connections
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
REF
20 MHz
10 MHz
5 MHz
20 MHz
Figure 6 demonstrates the SuperClock in a clock divider application.
2Q0 is fed back to the FB input and programmed for zero skew. 3Qx
is programmed to divide by four. 4Qx is programmed to divide by two.
Note that the rising edges of the 4Qx and 3Qx outputs are aligned.
The 1Qx outputs are programmed to zero skew and are aligned with
the 2Qx outputs. In this example, the FS input is grounded to
configure the device in the 15 to 30 MHz range since the highest
frequency output is running at 20 MHz.
Figure 7 shows some of the functions that are selectable on the 3Qx
and 4Qx outputs. These include inverted outputs and outputs that
offer divide-by-2 and divide-by-4 timing. An inverted output allows
the system designer to clock different sub-systems on opposite
edges, without suffering from the pulse asymmetry typical of non-
ideal loading. This function allows the two subsystems to each be
clocked 180 degrees out of phase, but still to be aligned within the
skew spec.
The divided outputs offer a zero-delay divider for portions of the
system that need the clock to be divided by either two or four, and
still remain within a narrow skew of the “1X” clock. Without this
feature, an external divider would need to be add-ed, and the
propagation delay of the divider would add to the skew between the
different clock signals.
These divided outputs, coupled with the Phase Locked Loop, allow
the SuperClock to multiply the clock rate at the REF input by either
two or four. This mode will enable the designer to distribute a low-
frequency clock between various portions of the system, and then
locally multiply the clock rate to a more suitable frequency, while still
maintaining the low-skew characteristics of the clock driver. The
SuperClock can perform all of the functions described above at the
same time. It can multiply by two and four or divide by two (and four)
at the same time that it is shifting its outputs over a wide range or
maintaining zero skew between selected outputs.
Figure 7. Multi-Function Clock Driver
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
20 MHz
Distribution
Clock
REF
LOAD
LOAD
LOAD
LOAD
Z0
Z0
Z0
Z0
80 MHz
Inverted
20 MHz
80 MHz
Zero Skew
80 MHz Skewed
–3.125ns (–4t
U)
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10 PS8450D 1 1/12 /08
PI6C3991
3.3V High-Speed, Low-V oltage Programmable
Skew Clock Buffer - SuperClock®
Figure 8. Board-to-Board Clock Distribution
Figure 8 shows the PI6C3991 connected in series to construct a zero
skew clock distribution tree between boards. Delays of the down
stream clock buffers can be programmed to compensate for the wire
length (i.e., select negative skew equal to the wire delay) necessary
to connect them to the master clock source, approximating a zero-
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
S
ystem
C
lock
REF LOAD
Z
0
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LOAD
Z
0
LOAD
LOAD
LOAD
Z
0
Z
0
L1
L2
L3
L4
delay clock tree. Cascaded clock buffers will accumulate low-fre-
quency jitter because of the non-ideal filtering characteristics of the
PLL filter. It is recommended that not more than two clock buffers be
connected in series.
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PI6C3991
3.3V High-Speed, Low-V oltage Programmable
Skew Clock Buffer - SuperClock®
11 PS8450D 1 1/12/08
Pericom Semiconductor Corporation • 1-800-435-2336 • http://www.pericom.com
Package Diagram - 32-Pin PLCC (J)
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005EJ5-1993C6IP23JreirraCpihCdedaeLcitsalP
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Ordering Information
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free & Green
• X suffix = Tape/Reel
