PD70201ILQ-TR - MICROSEMI - Datasheet.Live

_________________________________________________________________________________________________________

Rev.2.0, 17-Jan-2017 CPG – PoE BU

One Enterprise Aliso Viejo, CA 92656 USA

PD70101 / PD70201

Datasheet

Features

 IEEE802.3af and IEEE802.3at

Compliant

 Support for 4-pair Applications of up to

47.7W With a Single IC

 Two-events Classification

Identification With a Level Signal

Indicating Type 1 or Type 2 PSE

 Less Than 10 µA (typical) Offset

Current During Detection

 Signature Resistor is Disconnected

upon Detection

 Programmable Classification Setting

With a Single Resistor

 Integrated 0.6 Ohm Isolating MOSFET

Switch With Inrush Current Limit

 Power Off DC-DC Input Capacitor

Discharge

 100 kHz to 500 kHz Adjustable DC-DC

Switching Frequency

 DC-DC Frequency Can Be

Synchronized to External Clock

 Supports Low Power Mode Operation

for Higher Efficiency 50% Maximum

Duty Cycle

 Soft-start Circuit to Control The Output

Voltage Rise Time

 Two out-of-phase driver stages for

efficient synchronous rectification or

active clamp

 PoE Port Input UVLO with

Programmable Threshold and

Hysteresis

 Internal Differential Amplifier

Simplifying Non-isolated Step Down

Converter

 Over Load and Short Circuit Protection

 RoHS Compliant & Pb-Free

Applications

 IEEE802.3at and IEEE802.3af

powered devices such as IP

phones, WLAN Access Points and

Network Cameras.

 48V Input Telcom/Networks Hot

Swappable Power Supply.

Power Over Ethernet

802.3af/at PD Controller

The PD70101 and PD70201 are integrated Powered Device Interface and

PWM controllers for a DC-DC converter used in IEEE802.3af and

IEEE802.3at applications. The PD70101 can be used for IEEE802.3af or

IEEE802.3at Type 1 applications, while the PD70201 can also be used in

IEEE802.3at Type 2 applications.

A single PD70201 can be used in 4-pair applications which consumes up

to 47.7W.

These devices have a number of features designed to improve efficiency

and reliability:

Detection and Classification: The front end interface includes detection

and classification circuitry. The detection signature resistor is

disconnected upon completion of the detection phase. The system then

begins the classification phase. Classification can be configured for

Classes 0 to 4 via an external resistor. The PD70201 includes a

two-events classification identification circuit which generates a flag to

inform the PD application whether the Power Source Equipment (PSE) is

Type 1 or Type 2.

Capacitor: A current limited internal MOSFET switch charges the input

capacitor of the DC-DC converter. This capacitor is discharged in a timely

manner when the input power is removed.

Gate drivers: The PWM DC-DC controller has two built-in gate drivers

designed to swing between VCC and GND. These 2 out-of-phase driver

stages can be configured for synchronous rectification or active clamp.

Peak current mode control: The DC-DC converter employs peak current

mode control for better line and load step response. The switching

frequency can be set from 100kHz to 500kHz, enabling a size and

efficiency trade off.

Maximum duty cycle is limited to 50% to reduce the power MOSFET

switch voltage to two times the input voltage; a 150V rated MOSFET can

be used for the primary side switch. The secondary synchronous

MOSFET voltage rating depends on the output voltage and can be higher

or lower than the primary side MOSFET switch.

Soft-start circuit: The devices include a soft-start circuit to control the

output voltage rise time (user settable) at start up, and to limit the inrush

current. An integrated startup bias circuit powers the DC-DC controller,

until the device starts up by the voltage generated by the bootstrap circuit.

Low Voltage Protection Warning and Monitoring: Dual Under Voltage

Lock Out (UVLO), which monitors both the PoE Port Input Voltage and

VCC, ensures reliable operation during any system disturbances. The

PoE port UVLO has a programmable threshold and hysteresis to enable

tailoring to the desired turn on and turn off voltage.

An internal current sense amplifier with a Kelvin connection allows the use

of an extremely low resistor to measure the current sense threshold

voltage (200 mV) which optimizes efficiency.

Low Power Mode operation is provided to improve efficiency under light

loads such as when the PD is in standby. The user can define at what

power level the unit enters low power mode by means of a single resistor

value.

_________________________________________________________________________________________________________

Rev.2.0, 17-Jan-2017 CPG – PoE BU

One Enterprise Aliso Viejo, CA 92656 USA

PD70101 / PD70201

Datasheet

Pin Configuration

MSC

70101

YYWWX

RDET

PGOOD

RREF

RCLASS

VPN_IN

N/C

VL

GND

FB

DAO

COMP

VSP

VSN

RFREQ

SYNC

HYST

VINS

ENABLE

N/C

VPN_OUT

PGND

CSN

CSP

PG

VH

VCC

VAUX

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16

17

18

19

20

21

22

23

24

25262728

SS

RCLP

29303132

SG

VPP

MSC

70201

YYWWX

RDET

PGOOD

RREF

RCLASS

VPN_IN

N/C

AT_FLAG*

VL

GND

FB

DAO

COMP

VSP

VSN

RFREQ

SYNC

HYST

VINS

ENABLE

N/C

VPN_OUT

PGND

CSN

CSP

PG

VH

VCC

VAUX

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16

17

18

19

20

21

22

23

24

25262728

SS

RCLP

29303132

SG

VPP

Figure 1 · Pinout QFN Package(Top View)

YYWWX = Year /Week / lot code

Ordering Information

Pin Description

Number

PD70101

Pin Name

PD70201

Pin Name

Description

1

RDET

Valid Detection Resistor: Connect a 24.9kΩ, 1% resistor from this pin to

VPP.

2

PGOOD

Open Drain Output (active low): This flag is generated to indicate the

power rails (VPN_OUT) are ready.

3

RREF

Bias current resistor for the PD Interface. Connect a 240k 1% resistor

between this pin and VPN_IN.

4

RCLASS

Power Classification Setting: Connect external class resistor between

this pin and VPN_IN.

Ambient Temperature

Type

Package

Part Number

Packaging Type

-40°C to 85°C

RoHS2 compliant,

Pb-free

Matte Tin Pin Finish

QFN 5x5 Plastic 32 pin

PD70101ILQ (IEEE802.3af)

Bulk / Tube

PD70101ILQ-TR (IEEE802.3af)

Tape and Reel

PD70201ILQ (IEEE802.3at)

Bulk / Tube

PD70201ILQ-TR (IEEE802.3at)

Tape and Reel

_________________________________________________________________________________________________________

Rev.2.0, 17-Jan-2017 CPG – PoE BU

One Enterprise Aliso Viejo, CA 92656 USA

PD70101 / PD70201

Datasheet

Number

PD70101

Pin Name

PD70201

Pin Name

Description

5

VPN_IN

VPort Negative Input: Connected to the isolating switch input N-channel

MOSFET source.

6

N/C

Not Used.

7

N/C

AT_FLAG

Open Drain Output (active low): This flag indicates if the chip detects an

IEEE 802.3at compliant PSE.

8

VPN_OUT

VPort Negative Output: Connected to the isolating switch output. N-

channel MOSFET Drain.

9

N/C

Not Used.

10

ENABLE

Logic level Enable input for DC-DC controller. Pulling this pin to VL turns

on the DC-DC controller. This allows the DC-DC controller to be turned

on without power to the PD interface.

11

VINS

VPP input voltage sensing for UVLO comparator. Connect to an external

resistor divider from VPP to GND. Threshold is 1.2V reference.

12

HYST

Output of the VINS/UVLO comparator. This pin is used for VPP UVLO

hysteresis programming.

13

SYNC

External Clock synchronization for the DC-DC controller. Connect an

external clock as defined in the EC table to this pin to synchronize the

DC-DC converter switching frequency to this clock. PG rising edge is

synchronized with the clock rising edge.

14

RFREQ

DC-DC Switching Frequency Setting. Connect a resistor from this pin to

GND to set the switching frequency.

15

SS

Soft-start: Connect a capacitor from this pin to GND to set the soft-start

time of the DC-DC converter. This capacitor is charged with an internal

current source to 1.2V.

16

RCLP

Low Power Mode Clamp. Connect a resistor from this pin to GND to

program the LPM clampimg voltage or connect this pin to GND to disable

LPM.

17

VSN

Differential Amplifier's negative input. Connect this to the junction of a

resistor divider from Vo- to GND for the Direct Buck converter

application.

18

VSP

Differential Amplifier's positive input. Connect this to the junction of a

resistor divider from Vo+ to GND for the Direct Buck converter

application.

19

COMP

Error Amplifier Output. Short to FB pin when driven directly with an

optoisolator for Isolated DC-DC Converter. Connect to FB via RC

compensation networks for Non-Isolated Direct Buck Converter.

20

DAO

Differential Amplifier Output. Connect to FB (externally) for Non-Isolated

Direct Buck Converter.

21

FB

Inverting Input of the Error Amplifier. Connect to opto-coupler for Isolated

DC-DC. Connect to RC compensation networks for Non-isolated DC-DC

22

GND

This is Analog GND. Connect to a local AGND plane. Soft-start capacitor

and the frequency setting resistor return to this local GND plane.

_________________________________________________________________________________________________________

Rev.2.0, 17-Jan-2017 CPG – PoE BU

One Enterprise Aliso Viejo, CA 92656 USA

PD70101 / PD70201

Datasheet

Number

PD70101

Pin Name

PD70201

Pin Name

Description

23

VL

5V (GND reference) internal LDO Output. Connect a 1µF or higher

ceramic cap from VL to GND.

24

SG

Secondary Gate Driver. Output is the compliment of PG output. Leave

open (NC) if not used. SG is low when in Low Power Skip Mode.

25

PGND

This is the Power Ground. Connect to a local PGND plane. Input, VCC

decoupling capacitors, PG and SG drivers. Primary current sense

resistor return to this PGND.

26

CSN

Negative Input of the Current Sense Amplifier. Kelvin connect to the

PGND side of the primary current sense resistor.

27

CSP

Possitive Input of the Current Sense Amplifier. Kelvin connect to the Non-

PGND side of the primary current sense resistor.

28

PG

Primary Gate Driver. Connect to the gate of the primary side Power

MOSFET, directly or via a resistor.

29

VH

5V High side ( VCC reference) internal LDO Output. Connect a 0.1µF or

higher ceramic cap from VH to VCC.

30

VCC

Input Supply to the DC-DC Controller. Connect a 4.7µF or higher ceramic

capacitor from this pin to PGND. Alternately an parallel combination of

1µF ceramic and an greater than 10µF electrolytic capacitor can be used.

31

VAUX

Auxiliary voltage reference to VPN_OUT; this voltage can be used for

DC-DC startup when operated with a bootstrapped voltage source. For

applications with POE power only connect directly to VCC; for

applications using multiple power sources (such as a wall adaptor),

connect to VCC pin through a small, low current, 30V rated schottky

diode.

32

VPP

This is the positive terminal of the POE input port. Connect to the positive

terminal of the input bridges at the CDET positive side.

EP

Exposed Pad

Thermal Pad; electrically connected to VPN_IN. For proper thermal

management should be tied to a large copper fill or plane that is

electrically connected to VPN_IN.

_________________________________________________________________________________________________________

Rev.2.0, 17-Jan-2017 CPG – PoE BU

One Enterprise Aliso Viejo, CA 92656 USA

PD70101 / PD70201

Datasheet

Absolute Maximum Ratings

Parameter

Value

Units

VPP, RDET, VPN_OUT (with respect to VPN_IN)

-0.3V to 74

VDC

RREF, RCLASS (with respect to VPN_IN)

-0.3V to 6

V

PGOOD, AT_FLAG, VAUX (with respect to VPN_OUT)

-0.3V to 74

W

VCC (with respect to PGND)

-0.3V to 40

VDC

PG, SG (with respect to PGND)

-0.3V to 20

VDC

VL, VSN, VSP (with respect to PGND)

-0.3V to 6

V

VH (with respect to VCC)

-0.3V to VCC - 6

VDC

All Other Pins (with respect to GND)

-0.3V to VL + 0.3

VDC

ESD (HBM) Protection at all I/O pins*

± 1

kV

Maximum Junction Temperature (TJMAX)

+150

°C

Operational Ambient Temperature

-40 to +85

°C

Storage Temperature Range

-65 to +150

°C

Peak Package Solder Reflow Temperature (40 seconds maximum

exposure), MSL3

260

°C

Exceeding these ratings could cause damage to the device. All voltages are with respect to VPNIN. Currents are positive into, negative out of specified

terminal. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under

“Recommended Operating Conditions” are not implied. Exposure to “Absolute Maximum Ratings” for extended periods may affect device reliability. *All

pins except pin 2 (PGOOD) and pin 31 (VAUX). Pin 2 & 31 ESD Protection ±150V HBM.

Thermal Properties

Thermal Resistance

Typ

Units

θJC Junction to Case

5

°C/W

θJP Junction to Pad

4

θJA Junction to Ambient

23

Note: The Jx numbers assume no forced airflow. Junction Temperature is calculated using TJ = TA + (PD x JA). In

particular, θJA is a function of the PCB construction. The stated number above is for a four-layer board in

accordance with JESD-51 (JEDEC) with thermal vias.

Electrical Characteristics

Symbol

Parameter

Test Conditions / Comment

PD70101 & PD70201

Units

Min

Typ

Max

Unless otherwise specified, the following specifications apply over the operating ambient temperature of -40°C ≤ TA ≤ 85°C except where otherwise

noted with the following test conditions: VPP= 48V; VEN = HIGH, fs = 250 kHz. Production tests performed at 25°C. Unless otherwise specified VPP is

with respect to VPN_IN, VCC is with respect to PGND.

PD Interface

Power Supply

VPP

Input Voltage

0

55

57

V

_________________________________________________________________________________________________________

Rev.2.0, 17-Jan-2017 CPG – PoE BU

One Enterprise Aliso Viejo, CA 92656 USA

PD70101 / PD70201

Datasheet

Symbol

Parameter

Test Conditions / Comment

PD70101 & PD70201

Units

Min

Typ

Max

Unless otherwise specified, the following specifications apply over the operating ambient temperature of -40°C ≤ TA ≤ 85°C except where otherwise

noted with the following test conditions: VPP= 48V; VEN = HIGH, fs = 250 kHz. Production tests performed at 25°C. Unless otherwise specified VPP is

with respect to VPN_IN, VCC is with respect to PGND.

Detection Mode

DETRANGE

Detection Voltage Range.

Measured between

VPP and VPNIN

1.3

10.1

V

RDET-ON

Detection Switch ON Resistance

2.5V ≤ (∆VPP to VPNIN) ≤ 10.1V

Measured between

RDET and VPNIN

50



RDET-OFF

Detection is Disconnected

Measured between

VPP and VPNIN

10.1

12.8

V

RDET-OFF

Detection switch OFF resistance

12.8V ≤ (∆VPP to VPNIN) ≤ 57.0V

Measured between RDET and VPNIN

2.0

M

IOFFSET

Input offset current

2.5V ≤ VPP ≤ 10.1V

-40°C



TJ



85°C

16

μA

IOFFSET

2.5V ≤ VPP ≤ 10.1V

-40°C



TJ



55°C

10

μA

VRDET-ON

RDET reconnection level

Measured between VPP and VPNIN

1.95

3.0

4.85

V

Classification Mode

VTH-LOW-ON

Classification Current Source,

Turn ON Threshold Range

Measured at VPP

Turn on for any ICLASS while VPP

increases

11.4

13.7

V

VHST

Classification Disconnection

Minimum Hysteresis Voltage.

Hysteresis between

VTH-low-on and VTH-low-off

1

V

VTH-HIGH-OFF

Classification Current Source,

Turn OFF Threshold Range

Measured at VPP

Turn off while VPP increases

20.9

23.9

V

ICLASS-LIM

Current limit threshold

50.0

68

80.0

mA

ICLASS-DIS

Input current IPP when

classification function is disabled

Class 0

RCLASS = Open

3.0

mA

ICLASS-EN

Input current IPP when

classification function is enabled

Class 1

RCLASS = 133±1%

9.50

10.5

11.5

mA

Class 2;

RCLASS = 69.8 ±1%

17.5

18.5

19.5

mA

Class 3

RCLASS = 45.3 ±1%

26.5

28.0

29.5

mA

Class 4

RCLASS = 30.9 ±1%

38.0

40.0

42.0

mA

RCLASS Voltage

1.142

1.278

V

Mark

VMARK

Mark, working range

VPP failing edge

4.9

10.1

V

IMARK

Mark Current

0.25

4

mA

Isolation Switch

VSW-START

Isolation Switch MOSFET switches

from off to ILIM-LOW

36

42

V

_________________________________________________________________________________________________________

Rev.2.0, 17-Jan-2017 CPG – PoE BU

One Enterprise Aliso Viejo, CA 92656 USA

PD70101 / PD70201

Datasheet

Symbol

Parameter

Test Conditions / Comment

PD70101 & PD70201

Units

Min

Typ

Max

Unless otherwise specified, the following specifications apply over the operating ambient temperature of -40°C ≤ TA ≤ 85°C except where otherwise

noted with the following test conditions: VPP= 48V; VEN = HIGH, fs = 250 kHz. Production tests performed at 25°C. Unless otherwise specified VPP is

with respect to VPN_IN, VCC is with respect to PGND.

VSW-OFF

Isolation Switch MOSFET

switched off

30.5

34.5

V

ILIM-LOW

Startup current limit, ILIM-LOW

130

240

330

mA

VDIFF

VPN_IN to VPN_OUT Threshold

voltage for ILIM – LOW to ILIM-HIGH

switchover

When VPNIN to VPNOUT ≤ VDIFF,

Isolating switch switches over from ILIM-

LOW to ILIM-HIGH.

0.7

V

OCP

Over current protection limit

current

1500

1800

2000

mA

ILOAD

Continuous operation load

Isolating switch at ILIM-HIGH

PD70101

450

mA

PD70201

1123

SW-RDSON

Isolated Switch On resistance @

ILIM-HIGH

Total resistance between

VPNIN and VPNOUT

Isolating switch at ILIM-HIGH

0.6

Ω

DC/DC Capacitor Discharger

CIN

DC/DC input capacitance

For reference only

Guaranteed by design

(not tested in production)

220

264

µF

Discharge current

7.0V ≤ VPP to VPNOUT ≤ 30V

22.8

32

50

mA

AT_FLAG

Output low voltage

IOL = 0.75mA

0.4

V

IOL = 5mA

2.5

V

Leakage current

VAT_FLAG = 57V

1.7

µA

PGOOD

Output low voltage

IOL = 0.75mA

0.4

V

IOL MAX = 5mA

2.5

V

Leakage current

VPGOOD = 57V

1.7

µA

PD Interface Thermal Shutdown

Thermal Shutdown Temperature1

180

200

220

°C

VAUX (respect to VPN_OUT)

VAUX-OFF

VAUX Output Voltage Off (leakage

current)

PGOOD = High impedance

Load = 1MΩ

1

V

VAUX-ON

VAUX Output Voltage On

Isolating switch at ILIM-HIGH

and PGOOD = Low

9.8

10.5

11.8

V

IVAUXP

Output Current Peak

Capacitor = 30µF

When TLOAD ≤ 5mS

Isolating switch at ILIM-HIGH

and PGOOD = Low

0

10

mA

IVAUXC

Output Continuous Current

When TLOAD ≤10mS

Isolating switch at ILIM-HIGH

and PGOOD = Low

0

2

mA

_________________________________________________________________________________________________________

Rev.2.0, 17-Jan-2017 CPG – PoE BU

One Enterprise Aliso Viejo, CA 92656 USA

PD70101 / PD70201

Datasheet

Symbol

Parameter

Test Conditions / Comment

PD70101 & PD70201

Units

Min

Typ

Max

Unless otherwise specified, the following specifications apply over the operating ambient temperature of -40°C ≤ TA ≤ 85°C except where otherwise

noted with the following test conditions: VPP= 48V; VEN = HIGH, fs = 250 kHz. Production tests performed at 25°C. Unless otherwise specified VPP is

with respect to VPN_IN, VCC is with respect to PGND.

IVAUX

VAUX Output Current Limit

Isolating switch at ILIM-HIGH

and PGOOD = Low

10

32

mA

DC-DC Controller

VCC

Maximum Input Operating Voltage

20

V

IVCC

Input Current

VCC< VCC_UVLO or ENABLE = Low.

See Note 5

250

2000

µA

VENABLE and VINS = High; VVCC <

VCC_UVLO_UP; -40°C ≤ Temp ≤

+55°C. See Note 5

4.5

mA

VCC >VCC_UVLO & ENABLE = High,

No Load on PG, SG, VL, and FSW =

500kHz.

3

mA

VCC_UVLO

VCC UVLO Rising Threshold

VCC raising edge

8.85

9.15

9.5

V

VCC_UVLO

VCC UVLO Falling Threshold

VCC falling edge

7

7.3

7.6

V

POE Port Input UVLO

VINS

UVLO Threshold

1.171

1.200

1.229

V

VINS Input Current

-0.1

+0.1

µA

HYST-VOH

HYST Output High Voltage

ISOURCE = 1mA

2.8

V

HYST-VOL

HYST Output Low Voltage

ISINK = 3mA

0.4

V

Internal LDO’s

VL

+5V LDO

IL < 5mA

4.75

5

5.25

V

VH

-5V LDO

Reference to VCC

-5

V

Soft-Start

ISS_CHG

Soft-start Charging Current2

RFREQ = 33.2kΩ; VSOFTSTART = 0.5V

32

36

40

µA

ISS_DIS

Soft-start Discharging Current

VSOFTSTART = 0.5V; % of ISS_CHG

10

%

VSS_CH

Soft-start Completion Threshold1

% of 1.2V

90

95

%

VSS_DISCH

Soft-start Discharge Completion

Threshold1

50

mV

RSS_DISCH

Soft-start Discharge FET On

Resistance

50

Ω

tDISCH

Soft-start Discharge FET On Time1

1 cyc = 1/FFREQ

32

cyc

Switching Frequency and Synchronization

FFREQ

Switching Frequency Range

100

500

kHz

FFREQ

Switching Frequency Accuracy3

RFREQ = 33.2k

285

315

345

kHz

FSYNC

Synchronization Frequency Range

FSYNC > 2x FFREQ

200

1000

kHz

VSYNC-HIGH

Synchronization Voltage High

Threshold

2.4

5

V

VSYNC-LOW

Synchronization Voltage Low

Threshold

0.8

V

_________________________________________________________________________________________________________

Rev.2.0, 17-Jan-2017 CPG – PoE BU

One Enterprise Aliso Viejo, CA 92656 USA

PD70101 / PD70201

Datasheet

Symbol

Parameter

Test Conditions / Comment

PD70101 & PD70201

Units

Min

Typ

Max

Unless otherwise specified, the following specifications apply over the operating ambient temperature of -40°C ≤ TA ≤ 85°C except where otherwise

noted with the following test conditions: VPP= 48V; VEN = HIGH, fs = 250 kHz. Production tests performed at 25°C. Unless otherwise specified VPP is

with respect to VPN_IN, VCC is with respect to PGND.

PWSYNC_MIN

Synchronization Minimum Pulse

Width

100

ns

PWSYNC_MAX

Synchronization Maximum PWM

Duty

90

%

ISYNC

Synchronization Input Current

-1.3

+1.3

µA

Error Amplifier

GainDC_OPL

DC Open Loop Gain1

RLOAD = 100k

70

100

dB

AVUGBW

Unity Gain Bandwidth1

CLOAD = 10pF

2

5

MHz

ICOMP_OUT

Output Sourcing Current

0.2V ≤ VCOMP ≤ 1.3V

110

620

µA

ICOMP_IN

Output Sink Current

0.2V ≤ VCOMP ≤ 1.3V

145

495

µA

VEA_CMR

Input Common Mode Range

0

2

V

VFB

Feedback Voltage

COMP shorted to FB

1.171

1.200

1.229

V

IFB

FB Pin Input Current

-50

50

nA

VCOMP

Output Clamp Voltage

1.8

2.1

2.6

V

PWM Comparator

VRCLP

RCLP Voltage Range

0

1

V

Low Power Mode (Skip Pulse Mode)

Low Power Skip Mode

Threshold1,4

VCOMP Rising (% of VRCLP)

95

%

VCOMP Falling (% of VRCLP)

90

%

Current Sense Amplifier and Current Limit

GainCSA

Gain

Measure at DC

4.75

5.0

5.25

V/V

VCSA_CMR

Input Common Mode Range

0

2.0

V

Output Rise/Fall time1

10% to 90%

75

ns

tBLANK

Blanking Time1

50

100

ns

VILIM_TH

Current Limit Threshold

1.1

1.2

1.3

V

VIMAX_TH

Current Max Threshold

1.7

1.8

1.9

v

Differential Amplifier

GainDA

Gain

Measured at DC

6.86

7.0

7.14

V/V

AVUGBW_DA

Unity Gain Bandwidth1

5

MHz

VDA_CMR

Common Mode Range

0

3.5

V

Input Offset Voltage

-7

+7

mV

Input Bias Current

-1

+1

µA

Output Drivers

PG RdsONH

Primary Gate (PG) High On

Resistance

10

Ω

PG RdsONL

Primary Gate (PG) Low On

Resistance

5

Ω

SG RdsONH

Secondary Gate (SG) High On

Resistance

10

Ω

SG RdsONL

Secondary Gate (SG) Low On

Resistance

10

Ω

_________________________________________________________________________________________________________

Rev.2.0, 17-Jan-2017 CPG – PoE BU

One Enterprise Aliso Viejo, CA 92656 USA

PD70101 / PD70201

Datasheet

Symbol

Parameter

Test Conditions / Comment

PD70101 & PD70201

Units

Min

Typ

Max

Unless otherwise specified, the following specifications apply over the operating ambient temperature of -40°C ≤ TA ≤ 85°C except where otherwise

noted with the following test conditions: VPP= 48V; VEN = HIGH, fs = 250 kHz. Production tests performed at 25°C. Unless otherwise specified VPP is

with respect to VPN_IN, VCC is with respect to PGND.

TDEAD

Dead Time – PG low to SG high or

SG low to PG high

CLOAD on PG and SG = 1000pF

110

ns

PG Minimum On Time

120

ns

PG Maximum Duty Cycle

44.5

50

%

Logic (ENABLE Pin)

VHI

Logic High Threshold

2.0

V

VLO

Logic Low Threshold

0.8

V

Input Current

-1

1

µA

PWM Controller Thermal Shutdown

TSD

Thermal Shutdown Threshold1

157

°C

THYST

Threshold Hysteresis1

15

30

Notes:

1) Guaranteed by design

2) Soft Start Charge Current Equation: Iss_chg = 1.2V/RFREQ

3) Switching Frequency Equation:

   

 where Freq is [Hz]

4) Low Power Mode Clamp Equation: VCLAMP = 0.3 * (RRCLP/RFREQ)

5) Min and Maximum current are guaranteed by design.

_________________________________________________________________________________________________________

Rev.2.0, 17-Jan-2017 CPG – PoE BU

One Enterprise Aliso Viejo, CA 92656 USA

PD70101 / PD70201

Datasheet

Functional Block Diagram

PWM

LOGIC

&

Dead

Time

Control

Soft-start

EA

PWM

COMP CSA

Oscillator/Clock/Sync

VCC

IBLK & ILIM

ENABLE

SS FB COMP RFREQ

SYNC

VCCS

VL

VCC

PG

PGND

SG

CSN

5V LDO

REF

VCC UVLO VOUT+

VOUT-

VCC

+

-

+

-

AT FLAG

VCC

Detect

Discharge

ILIM 2 Events

Detect

PGOOD

Classification

RDET

CDET

RCLASS

RJ-45

CONNECTOR

5V LDO

VCC

VPPRDET

RCLASS

VPN

VPNO AT_FLG

POK

IREF

RREF

CSP

GND

HS

5VLDO

VH

DIFF

AMP

VSP

VSN

DAO

1.2Vref

VP UVLO/

PFW

SELECT

SYNC

DAO

VINS HYST

VP UVLO

RCLP

x7 LPM

x5

PGOOD

VCC

VAUX

VCC

58V

TVS

Figure 2 · PD70101/PD70201 Functional Block Diagram (PD70201 shown)

_________________________________________________________________________________________________________

Rev.2.0, 17-Jan-2017 CPG – PoE BU

One Enterprise Aliso Viejo, CA 92656 USA

PD70101 / PD70201

Datasheet

Typical Applications

+

-

+

-

RJ-45

CONNECTOR

VL

SYNC

Vout+

Vout-

Vout+

Vout-

VCC

VCC ATFLAG

BR-1

BR-2 C1

68nF/100V

C2

10uF/63V C3

2.2uF/100V

C4

10uF

25V

C5

100pF

100V

C11

0.1uF

10V

C10

0.1uF

25V

C6

22uF

25V

C7

10uF

25V

C12

22nF

25V

C8

22uF

25V C9

10uF

25V

C13

1uF

25V

C14

1uF/10V

C15

150nF

6.3V

C14

10nF

6.3V

R1

0.5W

R2

4.7 R3

10k

R3

24.9k

R5

0.05

R6

0

R7

R8

R9

10k

R12

24.9k

R10

95.3k

R9

39k

U3

TL431

U2

U4

R13 412k

R14

12.4k R15

392k

R16

10k

R17

10k

L1

10uH

(EMI)

L2

0.33uH

Notes:

Freq set for 250kHz

Turn On VPP ~ 42V and Off ~ 38V

Q1

FDS2582

SI7898DP

Q3

PN3906

Q2

FDS5680

D1

1A/50V T1: Np/Ns = 2.5, Naux/Ns =1

LNp = 18uH +/- 15%

T2

PE-68386

R18

0

R19

40.2k

R20

Np

Ns

Naux

TO

EXTERNAL

POWER

GOOD

MONITOR

TO

EXTERNAL

ENABLE

U1

PD70201

9 10 11 12 13 14 15 16

N/C

ENABLE

VINS

HYST

SYNC

RFREQ

SS

1

2

3

4

5

6

7

8

RDET

PGOOD

RREF

RCLASS

VPN_IN

N/C

AT_FLAG

VPN_OUT

GND

FB

DAO

COMP

VSP

VSN

RCLP

24

23

22

21

20

19

18

17

VL

32 31 30 29 28 27 26 25

VPP

VCC

VH

PG

CSP

CSN

PGND

SG

VAUX

Figure 3 · 12V2A Output Isolated Fly-back with Secondary Synchronous Rectification

_________________________________________________________________________________________________________

Rev.2.0, 17-Jan-2017 CPG – PoE BU

One Enterprise Aliso Viejo, CA 92656 USA

PD70101 / PD70201

Datasheet

Typical Applications

+

-

+

-

RJ-45

CONNECTOR

VL

SYNC

Vout+

Vout-

Vout+

Vout-

VCC ATFLAG

BR-1

BR-2

C1

100nF

/100V

C2

10F/63V C3

2.2uF/100V

C4

10uF

25V C5

22uF

25V

C6

10uF

25V

C7

NU

25V C8

NU

25V

C11

1uF

10V

R2

0.08

U4

R17

10k

R18

10k

L1

10uH

(EMI)

Notes:

Freq set for 300kHz

Turn On VPP ~ 42V and Off ~ 38V

Q1

FDS3580

D1

1A/50V

L2B

47uH

R7

36k

C13

3.3nF

L2A

47uH

C12

15pF

R6

10k R8

464k

R9

464k

R10

9.09k

R11

9.09k

D2

STPS5L60

C14

68nF

6.3V

R12 412k

R13

12.4k R14

392k

R15

33.2k R16

TO

EXTERNAL

ENABLE

R3

24.9k

R4

R5

TO

EXTERNAL

POWER

GOOD

MONITOR

VCC

C10

0.1uF

10V

C9

1uF

25V

R1

0

U1

PD70201

9 10 11 12 13 14 15 16

N/C

ENABLE

VINS

HYST

SYNC

RFREQ

SS

1

2

3

4

5

6

7

8

RDET

PGOOD

RREF

RCLASS

VPN_IN

N/C

AT_FLAG

VPN_OUT

GND

FB

DAO

COMP

VSP

VSN

RCLP

24

23

22

21

20

19

18

17

VL

32 31 30 29 28 27 26 25

VPP

VCC

VH

PG

CSP

CSN

PGND

SG

VAUX

58V

TVS

Figure 4 · 12V2.1A Output Non-Isolated Direct Buck Application

_________________________________________________________________________________________________________

Rev.2.0, 17-Jan-2017 CPG – PoE BU

One Enterprise Aliso Viejo, CA 92656 USA

PD70101 / PD70201

Datasheet

Theory of Operation

General Description

PD70101/PD70201 IC integrates IEEE 802.3af/at compliant PD Front-End functions including Detection, Physical

Layer Classification, Two-Events Classification (PD70201 only), Power Good, Soft Start Current Limiting, Over-

Current Protection, and Bulk Capacitor Discharge with a PWM controller. The integrated PWM controller function

provides a PWM controller solution with a minimum requirement of external components.

Detection IEEE 802.3af/at compliant detection is provided by means of a 24.9KΩ resistor connected between VPP and RDET

pin. RDET pin is connected to VPN_IN via an open drain MOSFET with a maximum specified RDSON of 50Ω.

Internal logic monitors VPP to VPN_IN and connects the RDET pin to VPN_IN when the rising VPP to VPN_IN

voltage is between 1.1V and 10.1V. When rising VPP to VPN_IN voltages exceed 10.1V, the MOSFET is switched

off. Once above 10.1V, falling VPP to VPN_IN voltage between 2.45V and 4.85V will reconnect RDET pin to

VPN_IN.

Physical Layer Classification

Physical Layer (hardware) Classification per IEEE 802.3af/at is generated via a regulated reference voltage of 1.2V,

switched onto the RCLASS pin. Internal logic monitors the VPP to VPN_IN voltage and connects the 1.2V reference

to RCLASS pin at a rising VPP to VPN_IN voltage threshold between 11.4V and 13.7V. Once VPP to VPN_IN has

exceeded the rising threshold, there is a 1V typical hysteresis between the VPP rising (turn-on) threshold and the

VPP falling (turn-off) threshold.

The 1.2V reference stays connected to the RCLASS pin until the VPP to VPN_IN rising voltage exceeds the upper

turn-off threshold of 20.9V to 23.9V. The 1.2V reference voltage is disconnected from the RCLASS pin at VPP to

VPN_IN voltages above the upper threshold.

Classification current signature is provided via a resistor connected between RCLASS pin and VPN_IN. The

classification current is therefore the current drawn by the PD70101/PD70201 IC during the classification phase, and

is simply the 1.2V reference voltage divided by the RCLASS resistor value. The maximum current available at the

RCLASS pin is current limited to 68mA (typical).

Two-Events Detection and AT Flag

The PD70201 IC provides IEEE 802.3at Type 2 compliant detection of the “Two Events Classification Signature”, and

generation of the AT flag. This feature is available on the PD70201 IC only.

Simply put, the “Two Events Classification Signature” is a mean by which an IEEE 802.3at Type 2 Power Source can

inform a compliant Power Device (PD) that it is AT Type 2 compliant, and as such is capable of providing AT Type 2

power levels.

The Power Source communicates the Type 2 compliant signature by toggling the VPP to VPN_IN voltage twice (2

“events”) during the Physical Layer Classification phase. The VPP to VPN_IN voltage is toggled from the Physical

Layer Classification’s voltage level (13.5V to 20.9V) down to a voltage “Mark” level. Voltage “Mark” level is specified

as a VPP to VPN_IN voltage of 4.9V to 10.1V.

PD70201 IC recognizes a VPP to VPN_IN falling edge from Classification level to Mark level as being one event of

the Two-Events Signature. If two such falling edges are detected, PD70201 will assert AT flag by means of an open

drain MOSFET connected between AT_FLAG pin and VPN_OUT.

AT_FLAG pin is active low; a low impedance state between AT_FLAG and VPN_OUT indicates a valid Two-Events

Classification Signature was received, and the Power Source is AT Type 2 compliant.

AT_FLAG MOSFET is capable of 5mA of current and can be pulled up to VPP.

Soft Start and Inrush Current Protection

PD70101/PD70201 IC contains an internal isolation switch that provides ground isolation between Power Source and

PD application during Detection and Classification phases. The isolation switch is a N-channel MOSFET, wired in a

_________________________________________________________________________________________________________

Rev.2.0, 17-Jan-2017 CPG – PoE BU

One Enterprise Aliso Viejo, CA 92656 USA

PD70101 / PD70201

Datasheet

common source configuration where the MOSFET’s Source is connected to Power Source ground at VPN_IN, and

the MOSFET’s Drain is connected to application’s primary ground at VPN_OUT

Internal logic monitors VPP to VPN_IN voltage and keeps the MOSFET in a high impedance state until VPP to

VPN_IN voltage reaches turn-on threshold of 36V to 42V. Once VPP to VPN_IN voltage exceeds this threshold, the

MOSFET is switched into one of two modes.

Mode into which the MOSFET is switched is determined by the voltage developed across the MOSFET, or put

another way, the VPN_OUT to VPN_IN differential voltage. Two modes are defined below:

Isolation Switch Modes

VPN_OUT to VPN_IN

Mode

Description

≥ 0.7V

Soft Start Mode

Limits VPN_OUT current to 240mA

(typical)

≤ 0.7V

Normal Operating Mode

Limits VPN_OUT current to 1.8A

(typical)

By controlling the MOSFET current based on VPN_OUT to VPN_IN voltage, inrush currents generated by fully

discharged bulk capacitors can be limited. This method limits current to a maximum of 350mA, compliant with IEEE

802.3af/at specification.

Soft Start current limiting is required to reduce occurrences of voltage sag at the PD input during device power-up. A

comparison is shown in Figure 3.

Figure 5 · Comparison of input voltages without Soft-start (hard startup), and Soft-start (soft startup)

Once bulk capacitance has charged up to a point where VPN_OUT to VPN_IN differential voltage is less than 0.7V,

the isolation MOSFET is switched into normal operating mode with MOSFET current limit set at 1.8A (typical), to

provide overcurrent protection.

PD70101 and PD70201 ICs are different in their respective isolation MOSFET’s continuous current handling

capability:

PD70101: 450mA (max.)

PD70201: 1123mA (max.)

An adequate heatsink for the PD70101/PD70201 IC’s exposed pad must be provided to achieve these current levels

without damaging the IC. A large, heavy copper fill area and/or a heavy ground plane with Thermal Vias are

recommended.

Internal logic monitoring VPP to VPN_IN will place the isolation switch MOSFET in a high impedance state if voltage

between VPP and VPN_IN drops below 31V to 34V.

10

20

30

40

50

60

VPD

[V]

T [ms]

Soft startup

Hard startup

Voltage sag!

DCDC

Inrush

C

I

Slope /



_________________________________________________________________________________________________________

Rev.2.0, 17-Jan-2017 CPG – PoE BU

One Enterprise Aliso Viejo, CA 92656 USA

PD70101 / PD70201

Datasheet

Over- Current Protection

An over-current protection is provided on the PD70101/PD70201 IC using the Isolation Switch MOSFET, which limits

the VPN_OUT current to 1.8A during normal operation. See previous description of Soft-start.

Power Good During Soft Start mode, the PD70101/PD70201 IC monitors VPN_OUT to VPN_IN differential voltage. When this

voltage is less than 0.7V (max.), the IC enters normal operation mode and the isolation switch current limit is

increased to 1.8A (typical). At this same 0.7V (max.) threshold the Power Good signal is asserted by means of an

open drain MOSFET between PGOOD and VPN_OUT.

PGOOD pin is active low; a low impedance state between PGOOD and VPN_OUT indicates the Soft Start mode has

finished and the isolation switch has transitioned into normal operating mode.

PGOOD MOSFET can handle current of 5mA and can be pulled up to VPP.

The application load should begin after no less than 80msec after PGOOD is activated.

Start-up Supply

PD70101/PD70201 IC provides a 10.5V (typical) regulated output used as a start-up supply for the integrated

DC/DC controller when VCC is provided via a bootstrap winding. This regulated supply is available at VAUX pin,

and is referenced to VPN_OUT pin. The VAUX start-up supply is current-limited at 10mA (min.).

For stability, the start-up regulator requires a minimum of 4.7µF ceramic capacitor connected directly between VAUX

and PGND pins (most applications will connect PGND to VPN_OUT).

For applications where power to the DC-DC controller is provided by POE only, the VAUX pin is connected directly

to VCC. For applications which have alternate power sources (such as a wall adaptor), the VAUX pin output is

connected to the VCC pin through a series diode. This diode is typically a low current diode with a 30V rating.

PD Interface Thermal Protection

Both PD70101 and PD70201 IC contain temperature sensors which individually monitor both the isolation MOSFET

and the Classification Current Source for over temperature conditions. In case of an over temperature condition, the

sensor will activate protection circuitry which will disconnect its respective monitored function.

Bulk Capacitor Discharge

The bulk capacitor discharge circuitry eliminates the need to place a diode in series with the VPP line to prevent an

application’s bulk capacitance from discharging through the detection resistor and the isolation switch MOSFET’s

body diode. Discharge current through the detection resistor can cause failure of the detection signature in cases

where a PD is connected and the bulk capacitance is not fully discharged.

During normal operation, PD70101/PD70201 IC continuously monitors voltage at VPP to VPN_IN. Should VPP to

VPN_IN voltage fall below isolation switch turn-off threshold (31V to 34V), isolation switch MOSFET is immediately

placed in a high-impedance state. At this point the internal logic monitors the voltage at VPP to VPN_OUT.

If VPP to VPN_OUT voltage is between 1.5V to 32V, a 23mA (min.) constant current source is connected across the

VPP and VPN_OUT pins. This constant current source provides bulk capacitor discharge.

A 220µF bulk capacitance can be discharged from 32V to 1.5V in a maximum period of 292ms.

DC-DC Start-up

The DC-DC controller starts up when it receives the PGOOD high signal from the Front End, or ENABLE goes high

provided that VCC UVLO have passed. When the PGOOD signal or ENABLE goes high, the start-up sequence

begins with ramping up the SS pin from GND to 1.2V. For isolated applications the output voltage may reach the

maximum level before the SS reaches 1.2V, depending on the output loading condition. In applications with lighter

loads, the output reaches regulation level sooner than in heavy loads, as in this mode the SS voltage directly

controls the peak inductor current; hence the energy is delivered to the load. The external secondary error amplifier

regulates the output voltage and controls the peak inductor current via the opto-coupler across the isolation barrier.

_________________________________________________________________________________________________________

Rev.2.0, 17-Jan-2017 CPG – PoE BU

One Enterprise Aliso Viejo, CA 92656 USA

PD70101 / PD70201

Datasheet

For non-isolated applications, because the internal error amplifier is used to close the regulation loop, the output

reaches the regulation level when SS reaches 1.2V.

An additional internal offset is added to the FB to ensure that COMP does not reach its upper limit because of

amplifier input offset. This offset is removed (slowly to avoid overshoot) when the SS ramp is complete.

Low Power Mode is not supported during SS ramp as it is not necessary.

Current Limit and Short Circuit Protection

The DC-DC converter is a peak current mode controller; an internal current sense amplifier with a gain of 5 monitors

the voltage across an external current sense resistor and regulates the output based on the current through the

resistor. If the output of the internal current sense amplifier reaches 1.2V, the converter will truncated the PWM

output, and thus limit the output current.

If the output of the internal current sense amplifier reaches 1.8V, the controller enters hiccup mode by discharging

the SS capacitor with a constant current that equals 10% of the charging current during ramp up.

This discharge continues until VSS = 50 mV where an internal ~50Ω MOSFET connected to SS turns on for 25 clock

cycles to ensure the SS capacitor fully discharges to GND before ramping back up and restart. The converter will

exit the hiccup mode when the over current condition is removed.

Low Power Mode Operation

The devices offer a pulse skipping operation for light load condition, referred as Low Power Mode (LPM), to improve

the efficiency of light load operation by reducing the power dissipation especially in high frequency switching. Using

an external resistor from RCLP pin to GND, the user can program the output power when the unit enters pulse

skipping.

Pulse skipping mode is disabled until SS ramp is completed, regardless of the LPM status.

Input (VPP & VCC) Under Voltage Lock Out

The PD interface circuit offers an internal PGOOD signal that can be used to start the DC-DC converter; however the

threshold of the PGOOD is fixed at VPN_OUT-VPN_IN ≤ 0.7V. This may not fit all possible applications. Therefore

the device offers an option to have a programmable UVLO which is tied to level of VPP-VPN_OUT, plus a

programmable hysteresis. The voltage developed across a simple resistor divider is sensed at VINS, and will

enable/disable the PWM controller at a nominal 1.2V threshold. A third resistor connected between VINS and HYST

pins allows programmable hysteresis. This feature enables the end user to tailor to any desired systems

application’s requirement for turn on and turn off time. In addition to the VPP sensing for UVLO, the devices also

have VCC UVLO to ensure that the PWM controller is always properly powered during operation. These features

provide robust solutions under various systems disturbances.

External Enable

The PD interface circuit provides an internal PGOOD signal that is used to enable the DC-DC converter when

powered by the POE input; however for applications that require input power from a wall adaptor, the internal

PGOOD signal is not functional. For these applications an external enable input is provided, allowing a non-POE

power source (such as a wall adaptor) the ability to start the DC-DC converter. The Enable pin is active high, and is

driven by a 5V maximum signal referenced to GND. When the DC-DC converter is powered by the PD interface

(POE power), the Enable pin will not disable the controller. It may be tied to ground or left floating when not used.

_________________________________________________________________________________________________________

Rev.2.0, 17-Jan-2017 CPG – PoE BU

One Enterprise Aliso Viejo, CA 92656 USA

PD70101 / PD70201

Datasheet

Package Outline Dimensions

The package is halogen free and meets RoHS2 and REACH standards.

D

E

e

A1

A

A3

L

b

D2

E2

Pin 1 ID

Top

Side

Bottom

Dim

MILLIMETERS

INCHES

MIN

MAX

MIN

MAX

A

0.80

1.00

0.031

0.039

A1

0

0.05

0

0.002

A3

0.20 REF

0.008 REF

b

0.18

0.30

0.007

0.012

D

5.00 BSC

0.197 BSC

D2

3.30

3.60

0.130

0.142

E

5.00 BSC

0.197 BSC

E2

3.30

3.60

0.130

0.142

e

0.50 BSC

0.02 BSC

L

0.30

0.50

0.012

0.020

Note:

1. Dimensions do not include protrusions; these shall not

exceed 0.155mm (.006”) on any side. Lead dimension

shall not include solder coverage.

2. Dimensions are in mm, inches are for reference only.

_________________________________________________________________________________________________________

Rev.2.0, 17-Jan-2017 CPG – PoE BU

One Enterprise Aliso Viejo, CA 92656 USA

PD70101 / PD70201

Datasheet

The information contained in the document (unless it is publicly available on the Web without access restrictions) is

PROPRIETARY AND CONFIDENTIAL information of Microsemi and cannot be copied, published, uploaded, posted,

transmitted, distributed or disclosed or used without the express duly signed written consent of Microsemi. If the recipient

of this document has entered into a disclosure agreement with Microsemi, then the terms of such Agreement will also

apply. This document and the information contained herein may not be modified, by any person other than authorized

personnel of Microsemi. No license under any patent, copyright, trade secret or other intellectual property right is granted

to or conferred upon you by disclosure or delivery of the information, either expressly, by implication, inducement,

estoppels or otherwise. Any license under such intellectual property rights must be approved by Microsemi in writing

signed by an officer of Microsemi.

Microsemi reserves the right to change the configuration, functionality and performance of its products at anytime without

any notice. This product has been subject to limited testing and should not be used in conjunction with life-support or

other mission-critical equipment or applications. Microsemi assumes no liability whatsoever, and Microsemi disclaims any

express or implied warranty, relating to sale and/or use of Microsemi products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.

Any performance specifications believed to be reliable but are not verified and customer or user must conduct and

complete all performance and other testing of this product as well as any user or customers final application. User or

customer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the

customer’s and user’s responsibility to independently determine suitability of any Microsemi product and to test and verify

the same. The information contained herein is provided “AS IS, WHERE IS” and with all faults, and the entire risk

associated with such information is entirely with the User. Microsemi specifically disclaims any liability of any kind

including for consequential, incidental and punitive damages as well as lost profit. The product is subject to other terms

and conditions which can be located on the web at http://www.microsemi.com/company/terms-and-conditions

Revision History

Revision Level / Date

Para. Affected

Description

1.0 Sep 25 2011

Production Data Sheet release

1.1 Feb 2012

Updated Document Formatting and Updated Address

Footer

1.2 Jun 25 2012

Update Switching Frequency Accuracy spec limits and

equation in note 3.

1.3 Nov 21 2013

Update IVcc disable, add note 5 and remove A from

70101A from the package pin out.

1.4 Feb 13 2014

General update

1.5 Feb 20 2014

TYPOs Fixes

1.6 Mar 20 2014

Update diff amp gain at Figure 2

1.7 Nov 13 2014

Update continuous operation load current parameter

on page 6

Update Pin 3 description on page 2

1.8 May 18 2015

Update diff amp and GND connection at Figure 2 and

3.

Add the diff amp input (VSN, VSP) to Absolute

Maximum Ratings table

1.9 November 2015

Added maximum value for VSW-START

2.0 January 2017

Changed MSL from 1 to 3, updated formatting and

disclaimer

For support contact: PoEsupport@microsemi.com

Visit our web site at: www.microsemi.com Catalog Number: DS_PD70101_PD70201

_____________________________________________________________________________________________________________________

Rev.2.0, 17-Jan-2017 CPG – PoE BU

One Enterprise Aliso Viejo, CA 92656 USA

PD70101 / PD70201

Datasheet

Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor

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and alternative energy markets. Products include high-performance, high-reliability analog and

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