Page 1 of 11
Document No. 70-0066-04 www. pse mi.com ©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
The PE4304 is a 75-ohm high-linearity, 6-bit RF Digital Step
Attenuator (DSA) covering a 31.5 dB attenuation range in 0.5
dB steps. Th e PE430 4 provides both a pa rallel (l atched or
direct mode) and serial CMOS control interface, operates on a
single 3-volt supply and maintains high attenuation accuracy
over frequency and temperature. It also has a unique control
interface that allows the user to select an initial attenuation
state at power-up. The PE4304 exhibits very low in sertion loss
and low power consumption. This functionality is delivered in a
4x4 mm QFN footprint.
The PE4304 is manufactured on Pe regrine’s UltraCMOS™
pro c ess, a patented variation of silicon-on-in sulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the econom y an d i nte gr ation of conventional
CMOS.
Pro duct Specificat ion
75 Ω RF Digital Attenuator
6-bit, 31.5 dB, DC – 2.0 GHz
Product Description
Figure 1. Functional Schematic Diagram
PE4304
Features
• 75 impedance
• Attenuation: 0.5 dB st e ps to 31.5 dB
• Low distortion for CATV and multi-carrier
applications
• Flexible parallel and serial programming
interfaces
• Unique power-up state selection
• Positive CMOS control logic
• Hi gh att en uation acc ur ac y an d li n ear i ty
over temperature and frequency
• Very low power consumption
• Single-sup pl y operati on
• Packaged in a 20 lead 4x4 mm QFN
Table 1. Electrical Specifications @ +25 °C, VDD = 3.0 V, Zo = 75 Ω
Notes: 1. Device Linearity will begin to degrade below 1Mhz
2. Max input rating in Table 3 & Figures on Pages 4 to 6 for data across frequency.
3. Note Absolute Maximum in Table 3.
4. Measured in a 50 system.
Control Logic Interface
Parallel Control
Power-Up Control
Serial Control
RF Input RF Output
Switched Attenuator Array
6
3
2
Parameter Test Conditions Frequency Minimum Typical Maximum Units
Operation Frequency DC 2000 MHz
Inser t io n Los s2 DC 1.2 GHz - 1.4 1.8 dB
Attenuation Accuracy Any Bit or Bit
Combination DC 1.2 GHz - - ±(0 .15 + 4% of attenuati on
setting) dB
1 dB Compression3,4 1 MHz 1.2 GHz 30 34 - dBm
Input IP3 1,2,4 Two- t on e inputs up t o
+18 dBm 1 MHz 1.2 GHz - 52 - dBm
Return Loss DC 1.2 GHz 10 13 - dB
Switching Speed 50% co nt r ol t o 0. 5 dB
of final value - - 1 µs
Fig ur e 2. Pa ck ag e Typ e
4x4 mm 20-Lead QFN
Product Specification
PE4304
Page 2 of 11
©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0066-04 UltraCMOS™ RFIC Solutions
Table 2 . Pin Descriptions
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rate specified in Table 3.
Expose d Solder Pad Connection
The exposed solder pad on the bottom of the
package must be grounded for proper device
operation.
Note 1: Both RF ports must be DC blocked with an external series
capacitor or held at 0 VDC.
2: Latch E na bl e (LE ) has an interna l 100 k resistor to VDD.
3: Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to VSS (-VDD) to bypass and
disable internal negative voltage generator.
4. Place a 10 k resistor in series, as close to pin as possible.
Figure 3. Pin Configuration (Top View)
Latc h-Up Avoidance
Unlike conventiona l CMOS d evices, UltraCMO S™
devices are immune to latch-up.
Swi tc hing Frequency
The PE4304 has a maximum 25 kHz switching rate.
Resi st o r on Pin 1 & 3
A 10 k resistor on the inputs to Pin 1 & 3 (see
Figure 5 ) will eli minat e package re s onance betwe en
the RF input pin and the two digital inputs. Specified
attenuation error versus frequency performance is
dependent upon this condition.
V
DD
PUP1
PUP2
VDD
GND
1
20
19
18
17
16
15
14
13
12
11
6
7
8
9
10
2
3
4
5
C16
RF1
Data
Clock
LE GND
Vss/GND
P/S
RF2
C8
C4
C2
GND
C1
C0.5
20-lead QFN
4x4mm
Exposed Solder Pad
Pin
No. Pin
Name Description
1 C16 Attenuation control bit, 16dB (Note 4).
2 RF1 RF port (Note 1).
3 Data Serial interface data input (Note 4).
4 Clock Serial interface clock input.
5 LE Latch Enable input (Note 2).
6 VDD Power supply pin.
7 PUP1 Power-up selection bit, MSB.
8 PUP2 Power-up selection bit, LSB.
9 VDD Power supply pin.
10 GND Ground connection.
11 GND Ground connection.
12 Vss/GND Negative supply voltage or GND
connection(Note 3)
13 P/S Parallel/Serial mode select.
14 RF2 RF port (Note 1).
15 C8 Attenuation control bit, 8 dB.
16 C4 Attenuation control bit, 4 dB.
17 C2 Attenuation control bit, 2 dB.
18 GND Ground connection.
19 C1 Attenuation control bit, 1 dB.
20 C0.5 Attenuation control bit, 0.5 dB.
Pad dl e GN D Ground for pr op er operati on
Table 3. Absolute Maximum Ratings
Table 4. Operating Ranges
Symbol Parameter/Conditions Min Max Units
VDD Power supply voltage -0.3 4.0 V
VI Voltage on any input -0.3 VDD+
0.3 V
TST Storage temperature range -65 150 °C
PIN Input po wer (5 0) +30 dBm
VESD ESD voltage (H uman Body
Model) 500 V
Parameter Min Typ Max Units
VDD Power Supply
Voltage 2.7 3.0 3.3 V
IDD Power Supply
Current 100 µA
Digital Input High 0.7xVDD V
Digital Input Low 0.3xVDD V
Digital Input Leakage 1 µA
Input Pow er +24 dB m
Temperature range -40 85 °C
Product Specification
PE4304
Page 3 of 11
Document No. 70-0066-04 www. pse mi.com ©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Evaluation Kit
The Digital Attenuator Evaluation Kit board was
designed to ease customer evaluation of the
PE4304 Digital Step Attenuator.
J9 i s used in conj unc tion wi th the suppl ie d DC cabl e
to supply VDD, GND, and –VDD. If use of the internal
negative voltage generator is desired, then do not
connect –VDD (Black banana plug). If an external –
VDD is desired, then apply -3V.
J1 should be connected to the parallel port of a PC
with the supplied ribbon cable. The evaluation
software is written to operate the DSA in serial
mode, s o Swi tch 7 (P/ S) sh ould b e ON w ith al l othe r
switches off. Using the software, enable or disable
each attenuation setting to the desired combined
attenuation. The software automatically programs
the DSA each time an attenuation state is enabled or
disabled.
To evaluate the Power up options, first disconnect
the parallel ribbon cable from the evaluation board.
The parallel cable must be removed to prevent the
PC parallel port from biasing the control pins to
unknown states. During power up i n serial mode (P /
S=1 and LE=0) or in parallel mode with P/S=0 and
LE=1, the default power-up signal attenuation is set
to the val ue pr esent on the s ix c ontrol bits on t he si x
parallel data inputs (C0.5 to C16). This allows any
one of the 64 attenuation settings to be specified as
the power-up state.
To pow er up i n Par al l el m ode ( P/S= 0) w i th LE= 0, the
control bits are automatically set to one of four
possible values. These four values are selected by
the two power-up control bits, PUP1 and PUP2, as
shown in the Parallel PUP Truth Table (Table 6).
Figure 4. Evaluation Board Layout
Figure 5. Evaluation Board Schematic
Note: Res i s tors on pins 1 and 3
are requir ed to avoid pack age
resonanc e and m eet error
specif ications over f r equenc y .
Peregr ine S pec ificat ion 101/0112
Peregr ine S pec ificat ion 102/0142
Product Specification
PE4304
Page 4 of 11
©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0066-04 UltraCMOS™ RFIC Solutions
-35
-30
-25
-20
-15
-10
-5
0
0 400 800 1200 1600 2000
Return Loss (dB)
RF Frequency (MHz)
-40
-35
-30
-25
-20
-15
-10
-5
0
0 400 800 1200 1600 2000
Input Return Loss (dB)
RF Frequency (MHz)
31.5dB
8dB
16dB
0
5
10
15
20
25
30
35
0 400 800 1200 1600 2000
Attenuation (dB)
RF Frequency (MHz)
31.5dB
16dB
8dB
4dB
2dB
0.5dB 1dB
-5
-4
-3
-2
-1
0
0 400 800 1200 1600 2000
Insertion Loss (dB)
RF Frequency (MHz)
Typical Performance Data @ 25°C, VDD = 3.0 V (unless otherwise specified)
Fig ure 7. At t enu at ion at Majo r st ep s
Figure 9. Output Return Loss at Major
Attenuation Ste ps
Figure 8. Input Return Loss at Major
Attenuation Ste ps
Figure 6. Insertion Loss
Product Specification
PE4304
Page 5 of 11
Document No. 70-0066-04 www. pse mi.com ©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
-0.6
-0.4
-0.2
0
0.2
0.4
0 5 10 15 20 25 30 35 40
Error 510 Mhz
10Mhz error 85
500MHz, -40C
500MHz, 85C
500MHz, 25C
-0.4
-0.2
0
0.2
0.4
0.6
0 5 10 15 20 25 30 35 40
Attenuation Error (dB)
Attenuation Setting (dB)
10MHz, -40C
10MHz, 85C
10MHz, 25C
-1
-0.75
-0.5
-0.25
0
0.25
0.5
0 5 10 15 20 25 30 35 40
Attenuation E rror (dB)
Attenuation Setting (dB)
10MHz
1210MHz
1010MHz
750MHz
510MHz
250MHz
-2
-1.5
-1
-0.5
0
0.5
1
0 400 800 1200 1600 2000
Attenuation Error (dB)
RF Frequency (MHz)
8dB
16dB
31.5dB
Figure 11. Attenuation Error Vs. Attenuation
Setting
Figure 13. Attenuation Error Vs. Attenuation
Setting
Figure 12. Attenuation Error Vs. Attenuation
Setting
Figure 10. Attenuation Error Vs. Frequency
Typical Performance Data @ 25°C, VDD = 3.0 V (unless otherwise specified)
Note: Positive attenuation err or indicates higher attenuation than t ar get value
Product Specification
PE4304
Page 6 of 11
©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0066-04 UltraCMOS™ RFIC Solutions
20
25
30
35
40
45
50
55
60
0 400 800 1200 1600 2000
Input IP3 (dBm)
RF Frequency (MHz)
0
5
10
15
20
25
30
35
40
0 400 800 1200 1600 2000
Compression (dB)
RF Frequency (MHz)
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0 5 10 15 20 25 30 35 40
Attenuation Error (dB)
Attenuation Setting (dB)
1200MHz, 85C
1200MHz, 25C
1200MHz, -40C
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0 5 10 15 20 25 30 35 40
Attenuation Error (dB)
Attenuation Setting (dB)
1000MHz, -40C
1000MHz, 85C
1000MHz, 25C
Figure 15. Input IP3 Vs. Frequency
Figure 16. Input 1dB Compression
(Major attenuation states, 50 System)
Figure 14. Attenuation Error Vs. Frequency
Typical Performance Data @ 25°C, VDD = 3.0 V (unless otherwise specified)
Figure 17. Input IP3 Vs. Frequency
(Major attenuation states, 50 System)
Note: Positive attenuation err or indicates higher attenuation than t ar get value
Product Specification
PE4304
Page 7 of 11
Document No. 70-0066-04 www. pse mi.com ©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Programming Options
Parallel/Serial Se lection
Either a parallel or serial interface can be used to
control the PE4304. The P/S bit provides this
selection, with P/S=LOW se lecting the parallel
interface and P/S=HIGH selecting the serial
interface.
Parallel Mode Interface
The parallel interface consists of five CMOS-
compatible control lines that select the desired
attenuation state, as shown in Table 5.
The parallel interface timing requirements are
defined by Figure 19 (Parallel Interface Timing
Diagram), Table 9 (Parallel Interface AC
Characteristics), and switching speed (Table 1).
For latched parallel programming the Latch Enable
(LE) should be held LOW while changing attenuation
state control values, then pulse LE HIGH to LOW
(per Figure 19) to latch new attenuation state into
device.
For direct parallel programming, the Latch Enable
(LE) line should be pulled HIGH. Changing
at tenu ation state contro l v alues will c hange device
state to new attenuation. Direct Mode is ideal for
manual control of the device (using hardwire,
switches, or jumpers).
Table 5. Truth Table
Note: Not all 64 possible combinations of C0.5-C16 are shown in table
Serial Interface
The serial interface is a 6-bit serial-in, parallel-out
shift register buffered by a transparent latch. It is
controlled by three CMOS-compatible signals: Data,
Clock, and Latch Enable (LE). The Data and Clock
inputs allow data to be serially entered into the shift
register, a process that is independent of the state of
the LE input.
The LE input controls the latch. When LE is HIGH,
the latch is transparent and the contents of the serial
shift register control the attenuator. When LE is
brought LOW, data in the shift register is latched.
The shift register should be loaded while LE is held
LOW to prevent the attenuator value from changing
as data is entered. The LE input should then be
toggled HIGH and brought LOW again, latching the
new data. The timing for this operation is defined by
Figure 18 (Serial Interface Timing Diagram) and
Table 8 (AC Characteristics).
Power-up Control Settings
The PE4304 always assumes a specifiable
attenuation setting on power-up. This feature exists
for both the Serial and Parallel modes of operation,
and allows a known attenuation state to be
established before an initial serial or parallel control
word is provided.
When the attenuator powers up in Serial mode (P/
S=1), the six control bits are set to whatever data is
present on the six parallel data inputs (C0.5 to C16).
This allows any one of the 64 attenuation settings to
be specified as the power-up state.
When the attenuator powers up in Parallel mode (P/
S=0) with LE=0, the control bits are automatically set
to one of four possible values. These four values
are selected by the two power-up control bits, PUP1
and PUP2, as shown in Table 6 (Power-Up Truth
Table, Parallel Mode).
Table 6. Parallel PUP Truth Table
Note: Power up with LE=1 provides normal parallel operation
with C 0.5-C16, and PU P1 an d PUP2 are not active.
P/S C16 C8 C4 C2 C1 C0.5
Attenuation
State
0 0 0 0 0 0 0 Reference Loss
0 0 0 0 0 0 1 0.5 dB
0 0 0 0 0 1 0 1 dB
0 0 0 0 1 0 0 2 dB
0 0 0 1 0 0 0 4 dB
0 0 1 0 0 0 0 8 dB
0 1 0 0 0 0 0 16 dB
0 1 1 1 1 1 1 31.5 dB
P/S LE PUP2 PUP1 Attenuation State
0 0 0 0 Reference Loss
0 0 1 0 8 dB
0 0 0 1 16 dB
0 0 1 1 31 dB
0 1 X X Defi ned by C0.5-C16
Product Specification
PE4304
Page 8 of 11
©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0066-04 UltraCMOS™ RFIC Solutions
Table 7. 6-Bit Attenuator Serial Programming
Register Map
Table 9. Parallel Interface AC Characteristics
Figure 19. Parallel Interface Timing Diagra m
Table 8. Serial Interface AC Characteristics
Figure 18. Se rial Interface Timing Diagram
LE
Clock
Data MSB LSB
t
LESUP
t
SDSUP
t
SDHLD
t
LEPW
B5 B4 B3 B2 B1 B0
C16C8C4C2C1C0.5
↑↑
LSB (last in)MSB (first in)
Note: fClk is verified during the functional pattern test. Serial
programming sections of the functional pattern are clocked
at 10 MHz to verify fclk specification.
VDD = 3.0 V, -40° C < TA < 85 ° C, un le ss otherw i se sp ecified
t
PDSUP
t
PDHLD
Parallel Data
C16:C0.5
LE
t
LEPW
VDD = 3.0 V, -40° C < TA < 85 ° C, un le ss otherw i se sp ecified
Symbol Parameter Min Max Unit
fClk Serial data clock
frequency (Note 1) 10 MHz
tClkH Serial clock HIGH time 30 ns
tClkL Serial clock LOW time 30 ns
tLESUP LE set-up time after last
clock falling ed ge 10 ns
tLEPW LE mi ni mum p uls e w id t h 30 ns
tSDSUP Seri al d ata set- up ti me
before clock rising edge 10 ns
tSDHLD Serial dat a hold time
after clock falling edge 10 ns
Symbol Parameter Min Max Unit
tLEPW LE mini mu m puls e w id th 10 ns
tPDSUP Data set-up time before
ris in g ed ge of LE 10 ns
tPDHLD Data hold time a fter
falling edge of LE 10 ns
Product Specification
PE4304
Page 9 of 11
Document No. 70-0066-04 www. pse mi.com ©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Figure 20. Package Drawing
1.00
1.00
2.00
2.00
0.23
0.10 C A B
EXPOSED PAD
4.00
DETAIL A
16
15
115
1
6
20
10
0.50 TYP
2.00 TYP
0.55
2
1
DETAIL A
0.18
0.18
0.435
0.435
SEATING
PLANE
0.08 C
0.10 C
0.020
0.20 REF
EXPOSED PAD &
TERMINAL PADS
0.80
- C -
2.00 X 2.00
2.00
2.00
4.00
4.00
- B -
- A -
INDEX AREA
0.25 C
1. Dimension applies to metallized terminal and is measured
between 0.25 and 0.30 from terminal tip.
2. Coplanarity applies to the exposed heat sink slug as well as the
terminals.
3. Dimensions are in millimeters.
Product Specification
PE4304
Page 10 of 11
©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0066-04 UltraCMOS™ RFIC Solutions
Figure 21. Marking Specifications
Figure 22. Tape and Reel Drawing
4304
YYWW
ZZZZZ
YYWW = Date Code
ZZZZZ = Last five digits of PSC Lot Number
Table 10. Ordering Information
Or der Code Part Marking Description Package Shipping Method
4304-01 4304 PE4304-20MLP 4x4mm-75A 20-lead 4x4 mm QFN 75 units / Tube
4304-02 4304 PE4304-20MLP 4x4mm-3000C 20-lead 4x4 mm QFN 3000 units / T&R
4304-00 PE4304-EK PE4304-20MLP 4x4mm-EK Evaluation Kit 1 / Box
4304-51 4304 PE4 304G -2 0M LP 4x 4 m m- 7 5A Gr ee n 20-l ead 4x 4 m m QFN 75 unit s / Tube
4304-52 4304 PE4 304G -2 0M LP 4x 4 m m- 3 00 0C Gr ee n 20-l ead 4x 4 m m QFN 30 00 un its / T&R
Product Specification
PE4304
Page 11 of 11
Document No. 70-0066-04 www. pse mi.com ©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Sales Offices
The Americas
Peregrine Semiconductor Corporation
9450 Carr oll Park Drive
San Diego, CA 92121
Tel: 858-731-9400
Fax: 858-731-9499
North Asia Pacific
Peregrine Semiconductor K.K.
Teiko k u Hote l Tower 10B-6
1- 1-1 Uchisa iwa i-ch o, Ch iy o da-k u
Tokyo 100-0011 Japan
Tel: +81-3-3502-5211
Fax: +81-3-3502-5213
Peregrine Semiconductor, Korea
#B-2402, Kolon Tripolis, #210
Geumgok-dong, Bundang-gu, Seongnam-si
Gyeonggi-do, 463-480 S. Korea
Tel: +82-31-728-4300
Fax: +82-31-728-4305
Europe
Peregrine Semiconductor Europe
Bâtiment Maine
13-15 rue des Q uatre Vents
F-92380 Garches , France
Tel: +33-1-4741-9173
Fax : +33-1 -4741 -917 3
For a list of representat ives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data
sheet contains design target specif icat ions for product
development. Specifications and features may change in
any manner without notice.
Preliminary Specification
The data sheet contains pr eliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data . In the event Peregrine
dec ide s to cha nge the spe c ific a tions, Pereg rine will not ify
cust omers of the intended changes by issu ing a DCN
(Document Change Notice).
The information in this data sheet is believed to be reliable.
Howeve r, Peregrine assum es no liability f or th e use of this
information. Use shall be entirely at the user’s own r isk.
No patent rights or licenses to any cir cuits descr ibed in t his
data sheet are implied or granted t o any third party.
Peregrine’s pr oducts are not designed or intended f or use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Per egrine product could
create a situation in which personal injury or death m ight occur.
Peregr ine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The Peregr ine name, logo, and UTSi ar e registered t r ademarks
and UltraCMOS and HaRP ar e tr ademarks of Peregrine
Semiconductor Corp.
South As ia Pa cific
Peregrine Semiconductor, China
Shanghai, 200040, P.R. China
Tel: +86-21-5836-8276
Fax: +86-21-5836-7652
Spa ce and Defense Products
Americas :
Tel: 858-731-9453
Europe, Asia Pacific:
180 Rue Jean de Guiramand
13852 Aix-En-Provence Cedex 3, France
Tel: +33-4-4239-3361
Fax: +33-4-4239-7227
