Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 002-01232 Rev. *A Revised December 08, 2015
S29AL016D
16 Mbit (2 M x 8-Bit/1 M x 16-Bit), 3 V
Boot Sector Flash
This product has been retired and is not recommended for designs. For new and current designs, S29AL016J supercedes
S29AL016D. This is the factory-recommended migration path. Please refer to the S29AL016J data sheet for specifications and
ordering information.
Distinctive Characteristics
Architectural Advantages
Single Power Supply Operation
– Full voltage range : 2.7 to 3.6 volt read and write operations for
battery-powered applications
Manufactured on 200 nm Process Technology
– Fully compatib le with 20 0 nm Am29LV160D and MBM29LV160E
devices
Flexible Sector Architecture
– One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-one 64 Kbyte
sectors (byte mode)
– One 8 Kword, two 4 Kword, one 16 Kword, and thirty-one 32
Kword sectors (word mode)
Sector Protection Features
– A hardware method of lo cking a sector t o p re vent a ny prog ram o r
erase operations within that sect or
– Sectors can be locked in-system or via programming equipment
– Temporary Sector Unprotect feature allows code changes in
previously locked sectors
Unlock Bypass Program Command
– Reduces overall programming time when issuing multiple program
command sequences
Top or Bottom Boot Block Configurations Available
Compatibility with JEDEC standards
– Pinout and software compatible with single-power supply Flash
– Superior inadvertent write protection
Performance Characteristics
High Performance
– Access times as fast as 70 ns
– Extended temperature range (-40°C to +125°C)
Ultra Low Power Consumption (typical values at 5 MHz)
– 200 n A Automatic Sleep mode current
– 200 nA standby mode current
– 9 mA read current
– 20 mA program/erase current
Cycling Endurance: 1,000,000 cycles per sector typical
Data Retention: 20 years typical
Package Options
48-ball FBGA
48-pin TSOP
44-pin SOP
Software Features
CFI (Common Flash Interface) Compliant
– Provides device-specific information to the system, allowing host
software to easily reconfigure for different Flash devices
Erase Suspend/Erase Resume
– Suspends an er ase operation to read data from, or program data
to, a sector that is not being erased, then resumes the erase
operation
Data# Polling and Toggle Bits
– Provides a software method of detecting program or erase
operation completion
Hardware Features
Ready/Busy# Pin (RY/BY#)
– Provides a hardware method of detecting program or erase cycle
completion
Hardware Reset Pin (RESET#)
– Hardware method to reset the device to reading array data
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 2 of 105
S29AL016D
General Description
The S29AL016D is a 16 Mbit, 3.0 Volt-o nly Flash memory organized as 2,097,152 byte s or 1,048,576 words. The device is offered
in 48-ball FBGA, and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on
DQ7–DQ0. This device is designed to be programmed in-system with the standard system 3.0 volt VCC supply. A 12.0 V VPP or 5.0
VCC are not required for write or erase operations. The device can also be programmed in standard EPROM programmers.
The device offers access times of 70 ns and 90 ns allowing high speed microprocessors to operate without wait states. T o eliminate
bus contention the device has separate chip enable (CE#), write enable (WE#) and outp ut enable (OE#) controls.
The device requires only a single 3.0 volt power supply for both read and write functions. Internally gen erated and regulated
voltages are provided for the program and erase operations.
The S29AL016D is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are
written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-
machine that controls the erase and programming circuitry. Write cycles also interna lly latch addresses and data needed for the
programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an
internal algorithm that automati cally times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode
facilitates faster programming times by requiring only two write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. Th is initiates the Embedded Erase algorithm—an internal
algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During
erase, the device automatically times the erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7
(Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array
data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other
sectors. The device is fully erased when shipped from the factory.
Hardware data prote ction measures include a low VCC detector that automatically inhibits write operations during power
transitions. The hardware sector protec tion feature disables both program and erase operations in any combination of the sectors
of memory. This can be achieved in-system or via programming equipment.
The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or
program data to, any sector that is not selected for erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation in progres s and resets the internal state machine to readin g array data. The
RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system
microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features . When addresses have been stable for a specified amount of time, the device en ters
the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in
both these modes.
Spansion’s Flash technology combines years of Flas h memory manufacturing experience to produce th e highest levels of quality,
reliability and cost effectiveness. The device electrically erases a l l bit s w i t h i n a s e c t o r s i m u l t an eously via Fowler-Nordheim
tunneling. The data is programmed using hot electron injection.
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 3 of 53
S29AL016D
Contents
Distinctive Characteristics .................................................. 1
General Description ............................................................. 2
1. Product Selector Guide............................................... 4
2. Block Diagram.............................................................. 4
3. Connection Diagrams.................................................. 5
3.1 Special Handling Instructions......................................... 6
4. Pin Configu ration......................................................... 6
5. Logic Symbol ............................................................... 7
6. Ordering Information................................................... 7
6.1 S29AL016D Standard Products..................................... 7
7. Device Bus Operations................................................ 8
7.1 Word/Byte Configuration........... ... .............. ... .. .............. . 9
7.2 Requirements for Reading Array Data........................... 9
7.3 Writing Commands/Command Sequences.................... 9
7.4 Program and Erase Operation Status.......................... 10
7.5 Standby Mode.............................................................. 10
7.6 Automatic Sleep Mode................................................. 10
7.7 RESET#: Hardware Reset Pin. .................................... 10
7.8 Output Disable Mode................................................... 11
7.9 Autoselect Mode............................. .. ... .............. ... ....... 14
7.10 Sector Protection/Unprotection.................................... 14
7.11 Temporary Sector Unprotect........................................ 15
8. Common Flash Memory Interface (CFI)................... 20
8.1 Hardware Data Protection............................... ... ... ....... 22
9. Command Definitions................................................ 22
9.1 Reading Array Data ..................................................... 22
9.2 Reset Command....................... .............. ... ... .............. . 22
9.3 Autoselect Command Sequence ................................. 23
9.4 Word/Byte Program Command Sequence................... 23
9.5 Unlock Bypass Command Sequence .......................... 23
9.6 Chip Erase Command Sequen ce ................................ 24
9.7 Sector Erase Command Sequence ............................. 25
9.8 Erase Suspend/Erase Resume Commands................ 25
10. Command Definitions................................................ 27
11. Write Operation Status .............................................. 28
11.1 DQ7: Data# Polling...................................................... 28
11.2 RY/BY#: Ready/Busy#................................................. 29
11.3 DQ6: Toggle Bit I ......................................................... 30
11.4 DQ2: Toggle Bit II ........................................................ 30
11.5 Reading Toggle Bits DQ6/DQ2.................................... 30
11.6 DQ5: Exceeded Timing Limits ..................................... 31
11.7 DQ3: Sector Erase Timer............................................. 31
12. Absolute Maximum Ratings...................................... 32
13. Operating Ranges...................................................... 32
14. DC Charac te r i s t ic s..................................................... 33
14.1 CMOS Compatible.......................... .. .............. ... ... ....... 33
14.2 Zero Power Flash......................................................... 34
15. Test Conditions........................................................... 35
16. Key to Switching Waveforms..................................... 36
17. AC Characteristics...................................................... 37
17.1 Read Operations........................................................... 37
17.2 Hardware Reset (RESET#)........................................... 38
17.3 Word/Byte Co n fi g uration (BYTE#)................................ 38
17.4 Erase/Program Operations................. ... .............. .. ....... 40
17.5 Temporary Se cto r Un pr otect......................................... 43
17.6 Alternate CE# Controlled Erase/Program Operations .. 44
18. Erase and Programming Performance ..................... 45
19. TSOP, SO, and BGA Pin Capacitance ....................... 46
20. Physical Dimensions.................................................. 47
20.1 TS 048—48-Pin Standard TSOP.................................. 47
20.2 VBK048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
8.15 mm x 6.15 mm ......................................................48
20.3 SO044—44-Pin Small Outline Package (SOP)
28.20 mm x 13.30 mm ..................................................49
21. Revision Summary...................................................... 50
21.1 Revision A (May 4, 2004).............................................. 50
21.2 Revision A1 (July 28, 2004)................ ... .. .............. ... ... . 50
21.3 Revision A2 (December 17, 2004)................................ 50
21.4 Revision A3 (June 1, 2005).............. .............. ... ............ 50
21.5 Revision A4 (June 17, 2005)............ .............. ... ............ 51
21.6 Revision A5 (May 22, 2006).......................................... 51
21.7 Revision A6 (Se pt ember 7, 2007)................................. 51
21.8 Revision A7 (November 27, 2007)................................ 51
21.9 Revision A8 (February 27, 2009)................ ... ... ............ 51
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 4 of 53
S29AL016D
1. Product Selector Guide
Note
See AC Characteristics on page 37 for full specifications.
2. Block Diagram
Family Part Number S29AL016D
Speed Option Voltage Range: VCC = 2.7–3.6 V 70 90
Max access time, ns (tACC)70 90
Max CE# access time, ns (tCE)70 90
Max OE# access time, ns (tOE)30 35
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
VCC Detector
State
Control
Command
Register
VCC
VSS
WE#
BYTE#
CE#
OE#
STB
STB
DQ0
–
DQ15 (A-1)
Sector Switches
RY/BY#
RESET#
Data
Latch
Y-Gating
Cell Matrix
Address Latch
A0–A19
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 5 of 53
S29AL016D
3. Connection Diagrams
A1
A15
A18
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RESET#
NC
NC
RY/BY#
A17
A7
A6
A5
A4
A3
A2
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
A16
DQ2
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
Standard TSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
RESET#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
V
SS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
WE#
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
Standard SOP
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 6 of 53
S29AL016D
3.1 Special Handling Instructions
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data
integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time.
4. Pin Configuration
A0–A19 20 addresses
DQ0–DQ14 15 data inputs/outputs
DQ15/A-1 DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode)
BYTE# Selects 8-bit or 16-bit mode
CE# Chip enable
OE# Out put enable
WE# Write enable
RESET# Hardware reset pin
RY/BY# Ready/Busy output
VCC 3.0 volt-only single power su pply (see Product Select or Guide on page 4 for speed options and voltage supp ly
tolerances)
VSS Device ground
NC Pin not connected internally
A1 B1 C1 D1 E1 F1 G1 H1
A2 B2 C2 D2 E2 F2 G2 H2
A3 B3 C3 D3 E3 F3 G3 H3
A4 B4 C4 D4 E4 F4 G4 H4
A5 B5 C5 D5 E5 F5 G5 H5
A6 B6 C6 D6 E6 F6 G6 H6
DQ15/A-1 V
SS
BYTE#A16A15A14A12A13
DQ13 DQ6DQ14DQ7A11A10A8A9
V
CC
DQ4DQ12DQ5A19NCRESET#WE#
DQ11 DQ3DQ10DQ2NCA18NCRY/BY#
DQ9 DQ1DQ8DQ0A5A6A17A7
OE# V
SS
CE#A0A1A2A4A3
FBGA
Top View, Balls Facing Down
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 7 of 53
S29AL016D
5. Logic Symbol
6. Ordering Information
This product has been retired and is not recommended for designs. For new and current designs, S29AL0 16J supercedes
S29AL016D. This is the factory-recommended migration path. Please refer to the S29AL 016J data sheet for specifications and
ordering information.
6.1 S29AL016D Standard Products
Spansion standard products are available in several packages and operating rang es. The order number (Valid Combination) is
formed by a combination of the elements below.
S29AL016D 70 T A I 01 0
Packing Type
0=Tray
1 = Tube
2 = 7” Tape and Reel
3 = 13” Tape and Reel
Model Number
01 = VCC = 2.7 - 3.6V, top boot sector device
02 = VCC = 2.7 - 3.6V, bottom boot sector device
Temper ature Range
I = Industrial (-40°C to +85°C)
N = Extended (-40°C to +125°C)
Package Material Set
A = Standard
F = Pb-Free
Package Type
T = Thin Small Outline Package (TSOP) Standard Pinout
B = Fine-pitch Ball-Grid Array Package
M = Small Outline Package (SOP) Standard Pinout
Speed Option
70 = 70 ns Access Speed
90 = 90 ns Access Speed
Device Number/Description
S29AL016D
16 Megabit Flash Memory manufactured using 200 nm process technology
3.0 Volt-only Read, Program, and Erase
20
16 or 8
DQ0–DQ15
(A-1)
A0–A19
CE#
OE#
WE#
RESET#
BYTE# RY/BY#
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 8 of 53
S29AL016D
Notes
1. Type 0 is standard. Specify other options as required.
2. Type 1 is standard. Specify other options as required.
3. TSOP and SOP package markings omit packing type designator from order ing part number.
4. BGA package marking omits leading S29 and packing type designator from ordering part number.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
7. Device Bus Operations
This section describes the re quirements and use of the device bus operations, which are initiated through the internal command
register. The command registe r itself doe s not occupy any addressable memory location. The register is composed of latches that
store the commands, along with the address and data information needed to execute the command. The contents of the register
serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table lists the device bus
operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these
operations in further detail.
S29AL016D Valid Combinations
Package
Description
Device
Number Speed
Option
Package Type,
Material, and
Temperature Range Model
Number Packing
Type
S29AL016D 70, 90
TAI , TFI,
TAN, TFN
01, 02
0, 3
(Note 1) TS048 (Note 3) TSOP
BAI, BFI,
BAN, BFN 0, 2, 3
(Note 1) VBK048 (Note 4) Fine-Pitch BGA
MAI, MFI,
MAN, MFN 0, 1, 3
(Note 2) SO044 (Note 3) SOP
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 9 of 53
S29AL016D
Legend
L = Logic Low = VIL
H = Logic High = VIH
VID = 12.0 0.5 V
X = Don’t Care
AIN = Address In
DIN = Data In
DOUT = Data Out
Notes
1. Addresses are A19:A0 in word mode (BYTE# = VIH), A19: A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See Sector Protection/Unprotection on page 14.
7.1 Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is
set at logic 1, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by
CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
7.2 Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the
device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines
whether the device outputs array da ta in words or bytes.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no
spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the
device data outputs. The device remains enabled for read access until the command regi ster contents are altered.See Reading
Array Data on page 22 for more information. Refer to the AC Read Operations on page 37 for timing specifications and to
Figure 17.1 on page 37 for the timing diagram. ICC1 in DC Characteristics on page 33 represents the active current specification for
reading array data.
7.3 Writing Commands/Command Sequences
To write a command or comma nd sequence (which includes programming data to the device and era sing sectors of memory), the
system must drive WE# and CE# to VIL, and OE# to VIH.
S29AL016D Device Bus Oper ations
Operation CE# OE# WE# RESET# Addresses
(Note 1) DQ0–
DQ7
DQ8–DQ15
BYTE#
= VIH
BYTE#
= VIL
Read L L H H AIN DOUT DOUT DQ8–DQ14 = High-Z,
DQ15 = A-1
Write L H L H AIN DIN DIN
Standby VCC
0.3 V XXVCC
0.3 V X High-Z High-Z High-Z
Output Disable L H H H X High-Z High-Z High-Z
Reset X X X L X High-Z High-Z High-Z
Sector Protect (Note 2) LHL V
ID
Sector Address,
A6 = L, A1 = H,
A0 = L DIN XX
Sector Unprotect (Note 2) LHL V
ID
Sector Address,
A6 = H, A1 = H,
A0 = L DIN XX
Temporary Sector
Unprotect XXX V
ID AIN DIN DIN High-Z
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 10 of 53
S29AL016D
For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. See Word/Byte
Configuration on page 9 for more information.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode,
only two write cycles are required to program a word or byte, instead of four. Word/Byte Program Command Sequence on page 23
has details on programming data to the device using both standard and Unlock Bypass command seque nces.
An erase operation can erase one sector, multiple sectors, or the entire device. Table on page 11 and Table on page 13 indicate
the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector.
The Command Definitions on page 22 has details on erasing a sector or the entire chip, or suspen ding/resuming the erase
operation.
After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read
autoselect codes from the intern al register (which is separate from the memory arra y) on DQ7–DQ0. Standard read cycle timings
apply in this mode. Refer to Autoselect Mode on page 14 and Autoselect Command Sequence on page 23 for more information.
ICC2 in DC Characteristics on page 33 represents the active current specification for the write mode. AC Characteristics on page 37
contains timing specification tables and timin g diagrams for write operations.
7.4 Program and Erase Operation Status
During an erase or program opera tion, the system may check the status of the operation by reading the status bits on DQ7–DQ0.
Standard read cycle timings and ICC read specifications apply. Refer to Write Operation Status on page 28 for more information, and
to AC Characteristics on pag e 37 for timing diagrams.
7.5 Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of th e OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC 0.3 V. (Note that this is a more
restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC 0.3 V, the device will be in the standby
mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in
either of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation is comple ted.
ICC3 and ICC4 represents the standby current specifi cati on shown in the table in DC Characteristics on page 33.
7.6 Automatic Sleep Mode
The automatic slee p mode minimizes Flash device energy consumption. Th e device automatically enables this mode when
addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals.
Standard address access timings provide new data when addresses are changed. While in sle ep m ode, output data is latched and
always available to the system. ICC4 in the DC Characteristics on page 33 represents the automatic sleep mode current
specification.
7.7 RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET#
pin to VIL for at least a period of tRP, the device immediately terminates any operation in progress, tristates all data output pins, and
ignores all read/write attempts for the dura tion of the RESET# pulse. The device also resets the internal state machine to reading
array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence,
to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby
current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the
system to read the boot-up firmware from the Flash me mory.If RESET# is asserted during a program or erase operation, the RY/
BY# pin remains a 0 (busy) until the internal re set operation is complete, which requires a time of tREADY (during Embedded
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 11 of 53
S29AL016D
Algorithms).The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing (RY/BY# pin is 1), the reset operation is completed within a time of tREADY (not
during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH.Refer to the tables in AC
Characteristics on page 37 for RESET# parameters and to Figure 17.2 on page 38 for the timing diagram.
7.8 Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. Th e output pins are placed in the high impedance state.
Sector Address Tables (Top Boot Device)
Sector A19 A18 A17 A16 A15 A14 A13 A12
Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecimal)
Byte Mode (x8) Word Mode (x16)
SA000000XXX 64/32 000000–00FFFF 00000–07FFF
SA100001XXX 64/32 010000–01FFFF 08000–0FFFF
SA200010XXX 64/32 020000–02FFFF 10000–17FFF
SA300011XXX 64/32 030000–03FFFF 18000–1FFFF
SA400100XXX 64/32 040000–04FFFF 20000–27FFF
SA500101XXX 64/32 050000–05FFFF 28000–2FFFF
SA600110XXX 64/32 060000–06FFFF 30000–37FFF
SA700111XXX 64/32 070000–07FFFF 38000–3FFFF
SA801000XXX 64/32 080000–08FFFF 40000–47FFF
SA901001XXX 64/32 090000–09FFFF 48000–4FFFF
SA1001010XXX 64/32 0A0000–0AFFFF 50000–57FFF
SA1101011XXX 64/32 0B0000–0BFFFF 58000–5FFFF
SA1201100XXX 64/32 0C0000–0CFFFF 60000–67FFF
SA1301101XXX 64/32 0D0000–0DFFFF 68000–6FFFF
SA1401110XXX 64/32 0E0000–0EFFFF 70000–77FFF
SA1501111XXX 64/32 0F0000–0FFFFF 78000–7FFFF
SA1610000XXX 64/32 100000–10FFFF 80000–87FFF
SA1710001XXX 64/32 110000–11FFFF 88000–8FFFF
SA1810010XXX 64/32 120000–12FFFF 90000–97FFF
SA1910011XXX 64/32 130000–13FFFF 98000–9FFFF
SA2010100XXX 64/32 140000–14FFFF A0000–A7FFF
SA2110101XXX 64/32 150000–15FFFF A8000–AFFFF
SA2210110XXX 64/32 160000–16FFFF B0000–B7FFF
SA2310111XXX 64/32 170000–17FFFF B8000–BFFFF
SA2411000XXX 64/32 180000–18FFFF C0000–C7FFF
SA2511001XXX 64/32 190000–19FFFF C8000–CFFFF
SA2611010XXX 64/32 1A0000–1AFFFF D0000–D7FFF
SA2711011XXX 64/32 1B0000–1BFFFF D8000–DFFFF
SA2811100XXX 64/32 1C0000–1CFFFF E0000–E7FFF
SA2911101XXX 64/32 1D0000–1DFFFF E8000–EFFFF
SA3011110XXX 64/32 1E0000–1EFFFF F0000–F7FFF
SA31111110XX 32/16 1F0000–1F7FFF F8000–FBFFF
SA3211111100 8/4 1F8000–1F9FFF FC000–FCFFF
SA3311111101 8/4 1FA000–1FBFFF FD000–FDFFF
SA341111111X 16/8 1FC000–1FFFFF FE000–FFFFF
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 12 of 53
S29AL016D
Note
Address range is A19:A-1 in byte mode and A19:A0 in word mode. See Word/Byte Configuration on page 9.
Sector Address Tables (Bottom Boot Device)
Sector A19 A18 A17 A16 A15 A14 A13 A12
Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecimal)
Byte Mode (x8) Word Mode (x16)
SA00000000X 16/8 000000–003FFF 00000–01FFF
SA100000010 8/4 004000–005FFF 02000–02FFF
SA200000011 8/4 006000–007FFF 03000–03FFF
SA3000001XX 32/16 008000–00FFFF 04000–07FFF
SA400001XXX 64/32 010000–01FFFF 08000–0FFFF
SA500010XXX 64/32 020000–02FFFF 10000–17FFF
SA600011XXX 64/32 030000–03FFFF 18000–1FFFF
SA700100XXX 64/32 040000–04FFFF 20000–27FFF
SA800101XXX 64/32 050000–05FFFF 28000–2FFFF
SA900110XXX 64/32 060000–06FFFF 30000–37FFF
SA1000111XXX 64/32 070000–07FFFF 38000–3FFFF
SA1101000XXX 64/32 080000–08FFFF 40000–47FFF
SA1201001XXX 64/32 090000–09FFFF 48000–4FFFF
SA1301010XXX 64/32 0A0000–0AFFFF 50000–57FFF
SA1401011XXX 64/32 0B0000–0BFFFF 58000–5FFFF
SA1501100XXX 64/32 0C0000–0CFFFF 60000–67FFF
SA1601101XXX 64/32 0D0000–0DFFFF 68000–6FFFF
SA1701110XXX 64/32 0E0000–0EFFFF 70000–77FFF
SA1801111XXX 64/32 0F0000–0FFFFF 78000–7FFFF
SA1910000XXX 64/32 100000–10FFFF 80000–87FFF
SA2010001XXX 64/32 110000–11FFFF 88000–8FFFF
SA2110010XXX 64/32 120000–12FFFF 90000–97FFF
SA2210011XXX 64/32 130000–13FFFF 98000–9FFFF
SA2310100XXX 64/32 140000–14FFFF A0000–A7FFF
SA2410101XXX 64/32 150000–15FFFF A8000–AFFFF
SA2510110XXX 64/32 160000–16FFFF B0000–B7FFF
SA2610111XXX 64/32 170000–17FFFF B8000–BFFFF
SA2711000XXX 64/32 180000–18FFFF C0000–C7FFF
SA2811001XXX 64/32 190000–19FFFF C8000–CFFFF
SA2911010XXX 64/32 1A0000–1AFFFF D0000–D7FFF
SA3011011XXX 64/32 1B0000–1BFFFF D8000–DFFFF
SA3111100XXX 64/32 1C0000–1CFFFF E0000–E7FFF
SA3211101XXX 64/32 1D0000–1DFFFF E8000–EFFFF
SA3311110XXX 64/32 1E0000–1EFFFF F0000–F7FFF
SA3411111XXX 64/32 1F0000–1FFFFF F8000–FFFFF
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 13 of 53
S29AL016D
Note
Address range is A19:A-1 in byte mode and A19:A0 in word mode. See the Word/Byte Configuration on page 9.
Sector Address Tables (Bottom Boot Device)
Sector A19 A18 A17 A16 A15 A14 A13 A12
Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecimal)
Byte Mode (x8) Word Mode (x16)
SA00000000X 16/8 000000–003FFF 00000–01FFF
SA100000010 8/4 004000–005FFF 02000–02FFF
SA200000011 8/4 006000–007FFF 03000–03FFF
SA3000001XX 32/16 008000–00FFFF 04000–07FFF
SA400001XXX 64/32 010000–01FFFF 08000–0FFFF
SA500010XXX 64/32 020000–02FFFF 10000–17FFF
SA600011XXX 64/32 030000–03FFFF 18000–1FFFF
SA700100XXX 64/32 040000–04FFFF 20000–27FFF
SA800101XXX 64/32 050000–05FFFF 28000–2FFFF
SA900110XXX 64/32 060000–06FFFF 30000–37FFF
SA1000111XXX 64/32 070000–07FFFF 38000–3FFFF
SA1101000XXX 64/32 080000–08FFFF 40000–47FFF
SA1201001XXX 64/32 090000–09FFFF 48000–4FFFF
SA1301010XXX 64/32 0A0000–0AFFFF 50000–57FFF
SA1401011XXX 64/32 0B0000–0BFFFF 58000–5FFFF
SA1501100XXX 64/32 0C0000–0CFFFF 60000–67FFF
SA1601101XXX 64/32 0D0000–0DFFFF 68000–6FFFF
SA1701110XXX 64/32 0E0000–0EFFFF 70000–77FFF
SA1801111XXX 64/32 0F0000–0FFFFF 78000–7FFFF
SA1910000XXX 64/32 100000–10FFFF 80000–87FFF
SA2010001XXX 64/32 110000–11FFFF 88000–8FFFF
SA2110010XXX 64/32 120000–12FFFF 90000–97FFF
SA2210011XXX 64/32 130000–13FFFF 98000–9FFFF
SA2310100XXX 64/32 140000–14FFFF A0000–A7FFF
SA2410101XXX 64/32 150000–15FFFF A8000–AFFFF
SA2510110XXX 64/32 160000–16FFFF B0000–B7FFF
SA2610111XXX 64/32 170000–17FFFF B8000–BFFFF
SA2711000XXX 64/32 180000–18FFFF C0000–C7FFF
SA2811001XXX 64/32 190000–19FFFF C8000–CFFFF
SA2911010XXX 64/32 1A0000–1AFFFF D0000–D7FFF
SA3011011XXX 64/32 1B0000–1BFFFF D8000–DFFFF
SA3111100XXX 64/32 1C0000–1CFFFF E0000–E7FFF
SA3211101XXX 64/32 1D0000–1DFFFF E8000–EFFFF
SA3311110XXX 64/32 1E0000–1EFFFF F0000–F7FFF
SA3411111XXX 64/32 1F0000–1FFFFF F8000–FFFFF
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 14 of 53
S29AL016D
7.9 Autoselect Mode
The autoselect mode provid es manufacturer and device identification, and sector protection verification, through identifi er codes
output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be
programmed with its corresponding programming algorithm. However, th e autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1,
and A0 must be as shown in Table . In addition, when verifying sector protection, the sector address must appear on the appropriate
highest order address bits (see Table on page 11 and Table on page 13). Table shows the remaining address bits that are don’t
care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier
code on DQ7-DQ0.
To access the autoselect codes in-system, the host system can issue the autoselect command via the c ommand register, as shown
in Table on page 27. This method does not require VID. See Command Definitions on page 22 for details on using the autoselect
mode.
Legend
L = Logic Low = VIL
H = Logic High = VIH
SA = Sector Address
X = Don’t care
Note
The autoselect codes may also be accessed in-system via command sequences. See Table on page 27.
7.10 Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection
feature re-enables both program and erase operations in previ ously protected sectors.
The device is shipped with all sectors unprotected. Spansion offe rs the option of programming and protecting sectors at its factory
prior to shipping the device through Spansi on’s ExpressFlash™ Service. Contact a Spansion representative for details.
It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode on page 14 for details.
Sector protection/unprotection can be implemented via two methods.
The primary method requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment.
Figure on page 16 shows the algorithms and Figure 17.12 on pa ge 44 shows the timing diagram. This method uses standard
microprocessor bus cycle timing. For sector unprotect, al l unprotected sectors must first be protected prior to the first sector
unprotect write cycle.
The alternate method intended only for programming equipment requires VID on address pin A9 and OE#. This method is
compatible with programmer routines written for earlier 3.0 volt-only Spansion flash devices. Details on this method are provid ed in
a supplement, publication number 21468. Contact a Spansion representative to request a cop y.
S29AL016D Autoselect Code s (High Voltage Method)
Description Mode CE# OE# WE#
A19
to
A12
A11
to
A10 A9
A8
to
A7 A6
A5
to
A4
A3
to
A2 A1 A0
DQ8
to
DQ15
DQ7
to
DQ0
Manufacturer ID: Spansion L L H X X VID XLXLLL X 01h
Device ID:
S29AL016D
(Top Boot Block)
Word L L H XXV
ID XLXLLH22h C4h
Byte L L H X C4h
Device ID:
S29AL016D
(Bottom Boot Block)
Word L L H XXV
ID XLXLLH22h 49h
Byte L L H X 49h
Sector Protection Verification L L H SA X VID XLXLHL X 01h (protected)
X 00h (unprotected)
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 15 of 53
S29AL016D
7.11 Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is
activated by sett ing the R ESET# pi n to VID. During this mode, formerly protected sectors can be programmed or erased by selecting
the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again.
Figure 7.1 shows the algorithm, and Figure 1 7.11 on pag e 43 shows the timing diagrams, for this feature.
Figure 7.1 Temporary Sector Unprotect Operation
Notes
1. All protected sectors unprotected.
2. All previously protected sectors are protect ed once again.
Figure 7.2 In-System Sector Protect/Unprotect Algo rithms
3.
START
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 7.2)
RESET# = VID
(Note 1)
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 16 of 53
S29AL016D
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Set up sector
address
Wait 150 µs
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
A1 = 1, A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = V
ID
Wait 1 μs
First Write
Cycle = 60h?
Data = 01h?
Remove V
ID
from RESET#
Write reset
command
Sector Protect
complete
Yes
Yes
No
PLSCNT
= 25?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Unprotect Mode No
Sector Unprotect:
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Set up first sector
address
Wait 15 ms
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = V
ID
Wait 1 μs
Data = 00h?
Last sector
verified?
Remove V
ID
from RESET#
Write reset
command
Sector Unprotect
complete
Yes
No
PLSCNT
= 1000?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Unprotect Mode
No All sectors
protected?
Yes
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
Set up
next sector
address
No
Yes
No
Yes
No
No
Yes
No
Sector Protect
Algorithm Sector Unprotect
Algorithm
First Write
Cycle = 60h?
Protect another
sector?
Reset
PLSCNT = 1
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 17 of 53
S29AL016D
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Set up sector
address
Wait 150 µs
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
A1 = 1, A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = V
ID
Wait 1 μs
First Write
Cycle = 60h?
Data = 01h?
Remove V
ID
from RESET#
Write reset
command
Sector Protect
complete
Yes
Yes
No
PLSCNT
= 25?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Unprotect Mode No
Sector Unprotect:
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Set up first sector
address
Wait 15 ms
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = V
ID
Wait 1 μs
Data = 00h?
Last sector
verified?
Remove V
ID
from RESET#
Write reset
command
Sector Unprotect
complete
Yes
No
PLSCNT
= 1000?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Unprotect Mode
No All sectors
protected?
Yes
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
Set up
next sector
address
No
Yes
No
Yes
No
No
Yes
No
Sector Protect
Algorithm Sector Unprotect
Algorithm
First Write
Cycle = 60h?
Protect another
sector?
Reset
PLSCNT = 1
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 18 of 53
S29AL016D
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Set up sector
address
Wait 150 µs
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
A1 = 1, A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = V
ID
Wait 1 μs
First Write
Cycle = 60h?
Data = 01h?
Remove V
ID
from RESET#
Write reset
command
Sector Protect
complete
Yes
Yes
No
PLSCNT
= 25?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Unprotect Mode No
Sector Unprotect:
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Set up first sector
address
Wait 15 ms
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = V
ID
Wait 1 μs
Data = 00h?
Last sector
verified?
Remove V
ID
from RESET#
Write reset
command
Sector Unprotect
complete
Yes
No
PLSCNT
= 1000?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Unprotect Mode
No All sectors
protected?
Yes
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
Set up
next sector
address
No
Yes
No
Yes
No
No
Yes
No
Sector Protect
Algorithm Sector Unprotect
Algorithm
First Write
Cycle = 60h?
Protect another
sector?
Reset
PLSCNT = 1
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 19 of 53
S29AL016D
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Set up sector
address
Wait 150 µs
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
A1 = 1, A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = V
ID
Wait 1 μs
First Write
Cycle = 60h?
Data = 01h?
Remove V
ID
from RESET#
Write reset
command
Sector Protect
complete
Yes
Yes
No
PLSCNT
= 25?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Unprotect Mode No
Sector Unprotect:
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Set up first sector
address
Wait 15 ms
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = V
ID
Wait 1 μs
Data = 00h?
Last sector
verified?
Remove V
ID
from RESET#
Write reset
command
Sector Unprotect
complete
Yes
No
PLSCNT
= 1000?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Unprotect Mode
No All sectors
protected?
Yes
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
Set up
next sector
address
No
Yes
No
Yes
No
No
Yes
No
Sector Protect
Algorithm Sector Unprotect
Algorithm
First Write
Cycle = 60h?
Protect another
sector?
Reset
PLSCNT = 1
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 20 of 53
S29AL016D
8. Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system softw are interrogation handshake, which allows
specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-
independent, JEDEC ID-independent, and forward- and backward-compati ble for the specified flash device families. Flash vendors
can standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or
address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses
given in Table to Table on page 21. In word mode, the upper address bits (A7–MSB) must be all zeros. To terminate reading CFI
data, the system must write the reset command.
The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query
mode, and the system can read CFI data at th e addresses given in Table to Table on page 21. The system must write the reset
command to return the device to the autoselect mode.
For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://
www.amd.com/products/nvd/overview/cfi.html. Alternatively, contact a Spansion representative for copies of these documents.
CFI Query Identification String
Addresses
(Word Mode) Addresses
(Byte Mode) Data Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h Query Unique ASCII string “QRY”
13h
14h 26h
28h 0002h
0000h Primary OEM Command Set
15h
16h 2Ah
2Ch 0040h
0000h Address for Primary Extended Table
17h
18h 2Eh
30h 0000h
0000h Alternate OEM Command Set (00h = none exists)
19h
1Ah 32h
34h 0000h
0000h Address for Alternate OEM Extended Table (00h = none exists)
System Interface String
Addresses
(Word Mode) Addresses
(Byte Mode) Data Description
1Bh 36h 0027h VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch 38h 0036h VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP pin present)
1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present)
1Fh 3Eh 0004h Typical timeout per single byte/word write 2N µs
20h 40h 0000h T ypical timeout for Min. size buffer write 2N µs (00h = not supported)
21h 42h 000Ah Typical timeout per individual block erase 2N ms
22h 44h 0000h Typical timeout for full chip erase 2N ms (0 0h = not supported)
23h 46h 0005h Max. timeout for byte/word write 2N times typical
24h 48h 0000h Max. timeout for buffer wri te 2N times typical
25h 4Ah 0004h Max. timeout per individual block erase 2N tim es typi cal
26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 21 of 53
S29AL016D
Device Geometry Definition
Addresses
(Word Mode) Addresses
(Byte Mode) Data Description
27h 4Eh 0015h Device Size = 2N byte
28h
29h 50h
52h 0002h
0000h Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh 54h
56h 0000h
0000h Max. number of byte in multi-byte write = 2N
(00h = not supported )
2Ch 58h 0004h Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
0000h
0000h
0040h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
62h
64h
66h
68h
0001h
0000h
0020h
0000h
Erase Block Region 2 Information
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0080h
0000h
Erase Block Region 3 Information
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
001Eh
0000h
0000h
0001h
Erase Block Region 4 Information
Primary Vendor-Specific Extended Query
Addresses
(Word Mode) Addresses
(Byte Mode) Data Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h Query-unique ASCII string “PRI”
43h 86h 0031h Major version number, ASCII
44h 88h 0030h Minor version number, ASCII
45h 8Ah 0000h Address Sensitive Unlock
0 = Required, 1 = Not Required
46h 8Ch 0002h Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h 8Eh 0001h Sector Protect
0 = Not Supported, X = Number of sectors per group
48h 90h 0001h Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h 92h 0004h Sector Protect/Unprotect scheme
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode
4Ah 94h 0000h Simultaneous Operation
00 = Not Supported, 01 = Supported
4Bh 96h 0000h Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch 98h 0000h Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 22 of 53
S29AL016D
8.1 Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent
writes (refer to Table on page 27 for command defin itions). In addition, the following hardware data protection measures prevent
accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and
power-down transitions, or from system noise.
8.1.1 Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down.
The command register and all internal program/erase circuits are disabled, and the devi ce resets. Subsequent writes are ignored
until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when
VCC is greater than VLKO.
8.1.2 Write Pulse Glitch Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
8.1.3 Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be
a logical zero while OE# is a logical one.
8.1.4 Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal
state machine is a ut om at ica l l y rese t to readi n g array data on power-up.
9. Command Definitions
Writing specific address and data commands or sequences into the command register initiates device operations. Table on page 27
defines the valid register command seque nces. Writing incorrect address and data values or writing them in the improper
sequence resets the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE#
or CE#, whichever happens first. Refer to the appropriate timing diagrams in AC Characteristics on page 37.
9.1 Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device
is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data
using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data.
After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same
exception. See Erase Suspend/Erase Resume Commands on page 25 for more information on this mode.
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect
mode. See Reset Command on page 22.
See also Requirements for Reading Array Data on page 9 for more information. The Read Operations on page 37 provides the read
parameters, and Figure 17.1 on page 37 shows the timing diag ram.
9.2 Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command.
The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This
resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is
complete.
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 23 of 53
S29AL016D
The reset command may be written between the sequence cycles in a program command sequence before programming begins.
This resets the device to reading array data (also applies to programming in Erase Suspen d mode). Once programming begins,
however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect
mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspen d).
If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also
applies during Erase Suspend).
9.3 Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether
or not a sector is protected. Table on page 27 shows the address and data requirements. This method is an alternative to that
shown in Table on page 14, which is intended for PROM programme rs and requires V ID on address bit A9.
The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then
enters the autoselect mode, and the system may read at any address any number of times, without initiating another command
sequence.
A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h returns the device code. A read
cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is
protected, or 00h if it is unprotected. Refer to Table on page 11 and Table on page 13 for valid sector addresses.
The system must write the reset command to exit the autoselect mode and return to reading array data.
9.4 Word/Byte Program Command Sequence
The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle
operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up
command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is
not required to provide further controls or timings. The device automatica lly generates the program pulses and verifies the
programmed cell margin. Table on page 27 shows the address and data requirements for the byte program command sequence.
When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer
latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See Write Operation Status
on page 28 for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately
terminates the programming operation. The Byte Program command sequence should be reinitiated once the device has reset to
reading array data, to ensure data integrity.
Programming is allowed in any sequence and across sector boundarie s. A bit cannot be programmed from a 0 back to a 1.
Attempting to do so may halt the operation and set DQ5 to 1, or cause the Data# Polling algorithm to indicate the operation was
successful. However, a succeeding read will show that the data is still 0. Only erase operations can convert a 0 to a 1.
9.5 Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program
command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a thi rd
write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock
bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the
unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence,
resulting in faster total programming time. Table on page 27 shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock
bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data.
Figure 9.1 on page 24 illustrates the algorithm for the program operation. See Erase/Program Op erations on page 40 for
parameters, and to Figure 17.5 on page 40 for timing diagrams.
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 24 of 53
S29AL016D
Figure 9.1 Program Operation
Note
See Table on page 27 for program command sequence.
9.6 Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a
set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the
Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these operations. Table on page 27 shows the address and data requirements for
the chip erase command sequence.
Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip
erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device
has returned to reading array data, to ensure data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See Write Operation Status
on page 28 for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading
array data and addresses are no longer latched.
Figure 9.2 on page 26 illustrates the algorithm for the erase operation. See Erase/Program Operations on page 40 for parameters,
and Figure 17.6 on page 41 for timing diagrams.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 25 of 53
S29AL016D
9.7 Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by
a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector
erase command. Table on page 27 shows the address and data requirements for the sector erase command sequence.
The device does not requ ire the system to preprogram the memory prior to erase. The Embedded Erase alg orithm automaticall y
programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any
controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period, additional sector
addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the
number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs,
otherwise the last address and command might not be accepted, and erasure may begin. It is recommend ed that processor
interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector
Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 µs, the system
need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the
device to reading array data. The system must rewrite the command sequence and any additional sector addresses and
commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out. (See DQ3: Sector Erase Timer on page 31.) The
time-out begins from the rising edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note that
a hardware reset during the sector erase operation immediately terminates the opera tion. The Sector Erase command sequence
should be reinitiated once the device has returned to reading array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the device returns to reading array data and ad dresses are no longer latched.
The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to Write Operation Status
on page 28 for information on these status bits.)
Figure 9.2 on page 26 illustrates the algorithm for the erase operation. Refer to Erase/Program Operations on page 40 for
parameters, and to Figure 17.6 on page 41 for timing diagrams.
9.8 Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to,
any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out
period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase
operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately
terminates the time-out period and suspends the erase op eration. Addresses are don’t-cares when writing the Erase Suspend
command.
When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 µs to suspend
the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device
immediately terminates the time-out period and suspends the erase operation.
After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for
erasure. (The device “erase suspends” all sectors selected for erasure.) Normal read and write timings and command definitions
apply. Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or
DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See Write Operation Status on page 28
for information on these status bits.
After an erase-suspended program operation is comple te, the system can once again read array data within non-suspended
sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard
program operation. See Write Operation Status on page 28 for more information.
The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows
reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See
Autoselect Command Sequence on page 23 for more information.
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 26 of 53
S29AL016D
The system must write the Erase Resume command (address bits are don’t care) to exit the erase suspend mode and continue the
sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after
the device has resumed erasing.
Figure 9.2 Erase Operation
Notes
1. See Table on page 27 for erase command sequence.
2. See DQ3: Sector Erase Timer on page 31 for more information.
START
Write Erase
Command Sequence
Data Poll
from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 27 of 53
S29AL016D
10. Command Definitions
Legend
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latc h on the falling edge of the WE# or CE# pulse, whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (i n autoselect mode) or erased. Address bi ts A19–A12 uniquely se lect any sector.
Notes
1. See Table on page 9 for description of bus ope rations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 are don’t cares for unlock and command cycles.
5. Address bit s A19–A11 are don’t cares for unlock and command cycles, unless SA or PA required.
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data).
8. The fourth cycle of the autoselect command sequence is a read cycle.
9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more information.
10.Command is valid when device is ready to read array dat a or when device is in autoselect mode.
11. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
12.The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. F0 is also acceptable.
S29AL016D Command Definitions
Command
Sequence
(Note 1)
Cycles
Bus Cycles (Notes 2–5)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1RARD
Reset (Note 7) 1XXX F0
Autoselect (Note 8)
Manufacturer ID Word 4555 AA 2AA 55 555 90 X00 01
Byte AAA 555 AAA
Device ID,
Top Boot Block Word 4555 AA 2AA 55 555 90 X01 22C4
Byte AAA 555 AAA X02 C4
Device ID,
Bottom Boot Block Word 4555 AA 2AA 55 555 90 X01 2249
Byte AAA 555 AAA X02 49
Sector Protect Verify
(Note 9)
Word
4
555
AA
2AA
55
555
90
(SA)
X02 XX00
XX01
Byte AAA 555 AAA (SA)
X04 00
01
CFI Query (Note 10) Word 155 98
Byte AA
Program Word 4555 AA 2AA 55 555 A0 PA PD
Byte AAA 555 AAA
Unlock Bypass Word 3555 AA 2AA 55 555 20
Byte AAA 555 AAA
Unlock Bypass Program (Note 11) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 12) 2XXX 90 XXX 00
Chip Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Byte AAA 555 AAA AAA 555 AAA
Sector EraseWord 6555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Byte AAA 555 AAA AAA 555
Erase Suspend (Note 13) 1 XXX B0
Erase Resume (Note 14) 1XXX 30
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 28 of 53
S29AL016D
13.The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Su spend mode. The Erase Suspend command is valid
only during a sector erase operation.
14.The Erase Resume command is valid only during the Erase Suspend mode.
11. Write Operation Status
The device provides several bits to dete rmine the status of a write operation: DQ2, DQ3, DQ5 , DQ6 , DQ7, and RY/BY#. Table
on page 32 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for
determining whether a program or erase operation is complete or in progress. These three bits are discussed first.
11.1 DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether
the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command
sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7
status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs
the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program
address fall s wi thin a protected secto r, Da ta# Polling on DQ7 is active for approximately 1 µs, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase algorithm is complete, or if
the device enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7. This is analogous to the complement/true datum
output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to 1; prior to this, the
device outputs the complement, or 0. The system must provide an address within any of the sectors selected for erasure to read
valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for
approximately 100 µs, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignore s the selected sectors that are protected.
When the system detects DQ7 has changed fro m the comple ment to true data, it can read valid data at DQ7–DQ0 on the following
read cycles. This is because DQ7 may change asynchronously with DQ0–DQ6 whil e Output Enable (OE#) is asserted low.
Figure 1 7.8 on page 42, illustrates this.
Table on page 32 shows the outputs for Data# Po ll i n g on DQ 7. Figure 11.2 on page 31 shows the Data# Polli ng algorithm.
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 29 of 53
S29AL016D
Figure 1 1.1 Data# Polling Algorithm
Notes
1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector select ed for erasure. Duri ng chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.
11.2 RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The
RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output,
several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.)
If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby
mode.
Table on page 32 shows the outputs for RY/BY#. Figures Figure 17.1 on page 37, Figure 17.2 on page 38, Figure 17.5 on page 40
and Figure 17.6 on page 41 shows RY/BY# for read, reset, program, and erase operations, respectively.
DQ7 = Data? Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 30 of 53
S29AL016D
11.3 DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device
has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE#
pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successi ve read cycles to any address cause DQ6 to toggle. (The
system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs,
then returns to reading array data. If not all selected sectors are protected, the Embedded Eras e algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the
device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase
Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-
suspended. Alternatively, the system can use DQ7 (see DQ7: Data# Polling on page 28).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is
written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete.
Table on page 32 shows the outputs for Toggle Bit I on DQ6. Figure 11.2 on page 31 shows the toggle bit algorithm in flowchart
form, and Reading Toggle Bits DQ6/DQ2 on page 30 explains the algorithm. Fi gure 17 .9 on page 42 shows the toggle bit timin g
diagrams. Figure 17.10 on page 43 shows the differences between DQ2 and DQ6 in graph ical form. See also the subsection on
DQ2: Toggle Bit II on pag e 30.
11.4 DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded
Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE#
pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use
either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-
suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspen d, but cannot distinguish
which sectors are selected for erasure. Thus, both status bits are required for sector and mo de information. Refer to Table
on page 32 to compare outputs for DQ2 and DQ6.
Figure 11.2 on page 31 shows the toggle bit algorithm in flowchart form, and the section Reading Toggle Bits DQ6/DQ2 on page 30
explains the algorithm. See also the DQ6: Toggle Bit I on page 30 subsection. Figure 17.9 on page 42 shows the toggle bit timing
diagram. Figure 17.10 on page 43 shows the differences between DQ2 and DQ6 in graphical form.
11.5 Reading Toggle Bits DQ6/DQ2
Refer to Figure 11.2 on page 31 for the following discussion. When ever the system initially begins reading toggl e bit status, it must
read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggli n g. Typically , the system would note and store the
value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or erase operation. T he system can read array data on
DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note
whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has
successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully,
and the system must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system
may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous
paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the operation (top of Figure 11.2 on page 31).
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 31 of 53
S29AL016D
Figure 11.2 Toggle Bit Algorithm
Notes
1. Read toggle bit twice to det ermine whether or not it is toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. See text.
11.6 DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pul se count limit. Under these conditio ns DQ5
produces a 1. This is a failure condition that indicates the program or erase cycle was not successfully completed.
The DQ5 failure condition may appear if the system tries to program a 1 to a location that is previously programmed to 0. Only an
erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when the operation ha s
exceeded the timing limits, DQ5 produces a 1.
Under both these conditions, the system must issue the reset command to return the device to reading array data.
11.7 DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has
begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire
time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from 0 to 1. The
system may ignore D Q3 if the system can guaran tee that the time betwe en additional sector erase commands will always be less
than 50 s. See also Sector Era s e Command Sequence on page 25.
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle? No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
= Toggle?
Read DQ7–DQ0
Twice
Read DQ7–DQ0
(Note 1)
(Notes 1, 2)
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 32 of 53
S29AL016D
After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit
I) to ensure the device has accepted the command sequence, and then read DQ3 . If DQ3 is 1, the internally controlled erase cycle
has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is comple te. If DQ3 is 0, the
device will accept additional sector er ase commands. To ensure the command has been accepted, the system software should
check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check,
the last command might not have been accep te d. Table shows the outputs for DQ3.
Notes
1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See DQ5: Exceeded Timing Limits
on page 31 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
12. Absolute Maximum Ratings
Notes
1. Minimum DC volta ge on input or I/O pins is –0.5 V. During volt age transitions, input or I/O pin s may oversh oot VSS to –2.0 V for periods of up to 20 ns. See Figure 13.1
on page 33. Maximum DC volt age on input or I /O pins is VCC +0.5 V. During voltage t ransiti ons, inp ut or I/O pins may oversho ot to V CC +2.0 V fo r periods up t o 20 ns.
See Figure 13.2 on page 33.
2. Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During voltage transitions, A9, OE#, and RESET# may overshoot VSS to –2.0 V for periods of up
to 20 ns. See Figure 13.1 on page 33. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Durati on of the short circuit should not be grea ter than one second.
4. Stresses above those list ed under Absolute Maximum Ratings may cause permanen t damage to the device. This is a stress rating only; functional operation of the
device at these or any o ther conditi ons abov e those indicat ed in the operat ional secti ons of this d ata sheet is n ot implie d. Ex posure of the device to absolute maximum
rating conditions for extended period s may affect device reliability.
13. Operating Ranges
Industrial (I) Devices
Ambient Temperature (TA) -40°C to +85°C
Extended (N) Devices
Ambient Temperature (TA) -40°C to +125°C
VCC Supply Voltages
VCC for standard voltage range 2.7 V to 3.6 V
Operating ranges define those limits between which the functionality of the devi ce is guaranteed.
Write Operation Status
Operation DQ7
(Note 2) DQ6 DQ5
(Note 1) DQ3 DQ2
(Note 2) RY/BY#
Standard
Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0
Erase
Suspend
Mode
Reading within Erase
Suspended Sector 1 No toggle 0 N/A Toggle 1
Readin g w i th i n N on-Erase
Suspended Sector Data Data Data Data Data 1
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0
Storage Temperature Plastic Packages –65C to +150C
Ambient Temperature with Power Applied –65C to +125C
Voltage with Respect to Ground
VCC (Note 1) –0.5 V to +4.0 V
A9, OE#, and RESET# (Note 2) –0.5 V to +12.5 V
All other pins (Note 1) –0.5 V to VCC+0.5 V
Output Short Circuit Curren t (Note 3) 200 mA
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 33 of 53
S29AL016D
Figure 13.1 Maximum Negative Overshoot Waveform
Figure 13.2 Maximum Positive Overshoot Waveform
14. DC Characteristics
14.1 CMOS Compatible
Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC,
VCC = VCC max 1.0
µAILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V 35
ILO Output Leakage Current VOUT = VSS to VCC,
VCC = VCC max 1.0
ICC1 VCC Active Read Current
(Notes 1, 2)
CE# = VIL, OE# = VIH,
Byte Mode
10 MHz 15 30
mA
5 MHz 9 16
1 MHz 2 4
CE# = VIL, OE# = VIH,
Word Mode
10 MHz 18 35
5 MHz 9 16
1 MHz 2 4
ICC2 VCC Active Write Current
(Notes 2, 3, 5)CE# = VIL, OE# = VIH 20 35 mA
ICC3 VCC Standby Current (Notes 2, 4) CE#, RESET# = VCC0.3 V 0.2
5
µA
ICC4 VCC Standby Current During Reset
(Notes 2, 4)RESET# = VSS 0.3 V 0.2 µA
ICC5 Automatic Sleep Mode
(Notes 2, 4, 6)VIH = VCC 0.3 V;
VIL = VSS 0.3 V 0.2 µA
20 ns
20 ns
+0.8 V
–0.5 V
20 ns
–2.0 V
20 ns
VCC
+2.0 V
VCC
+0.5 V
20 ns
2.0 V
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 34 of 53
S29AL016D
Notes
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. At extended temperature range (>+85C), typical current is 5 µA and maximum current is 10 µA.
5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns.
Typical sleep mode current is 200 nA.
6. Not 100% tested.
14.2 Zero Power Flash
Figure 14.1 ICC1 Current vs. Time (Sh owing Active and Automatic Sleep Currents)
Note
Addresses are switching at 1 MHz
VIL Input Low Voltage –0.5 0.8
V
VIH Input High Voltage 0.7 x VCC VCC + 0.3
VID Voltage for Autoselect and Temporary
Sector Unprotect VCC = 3.3 V 11.5 12.5
VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45
VOH1 Output High Voltage IOH = -2.0 mA, VCC = VCC min 2.4
VOH2 IOH = -100 µA, VCC = VCC min V
CC–0.4
VLKO Low VCC Lock-Out Voltage 2.3 2.5
Parameter Description Test Conditions Min Typ Max Unit
25
20
15
10
5
00 500 1000 1500 2000 2500 3000 3500 4000
Supply Current in mA
Time in ns
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 35 of 53
S29AL016D
Figure 14.2 Typical ICC1 vs. Frequency
Note
T = 25 C
15. Test Conditions
Figure 15.1 Test Setup
Note
Diodes are IN3064 or equivalent.
10
8
2
0
12345
Frequency in MHz
Supply Current in mA
2.7 V
3.6 V
4
6
2.7 k
CL6.2 k
3.3 V
Device
Under
Test
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 36 of 53
S29AL016D
16. Key to Switching Waveforms
Figure 16.1 Input Waveforms and Measu r ement Levels
Test Specifications
Test Condition 70 90 Unit
Output Load 1 TTL gate
Output Load Capacitance, CL
(including jig capacit ance) 30 100 pF
Input Rise and Fall Times 5ns
Input Pulse Levels 0.0 or VCC
VInput timing measurement reference levels 0.5 VCC
Output timing measurement reference levels 0.5 VCC
Waveform Inputs Outputs
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance Stat e (High Z)
V
CC
0.0 V 0.5 VCC OutputMeasurement LevelInput 0.5 VCC
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 37 of 53
S29AL016D
17. AC Characteristics
17.1 Read Operations
Notes
1. Not 100% tested.
2. See Figure 15.1 on page 35 and Table on page 36 for test specifications.
Figure 17.1 Read Operations Timings
Parameter
Description
Speed Options
JEDEC Std Test Setup 70 9 0 Unit
tAVAV tRC Read Cycle Time (Note 1) Min 70 90
ns
tAVQV tACC Address to Output Delay CE# = VIL
OE# = VIL Max 70 90
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 70 90
tGLQV tOE Output Enable to Output Delay Max 30 35
tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 16
tGHQZ tDF Output Enable to Output High Z (Note 1) Max 16
tSR/W Latency Between Read and Write Operations Min 20
tOEH Output Enable
Hold T ime (Note 1)
Read Min 0
Toggle and
Data# Polling Min 10
tAXQX tOH Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First (Note 1) Min 0
tCE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output Valid
HIGH Z
Addresses Stable
tRC
tACC
tOEH
tOE
0 V
RY/BY#
RESET#
tDF
tSR/W
tOH
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 38 of 53
S29AL016D
17.2 Hardware Reset (RESET#)
Note
Not 100% tested.
Figure 17.2 RESET# Timings
17.3 Word/Byte Configuration (BYTE#)
Parameter
Description All Speed OptionsJEDEC S td Test Setup Unit
tREADY RESET# Pin Low (During Embedded Algorithms) to
Read or Write (See Note) Max 20 µs
tREADY RESET# Pin Low (NOT During Embedded Algor ithms) to
Read or Write (See Note) Max 500
ns
tRP RESET# Pulse Width
Min
500
tRH RESET# High Time Before Read (See Note) 50
tRPD RESET# Low to Standby Mode 20 µs
tRB RY/BY# Recovery Time 0 ns
Parameter Speed Options
JEDEC Std Description 70 90 Unit
tELFL/tELFH CE# to BYTE# Switching Low or High Max 5
nstFLQZ BYTE# Switching Low to Output HIGH Z Max 16
tFHQV BYTE# Switching High to Output Active Min 70 90
RESET#
RY/BY#
RY/BY#
t
RP
t
Ready
Reset Timings NOT during Embedded Algorithms
t
Ready
CE#, OE#
t
RH
CE#, OE#
Reset Timings during Embedded Algorithms
RESET#
t
RP
t
RB
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 39 of 53
S29AL016D
Figure 17.3 BYTE# Timings for Read Operations
Figure 17.4 BYTE# Timings for Write Operations
Note
Refer to the Erase/Program Operations ta ble for tAS and tAH specifications.
DQ15
Output
Data Output
(DQ0–DQ7)
CE#
OE#
BYTE#
tELFL
DQ0–DQ14 Data Output
(DQ0–DQ14)
DQ15/A-1 Address
Input
tFLQZ
BYTE#
Switching
from word
to byte
mode
DQ15
Output
Data Output
(DQ0–DQ7)
BYTE#
tELFH
DQ0–DQ14 Data Output
(DQ0–DQ14)
DQ15/A-1 Address
Input
tFHQV
BYTE#
Switching
from byte to
word mode
CE#
WE#
BYTE#
The falling edge of the last WE# signal
tHOLD (tAH)
tSET
(tAS)
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 40 of 53
S29AL016D
17.4 Erase/Program Operations
Notes
1. Not 100% tested.
2. See Erase and Programming Performance on page 45 for more information.
Figure 17.5 Program Operation T imings
Notes
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Parameter Speed Options
JEDEC Std Description 70 90 Unit
tAVAV tWC Write Cycle Time (Note 1)
Min
70 90
ns
tAVWL tAS Address Setup Time 0
tWLAX tAH Address Hold Time 45
tDVWH tDS Data Setup Time 35 45
tWHDX tDH Data Hold Time 0
tOES Output Enable Setup Time 0
tGHWL tGHWL Read Recovery Time Before Write
(OE# High to WE# Low) 0
tELWL tCS CE# Setup Time 0
tWHEH tCH CE# Hold T i me 0
tWLWH tWP Write Pulse Width 35
tWHWL tWPH Write Pulse Width High 30
tSR/W Latency Between Read and Write Operations Min 20 ns
tWHWH1 tWHWH1 Programming Operation (Note 2) Byte
Typ
5µs
Word 7
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) 0.7 sec
tVCS VCC Setup Time (Note 1) Min 50 µs
tRB Recovery Time from RY/BY# 0 ns
tBUSY Program/Erase Valid to RY/BY# Delay Max 90
OE#
WE#
CE#
V
CC
Data
Addresses
t
DS
tAH
tDH
tWP
PD
tWHWH1
tWC tAS
tWPH
tVCS
555h PA PA
Read Status Data (last two cycles)
A0h
tCS
Status DOUT
Program Command Sequence (last two cycles)
RY/BY#
tRB
t
BUSY
tCH
PA
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 41 of 53
S29AL016D
Figure 17.6 Chip/Sector Erase Operation Timings
Notes
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 28).
2. Illustration shows device in word mode.
Figure 17.7 Back to Back Read/Write Cycle Timing
OE#
CE#
Addresses
VCC
WE#
Data
2AAh SA
tAH
tWP
tWC tAS
tWPH
555h for chip erase
10 for Chip Erase
30h
tDS
tVCS
tCS
tDH
55h
tCH
In
Progress Complete
tWHWH2
VA
VA
Erase Command Sequence (last two cycles) Read Status Data
RY/BY#
tRB
tBUSY
Addresses
CE#
OE#
WE#
Data Valid In Valid Out
Valid
In Valid
Out
PA PA PA PA
tWC
tACC
tCE
tOE tCP
tAH tCPH
tGHWL
tWP
tWDH tDS tDH tOH
tDF
tSR/W
tRC
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 42 of 53
S29AL016D
Figure 17.8 Data# Polling Timi ngs (During Embe dded Algorithms)
Note
VA = Valid address. Illustration shows first status cycle after co mmand sequence, last status read cycle, and array data read cycle.
Figure 17.9 Toggle Bit Timings (During Embedded Algorithms)
Note
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.
WE#
CE#
OE#
High Z
tOE
High Z
DQ7
DQ0–DQ6
RY/BY#
tBUSY
Complement True
Addresses VA
tOEH
tCE
tCH
tOH
tDF
VA VA
Status Data
Complement
Status Data True
Valid Data
Valid Data
tACC
tRC
WE#
CE#
OE#
High Z
tOE
DQ6/DQ2
RY/BY#
tBUSY
Addresses VA
tOEH
tCE
tCH
tOH
tDF
VA VA
tACC
tRC
Valid DataValid StatusValid Status
(first read) (second read) (stops toggling)
Valid Status
VA
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 43 of 53
S29AL016D
Figure 17.10 D Q2 vs. DQ6 for Erase and Erase Suspend Operations
Note
The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector.
17.5 Temporary Sector Unprotect
Note
Not 100% tested.
Figure 17.11 Temporary Sector Unprotect/Timing Diagram
Parameter
All Speed OptionsJEDEC Std Description Unit
tVIDR VID Rise and Fall Time (See Note) Min 500 ns
tRSP RESET# Setup Time for Temporary Sector Unprotect Min 4 µs
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
RESET#
tVIDR
12 V
0 or 3 V
CE#
WE#
RY/BY#
tVIDR
tRSP
Program or Erase Command Sequence
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 44 of 53
S29AL016D
Figure 17.12 Sector Protect/Unprotect Timing Diagram
Note
For sector protect , A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
17.6 Alternate CE# Controlled Erase/Program Operations
Notes
1. Not 100% tested.
2. See Erase and Programming Performance on page 45 for more information.
Parameter Speed Options
JEDEC Std Description 70 90 Unit
tAVAV tWC Write Cycle Time (Note 1) Min 70 90 ns
tAVEL tAS Address Setup Time Min 0 ns
tELAX tAH Addr ess Hold Time Min 45 45 ns
tDVEH tDS Data Setup Time Min 35 45 ns
tEHDX tDH Data Hold Time Min 0 ns
tOES Output Enable Setup Time Min 0 ns
tGHEL tGHEL Read Recovery Time Before Write
(OE# High to WE# Low) Min 0 ns
tWLEL tWS WE# Setup Time Min 0 ns
tEHWH tWH WE# Hold Time Min 0 ns
tELEH tCP CE# Pulse Width Min 35 35 ns
tEHEL tCPH CE# Pulse Widt h High Min 30 ns
tSR/W Latency Between Read and Wr ite Operations Min 20 ns
tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 5 µs
Word Typ 7
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec
Sector Protect: 150 µs
Sector Unprotect: 15 ms
1 µs
RESET#
SA, A6,
A1, A0
Data
CE#
WE#
OE#
60h 60h 40h
Valid* Valid* Valid*
Status
Sector Protect/Unprotect Verify
V
ID
V
IH
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 45 of 53
S29AL016D
Figure 17.13 Alternate CE# Controlled Write Operatio n Timings
Notes
1. PA = program address, PD = program data, DQ7# = complement of the data written to th e device, DOUT = data written to the device.
2. Figure indicates the last two bus cycles of the command sequence.
3. Word mode address used as an example.
18. Erase and Programming Performance
Notes
1. Typical program and erase times assume the following conditions: 25C, VCC = 3.0 V, 100,000 cycles, checkerboard data pat tern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster th an th e maxi mum progr am
times listed.
4. In the pre-programming step of the Embedded Erase algo rithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four -bus-cycle seque nce for the program command. See Table on page 27 for further information on
command definitions.
6. The device has a minimum erase and program cycle endurance of 100,000 cycles per sector.
Parameter Typ (Note 1) Max (Note 2) Unit Comments
Sector Erase Time 0.7 10 s Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time 25 s
Byte Programming Time 7 210 µs
Excludes system level
overhead (Note 5)
Word Programming Time 7 210 µs
Chip Programming Time
(Note 3)
Byte Mode 11 33 s
Word Mode 7.2 21.6 s
t
GHEL
t
WS
OE#
CE#
WE#
RESET#
t
DS
Data
t
AH
Addresses
t
DH
t
CP
DQ7# D
OUT
t
WC
t
AS
t
CPH
PA
Data# Polling
A0 for program
55 for erase
t
RH
t
WHWH1 or 2
RY/BY#
t
WH
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase PA for program
SA for sector erase
555 for chip erase
t
BUSY
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 46 of 53
S29AL016D
19. TSOP, SO, and BGA Pin Capacitance
Notes
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
Parameter Symbol Parameter Description Test Setup Pac kage Typ Max Unit
CIN Input Capacitance VIN = 0 TSOP, SO 6 7.5 pF
BGA 4.2 5.0 pF
COUT Output Capacitance VOUT = 0 TSOP, SO 8.5 12 pF
BGA 5.4 6.5 pF
CIN2 Control Pin Capacitance VIN = 0 TSOP, SO 7.5 9 pF
BGA 3.9 4.7 pF
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 47 of 53
S29AL016D
20. Physical Dimensions
20.1 TS 048— 48-Pin Standard TSOP
Note
For reference only. BSC is an ANSI standard for Basic Space Centering.
6
2
3
4
5
7
8
9
MO-142 (D) DD
48
MIN
0.05
0.95
0.17
0.17
0.10
0.10
18.30
19.80
0.50
0˚
0.08
11.90
0.50 BASIC
MAX
0.15
1.20
0.27
0.16
0.21
8˚
0.20
18.50
12.10
0.70
20.20
0.23
1.05
0.20
1.00
0.22
18.40
20.00
0.60
12.00
NOM
Symbol
Jedec
b1
A2
A1
A
D
L
e
E
D1
b
c1
c
0
R
N
1
NOTES:
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP).
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF
CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT
HORIZONTAL SURFACE.
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS
0.15mm (.0059") PER SIDE.
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE
0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE
BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND
0.25MM (0.0098") FROM THE LEAD TIP.
LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE.
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
N
+1
2
N
1
2
N
3
REVERSE PIN OUT (TOP VIEW)
C
e
A1
A2
2X (N/2 TIPS)
0.10
9
SEATING
PLANE
A
SEE DETAIL A
B
B
AB
E
D1
D
2X
2X (N/2 TIPS)
0.25
2X 0.10
0.10
N
5
+1
N
2
4
5
1
N
2
2
STANDARD PIN OUT (TOP VIEW)
SEE DETAIL B
DETAIL A
(c)
θ°
L
0.25MM (0.0098") BSC
C
R
GAUGE PLANE
PARALLEL TO
SEATING PLANE
b
b1
(c)
76
c1
WITH PLATING
BASE METAL
7
0.08MM (0.0031") M C A - B S
SECTION B-B
DETAIL B
X
e/2
X = A OR B
3355 \ 16-038.10c
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 48 of 53
S29AL016D
20.2 VBK048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 8.15 mm x 6.15 m m
3338 \ 16-038.25
b
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEP
T
AS NOTED).
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
N IS THE TOTAL NUMBER OF SOLDER BALLS.
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
8. NOT USED.
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
SIDE VIEW
TOP VIEW
SEATING PLANE
A2
A
(4X)
0.10
10
D
E
C0.10
A1
C
B
A
C0.08
BOTTOM VIEW
A1 CORNE
R
BA
M
φ 0.15 C
M
7
7
6
eSE
SD
6
5
4
3
2
A
BCDEFG
1
H
φb
E1
D1
C
φ 0.08
PIN A1
CORNER
INDEX MARK
PACKAGE VBK 048
JEDEC N/A
8.15 mm x 6.15 mm NOM
PACKAGE
SYMBOL MIN NOM MAX NOTE
A --- --- 1.00 OVERALL THICKNESS
A1 0.18 --- --- BALL HEIGHT
A2 0.62 --- 0.76 BODY THICKNESS
D 8.15 BSC. BODY SIZE
E 6.15 BSC. BODY SIZE
D1 5.60 BSC. BALL FOOTPRINT
E1 4.00 BSC. BALL FOOTPRINT
MD 8 ROW MATRIX SIZE D DIRECTION
ME 6 ROW MATRIX SIZE E DIRECTION
N 48 TOTAL BALL COUNT
φb 0.35 --- 0.43 BALL DIAMETER
e 0.80 BSC. BALL PITCH
SD / SE 0.40 BSC. SOLDER BALL PLACEMENT
--- DEPOPULATED SOLDER BALLS
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 49 of 53
S29AL016D
20.3 SO044—44-Pin Small Outline Package (SOP) 28.20 mm x 13.30 mm
Dwg rev AC; 10/99
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 50 of 53
S29AL016D
21. Revision Summary
Spansion Publication Number: S29AL016D_00
21.1 Revision A (May 4, 2004)
Initial Release.
21.2 Revision A1 (July 28, 2004)
Ordering Information
Updated ordering information: model number, speed options, and valid combinations for TSOP and BGA packages.
DC Characteristics
Updated Max information for ICC2.
Physical Dimensions
Updated VBK048 and TS048 drawings.
21.3 Revision A2 (December 17, 2004)
Data Sheet Type
Changed from Advance Information to Preliminary.
Ordering Information
Updated ordering information: Small Outline Package options
Physical Dimensions
Added SO044 Package.
21.4 Revision A3 (June 1, 2005)
Global
Updated status to full data sheet.
Ordering Information
Added tube and tray packing types.
Added Extended Tempe r ature range.
Valid Combinations Table
Added two designators to packing types.
Added package types for extend ed temperature.
Added Note for this table.
Operating Ranges
Added Extended Tempe r ature range information.
Erase and Programming Performance
Changed Byte Programing Time values for Typical and Maximum.
Pin Capacitance Table
Added SO package to Pin Capacitance table.
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 51 of 53
S29AL016D
Global
Updated Trademark.
21.5 Revision A4 (June 17, 2005)
Ordering Information
Changed packing type from “1, 3” to “0, 1, 3”
21.6 Revision A5 (M ay 22, 2006)
AC Characteristics
Added tSR/W parameter to read and erase/program operations tables. Added back-to-back read/write cycle timing diagram.
Changed maximum value for tDF and tFLQZ.
21.7 Revision A6 (September 7, 2007)
Command Definitions Table
Changed the 2nd cycle data of the Unlock Bypass Reset command from 'F0' to '00'.
21.8 Revision A7 (November 27, 2007)
Figure: Read Operations Timings
Updated figure
21.9 R evision A8 (F ebruary 27, 2009)
Global
Added obsolescence information to Cover Sheet, Distinctive Characteristics, and Ordering Information section s of data sheet.
Document History Page
Document Title:S29AL016D 16 Mbit (2 M x 8-Bit/1 M x 16-Bit), 3 V Boot Sector Flash
Document Number: 00 2-01232
Rev. ECN No. Orig. of
Change Submission
Date Description of Change
** - RYSU
05/04/2004 Initial release
07/28/2004 Ordering Information
Updated ordering information: model number, speed options, and valid
combinations for TSOP and BGA
packages.
DC Characteristics
Updated Max information for ICC2.
Physical Dimensions
Updated VBK048 and TS048 drawings.
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Page 52 of 53
S29AL016D
** - RYSU
12/17/2004 Data Sheet Type
Changed from Advance Information to Preliminary.
Ordering Information
Updated ordering information: Small Outline Package options
Physical Dimensions
Added SO044 Package.
06/01/2005 Global
Updated status to full data sheet.
Ordering Information
Added tube and tray packing types.
Added Extended Temperature range.
Valid Combin ations Table
Added two designators to packing types.
Added package types for extended temperature.
Added Note for this table.
Operating Ranges
Added Extended Temperature range informati on.
Erase and Programming Performance
Changed Byte Programing Time va lues for Typical and Maximum.
Pin Capacitance Table
Added SO package to Pin Capacitance table.
Global
Updated Trademark.
06/17/2005 Ordering Information
Changed packing type from “1, 3” to “0, 1, 3”
** - RYSU
05/22/2006 AC Characteristics
Added tSR/W parameter to read and erase/program operations tables.
Added back-to-back read/write cycle
timing diagram. Changed maximu m value for tDF and tFLQZ.
09/07/2007 Command Definition s Table
Changed the 2nd cycle data of the Unlock Bypass Reset command from
'F0' to '00'.
11/27/2007 Figure: Read Operations Timings
Updated figure
02/27/2009 Global
Added obsolescence information to Cover Sheet, Distinctive
Characteristics, and Ordering Information
sections of data sheet.
*A 5034596 RYSU 12/07/2015 Updated to Cypress Template
Document History Page (Continued)
Document Title:S29AL016D 16 Mbit (2 M x 8-Bit/1 M x 16-Bit), 3 V Boot Sector Flash
Document Number: 00 2-01232
Rev. ECN No. Orig. of
Change Submission
Date Description of Change
These parts are obsoleted and the
datasheet is available for reference.
Document Number: 002-01232 Rev. *A Revised December 08, 2015 Page 53 of 53
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© Cypress Semicondu ctor Corpor ation, 2004-2015. The informatio n cont ained herei n is subject to chan ge without no tice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
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S29AL016D
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These parts are obsoleted and the
datasheet is available for reference.
