To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. User's Manual 16 H8S/2600 Series, H8S/2000 Series Software Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family Rev.4.00 2006.02 Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. 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When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Rev. 4.00 Feb 24, 2006 page ii of xiv Preface The H8S/2600 Series and the H8S/2000 Series are built around an H8S/2000 CPU core. The H8S/2600 and H8S/2000 CPUs have the same internal 32-bit architecture. Both CPUs execute basic instructions in one state, have sixteen 16-bit registers, and have a concise, optimized instruction set. They can address a 16-Mbyte linear address space.Programs coded in the highlevel language C can be compiled to high-speed executable code. For easy migration, the instruction set is upward-compatible with the H8/300H, H8/300, and H8/300L Series at the object-code level. The H8S/2600 CPU is upward-compatible with the H8S/2000 CPU at the object-code level, and supports sum of products instructions. This manual gives details of the H8S/2600 and H8S/2000 instructions and can be sued with all microcontrollers in the H8S/2600 Series and the H8S/2000 Series. For hardware details, refer to the relevant microcontroller hardware manuals. Rev. 4.00 Feb 24, 2006 page iii of xiv Rev. 4.00 Feb 24, 2006 page iv of xiv Main Revisions for This Edition Item Page Revisions (See Manual for Details) 1.1.1 Features 2 Note * added -- Maximum clock frequency: 20 MHz* Note: * The maximum operating frequency and instruction execution time differ depending on the product. 2.2.22 CLRMAC 90 2.2.24 DAA 94 Description 2.2.37 LDMAC 130 Table amended C Flag before Adjustment Upper 4 Bits before Adjustment H Flag before Adjustment Lower 4 Bits Value before Added Adjustment (Hexadecimal) C Flag after Adjustment 0 A to F 1 0 to 3 66 1 1 0 to 2 0 0 to 9 60 1 1 0 to 2 0 A to F 66 1 1 0 to 3 1 0 to 3 66 1 Further explanation added to note The number of states may differ depending on the product. For details, refer to the hardware manual of the product in question. Operand Format and Number of States Required for Execution 2.2.42 (1) MULXS (B) Further explanation added to note The number of states may differ depending on the product. For details, refer to the hardware manual of the product in question. Operand Format and Number of States Required for Execution 151 Operand Format and Number of States Required for Execution 2.2.42 (2) MULXS (W) 152 Operand Format and Number of States Required for Execution 2.2.43 (1) MULXU (B) 153 Operand Format and Number of States Required for Execution 2.2.43 (2) MULXU (W) 154 Operand Format and Number of States Required for Execution Rev. 4.00 Feb 24, 2006 page v of xiv Item Page Revisions (See Manual for Details) 2.2.64 STMAC 232 Table amended Operand Format and Number of States Required for Execution Instruction Format 1st byte 2nd byte 0 2 2 0 erd 0 2 3 0 erd 3rd byte 4th byte Further explanation added to note The number of states may differ depending on the product. For details, refer to the hardware manual of the product in question. Note 7 amended and note 10 added No. of States*1 Mnemonic Normal Table 2.1 Instruction Set 250, 251, 260, 262 Advanced 2.3 Instruction Set DAS MULXU DAS Rd MULXU.B Rs,Rd MULXU.W Rs,ERd MULXS MULXS.B Rs,Rd MULXS.W Rs,ERd 1 3 (12*7) *4 *10 4 (20*7) *4 *10 4 (13*7) *5 *10 5 (21*7) *5 *10 No. of States*1 Normal Advanced Mnemonic MAC*9 MAC @ERn+,@ERm+ 4 CLRMAC*9 CLRMAC LDMAC*9 LDMAC ERs,MACH 2*6 *10 2*6 *10 LDMAC ERs,MACL 2*6 *10 STMAC MACH,ERd STMAC MACL,ERd 1*6 *10 1*6 *10 STMAC*9 No. of States*1 TRAPA TRAPA #x:2 RTE RTE Advanced Normal Mnemonic 7[9] *7 8[9]*7 5[9]*7 Notes: 7. Values in parentheses ( ) are for the H8S/2000 CPU. Values in square brackets [ ] apply to interrupt control modes 2 and 3. 10. The number of states may differ depending on the product. For details, refer to the hardware manual of the product in question. Rev. 4.00 Feb 24, 2006 page vi of xiv Item Page Revisions (See Manual for Details) 2.6 Number of States Required for Instruction Execution 283, 285, 286, 288 Note 6 added Table 2.5 Number of Cycles in Instruction Execution Instruction Fetch Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation K L M N Instruction Mnemonic I J CLRMAC*5 CLRMAC 1 1 Instruction Fetch Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation K L M N *3 *6 Instruction Mnemonic I J LDMAC*5 LDMAC ERs,MACH 1 1 *3 *6 LDMAC ERs,MACL 1 1 *3 *6 Instruction Fetch Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation I J K L M N H8S/2600 2 2 H8S/2000 2 1 1 MULXS.W Rs,ERd H8S/2600 2 3 *3 *6 Instruction Mnemonic MULXS MULXS.B Rs,Rd MULXU *3 *6 H8S/2000 2 1 9 H8S/2600 1 2 *3 *6 H8S/2000 1 1 1 MULXU.W Rs,ERd H8S/2600 1 3 *3 *6 H8S/2000 1 1 9 Instruction Fetch Branch Address Read Stack Operation Byte Data Access Word Data Access I J K L M MULXU.B Rs,Rd Internal Operation Instruction Mnemonic STMAC* STMAC MACH,ERd 1 3 6 0* * STMAC MACL,ERd 1 3 6 0* * 5 N Notes: 6. The number of states may differ depending on the product. For details, refer to the hardware manual of the product in question. 2.7 Bus States During Instruction Execution 290 :M deleted from legend Table 2.6 Instruction Execution Cycles 293 to 302 All instances of :M deleted from table 3.3.5 Usage Notes 312, 313 Newly added Rev. 4.00 Feb 24, 2006 page vii of xiv Rev. 4.00 Feb 24, 2006 page viii of xiv Contents Section 1 CPU ...................................................................................................................... 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Overview........................................................................................................................... 1.1.1 Features................................................................................................................ 1.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU .................................. 1.1.3 Differences from H8/300 CPU ............................................................................ 1.1.4 Differences from H8/300H CPU.......................................................................... CPU Operating Modes ...................................................................................................... Address Space................................................................................................................... Register Configuration...................................................................................................... 1.4.1 Overview.............................................................................................................. 1.4.2 General Registers ................................................................................................. 1.4.3 Control Registers ................................................................................................. 1.4.4 Initial Register Values.......................................................................................... Data Formats..................................................................................................................... 1.5.1 General Register Data Formats ............................................................................ 1.5.2 Memory Data Formats ......................................................................................... Instruction Set ................................................................................................................... 1.6.1 Overview.............................................................................................................. 1.6.2 Instructions and Addressing Modes ..................................................................... 1.6.3 Table of Instructions Classified by Function ....................................................... 1.6.4 Basic Instruction Formats .................................................................................... Addressing Modes and Effective Address Calculation ..................................................... 1 1 1 2 3 4 5 10 11 11 12 13 15 16 16 18 19 19 20 22 32 33 Section 2 Instruction Descriptions .................................................................................. 41 2.1 2.2 Tables and Symbols .......................................................................................................... 2.1.1 Assembly-Language Format ................................................................................ 2.1.2 Operation ............................................................................................................. 2.1.3 Condition Code .................................................................................................... 2.1.4 Instruction Format................................................................................................ 2.1.5 Register Specification .......................................................................................... 2.1.6 Bit Data Access in Bit Manipulation Instructions................................................ Instruction Descriptions .................................................................................................... 2.2.1 (1) ADD (B).......................................................................................................... 2.2.1 (2) ADD (W)......................................................................................................... 2.2.1 (3) ADD (L).......................................................................................................... 2.2.2 ADDS.............................................................................................................. 2.2.3 ADDX ............................................................................................................. 2.2.4 (1) AND (B).......................................................................................................... 41 42 43 44 44 45 46 47 48 49 50 51 52 53 Rev. 4.00 Feb 24, 2006 page ix of xiv 2.2.4 (2) 2.2.4 (3) 2.2.5 (1) 2.2.5 (2) 2.2.6 2.2.7 2.2.8 2.2.9 2.2.10 2.2.11 2.2.12 2.2.13 2.2.14 2.2.15 2.2.16 2.2.17 2.2.18 2.2.19 2.2.20 2.2.21 2.2.22 2.2.23 (1) 2.2.23 (2) 2.2.23 (3) 2.2.24 2.2.25 2.2.26 (1) 2.2.26 (2) 2.2.26 (3) 2.2.27 (1) 2.2.27 (2) 2.2.28 (1) 2.2.28 (2) 2.2.29 (1) 2.2.29 (2) 2.2.30 (1) 2.2.30 (2) 2.2.31 (1) 2.2.31 (2) 2.2.32 (1) 2.2.32 (2) AND (W)......................................................................................................... AND (L).......................................................................................................... ANDC ............................................................................................................. ANDC ............................................................................................................. BAND ............................................................................................................. Bcc .................................................................................................................. BCLR .............................................................................................................. BIAND ............................................................................................................ BILD ............................................................................................................... BIOR ............................................................................................................... BIST ................................................................................................................ BIXOR ............................................................................................................ BLD................................................................................................................. BNOT.............................................................................................................. BOR ................................................................................................................ BSET............................................................................................................... BSR ................................................................................................................. BST ................................................................................................................. BTST............................................................................................................... BXOR.............................................................................................................. CLRMAC........................................................................................................ CMP (B) .......................................................................................................... CMP (W)......................................................................................................... CMP (L) .......................................................................................................... DAA ................................................................................................................ DAS................................................................................................................. DEC (B) .......................................................................................................... DEC (W) ......................................................................................................... DEC (L)........................................................................................................... DIVXS (B) ...................................................................................................... DIVXS (W) ..................................................................................................... DIVXU (B) ..................................................................................................... DIVXU (W) .................................................................................................... EEPMOV (B) .................................................................................................. EEPMOV (W)................................................................................................. EXTS (W) ....................................................................................................... EXTS (L)......................................................................................................... EXTU (W)....................................................................................................... EXTU (L)........................................................................................................ INC (B) ........................................................................................................... INC (W) .......................................................................................................... Rev. 4.00 Feb 24, 2006 page x of xiv 54 55 56 57 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 91 92 93 94 96 98 99 100 101 103 105 107 109 110 112 113 114 115 116 117 2.2.32 (3) 2.2.33 2.2.34 2.2.35 (1) 2.2.35 (2) 2.2.35 (3) 2.2.35 (4) 2.2.36 2.2.37 2.2.38 2.2.39 (1) 2.2.39 (2) 2.2.39 (3) 2.2.39 (4) 2.2.39 (5) 2.2.39 (6) 2.2.39 (7) 2.2.39 (8) 2.2.39 (9) 2.2.40 2.2.41 2.2.42 (1) 2.2.42 (2) 2.2.43 (1) 2.2.43 (2) 2.2.44 (1) 2.2.44 (2) 2.2.44 (3) 2.2.45 2.2.46 (1) 2.2.46 (2) 2.2.46 (3) 2.2.47 (1) 2.2.47 (2) 2.2.47 (3) 2.2.48 (1) 2.2.48 (2) 2.2.49 (1) 2.2.49 (2) 2.2.50 (1) 2.2.50 (2) INC (L)............................................................................................................ JMP ................................................................................................................. JSR .................................................................................................................. LDC (B) .......................................................................................................... LDC (B) .......................................................................................................... LDC (W) ......................................................................................................... LDC (W) ......................................................................................................... LDM................................................................................................................ LDMAC .......................................................................................................... MAC................................................................................................................ MOV (B) ......................................................................................................... MOV (W) ........................................................................................................ MOV (L) ......................................................................................................... MOV (B) ......................................................................................................... MOV (W) ........................................................................................................ MOV (L) ......................................................................................................... MOV (B) ......................................................................................................... MOV (W) ........................................................................................................ MOV (L) ......................................................................................................... MOVFPE ........................................................................................................ MOVTPE ........................................................................................................ MULXS (B) .................................................................................................... MULXS (W) ................................................................................................... MULXU (B).................................................................................................... MULXU (W)................................................................................................... NEG (B) .......................................................................................................... NEG (W) ......................................................................................................... NEG (L) .......................................................................................................... NOP................................................................................................................. NOT (B) .......................................................................................................... NOT (W) ......................................................................................................... NOT (L) .......................................................................................................... OR (B)............................................................................................................. OR (W)............................................................................................................ OR (L) ............................................................................................................. ORC ................................................................................................................ ORC ................................................................................................................ POP (W) .......................................................................................................... POP (L) ........................................................................................................... PUSH (W) ....................................................................................................... PUSH (L) ........................................................................................................ 118 119 120 122 123 124 126 128 130 131 134 135 136 137 139 141 143 145 147 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 Rev. 4.00 Feb 24, 2006 page xi of xiv 2.2.51 (1) 2.2.51 (2) 2.2.51 (3) 2.2.51 (4) 2.2.51 (5) 2.2.51 (6) 2.2.52 (1) 2.2.52 (2) 2.2.52 (3) 2.2.52 (4) 2.2.52 (5) 2.2.52 (6) 2.2.53 (1) 2.2.53 (2) 2.2.53 (3) 2.2.53 (4) 2.2.53 (5) 2.2.53 (6) 2.2.54 (1) 2.2.54 (2) 2.2.54 (3) 2.2.54 (4) 2.2.54 (5) 2.2.54 (6) 2.2.55 2.2.56 2.2.57 (1) 2.2.57 (2) 2.2.57 (3) 2.2.57 (4) 2.2.57 (5) 2.2.57 (6) 2.2.58 (1) 2.2.58 (2) 2.2.58 (3) 2.2.58 (4) 2.2.58 (5) 2.2.58 (6) 2.2.59 (1) 2.2.59 (2) 2.2.59 (3) ROTL (B) ........................................................................................................ ROTL (B) ........................................................................................................ ROTL (W)....................................................................................................... ROTL (W)....................................................................................................... ROTL (L) ........................................................................................................ ROTL (L) ........................................................................................................ ROTR (B)........................................................................................................ ROTR (B)........................................................................................................ ROTR (W)....................................................................................................... ROTR (W)....................................................................................................... ROTR (L) ........................................................................................................ ROTR (L) ........................................................................................................ ROTXL (B) ..................................................................................................... ROTXL (B) ..................................................................................................... ROTXL (W) .................................................................................................... ROTXL (W) .................................................................................................... ROTXL (L) ..................................................................................................... ROTXL (L) ..................................................................................................... ROTXR (B)..................................................................................................... ROTXR (B)..................................................................................................... ROTXR (W).................................................................................................... ROTXR (W).................................................................................................... ROTXR (L) ..................................................................................................... ROTXR (L) ..................................................................................................... RTE ................................................................................................................. RTS ................................................................................................................. SHAL (B) ........................................................................................................ SHAL (B) ........................................................................................................ SHAL (W)....................................................................................................... SHAL (W)....................................................................................................... SHAL (L) ........................................................................................................ SHAL (L) ........................................................................................................ SHAR (B)........................................................................................................ SHAR (B)........................................................................................................ SHAR (W)....................................................................................................... SHAR (W)....................................................................................................... SHAR (L) ........................................................................................................ SHAR (L) ........................................................................................................ SHLL (B) ........................................................................................................ SHLL (B) ........................................................................................................ SHLL (W) ....................................................................................................... Rev. 4.00 Feb 24, 2006 page xii of xiv 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 2.3 2.4 2.5 2.6 2.7 2.8 2.2.59 (4) SHLL (W) ....................................................................................................... 2.2.59 (5) SHLL (L)......................................................................................................... 2.2.59 (6) SHLL (L)......................................................................................................... 2.2.60 (1) SHLR (B) ........................................................................................................ 2.2.60 (2) SHLR (B) ........................................................................................................ 2.2.60 (3) SHLR (W) ....................................................................................................... 2.2.60 (4) SHLR (W) ....................................................................................................... 2.2.60 (5) SHLR (L) ........................................................................................................ 2.2.60 (6) SHLR (L) ........................................................................................................ 2.2.61 SLEEP............................................................................................................. 2.2.62 (1) STC (B) ........................................................................................................... 2.2.62 (2) STC (B) ........................................................................................................... 2.2.62 (3) STC (W) .......................................................................................................... 2.2.62 (4) STC (W) .......................................................................................................... 2.2.63 STM ................................................................................................................ 2.2.64 STMAC........................................................................................................... 2.2.65 (1) SUB (B)........................................................................................................... 2.2.65 (2) SUB (W) ......................................................................................................... 2.2.65 (3) SUB (L)........................................................................................................... 2.2.66 SUBS............................................................................................................... 2.2.67 SUBX .............................................................................................................. 2.2.68 TAS ................................................................................................................. 2.2.69 TRAPA............................................................................................................ 2.2.70 (1) XOR (B) .......................................................................................................... 2.2.70 (2) XOR (W)......................................................................................................... 2.2.70 (3) XOR (L) .......................................................................................................... 2.2.71 (1) XORC.............................................................................................................. 2.2.71 (2) XORC.............................................................................................................. Instruction Set ................................................................................................................... Instruction Code................................................................................................................ Operation Code Map......................................................................................................... Number of States Required for Instruction Execution ...................................................... Bus States During Instruction Execution .......................................................................... Condition Code Modification ........................................................................................... 213 214 215 216 217 218 219 220 221 222 223 224 225 227 229 231 233 235 236 237 238 239 240 242 243 244 245 246 247 263 274 278 290 304 Section 3 Processing States .............................................................................................. 309 3.1 3.2 3.3 Overview........................................................................................................................... Reset State......................................................................................................................... Exception-Handling State ................................................................................................. 3.3.1 Types of Exception Handling and Their Priority ................................................. 3.3.2 Reset Exception Handling.................................................................................... 309 310 311 311 312 Rev. 4.00 Feb 24, 2006 page xiii of xiv 3.4 3.5 3.6 3.3.3 Trace .................................................................................................................... 3.3.4 Interrupt Exception Handling and Trap Instruction Exception Handling ............ 3.3.5 Usage Notes ......................................................................................................... Program Execution State................................................................................................... Bus-Released State............................................................................................................ Power-Down State ............................................................................................................ 3.6.1 Sleep Mode .......................................................................................................... 3.6.2 Software Standby Mode....................................................................................... 3.6.3 Hardware Standby Mode ..................................................................................... 312 312 312 314 315 315 315 315 316 Section 4 Basic Timing ...................................................................................................... 317 4.1 4.2 4.3 4.4 Overview........................................................................................................................... On-Chip Memory (ROM, RAM) ...................................................................................... On-Chip Supporting Module Access Timing.................................................................... External Address Space Access Timing............................................................................ Rev. 4.00 Feb 24, 2006 page xiv of xiv 317 317 319 320 Section 1 CPU Section 1 CPU 1.1 Overview The H8S/2600 CPU and the H8S/2000 CPU are high-speed central processing units with a common an internal 32-bit architecture. Each CPU is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU and H8S/2000 CPU have sixteen 16-bit general registers, can address a 4-Gbyte linear address space, and are ideal for realtime control. 1.1.1 Features The H8S/2600 CPU and H8S/2000 CPU have the following features. * Upward-compatible with H8/300 and H8/300H CPUs Can execute H8/300 and H8/300H object programs * General-register architecture Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) * Sixty-nine basic instructions (H8S/2000 CPU has sixty-five) 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions Multiply-and-accumulate instruction (H8S/2600 CPU only) * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 4-Gbyte address space Program: 16 Mbytes Data: 4 Gbytes Rev. 4.00 Feb 24, 2006 page 1 of 322 REJ09B0139-0400 Section 1 CPU * High-speed operation All frequently-used instructions execute in one or two states Maximum clock frequency: 20 MHz* 8/16/32-bit register-register add/subtract: 50 ns 8 x 8-bit register-register multiply: 150 ns (H8S/2000 CPU: 600 ns) 16 / 8-bit register-register divide: 600 ns 16 x 16-bit register-register multiply: 200 ns (H8S/2000 CPU: 1000 ns) 32 / 16-bit register-register divide: 1000 ns * Two CPU operating modes Normal mode Advanced mode * Power-down modes Transition to power-down state by SLEEP instruction CPU clock speed selection Note: * The maximum operating frequency and instruction execution time differ depending on the product. 1.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU Differences between the H8S/2600 CPU and the H8S/2000 CPU are as follows. * Register configuration The MAC register is supported only by the H8S/2600 CPU. For details, see section 1.4, Register Configuration. * Basic instructions The MAC, CLRMAC, LDMAC, and STMAC instructions are supported only by the H8S/2600 CPU. For details, see section 1.6, Instruction Set, and Section 2, Instruction Descriptions. * Number of states required for execution The number of states required for execution of the MULXU and MULXS instructions. For details, see section 2.6, Number of States Required for Execution. In addition, there may be defferences in address spaces, EXR register functions, power-down states, and so on. For details, refer to the relevant microcontroller hardware manual. Rev. 4.00 Feb 24, 2006 page 2 of 322 REJ09B0139-0400 Section 1 CPU 1.1.3 Differences from H8/300 CPU In comparison with the H8/300 CPU, the H8S/2600 CPU and H8S/2000 CPU have the following enhancements. * More general registers and control registers Eight 16-bit registers, one 8-bit and two 32-bit control registers have been added. * Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 4-Gbyte address space. * Enhanced addressing The addressing modes have been enhanced to make effective use of the 4-Gbyte address space. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. A multiply-and-accumulate instruction has been added. (H8S/2600CPU only) Two-bit shift and rotate instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. Rev. 4.00 Feb 24, 2006 page 3 of 322 REJ09B0139-0400 Section 1 CPU 1.1.4 Differences from H8/300H CPU In comparison with the H8/300H CPU, the H8S/2600 CPU and H8S/2000 CPU have the following enhancements. * Additional control register One 8-bit and two 32-bit control registers have been added. * Expanded address space Advanced mode supports a maximum 4-Gbyte data address space. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. A multiply-and-accumulate instruction has been added (H8S/2600 CPU only). Two-bit shift and rotate instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. Rev. 4.00 Feb 24, 2006 page 4 of 322 REJ09B0139-0400 Section 1 CPU 1.2 CPU Operating Modes Like the H8/300H CPU, the H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 4-Gbyte total address space, of which up to 16 Mbytes can be used for program code and up to 4 Gbytes for data. The mode is selected with the mode pins of the microcontroller. For further information, refer to the relevant microcontroller hardware manual. Normal mode Maximum 64 kbytes, program and data areas combined CPU operating modes Advanced mode Maximum 16-Mbyte program area and 4-Gbyte data area, maximum 4 Gbytes for program and data areas combined Figure 1.1 CPU Operating Modes (1) Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. Address Space: A maximum address space of 64 kbytes can be accessed, as in the H8/300 CPU. Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (R0 to R7) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@-Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register will be affected. Instruction Set: All additional instructions and addressing modes not found in the H8/300 CPU can be used. Only the lower 16 bits of effective addresses (EA) are valid. Rev. 4.00 Feb 24, 2006 page 5 of 322 REJ09B0139-0400 Section 1 CPU Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits (figure 1.2). The exception vector table differs depending on the microcontroller. Refer to the relevant microcontroller hardware manual for further information. H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Power-on reset exception vector Manual reset exception vector (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 1.2 Exception Vector Table (Normal Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. Rev. 4.00 Feb 24, 2006 page 6 of 322 REJ09B0139-0400 Section 1 CPU Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 1.3. When EXR is invalid, it is not pushed onto the stack. For details, see the relevant hardware manual. SP PC (16 bits) EXR*1 Reserved*1 *3 CCR CCR*3 SP *2 (SP ) PC (16 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored on return. Figure 1.3 Stack Structure in Normal Mode (2) Advanced Mode In advanced mode the data address space is larger than for the H8/300H CPU. Address Space: The 4-Gbyte maximum address space provides linear access to a maximum 16 Mbytes of program code and maximum 4 Gbytes of data. Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. Instruction Set: All instructions and addressing modes can be used. Rev. 4.00 Feb 24, 2006 page 7 of 322 REJ09B0139-0400 Section 1 CPU Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 1.4). The exception vector table differs depending on the microcontroller. Refer to the relevant microcontroller hardware manual for further information. H'00000000 Reserved Power-on reset exception vector H'00000003 H'00000004 Reserved Manual reset exception vector H'00000007 H'00000008 Exception vector table H'0000000B (Reserved for system use) H'0000000C H'00000010 Reserved Exception vector 1 Figure 1.4 Exception Vector Table (Advanced Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the top area from H'00000000 to H'000000FF. Note that this area is also used for the exception vector table. Rev. 4.00 Feb 24, 2006 page 8 of 322 REJ09B0139-0400 Section 1 CPU Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 1.5. When EXR is invalid, it is not pushed onto the stack. For details, see the relevant hardware manual. EXR*1 Reserved*1 *3 CCR SP SP Reserved PC (24 bits) (a) Subroutine Branch *2 (SP ) PC (24 bits) (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored on return. Figure 1.5 Stack Structure in Advanced Mode Rev. 4.00 Feb 24, 2006 page 9 of 322 REJ09B0139-0400 Section 1 CPU 1.3 Address Space Figure 1.6 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 4-Gbyte address space in advanced mode. The address space differs depending on the operating mode. For details, refer to the relevant microcontroller hardware manual. H'0000 H'00000000 H'FFFF Program area H'00FFFFFF Data area H'FFFFFFFF (a) Normal Mode (b) Advanced Mode Figure 1.6 Memory Map Rev. 4.00 Feb 24, 2006 page 10 of 322 REJ09B0139-0400 Section 1 CPU 1.4 Register Configuration 1.4.1 Overview The CPUs have the internal registers shown in figure 1.7. There are two types of registers: general registers and control registers. The H8S/2000 CPU does not support the MAC register. General Registers (Rn) and Extended Registers (En) 15 07 07 0 ER0 E0 R0H R0L ER1 E1 R1H R1L ER2 E2 R2H R2L ER3 E3 R3H R3L ER4 E4 R4H R4L ER5 E5 R5H R5L ER6 E6 R6H R6L ER7 (SP) E7 R7H R7L Control Registers (CR) 23 0 PC 7 6 5 4 3 2 1 0 EXR T -- -- -- -- I2 I1 I0 7 6 5 4 3 2 1 0 CCR I UI H U N Z V C 63 MAC 32 41 MACH Sign extension MACL 31 Legend: SP: PC: EXR: T: I2 to I0: CCR: I: UI: 0 Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit User bit or interrupt mask bit H: U: N: Z: V: C: MAC: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Multiply-accumulate register Figure 1.7 CPU Registers Rev. 4.00 Feb 24, 2006 page 11 of 322 REJ09B0139-0400 Section 1 CPU 1.4.2 General Registers The CPUs have eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. Figure 1.8 illustrates the usage of the general registers. The usage of each register can be selected independently. * Address registers * 32-bit registers * 16-bit registers * 8-bit registers E registers (extended registers) (E0 to E7) RH registers (R0H to R7H) ER registers (ER0 to ER7) R registers (R0 to R7) RL registers (R0L to R7L) Figure 1.8 Usage of General Registers General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 1.9 shows the stack. Rev. 4.00 Feb 24, 2006 page 12 of 322 REJ09B0139-0400 Section 1 CPU Free area SP (ER7) Stack area Figure 1.9 Stack 1.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR), and 64-bit multiply-accumulate register (MAC: H8S/2600 CPU only). (1) Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 16 bits (one word) or a multiple of 16 bits, so the least significant PC bit is ignored. When an instruction is fetched, the least significant PC bit is regarded as 0. (2) Extended Control Register (EXR) This 8-bit register contains the trace bit (T) and three interrupt mask bits (I2 to I0). Bit 7--Trace Bit (T): Selects trace mode. When this bit is cleared to 0, instructions are executed in sequence. When this bit is set to 1, a trace exception is generated each time an instruction is executed. Bits 6 to 3--Reserved: These bits are reserved, always read as 1. Bits 2 to 0--Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details refer to the relevant microcontroller hardware manual. Rev. 4.00 Feb 24, 2006 page 13 of 322 REJ09B0139-0400 Section 1 CPU Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions. All interrupts, including NMI, are disabled for three states after one of these instructions is executed, except for STC. (3) Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7--Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exceptionhandling sequence. Bit 6--User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit. For details refer to the relevant microcontroller hardware manual. Bit 5--Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Bit 4--User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3--Negative Flag (N): Stores the value of the most significant bit (sign bit) of data. Bit 2--Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1--Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0--Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * Add instructions, to indicate a carry * Subtract instructions, to indicate a borrow * Shift and rotate instructions, to store the value shifted out of the end bit The carry flag is also used as a bit accumulator by bit manipulation instructions. Rev. 4.00 Feb 24, 2006 page 14 of 322 REJ09B0139-0400 Section 1 CPU Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to the detailed descriptions of the instructions starting in section 2.2.1. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. (4) Multiply-Accumulate Register (MAC) The MAC register is supported only by the H8S/2600 CPU. This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32-bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are a sign extension. 1.4.4 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. Rev. 4.00 Feb 24, 2006 page 15 of 322 REJ09B0139-0400 Section 1 CPU 1.5 Data Formats The CPUs can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 1.5.1 General Register Data Formats Figure 1.10 shows the data formats in general registers. Data Type Register Number Data Format 1-bit data RnH 7 0 7 6 5 4 3 2 1 0 Don't care Don't care 7 0 7 6 5 4 3 2 1 0 1-bit data 4-bit BCD data RnL RnH 4 3 7 Upper 4-bit BCD data 0 Lower Don't care RnL Byte data RnH 4 3 7 Upper Don't care 7 0 Lower 0 Don't care MSB Byte data LSB RnL 7 0 Don't care MSB Figure 1.10 General Register Data Formats Rev. 4.00 Feb 24, 2006 page 16 of 322 REJ09B0139-0400 LSB Section 1 CPU Word data Rn Word data En 15 0 MSB 15 0 MSB Longword data LSB ERn 31 MSB LSB 16 15 En 0 Rn LSB Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 1.10 General Register Data Formats (cont) Rev. 4.00 Feb 24, 2006 page 17 of 322 REJ09B0139-0400 Section 1 CPU 1.5.2 Memory Data Formats Figure 1.11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. Data Type Data Format Address 7 1-bit data Address L Byte data Address L MSB Word data 7 0 6 5 4 3 2 1 0 LSB Address 2M MSB Address 2M + 1 Longword data LSB Address 2N MSB Address 2N + 1 Address 2N + 2 Address 2N + 3 LSB Figure 1.11 Memory Data Formats When the stack pointer (ER7) is used as an address register to access the stack, the operand size should be word size or longword size. Rev. 4.00 Feb 24, 2006 page 18 of 322 REJ09B0139-0400 Section 1 CPU 1.6 Instruction Set 1.6.1 Overview The H8S/2600 CPU has 69types of instructions, while the H8S/2000 CPU has 65 types. The instructions are classified by function as shown in table 1.1. For a detailed description of each instruction, see section 2.2, Instruction Descriptions. Table 1.1 Instruction Classification Function Instructions Size Types Data transfer MOV 2 2 POP* , PUSH* BWL 5 LDM, STM L MOVFPE, MOVTPE B ADD, SUB, CMP, NEG BWL ADDX, SUBX, DAA, DAS B Arithmetic operations INC, DEC BWL ADDS, SUBS L MULXU, DIVXU, MULXS, DIVXS BW EXTU, EXTS 4 TAS* WL 19 B MAC, LDMAC, STMAC, CLRMAC* Logic operations WL 1 AND, OR, XOR, NOT -- 4* BWL 4 1 Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL 8 Bit manipulation B 14 Branch BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR 3 Bcc* , JMP, BSR, JSR, RTS -- 5 System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP -- 9 Block data transfer EEPMOV -- H8S/2600 CPU: Total 69 types Legend: Notes: 1. 2. 3. 4. 1 H8S/2000 CPU: Total 65 types B: Byte size W: Word size L: Longword size The MAC, LDMAC, STMAC, and CLRMAC instructions are supported only by the H8S/2600 CPU. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. Bcc is the generic designation of a conditional branch instruction. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev. 4.00 Feb 24, 2006 page 19 of 322 REJ09B0139-0400 Arithmetic operations BWL WL B -- -- -- -- -- -- -- -- -- -- -- ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS MULXU, DIVXU MULXS, DIVXS NEG EXTU, EXTS TAS*2 MAC*1 CLRMAC*1 LDMAC*1, STMAC*1 -- MOVEPE, MOVTPE SUB -- LDM, STM ADD, CMP -- BWL #xx POP, PUSH Rn Rev. 4.00 Feb 24, 2006 page 20 of 322 REJ09B0139-0400 L -- -- -- WL BWL BW BW B BWL L B BWL BWL -- -- -- BWL @ERn -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- BWL @(d:16,ERn) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BWL @(d:32,ERn) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BWL @-ERn/@ERn+ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BWL B @aa:8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- @aa:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- BWL @aa:24 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- @aa:32 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BWL @(d:8,PC) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- @(d:16,PC) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- @@aa:8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- L WL Table 1.2 MOV Instruction 1.6.2 Data transfer Function Addressing Modes Section 1 CPU Instructions and Addressing Modes Table 1.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU and H8S/2000 CPU can use. Combinations of Instructions and Addressing Modes B -- -- ANDC, ORC, XORC NOP Block data transfer Rn -- -- -- B B -- -- -- -- -- -- B BWL BWL BWL @ERn -- -- -- W W -- -- -- -- -- -- B -- -- -- @(d:16,ERn) -- -- -- W W -- -- -- -- -- -- -- -- -- -- @(d:32,ERn) -- -- -- W W -- -- -- -- -- -- -- -- -- -- @-ERn/@ERn+ -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- @aa:8 Notes: 1. Supported only by the H8S/2600 CPU 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Legend: B: Byte W: Word L: Longword B -- SLEEP -- -- RTE STC -- -- TRAPA RTS LDC System control -- -- Bcc, BSR Branch JMP, JSR -- Bit manipulation -- BWL -- NOT AND, OR, XOR Instruction #xx Shift Logic operations Function Addressing Modes @aa:16 -- -- -- W W -- -- -- -- -- -- B -- -- -- @aa:24 -- -- -- -- -- -- -- -- -- -- -- -- -- -- @aa:32 -- -- -- W W -- -- -- -- -- -- B -- -- -- @(d:8,PC) -- -- -- -- -- -- -- -- -- -- -- -- -- -- @(d:16,PC) -- -- -- -- -- -- -- -- -- -- -- -- -- -- @@aa:8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BW -- -- -- -- -- -- -- -- -- Section 1 CPU Rev. 4.00 Feb 24, 2006 page 21 of 322 REJ09B0139-0400 Section 1 CPU 1.6.3 Table of Instructions Classified by Function Table 1.3 summarizes the instructions in each functional category. The notation used in table 1.3 is defined next. Operation Notation Rd General register (destination)* Rs General register (source)* Rn General register* ERn General register (32-bit register) MAC Multiply-accumulate register (32-bit register) (EAd) Destination operand (EAs) Source operand EXR Extended control register CCR Condition-code register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition - Subtraction x Multiplication / Division Logical AND Logical OR Logical exclusive OR Move Logical not (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Rev. 4.00 Feb 24, 2006 page 22 of 322 REJ09B0139-0400 Section 1 CPU Table 1.3 Instructions Classified by Function Type Instruction Size* Function Data transfer MOV B/W/L (EAs) Rd, Rs (EAd) 1 Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B (EAs) Rd Moves external memory contents (addressed by @aa:16) to a general register in synchronization with an E clock. MOVTPE B Rs (EAs) Moves general register contents to an external memory location (addressed by @aa:16) in synchronization with an E clock. POP W/L @SP+ Rn Pops a register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. PUSH W/L Rn @-SP Pushes a register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. LDM L @SP+ Rn (register list) Pops two or more general registers from the stack. STM L Rn (register list) @-SP Pushes two or more general registers onto the stack. Rev. 4.00 Feb 24, 2006 page 23 of 322 REJ09B0139-0400 Section 1 CPU Type Instruction Size* Function Arithmetic operations ADD B/W/L Rd Rs Rd, Rd #IMM Rd 1 SUB ADDX Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) B SUBX INC Performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register. B/W/L DEC ADDS L Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. B DAS MULXU Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) SUBS DAA Rd Rs C Rd, Rd #IMM C Rd Rd decimal adjust Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4bit BCD data. B/W Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. MULXS B/W Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. DIVXU B/W Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. DIVXS B/W Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. Rev. 4.00 Feb 24, 2006 page 24 of 322 REJ09B0139-0400 Section 1 CPU Type Instruction Size* Function Arithmetic operations CMP B/W/L Rd - Rs, Rd - #IMM 1 Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. NEG B/W/L 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. EXTU W/L Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. EXTS TAS W/L Rd (sign extension) Rd B Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. 2 @ERd - 0, 1 (<bit 7> of @ERd)* Tests memory contents, and sets the most significant bit (bit 7) to 1. MAC -- (EAs) x (EAd) + MAC MAC Performs signed multiplication on memory contents and adds the result to the multiply-accumulate register. The following operations can be performed: 16 bits x 16 bits +32 bits 32 bits, saturating 16 bits x 16 bits + 42 bits 42 bits, non-saturating Supported by H8S/2600 CPU only. CLRMAC -- 0 MAC Clears the multiply-accumulate register to zero. Supported by H8S/2600 CPU only. LDMAC STMAC L Rs MAC, MAC Rd Transfers data between a general register and the multiply-accumulate register. Supported by H8S/2600 CPU only. Rev. 4.00 Feb 24, 2006 page 25 of 322 REJ09B0139-0400 Section 1 CPU Type Instruction Size* Function Logic operations AND B/W/L Rd Rs Rd, Rd #IMM Rd 1 Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. NOT B/W/L (Rd) (Rd) Takes the one's complement of general register contents. Shift operations SHAL B/W/L SHAR Rd (shift) Rd Performs an arithmetic shift on general register contents. 1-bit or 2-bit shift is possible. SHLL B/W/L SHLR Rd (shift) Rd Performs a logical shift on general register contents. 1-bit or 2-bit shift is possible. ROTL B/W/L ROTR Rd (rotate) Rd Rotates general register contents. 1-bit or 2-bit rotation is possible. ROTXL B/W/L ROTXR Rd (rotate) Rd Rotates general register contents through the carry bit. 1-bit or 2-bit rotation is possible. Rev. 4.00 Feb 24, 2006 page 26 of 322 REJ09B0139-0400 Section 1 CPU Type Instruction Size* Function Bit-manipulation instructions BSET B 1 (<bit-No.> of <EAd>) 1 Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 (<bit-No.> of <EAd>) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B (<bit-No.> of <EAd>) (<bit-No.> of <EAd>) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BTST B (<bit-No.> of <EAd>) Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BAND B C (<bit-No.> of <EAd>) C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIAND B C (<bit-No.> of <EAd>) C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BOR B C (<bit-No.> of <EAd>) C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIOR B C (<bit-No.> of <EAd>) C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. Rev. 4.00 Feb 24, 2006 page 27 of 322 REJ09B0139-0400 Section 1 CPU Type Instruction Size* Function Bit-manipulation instructions BXOR B C (<bit-No.> of <EAd>) C 1 Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C (<bit-No.> of <EAd>) C Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B (<bit-No.> of <EAd>) C Transfers a specified bit in a general register or memory operand to the carry flag. BILD B (<bit-No.> of <EAd>) C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. BST B C (<bit-No.> of <EAd>) Transfers the carry flag value to a specified bit in a general register or memory operand. BIST B C (<bit-No.> of <EAd>) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data. Rev. 4.00 Feb 24, 2006 page 28 of 322 REJ09B0139-0400 Section 1 CPU Type Instruction Size* Function Branch instructions Bcc -- Branches to a specified address if a specified condition is true. The branching conditions are listed below. 1 Mnemonic Description Condition BRA(BT) Always (true) Always BRN(BF) Never (false) Never BHI High CZ=0 BLS Low or same CZ=1 BCC(BHS) Carry clear (high or same) C=0 BCS(BLO) Carry set (low) C=1 BNE Not equal Z=0 BEQ Equal Z=1 BVC Overflow clear V=0 BVS Overflow set V=1 BPL Plus N=0 BMI Minus N=1 BGE Greater or equal N V = 0 BLT Less than NV=1 BGT Greater than Z (N V) = 0 BLE Less or equal Z (N V) = 1 JMP -- Branches unconditionally to a specified address. BSR -- Branches to a subroutine at a specified address. JSR -- Branches to a subroutine at a specified address. RTS -- Returns from a subroutine Rev. 4.00 Feb 24, 2006 page 29 of 322 REJ09B0139-0400 Section 1 CPU Type Instruction Size* Function System control instructions TRAPA -- Starts trap-instruction exception handling. RTE -- Returns from an exception-handling routine. 1 SLEEP -- Causes a transition to a power-down state. LDC B/W (EAs) CCR, (EAs) EXR Moves the source operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. STC B/W CCR (EAd), EXR (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. ANDC B CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data. ORC B CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data. XORC B CCR #IMM CCR, EXR #IMM EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. NOP -- PC + 2 PC Only increments the program counter. Rev. 4.00 Feb 24, 2006 page 30 of 322 REJ09B0139-0400 Section 1 CPU Type Instruction Size* Function Block data transfer instruction EEPMOV.B -- if R4L 0 then Repeat @ER5+ @ER6+ R4L - 1 R4L Until R4L = 0 else next; EEPMOV.W -- if R4 0 then Repeat @ER5+ @ER6+ R4 - 1 R4 Until R4 = 0 else next; 1 Transfers a data block according to parameters set in general registers R4L or R4, ER5, and ER6. R4L or R4: size of block (bytes) ER5: starting source address ER6: starting destination address Execution of the next instruction begins as soon as the transfer is completed. Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev. 4.00 Feb 24, 2006 page 31 of 322 REJ09B0139-0400 Section 1 CPU 1.6.4 Basic Instruction Formats The H8S/2600 or H8S/2000 instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. Condition Field: Specifies the branching condition of Bcc instructions. Figure 1.12 shows examples of instruction formats. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op rn rm MOV.B @(d:16, Rn), Rm, etc. EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:8, etc Figure 1.12 Instruction Formats Rev. 4.00 Feb 24, 2006 page 32 of 322 REJ09B0139-0400 Section 1 CPU 1.7 Addressing Modes and Effective Address Calculation (1) Addressing Modes The CPUs support the eight addressing modes listed in table 1.4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 1.4 Addressing Modes No. Addressing Mode Symbol 1 Register direct Rn 2 Register indirect @ERn 3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn) 4 Register indirect with post-increment @ERn+ Register indirect with pre-decrement @-ERn 5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32 6 Immediate #xx:8/#xx:16/#xx:32 7 Program-counter relative @(d:8,PC)/@(d:16,PC) 8 Memory indirect @@aa:8 1. Register Direct--Rn: The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2. Register Indirect--@ERn: The register field of the instruction code specifies an address register (ERn) which contains the address of the operand in memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). 3. Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn): A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. Rev. 4.00 Feb 24, 2006 page 33 of 322 REJ09B0139-0400 Section 1 CPU 4. Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn: * Register indirect with post-increment--@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or longword access, the register value should be even. * Register indirect with pre-decrement--@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. For word or longword access, the register value should be even. 5. Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32: The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 1.5 indicates the accessible absolute address ranges. Table 1.5 Absolute Address Access Ranges Absolute Address Data address Program instruction address Normal Mode Advanced Mode 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFFFF00 to H'FFFFFFFF 16 bits (@aa:16) H'0000 to H'FFFF H'00000000 to H'00007FFF, H'FFFF8000 to H'FFFFFFFF 32 bits (@aa:32) H'00000000 to H'FFFFFFFF 24 bits (@aa:24) H'00000000 to H'00FFFFFF For further details on the accessible range, refer to the relevant microcontroller hardware manual. Rev. 4.00 Feb 24, 2006 page 34 of 322 REJ09B0139-0400 Section 1 CPU 6. Immediate--#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. 7. Program-Counter Relative--@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. 8. Memory Indirect--@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction specifies a memory operand by an 8-bit absolute address. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'00000000 to H'000000FF in advanced mode). In normal mode the memory operand is a word operand and the branch address is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details refer to the relevant microcontroller hardware manual. Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode (b) Advanced Mode Figure 1.13 Branch Address Specification in Memory Indirect Mode Rev. 4.00 Feb 24, 2006 page 35 of 322 REJ09B0139-0400 Section 1 CPU If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or an instruction code to be fetched at the address preceding the specified address. (For further information, see section 1.5.2, Memory Data Formats.) (2) Effective Address Calculation Table 1.6 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Rev. 4.00 Feb 24, 2006 page 36 of 322 REJ09B0139-0400 4 3 rm rn r r disp r op r * Register indirect with pre-decrement @-ERn op Register indirect with post-increment or pre-decrement * Register indirect with post-increment @ERn+ op Register indirect with displacement @(d:16, ERn) or @(d:32, ERn) op Register indirect (@ERn) op Register direct (Rn) Addressing Mode and Instruction Format disp 1 2 4 0 1, 2, or 4 General register contents Byte Word Longword 0 0 0 0 1, 2, or 4 General register contents Sign extension General register contents General register contents Operand Size Value added 31 31 31 31 31 Effective Address Calculation 31 31 31 31 Operand is general register contents. Effective Address (EA) 0 0 0 0 Table 1.6 2 1 No. Section 1 CPU Effective Address Calculation Rev. 4.00 Feb 24, 2006 page 37 of 322 REJ09B0139-0400 Rev. 4.00 Feb 24, 2006 page 38 of 322 REJ09B0139-0400 6 op op abs abs abs op IMM Immediate #xx:8/#xx:16/#xx:32 @aa:32 op @aa:24 @aa:16 op abs Absolute address 5 @aa:8 Addressing Mode and Instruction Format No. Effective Address Calculation H'00 24 23 Sign extension 16 15 H'FFFFFF Operand is immediate data. 31 31 31 31 87 Effective Address (EA) 0 0 0 0 Section 1 CPU 8 7 No. abs op abs * Advanced mode op * Normal mode Memory indirect @@aa:8 op @(d:8, PC)/@(d:16, PC) Program-counter relative disp Addressing Mode and Instruction Format Reserved 31 31 31 23 abs 87 abs Memory contents 15 87 Memory contents H'000000 H'000000 disp PC contents Sign extension 23 23 Effective Address Calculation 0 0 0 0 0 0 31 24 23 H'00 24 23 H'0000 H'00 31 31 16 15 Effective Address (EA) 0 0 0 Section 1 CPU Rev. 4.00 Feb 24, 2006 page 39 of 322 REJ09B0139-0400 Section 1 CPU Rev. 4.00 Feb 24, 2006 page 40 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions Section 2 Instruction Descriptions 2.1 Tables and Symbols This section explains how to read the tables in section 2.2, describing each instruction. Note that the descriptions of some instructions extend over more than one page. [1] Mnemonic (Full Name) [3] Operation [2] Type [6] Condition Code [4] Assembly-Language Format [5] Operand Size [7] Description [8] Available Registers [9] Operand Format and Number of States Required for Execution [10] Notes [1] Mnemonic (Full Name): Gives the full and mnemonic names of the instruction. [2] Type: Indicates the type of instruction. [3] Operation: Describes the instruction in symbolic notation. (See section 2.1.2, Operation.) [4] Assembly-Language Format: Indicates the assembly-language format of the instruction. (See section 2.1.1, Assembler Format.) [5] Operand Size: Indicates the available operand sizes. [6] Condition Code: Indicates the effect of instruction execution on the flag bits in the CCR. (See section 2.1.3, Condition Code.) [7] Description: Describes the operation of the instruction in detail. [8] Available Registers: Indicates which registers can be specified in the register field of the instruction. [9] Operand Format and Number of States Required for Execution: Shows the addressing modes and instruction format together with the number of states required for execution. [10] Notes: Gives notes concerning execution of the instruction. Rev. 4.00 Feb 24, 2006 page 41 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.1.1 Assembly-Language Format Example: ADD. B <EAs>, Rd Destination operand Source operand Size Mnemonic The operand size is byte (B), word (W), or longword (L). Some instructions are restricted to a limited set of operand sizes. The symbol <EA> indicates that two or more addressing modes can be used. The H8S/2600 CPU supports the eight addressing modes listed next. Effective address calculation is described in section 1.7, Addressing Modes and Effective Address Calculation. Symbol Addressing Mode Rn Register direct @ERn Register indirect @(d:16, ERn)/@(d:32, ERn) Register indirect with displacement (16-bit or 32-bit) @ERn+/@-ERn Register indirect with post-increment or pre-decrement @aa:8/@aa:16/@aa:24/@aa:32 Absolute address (8-bit, 16-bit, 24-bit, or 32-bit) #xx:8/#xx:16/#xx:32 Immediate (8-bit, 16-bit, or 32-bit) @(d:8, PC)/@(d:16, PC) Program-counter relative (8-bit or 16-bit) @@aa:8 Memory indirect The suffixes :8, :16, :24, and :32 may be omitted. In particular, if the :8, :16, :24, or :32 designation is omitted in an absolute address or displacement, the assembler will optimize the length according to the value range. For details, refer to the H8S, H8/300 Series cross assembler user's manual. Note: ":2" and ":3" in "#xx (:2)" and "#xx (:3)" indicate the specifiable bit length. Do not include (:2) or (:3) in the assembler notation. Example: TRAPA #3 Rev. 4.00 Feb 24, 2006 page 42 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.1.2 Operation The symbols used in the operation descriptions are defined as follows. Rd General register (destination)* Rs General register (source)* Rn General register* ERn General register (32-bit register) MAC Multiply-accumulate register (32-bit register) (EAd) Destination operand (EAs) Source operand EXR Extended control register CCR Condition-code register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Add - Subtract x Multiply / Divide Logical AND Logical OR Logical exclusive OR Transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right Logical NOT (logical complement) ( ) < > Contents of effective address of the operand :8/:16/ :24/:32 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H and R0L to R7L), 16-bit registers (R0 to R7 and E0 to E7), and 32-bit registers (ER0 to ER7). Rev. 4.00 Feb 24, 2006 page 43 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.1.3 Condition Code Symbol Meaning The symbols used in the condition-code description are defined as follows. Changes according to the result of instruction execution * Undetermined (no guaranteed value) 0 Always cleared to 0 1 Always set to 1 -- Not affected by execution of the instruction Varies depending on conditions; see the notes For details on changes of the condition code, see section 2.8, Condition Code Modification. 2.1.4 Instruction Format The symbols used in the instruction format descriptions are listed below. Symbol Meaning IMM Immediate data (2, 3, 8, 16, or 32 bits) abs Absolute address (8, 16, 24, or 32 bits) disp Displacement (8, 16, or 32 bits) rs, rd, rn Register field (4 bits). The symbols rs, rd, and rn correspond to operand symbols Rs, Rd, and Rn. ers, erd, ern Register field (3 bits). The symbols ers, erd, and ern correspond to operand symbols ERs, ERd, and ERn. Rev. 4.00 Feb 24, 2006 page 44 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.1.5 Register Specification Address Register Specification: When a general register is used as an address register [@ERn, @(d:16, ERn), @(d:32, ERn), @ERn+, or @-ERn], the register is specified by a 3-bit register field (ers or erd). Data Register Specification: A general register can be used as a 32-bit, 16-bit, or 8-bit data register. When used as a 32-bit register, it is specified by a 3-bit register field (ers, erd, or ern). When used as a 16-bit register, it is specified by a 4-bit register field (rs, rd, or rn). The lower 3 bits specify the register number. The upper bit is set to 1 to specify an extended register (En) or cleared to 0 to specify a general register (Rn). When used as an 8-bit register, it is specified by a 4-bit register field (rs, rd, or rn). The lower 3 bits specify the register number. The upper bit is set to 1 to specify a low register (RnL) or cleared to 0 to specify a high register (RnH). This is shown next. Address Register 32-Bit Register 16-Bit Register 8-Bit Register Register Field General Register Register Field General Register Register Field General Register 000 001 . . 111 ER0 ER1 * * ER7 0000 0001 * * 0111 1000 1001 * * 1111 R0 R1 * * R7 E0 E1 * * E7 0000 0001 * * 0111 1000 1001 * * 1111 R0H R1H * * R7H R0L R1L * * R7L Rev. 4.00 Feb 24, 2006 page 45 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.1.6 Bit Data Access in Bit Manipulation Instructions Bit data is accessed as the n-th bit (n = 0, 1, 2, 3, ..., 7) of a byte operand in a general register or memory. The bit number is given by 3-bit immediate data, or by the lower 3 bits of a general register value. Example 1: To set bit 3 in R2H to 1 BSET R1L, R2H R1L Don't care 0 1 1 Bit number R2H 0 1 1 0 0 1 0 1 Set to 1 Example 2: To load bit 5 at address H'FFFF02 into the bit accumulator BLD #5, @H'FFFF02 #5 H'FFFF02 1 0 1 0 0 1 1 0 C Load The operand size and addressing mode are as indicated for register or memory operand data. Rev. 4.00 Feb 24, 2006 page 46 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2 Instruction Descriptions The instructions are described starting in section 2.2.1. Rev. 4.00 Feb 24, 2006 page 47 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.1 (1) ADD (B) ADD (ADD Binary) Add Binary H U N -- -- -- Z V C UI I Rd + (EAs) Rd Condition Code Operation H: Set to 1 if there is a carry at bit 3; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a carry at bit 7; otherwise cleared to 0. Assembly-Language Format ADD.B <EAs>, Rd Operand Size Byte Description This instruction adds the source operand to the contents of an 8-bit register Rd (destination operand) and stores the result in the 8-bit register Rd. Available Registers Rd: R0L to R7L, R0H to R7H Rs: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Instruction Format Mnemonic Operands Immediate ADD.B #xx:8, Rd 8 rd Register direct ADD.B Rs, Rd 0 8 Notes Rev. 4.00 Feb 24, 2006 page 48 of 322 REJ09B0139-0400 1st byte 2nd byte IMM rs 3rd byte 4th byte No. of States 1 rd 1 Section 2 Instruction Descriptions 2.2.1 (2) ADD (W) ADD (ADD Binary) Add Binary H U N -- -- -- Z V C UI I Rd + (EAs) Rd Condition Code Operation H: Set to 1 if there is a carry at bit 11; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a carry at bit 15; otherwise cleared to 0. Assembly-Language Format ADD.W <EAs>, Rd Operand Size Word Description This instruction adds the source operand to the contents of a 16-bit register Rd (destination operand) and stores the result in the 16-bit register Rd. Available Registers Rd: R0 to R7, E0 to E7 Rs: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Instruction Format Mnemonic Operands Immediate ADD.W #xx:16, Rd 7 9 1 rd Register direct ADD.W Rs, Rd 0 9 rs rd 1st byte 2nd byte 3rd byte 4th byte IMM No. of States 2 1 Notes Rev. 4.00 Feb 24, 2006 page 49 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions ADD (L) ADD (ADD Binary) Add Binary H U -- -- -- N Z V C UI I ERd + (EAs) ERd Condition Code Operation 2.2.1 (3) H: Set to 1 if there is a carry at bit 27; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a carry at bit 31; otherwise cleared to 0. Assembly-Language Format ADD.L <EAs>, ERd Operand Size Longword Description This instruction adds the source operand to the contents of a 32-bit register ERd (destination operand) and stores the result in the 32-bit register ERd. Available Registers ERd: ER0 to ER7 ERs: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Instruction Format Mnemonic Operands 1st byte Immediate ADD.L #xx:32, ERd 7 A Register direct ADD.L ERs, ERd 0 A Notes Rev. 4.00 Feb 24, 2006 page 50 of 322 REJ09B0139-0400 2nd byte 1 0 erd 1 ers 0 erd 3rd byte 4th byte 5th byte IMM 6th byte No. of States 3 1 Section 2 Instruction Descriptions 2.2.2 ADDS ADDS (ADD with Sign extension) Add Binary Address Data Condition Code Operation Rd + 1 ERd Rd + 2 ERd Rd + 4 ERd I UI H U N Z V C -- -- -- -- -- -- -- -- H: N: Z: V: C: Assembly-Language Format ADDS #1, ERd ADDS #2, ERd ADDS #4, ERd Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Operand Size Longword Description This instruction adds the immediate value 1, 2, or 4 to the contents of a 32-bit register ERd (destination operand). Unlike the ADD instruction, it does not affect the condition code flags. Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Operands Register direct ADDS Register direct ADDS Register direct ADDS Instruction Format 3rd byte 4th byte No. of States 1st byte 2nd byte #1, ERd 0 B 0 0 erd 1 #2, ERd 0 B 8 0 erd 1 #4, ERd 0 B 9 0 erd 1 Notes Rev. 4.00 Feb 24, 2006 page 51 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions ADDX ADDX (ADD with eXtend carry) Add with Carry UI H U N -- -- -- I Z V C Rd + (EAs) + C Rd Condition Code Operation 2.2.3 H: Set to 1 if there is a carry at bit 3; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a carry at bit 7; otherwise cleared to 0. Assembly-Language Format ADDX <EAs>, Rd Operand Size Byte Description This instruction adds the source operand and carry flag to the contents of an 8-bit register Rd (destination operand) and stores the result in the 8-bit register Rd. Available Registers Rd: R0L to R7L, R0H to R7H Rs: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Instruction Format Mnemonic Operands Immediate ADDX #xx:8, Rd 9 rd Register direct ADDX Rs, Rd 0 E Notes Rev. 4.00 Feb 24, 2006 page 52 of 322 REJ09B0139-0400 1st byte 2nd byte IMM rs 3rd byte 4th byte No. of States 1 rd 1 Section 2 Instruction Descriptions 2.2.4 (1) AND (B) AND (AND logical) Logical AND Condition Code Operation Rd (EAs) Rd U N Z V C -- -- -- -- I UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format AND.B <EAs>, Rd Operand Size Byte Description This instruction ANDs the source operand with the contents of an 8-bit register Rd (destination operand) and stores the result in the 8-bit register Rd. Available Registers Rd: R0L to R7L, R0H to R7H Rs: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Instruction Format Mnemonic Operands Immediate AND.B #xx:8, Rd E rd Register direct AND.B Rs, Rd 1 6 1st byte 2nd byte IMM rs 3rd byte 4th byte No. of States 1 rd 1 Notes Rev. 4.00 Feb 24, 2006 page 53 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.4 (2) AND (W) AND (AND logical) Logical AND Condition Code Operation Rd (EAs) Rd U N Z V C -- -- -- -- I UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format AND.W <EAs>, Rd Operand Size Word Description This instruction ANDs the source operand with the contents of a 16-bit register Rd (destination operand) and stores the result in the 16-bit register Rd. Available Registers Rd: R0 to R7, E0 to E7 Rs: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Instruction Format Mnemonic Operands Immediate AND.W #xx:16, Rd 7 9 6 rd Register direct AND.W Rs, Rd 6 6 rs rd Notes Rev. 4.00 Feb 24, 2006 page 54 of 322 REJ09B0139-0400 1st byte 2nd byte 3rd byte 4th byte IMM No. of States 2 1 Section 2 Instruction Descriptions 2.2.4 (3) AND (L) AND (AND logical) Logical AND Condition Code Operation ERd (EAs) ERd U N Z V C -- -- -- -- I UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format AND.L <EAs>, ERd Operand Size Longword Description This instruction ANDs the source operand with the contents of a 32-bit register ERd (destination operand) and stores the result in the 32-bit register ERd. Available Registers ERd: ER0 to ER7 ERs: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Instruction Format Mnemonic Operands 1st byte 2nd byte Immediate AND.L #xx:32, ERd 7 A 6 0 erd Register direct AND.L ERs, ERd 0 1 F 0 3rd byte 4th byte 5th byte IMM 6 6 0 ers 0 erd 6th byte No. of States 3 2 Notes Rev. 4.00 Feb 24, 2006 page 55 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.5 (1) ANDC ANDC (AND Control register) Logical AND with CCR I: UI: H: U: N: Z: V: C: Assembly-Language Format ANDC #xx:8, CCR Operand Size Byte I UI H U N Z V C CCR #IMM CCR Condition Code Operation Stores the corresponding bit of the result. Stores the corresponding bit of the result. Stores the corresponding bit of the result. Stores the corresponding bit of the result. Stores the corresponding bit of the result. Stores the corresponding bit of the result. Stores the corresponding bit of the result. Stores the corresponding bit of the result. Description This instruction ANDs the contents of the condition-code register (CCR) with immediate data and stores the result in the condition-code register. No interrupt requests, including NMI, are accepted immediately after execution of this instruction. Operand Format and Number of States Required for Execution Addressing Mode Immediate Mnemonic Operands ANDC #xx:8, CCR Notes Rev. 4.00 Feb 24, 2006 page 56 of 322 REJ09B0139-0400 Instruction Format 1st byte 0 6 2nd byte IMM 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions 2.2.5 (2) ANDC ANDC (AND Control register) Logical AND with EXR Condition Code Operation EXR #IMM EXR I UI H U N Z V C -- -- -- -- -- -- -- -- H: N: Z: V: C: Assembly-Language Format ANDC #xx:8, EXR Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Operand Size Byte Description This instruction ANDs the contents of the extended control register (EXR) with immediate data and stores the result in the extended control register. No interrupt requests, including NMI, are accepted for three states after execution of this instruction. Operand Format and Number of States Required for Execution Addressing Mode Immediate Mnemonic Operands ANDC #xx:8, EXR Instruction Format 1st byte 2nd byte 3rd byte 0 4 0 1 1 6 4th byte No. of States IMM 2 Notes Rev. 4.00 Feb 24, 2006 page 57 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.6 BAND BAND (Bit AND) Bit Logical AND Condition Code Operation C (<bit No.> of <EAd>) C H: N: Z: V: C: Assembly-Language Format BAND #xx:3, <EAd> V C -- -- -- -- -- -- -- I UI H U N Z Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Stores the result of the operation. Operand Size Byte Description This instruction ANDs a specified bit in the destination operand with the carry flag and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. The destination operand contents remain unchanged. Specified by #xx:3 Bit No. 7 0 <EAd> C Available Registers Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Rev. 4.00 Feb 24, 2006 page 58 of 322 REJ09B0139-0400 C #xx:3, Rd BAND BAND BAND BAND BAND Register direct Register indirect Absolute address Absolute address Absolute address 6 6 7 7 7 A A E C 6 1st byte 3 1 abs 0 erd 0 IMM 0 0 0 rd 2nd byte 7 7 6 6 3rd byte abs 0 IMM 0 IMM 0 0 abs 7 0 IMM 0 6th byte For the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. Notes 6 5th byte Instruction Format 4th byte Note: * The addressing mode is the addressing mode of the destination operand <EAd>. #xx:3, @aa:32 #xx:3, @aa:16 #xx:3, @aa:8 #xx:3, @ERd Operands Addressing Mnemonic Mode* Operand Format and Number of States Required for Execution 7 6 7th byte 0 IMM 0 8th byte 5 4 3 3 1 No. of States Section 2 Instruction Descriptions BAND (Bit AND) Bit Logical AND Rev. 4.00 Feb 24, 2006 page 59 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.7 Bcc Bcc (Branch conditionally) Conditional Branch Condition Code Operation If condition is true, then PC + disp PC else next; I UI H U N Z V C -- -- -- -- -- -- -- -- H: N: Z: V: C: Assembly-Language Format Bcc disp Condition field Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Operand Size -- Description If the condition specified in the condition field (cc) is true, a displacement is added to the program counter (PC) and execution branches to the resulting address. If the condition is false, the next instruction is executed. The PC value used in the address calculation is the starting address of the instruction immediately following the Bcc instruction. The displacement is a signed 8-bit or 16-bit value. The branch destination address can be located in the range from -126 to +128 bytes or -32766 to +32768 bytes from the Bcc instruction. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Meaning Always (true) Never (false) HIgh Low or Same Carry Clear (High or Same) Carry Set (LOw) Not Equal EQual oVerflow Clear oVerflow Set PLus MInus Greater or Equal Less Than Greater Than Less or Equal cc 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Condition True False CZ = 0 CZ = 1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV = 0 NV = 1 Z(NV) = 0 Z(NV) = 1 Signed/Unsigned* X > Y (unsigned) X Y (unsigned) X Y (unsigned) X < Y (unsigned) X Y (unsigned or signed) X = Y (unsigned or signed) X Y (signed) X < Y (signed) X > Y (signed) X Y (signed) Note: * If the immediately preceding instruction is a CMP instruction, X is the general register contents (destination operand) and Y is the source operand. Rev. 4.00 Feb 24, 2006 page 60 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions Bcc (Branch conditionally) Conditional Branch Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Program-counter BRA (BT) relative Program-counter BRN (BF) relative Program-counter BHI relative Program-counter BLS relative Program-counter Bcc (BHS) relative Program-counter BCS (BLO) relative Program-counter BNE relative Program-counter BEQ relative Program-counter BVC relative Program-counter BVS relative Program-counter BPL relative Program-counter BMI relative Program-counter BGE relative Program-counter BLT relative Program-counter BGT relative Program-counter BLE relative Operands d:8 d:16 d:8 d:16 d:8 d:16 d:8 d:16 d:8 d:16 d:8 d:16 d:8 d:16 d:8 d:16 d:8 d:16 d:8 d:16 d:8 d:16 d:8 d:16 d:8 d:16 d:8 d:16 d:8 d:16 d:8 d:16 1st byte 4 0 5 8 4 1 5 8 4 2 5 8 4 3 5 8 4 4 5 8 4 5 5 8 4 6 5 8 4 7 5 8 4 8 5 8 4 9 5 8 4 A 5 8 4 B 5 8 4 C 5 8 4 D 5 8 4 E 5 8 4 F 5 8 Instruction Format 2nd byte 3rd byte 4th byte disp 0 0 disp disp 1 0 disp disp 2 0 disp disp 3 0 disp disp 4 0 disp disp 5 0 disp disp 6 0 disp disp 7 0 disp disp 8 0 disp disp 9 0 disp disp A 0 disp disp B 0 disp disp C 0 disp disp D 0 disp disp E 0 disp disp F 0 disp No. of States 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 Notes 1. The branch destination address must be even. 2. In machine language BRA, BRN, BCC, and BCS are identical to BT, BF, BHS, and BLO, respectively. Rev. 4.00 Feb 24, 2006 page 61 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.8 BCLR BCLR (Bit CLeaR) Bit Clear Condition Code Operation 0 (<bit No.> of <EAd>) I UI H U N Z V C -- -- -- -- -- -- -- -- H: N: Z: V: C: Assembly-Language Format BCLR #xx:3, <EAd> BCLR Rn, <EAd> Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Operand Size Byte Description This instruction clears a specified bit in the destination operand to 0. The bit number can be specified by 3-bit immediate data, or by the lower three bits of an 8-bit register Rn. The specified bit is not tested. The condition-code flags are not altered. Specified by #xx:3 or Rn Bit No. 7 0 <EAd> 0 Available Registers Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Rn: R0L to R7L, R0H to R7H Rev. 4.00 Feb 24, 2006 page 62 of 322 REJ09B0139-0400 #xx:3, Rd BCLR BCLR BCLR BCLR BCLR BCLR BCLR BCLR BCLR BCLR Register direct Register indirect Absolute address Absolute address Absolute address Register direct Register indirect Absolute address Absolute address Absolute address 6 6 7 7 6 6 6 7 7 7 A A F D 2 A A F D 2 1st byte 3 1 abs 0 erd rn 3 1 abs 0 erd 0 IMM 8 8 0 rd 8 8 0 rd 2nd byte 6 6 7 7 2 2 2 2 3rd byte abs abs rn rn 0 IMM 0 IMM 0 0 0 0 abs abs 6 7 rn 0 IMM 0 0 6th byte For the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. Notes 2 2 5th byte Instruction Format 4th byte Note: * The addressing mode is the addressing mode of the destination operand <EAd>. Rn, @aa:32 Rn, @aa:16 Rn, @aa:8 Rn, @ERd Rn, Rd #xx:3, @aa:32 #xx:3, @aa:16 #xx:3, @aa:8 #xx:3, @ERd Operands Addressing Mnemonic Mode* Operand Format and Number of States Required for Execution 6 7 2 2 7th byte rn 0 IMM 0 0 8th byte 6 5 4 4 1 6 5 4 4 1 No. of States Section 2 Instruction Descriptions BCLR (Bit CLeaR) Bit Clear Rev. 4.00 Feb 24, 2006 page 63 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.9 BIAND BIAND (Bit Invert AND) Bit Logical AND Condition Code Operation C [ (<bit No.> of <EAd>)] C H: N: Z: V: C: Assembly-Language Format BIAND #xx:3, <EAd> V C -- -- -- -- -- -- -- I UI H U N Z Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Stores the result of the operation. Operand Size Byte Description This instruction ANDs the inverse of a specified bit in the destination operand with the carry flag and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. The destination operand contents remain unchanged. Specified by #xx:3 Bit No. 7 0 <EAd> Invert C Available Registers Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Rev. 4.00 Feb 24, 2006 page 64 of 322 REJ09B0139-0400 C #xx:3, Rd BIAND BIAND BIAND BIAND BIAND Register direct Register indirect Absolute address Absolute address Absolute address 6 6 7 7 7 A A E C 6 1st byte 3 1 abs 0 erd 1 IMM 0 0 0 rd 2nd byte 7 7 6 6 3rd byte abs 1 IMM 1 IMM 0 0 abs 7 1 IMM 0 6th byte For the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. Notes 6 5th byte Instruction Format 4th byte Note: * The addressing mode is the addressing mode of the destination operand <EAd>. #xx:3, @aa:32 #xx:3, @aa:16 #xx:3, @aa:8 #xx:3, @ERd Operands Addressing Mnemonic Mode* Operand Format and Number of States Required for Execution 7 6 7th byte 1 IMM 0 8th byte 5 4 3 3 1 No. of States Section 2 Instruction Descriptions BIAND (Bit Invert AND) Bit Logical AND Rev. 4.00 Feb 24, 2006 page 65 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.10 BILD BILD (Bit Invert LoaD) Bit Load Condition Code Operation (<bit No.> of <EAd>) C H: N: Z: V: C: Assembly-Language Format BILD #xx:3, <EAd> Operand Size V C -- -- -- -- -- -- -- I UI H U N Z Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Loaded with the inverse of the specified bit. Byte Description This instruction loads the inverse of a specified bit from the destination operand into the carry flag. The bit number is specified by 3-bit immediate data. The destination operand contents remain unchanged. Specified by #xx:3 Bit No. 7 0 <EAd> Invert Available Registers Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Rev. 4.00 Feb 24, 2006 page 66 of 322 REJ09B0139-0400 C #xx:3, Rd BILD BILD BILD BILD BILD Register direct Register indirect Absolute address Absolute address Absolute address 6 6 7 7 7 A A E C 7 1st byte 3 1 abs 0 erd 1 IMM 0 0 0 rd 2nd byte 7 7 7 7 3rd byte abs 1 IMM 1 IMM 0 0 abs 7 1 IMM 0 6th byte For the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. Notes 7 5th byte Instruction Format 4th byte Note: * The addressing mode is the addressing mode of the destination operand <EAd>. #xx:3, @aa:32 #xx:3, @aa:16 #xx:3, @aa:8 #xx:3, @ERd Operands Addressing Mnemonic Mode* Operand Format and Number of States Required for Execution 7 7 7th byte 1 IMM 0 8th byte 5 4 3 3 1 No. of States Section 2 Instruction Descriptions BILD (Bit Invert LoaD) Bit Load Rev. 4.00 Feb 24, 2006 page 67 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.11 BIOR BIOR (Bit Invert inclusive OR) Bit Logical OR Condition Code Operation C [ (<bit No.> of <EAd>)] C H: N: Z: V: C: Assembly-Language Format BIOR #xx:3, <EAd> V C -- -- -- -- -- -- -- I UI H U N Z Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Stores the result of the operation. Operand Size Byte Description This instruction ORs the inverse of a specified bit in the destination operand with the carry flag and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. The destination operand contents remain unchanged. Specified by #xx:3 Bit No. 7 0 <EAd> Invert C Available Registers Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Rev. 4.00 Feb 24, 2006 page 68 of 322 REJ09B0139-0400 C #xx:3, Rd BIOR BIOR BIOR BIOR BIOR Register direct Register indirect Absolute address Absolute address Absolute address 6 6 7 7 7 A A E C 4 1st byte 3 1 abs 0 erd 1 IMM 0 0 0 rd 2nd byte 7 7 4 4 3rd byte abs 1 IMM 1 IMM 0 0 abs 7 1 IMM 0 6th byte For the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. Notes 4 5th byte Instruction Format 4th byte Note: * The addressing mode is the addressing mode of the destination operand <EAd>. #xx:3, @aa:32 #xx:3, @aa:16 #xx:3, @aa:8 #xx:3, @ERd Operands Addressing Mnemonic Mode* Operand Format and Number of States Required for Execution 7 4 7th byte 1 IMM 0 8th byte 5 4 3 3 1 No. of States Section 2 Instruction Descriptions BIOR (Bit Invert inclusive OR) Bit Logical OR Rev. 4.00 Feb 24, 2006 page 69 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.12 BIST BIST (Bit Invert STore) Bit Store Condition Code Operation C (<bit No.> of <EAd>) I UI H U N Z V C -- -- -- -- -- -- -- -- H: N: Z: V: C: Assembly-Language Format BIST #xx:3, <EAd> Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Operand Size Byte Description This instruction stores the inverse of the carry flag in a specified bit location in the destination operand. The bit number is specified by 3-bit immediate data. Other bits in the destination operand remain unchanged. Specified by #xx:3 Bit No. 7 0 <EAd> C Available Registers Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Rev. 4.00 Feb 24, 2006 page 70 of 322 REJ09B0139-0400 Invert #xx:3, Rd BIST BIST BIST BIST BIST Register direct Register indirect Absolute address Absolute address Absolute address 6 6 7 7 6 A A F D 7 1st byte 3 1 abs 0 erd 1 IMM 8 8 0 rd 2nd byte 6 6 7 7 3rd byte abs 1 IMM 1 IMM 0 0 abs 6 1 IMM 0 6th byte For the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. Notes 7 5th byte Instruction Format 4th byte Note: * The addressing mode is the addressing mode of the destination operand <EAd>. #xx:3, @aa:32 #xx:3, @aa:16 #xx:3, @aa:8 #xx:3, @ERd Operands Addressing Mnemonic Mode* Operand Format and Number of States Required for Execution 6 7 7th byte 1 IMM 0 8th byte 6 5 4 4 1 No. of States Section 2 Instruction Descriptions BIST (Bit Invert STore) Bit Store Rev. 4.00 Feb 24, 2006 page 71 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.13 BIXOR BIXOR (Bit Invert eXclusive OR) Bit Exclusive Logical OR Condition Code Operation C [ (<bit No.> of <EAd>)] C H: N: Z: V: C: Assembly-Language Format BIXOR #xx:3, <EAd> V C -- -- -- -- -- -- -- I UI H U N Z Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Stores the result of the operation. Operand Size Byte Description This instruction exclusively ORs the inverse of a specified bit in the destination operand with the carry flag and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. The destination operand contents remain unchanged. Specified by #xx:3 Bit No. 7 0 <EAd> Invert C Available Registers Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Rev. 4.00 Feb 24, 2006 page 72 of 322 REJ09B0139-0400 C #xx:3, Rd BIXOR BIXOR BIXOR BIXOR BIXOR Register direct Register indirect Absolute address Absolute address Absolute address 6 6 7 7 7 A A E C 5 1st byte 3 1 abs 0 erd 1 IMM 0 0 0 rd 2nd byte 7 7 5 5 3rd byte abs 1 IMM 1 IMM 0 0 abs 7 1 IMM 0 6th byte For the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. Notes 5 5th byte Instruction Format 4th byte Note: * The addressing mode is the addressing mode of the destination operand <EAd>. #xx:3, @aa:32 #xx:3, @aa:16 #xx:3, @aa:8 #xx:3, @ERd Operands Addressing Mnemonic Mode* Operand Format and Number of States Required for Execution 7 5 7th byte 1 IMM 0 8th byte 5 4 3 3 1 No. of States Section 2 Instruction Descriptions BIXOR (Bit Invert eXclusive OR) Bit Exclusive Logical OR Rev. 4.00 Feb 24, 2006 page 73 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.14 BLD BLD (Bit LoaD) Bit Load Condition Code Operation (<Bit No.> of <EAd>) C H: N: Z: V: C: Assembly-Language Format BLD #xx:3, <EAd> V C -- -- -- -- -- -- -- I UI H U N Z Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Loaded from the specified bit. Operand Size Byte Description This instruction loads a specified bit from the destination operand into the carry flag. The bit number is specified by 3-bit immediate data. The destination operand contents remain unchanged. Specified by #xx:3 Bit No. 7 0 <EAd> C Available Registers Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Rev. 4.00 Feb 24, 2006 page 74 of 322 REJ09B0139-0400 #xx:3, Rd BLD BLD BLD BLD BLD Register direct Register indirect Absolute address Absolute address Absolute address 6 6 7 7 7 A A E C 7 1st byte 3 1 abs 0 erd 0 IMM 0 0 0 rd 2nd byte 7 7 7 7 3rd byte abs 0 IMM 0 IMM 0 0 abs 7 0 IMM 0 6th byte For the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. Notes 7 5th byte Instruction Format 4th byte Note: * The addressing mode is the addressing mode of the destination operand <EAd>. #xx:3, @aa:32 #xx:3, @aa:16 #xx:3, @aa:8 #xx:3, @ERd Operands Addressing Mnemonic Mode* Operand Format and Number of States Required for Execution 7 7 7th byte 0 IMM 0 8th byte 5 4 3 3 1 No. of States Section 2 Instruction Descriptions BLD (Bit LoaD) Bit Load Rev. 4.00 Feb 24, 2006 page 75 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.15 BNOT BNOT (Bit NOT) Bit NOT Condition Code Operation (<bit No.> of <EAd>) (bit No. of I <EAd>) UI H U N Z V C -- -- -- -- -- -- -- -- H: N: Z: V: C: Assembly-Language Format BNOT #xx:3, <EAd> BNOT Rn, <EAd> Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Operand Size Byte Description This instruction inverts a specified bit in the destination operand. The bit number is specified by 3bit immediate data or by the lower 3 bits of an 8-bit register Rn. The specified bit is not tested. The condition code remains unchanged. Specified by #xx:3 or Rn Bit No. 7 0 <EAd> Invert Available Registers Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Rn: R0L to R7L, R0H to R7H Rev. 4.00 Feb 24, 2006 page 76 of 322 REJ09B0139-0400 #xx:3, Rd BNOT BNOT BNOT BNOT BNOT BNOT BNOT BNOT BNOT BNOT Register direct Register indirect Absolute address Absolute address Absolute address Register direct Register indirect Absolute address Absolute address Absolute address 6 6 7 7 6 6 6 7 7 7 A A F D 1 A A F D 1 1st byte 3 1 abs 0 erd rn 3 1 abs 0 erd 0 IMM 8 8 0 rd 8 8 0 rd 2nd byte 6 6 7 7 1 1 1 1 3rd byte abs abs rn rn 0 IMM 0 IMM 0 0 0 0 abs abs 6 7 rn 0 IMM 0 0 6th byte For the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. Notes 1 1 5th byte Instruction Format 4th byte Note: * The addressing mode is the addressing mode of the destination operand <EAd>. Rn, @aa:32 Rn, @aa:16 Rn, @aa:8 Rn, @ERd Rn, Rd #xx:3, @aa:32 #xx:3, @aa:16 #xx:3, @aa:8 #xx:3, @ERd Operands Addressing Mnemonic Mode* Operand Format and Number of States Required for Execution 6 7 1 1 7th byte rn 0 IMM 0 0 8th byte 6 5 4 4 1 6 5 4 4 1 No. of States Section 2 Instruction Descriptions BNOT (Bit NOT) Bit NOT Rev. 4.00 Feb 24, 2006 page 77 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.16 BOR BOR (Bit inclusive OR) Bit Logical OR Condition Code Operation C (<bit No.> of <EAd>) C H: N: Z: V: C: Assembly-Language Format BOR #xx:3, <EAd> V C -- -- -- -- -- -- -- I UI H U N Z Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Stores the result of the operation. Operand Size Byte Description This instruction ORs a specified bit in the destination operand with the carry flag and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. The destination operand contents remain unchanged. Specified by #xx:3 Bit No. 7 0 <EAd> C Available Registers Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Rev. 4.00 Feb 24, 2006 page 78 of 322 REJ09B0139-0400 C #xx:3, Rd BOR BOR BOR BOR BOR Register direct Register indirect Absolute address Absolute address Absolute address 6 6 7 7 7 A A E C 4 1st byte 3 1 abs 0 erd 0 IMM 0 0 0 rd 2nd byte 7 7 4 4 3rd byte abs 0 IMM 0 IMM 0 0 abs 7 0 IMM 0 6th byte For the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. Notes 4 5th byte Instruction Format 4th byte Note: * The addressing mode is the addressing mode of the destination operand <EAd>. #xx:3, @aa:32 #xx:3, @aa:16 #xx:3, @aa:8 #xx:3, @ERd Operands Addressing Mnemonic Mode* Operand Format and Number of States Required for Execution 7 4 7th byte 0 IMM 0 8th byte 5 4 3 3 1 No. of States Section 2 Instruction Descriptions BOR (Bit inclusive OR) Bit Logical OR Rev. 4.00 Feb 24, 2006 page 79 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.17 BSET BSET (Bit SET) Bit Set Condition Code Operation 1 (<bit No.> of <EAd>) I UI H U N Z V C -- -- -- -- -- -- -- -- H: N: Z: V: C: Assembly-Language Format BSET #xx:3, <EAd> BSET Rn, <EAd> Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Operand Size Byte Description This instruction sets a specified bit in the destination operand to 1. The bit number can be specified by 3-bit immediate data, or by the lower three bits of an 8-bit register Rn. The specified bit is not tested. The condition code flags are not altered. Specified by #xx:3 or Rn Bit No. 7 0 <EAd> 1 Available Registers Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Rn: R0L to R7L, R0H to R7H Rev. 4.00 Feb 24, 2006 page 80 of 322 REJ09B0139-0400 #xx:3, Rd BSET BSET BSET BSET BSET BSET BSET BSET BSET BSET Register direct Register indirect Absolute address Absolute address Absolute address Register direct Register indirect Absolute address Absolute address Absolute address 6 6 7 7 6 6 6 7 7 7 A A F D 0 A A F D 0 1st byte 3 1 abs 0 erd rn 3 1 abs 0 erd 0 IMM 8 8 0 rd 8 8 0 rd 2nd byte 6 6 7 7 0 0 0 0 3rd byte abs abs rn rn 0 IMM 0 IMM 0 0 0 0 abs abs 6 7 rn 0 IMM 0 0 6th byte For the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. Notes 0 0 5th byte Instruction Format 4th byte Note: * The addressing mode is the addressing mode of the destination operand <EAd>. Rn, @aa:32 Rn, @aa:16 Rn, @aa:8 Rn, @ERd Rn, Rd #xx:3, @aa:32 #xx:3, @aa:16 #xx:3, @aa:8 #xx:3, @ERd Operands Addressing Mnemonic Mode* Operand Format and Number of States Required for Execution 6 7 0 0 7th byte rn 0 IMM 0 0 8th byte 6 5 4 4 1 6 5 4 4 1 No. of States Section 2 Instruction Descriptions BSET (Bit SET) Bit Set Rev. 4.00 Feb 24, 2006 page 81 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.18 BSR BSR (Branch to SubRoutine) Branch to Subroutine Condition Code Operation PC @-SP PC + disp PC I UI H U N Z V C -- -- -- -- -- -- -- -- H: N: Z: V: C: Assembly-Language Format BSR disp Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Operand Size -- Description This instruction branches to a subroutine at a specified address. It pushes the program counter (PC) value onto the stack as a restart address, then adds a specified displacement to the PC value and branches to the resulting address. The PC value pushed onto the stack is the address of the instruction following the BSR instruction. The displacement is a signed 8-bit or 16-bit value, so the possible branching range is -126 to +128 bytes or -32766 to +32768 bytes from the address of the BSR instruction. Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Program-counter relative BSR Operands Instruction Format No. of States 1st byte 2nd byte 3rd byte 4th byte Normal Advanced d:8 5 5 d:16 5 C Rev. 4.00 Feb 24, 2006 page 82 of 322 REJ09B0139-0400 disp 0 0 disp 3 4 4 5 Section 2 Instruction Descriptions BSR (Branch to SubRoutine) Branch to Subroutine Notes The stack structure differs between normal mode and advanced mode. In normal mode only the lower 16 bits of the program counter are pushed onto the stack. Ensure that the branch destination address is even. Reserved PC PC 23 16 15 87 0 23 Normal mode 16 15 87 0 Advanced mode Rev. 4.00 Feb 24, 2006 page 83 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.19 BST BST (Bit STore) Bit Store Condition Code Operation C (<bit No.> of <EAd>) I UI H U N Z V C -- -- -- -- -- -- -- -- H: N: Z: V: C: Assembly-Language Format BST #xx:3, <EAd> Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Operand Size Byte Description This instruction stores the carry flag in a specified bit location in the destination operand. The bit number is specified by 3-bit immediate data. Specified by #xx:3 Bit No. 7 <EAd> C Available Registers Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Rev. 4.00 Feb 24, 2006 page 84 of 322 REJ09B0139-0400 0 #xx:3, Rd BST BST BST BST BST Register direct Register indirect Absolute address Absolute address Absolute address 6 6 7 7 6 A A F D 7 1st byte 3 1 abs 0 erd 0 IMM 8 8 0 rd 2nd byte 6 6 7 7 3rd byte abs 0 IMM 0 IMM 0 0 abs 6 0 IMM 0 6th byte For the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. Notes 7 5th byte Instruction Format 4th byte Note: * The addressing mode is the addressing mode of the destination operand <EAd>. #xx:3, @aa:32 #xx:3, @aa:16 #xx:3, @aa:8 #xx:3, @ERd Operands Addressing Mnemonic Mode* Operand Format and Number of States Required for Execution 6 7 7th byte 0 IMM 0 8th byte 6 5 4 4 1 No. of States Section 2 Instruction Descriptions BST (Bit STore) Bit Store Rev. 4.00 Feb 24, 2006 page 85 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.20 BTST BTST (Bit TeST) Bit Test Operation Condition Code (<Bit No.> of <EAd>) Z N Z I -- -- -- -- -- UI H U V C -- -- H: Previous value remains unchanged. N: Previous value remains unchanged. Z: Set to 1 if the specified bit is zero; otherwise cleared to 0. V: Previous value remains unchanged. C: Previous value remains unchanged. Assembly-Language Format BTST #xx:3, <EAd> BTST Rn, <EAd> Operand Size Byte Description This instruction tests a specified bit in the destination operand and sets or clears the zero flag according to the result. The bit number can be specified by 3-bit immediate data, or by the lower three bits of an 8-bit register Rn. The destination operand contents remain unchanged. Specified by #xx:3 or Rn Bit No. 7 0 <EAd> Test Available Registers Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Rn: R0L to R7L, R0H to R7H Rev. 4.00 Feb 24, 2006 page 86 of 322 REJ09B0139-0400 #xx:3, Rd BTST BTST BTST BTST BTST BTST BTST BTST BTST BTST Register direct Register indirect Absolute address Absolute address Absolute address Register direct Register indirect Absolute address Absolute address Absolute address 6 6 7 7 6 6 6 7 7 7 A A E C 3 A A E C 3 1st byte 3 1 abs 0 erd rn 3 1 abs 0 erd 0 IMM 0 0 0 rd 0 0 0 rd 2nd byte 6 6 7 7 3 3 3 3 3rd byte abs abs rn rn 0 IMM 0 IMM 0 0 0 0 abs abs 6 7 rn 0 IMM 0 0 6th byte For the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. Notes 3 3 5th byte Instruction Format 4th byte Note: * The addressing mode is the addressing mode of the destination operand <EAd>. Rn, @aa:32 Rn, @aa:16 Rn, @aa:8 Rn, @ERd Rn, Rd #xx:3, @aa:32 #xx:3, @aa:16 #xx:3, @aa:8 #xx:3, @ERd Operands Addressing Mnemonic Mode* Operand Format and Number of States Required for Execution 6 7 3 3 7th byte rn 0 IMM 0 0 8th byte 5 4 3 3 1 5 4 3 3 1 No. of States Section 2 Instruction Descriptions BTST (Bit TeST) Bit Test Rev. 4.00 Feb 24, 2006 page 87 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.21 BXOR BXOR (Bit eXclusive OR) Bit Exclusive Logical OR Condition Code Operation C (<bit No.> of <EAd>) C H: N: Z: V: C: Assembly-Language Format BXOR #xx:3, <EAd> V C -- -- -- -- -- -- -- I UI H U N Z Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Stores the result of the operation. Operand Size Byte Description This instruction exclusively ORs a specified bit in the destination operand with the carry flag and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. The destination operand contents remain unchanged. Specified by #xx:3 Bit No. 7 0 <EAd> C Available Registers Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Rev. 4.00 Feb 24, 2006 page 88 of 322 REJ09B0139-0400 C #xx:3, Rd BXOR BXOR BXOR BXOR BXOR Register direct Register indirect Absolute address Absolute address Absolute address 6 6 7 7 7 A A E C 5 1st byte 3 1 abs 0 erd 0 IMM 0 0 0 rd 2nd byte 7 7 5 5 3rd byte abs 0 IMM 0 IMM 0 0 abs 7 0 IMM 0 6th byte For the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. Notes 5 5th byte Instruction Format 4th byte Note: * The addressing mode is the addressing mode of the destination operand <EAd>. #xx:3, @aa:32 #xx:3, @aa:16 #xx:3, @aa:8 #xx:3, @ERd Operands Addressing Mnemonic Mode* Operand Format and Number of States Required for Execution 7 5 7th byte 0 IMM 0 8th byte 5 4 3 3 1 No. of States Section 2 Instruction Descriptions BXOR (Bit eXclusive OR) Bit Exclusive Logical OR Rev. 4.00 Feb 24, 2006 page 89 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.22 CLRMAC CLRMAC (CLeaR MAC register) Initialize Multiply-Accumulate Register Condition Code Operation 0 MACH, MACL I UI H U N Z V C -- -- -- -- -- -- -- -- H: N: Z: V: C: Assembly-Language Format CLRMAC Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Operand Size -- Description This instruction simultaneously clears registers MACH and MACL. It is supported only by the H8S/2600 CPU. Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Operands -- CLRMAC -- Instruction Format 1st byte 2nd byte 0 A 1 3rd byte 4th byte 0 No. of States 2* Note: * A maximum of three additional states are required for execution of this instruction within three states after execution of a MAC instruction. For example, if there is a one-state instruction (such as NOP) between the MAC instruction and this instruction, this instruction will be two states longer. The number of states may differ depending on the product. For details, refer to the relevant microcontroller hardware manual of the product in question. Notes Execution of this instruction also clears the overflow flag in the multiplier to 0. Rev. 4.00 Feb 24, 2006 page 90 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.23 (1) CMP (B) CMP (CoMPare) Compare H U N -- -- -- Z V C UI I Rd - (EAs), set/clear CCR Condition Code Operation H: Set to 1 if there is a borrow at bit 3; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a borrow at bit 7; otherwise cleared to 0. Assembly-Language Format CMP.B <EAs>, Rd Operand Size Byte Description This instruction subtracts the source operand from the contents of an 8-bit register Rd (destination operand) and sets or clears the condition code bits according to the result. The contents of the 8-bit register Rd remain unchanged. Available Registers Rd: R0L to R7L, R0H to R7H Rs: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Instruction Format Mnemonic Operands Immediate CMP.B #xx:8, Rd A rd Register direct CMP.B Rs, Rd 1 C 1st byte 2nd byte IMM rs 3rd byte 4th byte No. of States 1 rd 1 Notes Rev. 4.00 Feb 24, 2006 page 91 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.23 (2) CMP (W) CMP (CoMPare) Compare H U N -- -- -- Z V C UI I Rd - (EAs), set/clear CCR Condition Code Operation H: Set to 1 if there is a borrow at bit 11; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a borrow at bit 15; otherwise cleared to 0. Assembly-Language Format CMP.W <EAs>, Rd Operand Size Word Description This instruction subtracts the source operand from the contents of a 16-bit register Rd (destination operand) and sets or clears the condition code bits according to the result. The contents of the 16bit register Rd remain unchanged. Available Registers Rd: R0 to R7, E0 to E7 Rs: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Instruction Format Mnemonic Operands Immediate CMP.W #xx:16, Rd 7 9 2 rd Register direct CMP.W Rs, Rd 1 D rs rd Notes Rev. 4.00 Feb 24, 2006 page 92 of 322 REJ09B0139-0400 1st byte 2nd byte 3rd byte 4th byte IMM No. of States 2 1 Section 2 Instruction Descriptions 2.2.23 (3) CMP (L) CMP (CoMPare) Compare U -- -- -- N Z V C H UI I ERd - (EAs), set/clear CCR Condition Code Operation H: Set to 1 if there is a borrow at bit 27; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a borrow at bit 31; otherwise cleared to 0. Assembly-Language Format CMP.L <EAs>, ERd Operand Size Longword Description This instruction subtracts the source operand from the contents of a 32-bit register ERd (destination operand) and sets or clears the condition code bits according to the result. The contents of the 32-bit register ERd remain unchanged. Available Registers ERd: ER0 to ER7 ERs: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Instruction Format Mnemonic Operands 1st byte Immediate CMP.L #xx:32, ERd 7 A Register direct CMP.L ERs, ERd 1 F 2nd byte 2 0 erd 1 ers 0 erd 3rd byte 4th byte 5th byte IMM 6th byte No. of States 3 1 Notes Rev. 4.00 Feb 24, 2006 page 93 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions DAA DAA (Decimal Adjust Add) Decimal Adjust Condition Code Operation Rd (decimal adjust) Rd UI H U N Z V -- -- * -- I * C 2.2.24 H: Undetermined (no guaranteed value). N: Set to 1 if the adjusted result is negative; otherwise cleared to 0. Z: Set to 1 if the adjusted result is zero; otherwise cleared to 0. V: Undetermined (no guaranteed value). C: Set to 1 if there is a carry at bit 7; otherwise left unchanged. Assembly-Language Format DAA Rd Operand Size Byte Description Given that the result of an addition operation performed by an ADD.B or ADDX instruction on 4-bit BCD data is contained in an 8-bit register Rd and the carry and half-carry flags, the DAA instruction adjusts the contents of the 8-bit register Rd (destination operand) by adding H'00, H'06, H'60, or H'66 according to the table below. C Flag before Adjustment Upper 4 Bits before Adjustment H Flag before Adjustment 0 0 to 9 0 0 to 9 00 0 0 0 to 8 0 A to F 06 0 0 0 to 9 1 0 to 3 06 0 0 A to F 0 0 to 9 60 1 0 9 to F 0 A to F 66 1 0 A to F 1 0 to 3 66 1 1 0 to 2 0 0 to 9 60 1 1 0 to 2 0 A to F 66 1 1 0 to 3 1 0 to 3 66 1 Rev. 4.00 Feb 24, 2006 page 94 of 322 REJ09B0139-0400 Lower 4 Bits Value before Added Adjustment (Hexadecimal) C Flag after Adjustment Section 2 Instruction Descriptions DAA (Decimal Adjust Add) Decimal Adjust Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands DAA Rd Instruction Format 1st byte 2nd byte 0 0 F 3rd byte 4th byte rd No. of States 1 Notes Valid results (8-bit register Rd contents and C, V, Z, N, and H flags) are not assured if this instruction is executed under conditions other than those described above. Rev. 4.00 Feb 24, 2006 page 95 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.25 DAS DAS (Decimal Adjust Subtract) Decimal Adjust Condition Code Operation Rd (decimal adjust) Rd UI H U N Z V C -- -- * -- I * 0 H: Undetermined (no guaranteed value). N: Set to 1 if the adjusted result is negative; otherwise cleared to 0. Z: Set to 1 if the adjusted result is zero; otherwise cleared to 0. V: Undetermined (no guaranteed value). C: Previous value remains unchanged. Assembly-Language Format DAS Rd Operand Size Byte Description Given that the result of a subtraction operation performed by a SUB.B, SUBX.B, or NEG.B instruction on 4-bit BCD data is contained in an 8-bit register Rd and the carry and half-carry flags, the DAS instruction adjusts the contents of the 8-bit register Rd (destination operand) by adding H'00, H'FA, H'A0, or H'9A according to the table below. C Flag before Adjustment Upper 4 Bits before Adjustment H Flag before Adjustment 0 0 to 9 0 0 to 9 00 0 0 0 to 8 1 6 to F FA 0 1 7 to F 0 0 to 9 A0 1 1 6 to F 1 6 to F 9A 1 Available Registers Rd: R0L to R7L, R0H to R7H Rev. 4.00 Feb 24, 2006 page 96 of 322 REJ09B0139-0400 Lower 4 Bits Value before Added Adjustment (Hexadecimal) C Flag after Adjustment Section 2 Instruction Descriptions DAS (Decimal Adjust Subtract) Decimal Adjust Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands DAS Rd Instruction Format 1st byte 2nd byte 1 0 F 3rd byte 4th byte rd No. of States 1 Notes Valid results (8-bit register Rd contents and C, V, Z, N, and H flags) are not assured if this instruction is executed under conditions other than those described above. Rev. 4.00 Feb 24, 2006 page 97 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.26 (1) DEC (B) DEC (DECrement) Decrement Condition Code Operation Rd - 1 Rd U N Z V C -- -- -- -- I UI H -- H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Previous value remains unchanged. Assembly-Language Format DEC.B Rd Operand Size Byte Description This instruction decrements an 8-bit register Rd (destination operand) and stores the result in the 8-bit register Rd. Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands DEC.B Rd Instruction Format 1st byte 2nd byte 1 0 A Notes An overflow is caused by the operation H'80 - 1 H'7F. Rev. 4.00 Feb 24, 2006 page 98 of 322 REJ09B0139-0400 rd 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions 2.2.26 (2) DEC (W) DEC (DECrement) Decrement Condition Code Operation Rd - 1 Rd Rd - 2 Rd U N Z V C -- -- -- -- I UI H -- H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Previous value remains unchanged. Assembly-Language Format DEC.W #1, Rd DEC.W #2, Rd Operand Size Word Description This instruction subtracts the immediate value 1 or 2 from the contents of a 16-bit register Rd (destination operand) and stores the result in the 16-bit register Rd. Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Instruction Format No. of States Mnemonic Operands Register direct DEC.W #1, Rd 1 B 5 rd 1 Register direct DEC.W #2, Rd 1 B D rd 1 1st byte 2nd byte 3rd byte 4th byte Notes An overflow is caused by the operations H'8000 - 1 H'7FFF, H'8000 - 2 H'7FFE, and H'8001 - 2 H'7FFF. Rev. 4.00 Feb 24, 2006 page 99 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.26 (3) DEC (L) DEC (DECrement) Decrement Condition Code Operation ERd - 1 ERd ERd - 2 ERd U N Z V C -- -- -- -- I UI H -- H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Previous value remains unchanged. Assembly-Language Format DEC.L #1, ERd DEC.L #2, ERd Operand Size Longword Description This instruction subtracts the immediate value 1 or 2 from the contents of a 32-bit register ERd (destination operand) and stores the result in the 32-bit register ERd. Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Instruction Format No. of States Mnemonic Operands Register direct DEC.L #1, ERd 1 B 7 0 erd 1 Register direct DEC.L #2, ERd 1 B F 0 erd 1 1st byte 2nd byte 3rd byte 4th byte Notes An overflow is caused by the operations H'80000000 - 1 H'7FFFFFFF, H'80000000 - 2 H'7FFFFFFE, and H'80000001 - 2 H'7FFFFFFF. Rev. 4.00 Feb 24, 2006 page 100 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.27 (1) DIVXS (B) DIVXS (DIVide eXtend as Signed) Divide Signed Condition Code Operation Rd / Rs Rd U N Z -- -- -- -- I UI H V C -- -- H: Previous value remains unchanged. N: Set to 1 if the quotient is negative; otherwise cleared to 0. Z: Set to 1 if the divisor is zero; otherwise cleared to 0. V: Previous value remains unchanged. C: Previous value remains unchanged. Assembly-Language Format DIVXS.B Rs, Rd Operand Size Byte Description This instruction divides the contents of a 16-bit register Rd (destination operand) by the contents of an 8-bit register Rs (source operand) and stores the result in the 16-bit register Rd. The division is signed. The operation performed is 16 bits / 8 bits 8-bit quotient and 8-bit remainder. The quotient is placed in the lower 8 bits of Rd. The remainder is placed in the upper 8 bits of Rd. The sign of the remainder matches the sign of the dividend. Rd Dividend 16 bits Rs / Divisor 8 bits Rd Remainder Quotient 8 bits 8 bits Valid results are not assured if division by zero is attempted or an overflow occurs. Available Registers Rd: R0 to R7, E0 to E7 Rs: R0L to R7L, R0H to R7H Rev. 4.00 Feb 24, 2006 page 101 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions DIVXS (DIVide eXtend as Signed) Divide Signed Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands DIVXS.B Rs, Rd Instruction Format 1st byte 2nd byte 3rd byte 4th byte 0 D 5 rs 1 0 1 rd No. of States 13 Notes The N flag is set to 1 if the dividend and divisor have different signs, and cleared to 0 if they have the same sign. The N flag may therefore be set to 1 when the quotient is zero. Rev. 4.00 Feb 24, 2006 page 102 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.27 (2) DIVXS (W) DIVXS (DIVide eXtend as Signed) Divide Signed Condition Code Operation ERd / Rs ERd U N Z -- -- -- -- I UI H V C -- -- H: Previous value remains unchanged. N: Set to 1 if the quotient is negative; otherwise cleared to 0. Z: Set to 1 if the divisor is zero; otherwise cleared to 0. V: Previous value remains unchanged. C: Previous value remains unchanged. Assembly-Language Format DIVXS.W Rs, ERd Operand Size Word Description This instruction divides the contents of a 32-bit register ERd (destination operand) by the contents of a 16-bit register Rs (source operand) and stores the result in the 32-bit register ERd. The division is signed. The operation performed is 32 bits / 16 bits 16-bit quotient and 16-bit remainder. The quotient is placed in the lower 16 bits (Rd) of the 32-bit register ERd. The remainder is placed in the upper 16 bits (Ed). The sign of the remainder matches the sign of the dividend. ERd Dividend 32 bits Rs / Divisor 16 bits ERd Remainder Quotient 16 bits 16 bits Valid results are not assured if division by zero is attempted or an overflow occurs. Available Registers ERd: ER0 to ER7 Rs: R0 to R7, E0 to E7 Rev. 4.00 Feb 24, 2006 page 103 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions DIVXS (DIVide eXtend as Signed) Divide Signed Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands DIVXS.W Rs, ERd Instruction Format 1st byte 2nd byte 3rd byte 4th byte 0 D 5 rs 1 0 3 0 erd No. of States 21 Notes The N flag is set to 1 if the dividend and divisor have different signs, and cleared to 0 if they have the same sign. The N flag may therefore be set to 1 when the quotient is zero. Rev. 4.00 Feb 24, 2006 page 104 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.28 (1) DIVXU (B) DIVXU (DIVide eXtend as Unsigned) Divide Condition Code Operation Rd / Rs Rd U N Z -- -- -- -- I UI H V C -- -- H: Previous value remains unchanged. N: Set to 1 if the divisor is negative; otherwise cleared to 0. Z: Set to 1 if the divisor is zero; otherwise cleared to 0. V: Previous value remains unchanged. C: Previous value remains unchanged. Assembly-Language Format DIVXU.B Rs, Rd Operand Size Byte Description This instruction divides the contents of a 16-bit register Rd (destination operand) by the contents of an 8-bit register Rs (source operand) and stores the result in the 16-bit register Rd. The division is unsigned. The operation performed is 16 bits / 8 bits 8-bit quotient and 8-bit remainder. The quotient is placed in the lower 8 bits of Rd. The remainder is placed in the upper 8 bits of Rd. Rd Dividend 16 bits Rs / Divisor 8 bits Rd Remainder Quotient 8 bits 8 bits Valid results are not assured if division by zero is attempted or an overflow occurs. Available Registers Rd: R0 to R7, E0 to E7 Rs: R0L to R7L, R0H to R7H Rev. 4.00 Feb 24, 2006 page 105 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions DIVXU (DIVide eXtend as Unsigned) Divide Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands DIVXU.B Rs, Rd Notes Rev. 4.00 Feb 24, 2006 page 106 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 5 rs 1 rd 3rd byte 4th byte No. of States 12 Section 2 Instruction Descriptions 2.2.28 (2) DIVXU (W) DIVXU (DIVide eXtend as Unsigned) Divide Condition Code Operation ERd / Rs ERd U N Z -- -- -- -- I UI H V C -- -- H: Previous value remains unchanged. N: Set to 1 if the divisor is negative; otherwise cleared to 0. Z: Set to 1 if the divisor is zero; otherwise cleared to 0. V: Previous value remains unchanged. C: Previous value remains unchanged. Assembly-Language Format DIVXU.W Rs, ERd Operand Size Word Description This instruction divides the contents of a 32-bit register ERd (destination operand) by the contents of a 16-bit register Rs (source register) and stores the result in the 32-bit register ERd. The division is unsigned. The operation performed is 32 bits / 16 bits 16-bit quotient and 16-bit remainder. The quotient is placed in the lower 16 bits (Rd) of the 32-bit register ERd. The remainder is placed in the upper 16 bits of (Ed). ERd Dividend 32 bits Rs / Divisor 16 bits ERd Remainder Quotient 16 bits 16 bits Valid results are not assured if division by zero is attempted or an overflow occurs. Available Registers ERd: ER0 to ER7 Rs: R0 to R7, E0 to E7 Rev. 4.00 Feb 24, 2006 page 107 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions DIVXU (DIVide eXtend as Unsigned) Divide Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands DIVXU.W Rs, ERd Notes Rev. 4.00 Feb 24, 2006 page 108 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 5 rs 3 0 erd 3rd byte 4th byte No. of States 20 Section 2 Instruction Descriptions 2.2.29 (1) EEPMOV (B) EEPMOV (MOVe data to EEPROM) Block Data Transfer Condition Code Operation if R4L 0 then repeat @ER5+ @ER6+ R4L - 1 R4L until R4L = 0 else next; I UI H U N Z V C -- -- -- -- -- -- -- -- H: N: Z: V: C: Assembly-Language Format EEPMOV.B Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Operand Size -- Description This instruction performs a block data transfer. It moves data from the memory location specified in ER5 to the memory location specified in ER6, increments ER5 and ER6, decrements R4L, and repeats these operations until R4L reaches zero. Execution then proceeds to the next instruction. The data transfer is performed a byte at a time, with R4L indicating the number of bytes to be transferred. The byte symbol in the assembly-language format designates the size of R4L (and limits the maximum number of bytes that can be transferred to 255). No interrupts are detected while the block transfer is in progress. When the EEPMOV.B instruction ends, R4L contains 0 (zero), and ER5 and ER6 contain the last transfer address + 1. Operand Format and Number of States Required for Execution Addressing Mode Mnemonic -- EEPMOV.B Operands Instruction Format 1st byte 2nd byte 3rd byte 4th byte No. of States 7 5 5 8 4 + 2n* B C 9 F Note: * n is the initial value of R4L. Although n bytes of data are transferred, 2(n + 1) data accesses are performed, requiring 2(n + 1) states. (n = 0, 1, 2, ..., 255). Notes This instruction first reads the memory locations indicated by ER5 and ER6, then carries out the block data transfer. Rev. 4.00 Feb 24, 2006 page 109 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.29 (2) EEPMOV (W) EEPMOV (MOVe data to EEPROM) Operation if R4 0 then repeat @ER5+ @ER6+ R4 - 1 R4 until R4 = 0 else next; Assembly-Language Format EEPMOV.W Block Data Transfer Condition Code I UI H U N Z V C -- -- -- -- -- -- -- -- H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Operand Size -- Description This instruction performs a block data transfer. It moves data from the memory location specified in ER5 to the memory location specified in ER6, increments ER5 and ER6, decrements R4, and repeats these operations until R4 reaches zero. Execution then proceeds to the next instruction. The data transfer is performed a byte at a time, with R4 indicating the number of bytes to be transferred. The word symbol in the assembly-language format designates the size of R4 (allowing a maximum 65535 bytes to be transferred). All interrupts are detected while the block transfer is in progress. If no interrupt occurs while the EEPMOV.W instruction is executing, when the EEPMOV.W instruction ends, R4 contains 0 (zero), and ER5 and ER6 contain the last transfer address + 1. If an interrupt occurs, interrupt exception handling begins after the current byte has been transferred. R4 indicates the number of bytes remaining to be transferred. ER5 and ER6 indicate the next transfer addresses. The program counter value pushed onto the stack in interrupt exception handling is the address of the next instruction after the EEPMOV.W instruction. See the note on EEPMOV.W instruction and interrupt. Rev. 4.00 Feb 24, 2006 page 110 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions EEPMOV (MOVe data to EEPROM) Block Data Transfer Operand Format and Number of States Required for Execution Addressing Mode Mnemonic -- EEPMOV.W Operands Instruction Format 1st byte 2nd byte 3rd byte 4th byte No. of States 7 D 5 8 4 + 2n* B 4 9 F Note: * n is the initial value of R4. Although n bytes of data are transferred, 2(n + 1) data accesses are performed, requiring 2(n + 1) states. (n = 0, 1, 2, ..., 65535). Notes This instruction first reads memory at the addresses indicated by ER5 and ER6, then carries out the block data transfer. EEPMOV.W Instruction and Interrupt If an interrupt request occurs while the EEPMOV.W instruction is being executed, interrupt exception handling is carried out after the current byte has been transferred. Register contents are then as follows: ER5: address of the next byte to be transferred ER6: destination address of the next byte R4: number of bytes remaining to be transferred The program counter value pushed on the stack in interrupt exception handling is the address of the next instruction after the EEPMOV.W instruction. Programs should be coded as follows to allow for interrupts during execution of the EEPMOV.W instruction. Example: L1: EEPMOV.W MOV.W R4,R4 BNE L1 Interrupt requests other than NMI are not accepted if they are masked in the CPU. During execution of the EEPMOV.B instruction no interrupts are accepted, including NMI. Rev. 4.00 Feb 24, 2006 page 111 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.30 (1) EXTS (W) EXTS (EXTend as Signed) Sign Extension Condition Code Operation (<Bit 7> of Rd) (<bits 15 to 8> of Rd) Assembly-Language Format U N Z V C -- -- -- -- I UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. EXTS.W Rd Operand Size Word Description This instruction copies the sign of the lower 8 bits in a 16-bit register Rd in the upward direction (copies Rd bit 7 to bits 15 to 8) to extend the data to signed word data. Rd 7 Bit 15 0 Rd 7 Bit 15 Don't care 0 Sign extension 8 bits 8 bits 8 bits 8 bits Sign bit Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands EXTS.W Rd Notes Rev. 4.00 Feb 24, 2006 page 112 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 1 D 7 rd 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions 2.2.30 (2) EXTS (L) EXTS (EXTend as Signed) Sign Extension Condition Code Operation (<Bit 15> of ERd) (<bits 31 to 16> of ERd) Assembly-Language Format U N Z V C -- -- -- -- I UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. EXTS.L ERd Operand Size Longword Description This instruction copies the sign of the lower 16 bits in a 32-bit register ERd in the upward direction (copies ERd bit 15 to bits 31 to 16) to extend the data to signed longword data. ERd 15 Bit 31 0 ERd 15 Bit 31 Don't care 0 Sign extension 16 bits 16 bits 16 bits 16 bits Sign bit Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands EXTS.L ERd Instruction Format 1st byte 2nd byte 1 F 7 0 erd 3rd byte 4th byte No. of States 1 Notes Rev. 4.00 Feb 24, 2006 page 113 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.31 (1) EXTU (W) EXTU (EXTend as Unsigned) Zero Extension Condition Code Operation 0 (<bits 15 to 8> of Rd) Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H 0 -- H: Previous value remains unchanged. N: Always cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. EXTU.W Rd Operand Size Word Description This instruction extends the lower 8 bits in a 16-bit register Rd to word data by padding with zeros. That is, it clears the upper 8 bits of Rd (bits 15 to 8) to 0. Rd 7 Bit 15 0 Don't care 8 bits Rd 7 Bit 15 0 Zero extension 8 bits 8 bits 8 bits Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands EXTU.W Rd Notes Rev. 4.00 Feb 24, 2006 page 114 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 1 5 7 rd 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions 2.2.31 (2) EXTU (L) EXTU (EXTend as Unsigned) Zero Extension Condition Code Operation 0 (<bits 31 to 16> of ERd) Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H 0 -- H: Previous value remains unchanged. N: Always cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. EXTU.L ERd Operand Size Longword Description This instruction extends the lower 16 bits (general register Rd) in a 32-bit register ERd to longword data by padding with zeros. That is, it clears the upper 16 bits of ERd (bits 31 to 16) to 0. ERd 15 Bit 31 0 Don't care 16 bits ERd 15 Bit 31 0 Zero extension 16 bits 16 bits 16 bits Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands EXTU.L ERd Instruction Format 1st byte 2nd byte 1 7 7 0 erd 3rd byte 4th byte No. of States 1 Notes Rev. 4.00 Feb 24, 2006 page 115 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.32 (1) INC (B) INC (INCrement) Increment Condition Code Operation Rd + 1 Rd U N Z V C -- -- -- -- I UI H -- H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Previous value remains unchanged. Assembly-Language Format INC.B Rd Operand Size Byte Description This instruction increments an 8-bit register Rd (destination operand) and stores the result in the 8-bit register Rd. Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands INC.B Rd Instruction Format 1st byte 2nd byte 0 0 A Notes An overflow is caused by the operation H'7F + 1 H'80. Rev. 4.00 Feb 24, 2006 page 116 of 322 REJ09B0139-0400 rd 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions 2.2.32 (2) INC (W) INC (INCrement) Increment Condition Code Operation Rd + 1 Rd Rd + 2 Rd U N Z V C -- -- -- -- I UI H -- H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Previous value remains unchanged. Assembly-Language Format INC.W #1, Rd INC.W #2, Rd Operand Size Word Description This instruction adds the immediate value 1 or 2 to the contents of a 16-bit register Rd (destination operand) and stores the result in the 16-bit register Rd. Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Instruction Format No. of States Mnemonic Operands Register direct INC.W #1, Rd 0 B 5 rd 1 Register direct INC.W #2, Rd 0 B D rd 1 1st byte 2nd byte 3rd byte 4th byte Notes An overflow is caused by the operations H'7FFF + 1 H'8000, H'7FFF + 2 H'8001, and H'7FFE + 2 H'8000. Rev. 4.00 Feb 24, 2006 page 117 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.32 (3) INC (L) INC (INCrement) Increment Condition Code Operation ERd + 1 ERd ERd + 2 ERd U N Z V C -- -- -- -- I UI H -- H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Previous value remains unchanged. Assembly-Language Format INC.L #1, ERd INC.L #2, ERd Operand Size Longword Description This instruction adds the immediate value 1 or 2 to the contents of a 32-bit register ERd (destination operand) and stores the result in the 32-bit register ERd. Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Instruction Format No. of States Mnemonic Operands Register direct INC.L #1, ERd 0 B 7 0 erd 1 Register direct INC.L #2, ERd 0 B F 0 erd 1 1st byte 2nd byte 3rd byte 4th byte Notes An overflow is caused by the operations H'7FFFFFFF + 1 H'80000000, H'7FFFFFFF + 2 H'80000001, and H'7FFFFFFE + 2 H'80000000. Rev. 4.00 Feb 24, 2006 page 118 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.33 JMP JMP (JuMP) Unconditional Branch Condition Code Operation Effective address PC I UI H U N Z V C -- -- -- -- -- -- -- -- H: N: Z: V: C: Assembly-Language Format JMP <EA> Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Operand Size -- Description This instruction branches unconditionally to a specified effective address. Available Registers ERn: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Instruction Format Mnemonic No. of States Operands 1st byte Register indirect JMP @ERn 5 9 Absolute address JMP @aa:24 5 A Memory indirect JMP @@aa:8 5 B 2nd byte 0 ern 3rd byte 4th byte Normal 0 2 abs abs Advanced 3 4 5 Notes The structure of the branch address and the number of states required for execution differ between normal mode and advanced mode. Ensure that the branch destination address is even. Rev. 4.00 Feb 24, 2006 page 119 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.34 JSR JSR (Jump to SubRoutine) Jump to Subroutine Condition Code Operation PC @-SP Effective address PC I UI H U N Z V C -- -- -- -- -- -- -- -- H: N: Z: V: C: Assembly-Language Format JSR <EA> Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Operand Size -- Description This instruction pushes the program counter onto the stack as a return address, then branches to a specified effective address. The program counter value pushed onto the stack is the address of the instruction following the JSR instruction. Available Registers ERn: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Instruction Format Mnemonic Operands Register indirect JSR @ERn 5 D Absolute address JSR @aa:24 5 E Memory indirect JSR @@aa:8 5 F 1st byte Rev. 4.00 Feb 24, 2006 page 120 of 322 REJ09B0139-0400 2nd byte 0 ern 3rd byte 0 abs abs No. of States 4th byte Normal Advanced 3 4 4 5 4 6 Section 2 Instruction Descriptions JSR (Jump to SubRoutine) Jump to Subroutine Notes The stack structure differs between normal mode and advanced mode. In normal mode only the lower 16 bits of the program counter are pushed onto the stack. Ensure that the branch destination address is even. Reserved PC PC 23 16 15 87 0 23 Normal mode 16 15 87 0 Advanced mode Rev. 4.00 Feb 24, 2006 page 121 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.35 (1) LDC (B) LDC (LoaD to Control register) Load CCR I: Assembly-Language Format LDC.B <EAs>, CCR N Z V C U H UI Loaded from the corresponding bit in the source operand. Loaded from the corresponding bit in the source operand. Loaded from the corresponding bit in the source operand. Loaded from the corresponding bit in the source operand. Loaded from the corresponding bit in the source operand. Loaded from the corresponding bit in the source operand. H: N: Operand Size Z: Byte I <EAs> CCR Condition Code Operation V: C: Description This instruction loads the source operand contents into the condition-code register (CCR). No interrupt requests, including NMI, are accepted immediately after execution of this instruction. Available Registers Rs: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Instruction Format Mnemonic Operands Immediate LDC.B #xx:8, CCR 0 7 Register direct LDC.B Rs, CCR 0 3 Notes Rev. 4.00 Feb 24, 2006 page 122 of 322 REJ09B0139-0400 1st byte 2nd byte IMM 0 3rd byte 4th byte No. of States 1 rs 1 Section 2 Instruction Descriptions 2.2.35 (2) LDC (B) LDC (LoaD to Control register) Load EXR Condition Code Operation <EAs> EXR I UI H U N Z V C -- -- -- -- -- -- -- -- H: N: Z: V: C: Assembly-Language Format LDC.B <EAs>, EXR Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Operand Size Byte Description This instruction loads the source operand contents into the extended control register (EXR). No interrupt requests, including NMI, are accepted for three states after execution of this instruction. Available Registers Rs: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Operands Immediate LDC.B Register direct LDC.B Instruction Format 1st byte 2nd byte 3rd byte #xx:8, EXR 0 1 4 1 0 Rs, EXR 0 3 1 rs 7 4th byte No. of States IMM 2 1 Notes Rev. 4.00 Feb 24, 2006 page 123 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.35 (3) LDC (W) LDC (LoaD to Control register) Assembly-Language Format LDC.W <EAs>, CCR I: H: N: Operand Size Word Z: V: C: I UI H U N Z V C (EAs) CCR Condition Code Operation Load CCR Loaded from the corresponding bit in the source operand. Loaded from the corresponding bit in the source operand. Loaded from the corresponding bit in the source operand. Loaded from the corresponding bit in the source operand. Loaded from the corresponding bit in the source operand. Loaded from the corresponding bit in the source operand. Description This instruction loads the source operand contents into the condition-code register (CCR). Although CCR is a byte register, the source operand is word size. The contents of the even address are loaded into CCR. No interrupt requests, including NMI, are accepted immediately after execution of this instruction. Available Registers ERs: ER0 to ER7 Rev. 4.00 Feb 24, 2006 page 124 of 322 REJ09B0139-0400 Notes Absolute address Register indirect with postincrement Register indirect with displacement @ERs, CCR Register indirect @aa:32, CCR 0 0 @aa:16, CCR LDC.W LDC.W 0 0 @ERs+, CCR @(d:32, ERs), CCR LDC.W 0 0 1 1 1 1 1 1 1st byte LDC.W @(d:16, ERs), CCR LDC.W LDC.W Operands Addressing Mnemonic Mode 4 4 4 4 4 4 0 0 0 0 0 0 2nd byte 6 6 6 7 6 6 B B D 8 F 9 3rd byte 2 0 0 ers 0 ers 0 ers 0 ers 0 0 0 0 0 0 4th byte 6 B 5th byte abs disp 2 0 6th byte Instruction Format Operand Format and Number of States Required for Execution abs 7th byte 8th byte disp 9th byte 5 4 4 6 4 3 No. of 10th byte States Section 2 Instruction Descriptions LDC (LoaD to Control register) Load CCR Rev. 4.00 Feb 24, 2006 page 125 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.35 (4) LDC (W) LDC (LoaD to Control register) Operation Load EXR Condition Code (EAs) EXR I UI H U N Z V C -- -- -- -- -- -- -- -- Assembly-Language Format LDC.W <EAs>, EXR H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Operand Size Word Description This instruction loads the source operand contents into the extended control register (EXR). Although EXR is a byte register, the source operand is word size. The contents of the even address are loaded into EXR. No interrupt requests, including NMI, are accepted for three states after execution of this instruction. Available Registers ERs: ER0 to ER7 Rev. 4.00 Feb 24, 2006 page 126 of 322 REJ09B0139-0400 Notes Absolute address Register indirect with postincrement Register indirect with displacement @ERs, EXR Register indirect @aa:32, EXR @aa:16, EXR LDC.W LDC.W @ERs+, EXR @(d:32, ERs), EXR LDC.W LDC.W @(d:16, ERs), EXR LDC.W LDC.W Operands Addressing Mnemonic Mode 0 0 0 0 0 0 1 1 1 1 1 1 1st byte 4 4 4 4 4 4 1 1 1 1 1 1 2nd byte 6 6 6 7 6 6 B B D 8 F 9 3rd byte 2 0 0 ers 0 ers 0 ers 0 ers 0 0 0 0 0 0 4th byte 6 B 5th byte abs disp 2 0 6th byte Instruction Format Operand Format and Number of States Required for Execution abs 7th byte 8th byte disp 9th byte 5 4 4 6 4 3 No. of 10th byte States Section 2 Instruction Descriptions LDC (LoaD to Control register) Load EXR Rev. 4.00 Feb 24, 2006 page 127 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.36 LDM LDM (LoaD to Multiple registers) Operation Restore Data from Stack Condition Code @SP+ ERn (register list) I UI H U N Z V C -- -- -- -- -- -- -- -- Assembly-Language Format LDM.L @SP+, <register list> H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Operand Size Longword Description This instruction restores data saved on the stack to a specified list of registers. Registers are restored in descending order of register number. Two, three, or four registers can be restored by one LDM instruction. The following ranges can be specified in the register list. Two registers: ER0-ER1, ER2-ER3, ER4-ER5, or ER6-ER7 Three registers: ER0-ER2 or ER4-ER6 Four registers: ER0-ER3 or ER4-ER7 Available Registers ERn: ER0 to ER7 Rev. 4.00 Feb 24, 2006 page 128 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions LDM (LoaD to Multiple registers) Restore Data from Stack Operand Format and Number of States Required for Execution Addressing Mnemonic Mode Instruction Format Operands 1st byte 2nd byte 3rd byte 4th byte No. of States -- LDM.L @SP+, (ERn-ERn+1) 0 1 1 0 6 D 7 0 ern+1 7 -- LDM.L @SP+, (ERn-ERn+2) 0 1 2 0 6 D 7 0 ern+2 9 -- LDM.L @SP+, (ERn-ERn+3) 0 1 3 0 6 D 7 0 ern+3 11 Notes Rev. 4.00 Feb 24, 2006 page 129 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.37 LDMAC LDMAC (LoaD to MAC register) Load MAC Register Operation Condition Code ERs MACH or ERs MACL I UI H U N Z V C -- -- -- -- -- -- -- -- H: N: Z: V: C: Assembly-Language Format LDMAC ERs, MAC register Operand Size Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Longword Description This instruction moves the contents of a general register to a multiply-accumulate register (MACH or MACL). If the transfer is to MACH, only the lowest 10 bits of the general register are transferred. Supported only by the H8S/2600 CPU. Available Registers ERs: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Operands Register direct LDMAC Register direct LDMAC Instruction Format 3rd byte 4th byte No. of States 1st byte 2nd byte ERs, MACH 0 3 2 0 ers 2* ERs, MACL 0 3 3 0 ers 2* Note: * A maximum of three additional states are required for execution of this instruction within three states after execution of a MAC instruction. For example, if there is a one-state instruction (such as NOP) between the MAC instruction and this instruction, this instruction will be two states longer. The number of states may differ depending on the product. For details, refer to the relevant microcontroller hardware manual of the product in question. Notes Execution of this instruction clears the overflow flag in the multiplier to 0. Rev. 4.00 Feb 24, 2006 page 130 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.38 MAC MAC (Multiply and ACcumulate) Operation (EAn) x (EAm) + MAC register MAC register ERn + 2 ERn ERm + 2 ERm Assembly-Language Format MAC @ERn+, @ERm+ Multiply and Accumulate Condition Code I UI H U N Z V C -- -- -- -- --* --* --* -- H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Operand Size -- Description This instruction performs signed multiplication on two 16-bit operands at addresses given by the contents of general registers ERn and ERm, adds the 32-bit product to the contents of the MAC register, and stores the sum in the MAC register. After this operation, ERn and ERm are both incremented by 2. The operation can be carried out in saturating or non-saturating mode, depending on the MACS bit in a system control register. (SYSCR) See the relevant hardware manual for further information. In non-saturating mode, MACH and MACL are concatenated to store a 42-bit result. The value of bit 41 is copied into the upper 22 bits of MACH as a sign extension. In saturating mode, only MACL is valid, and the result is limited to the range from H'80000000 (minimum value) to H'7FFFFFFF (maximum value). If the result overflows in the negative direction, H'80000000 (the minimum value) is stored in MACL. If the result overflows in the positive direction, H'7FFFFFFF (the maximum value) is stored in MACL. The LSB of the MACH register indicates the status of the overflow flag (V-MULT) in the multiplier. Other bits retain their previous contents. This instruction is supported only by the H8S/2600 CPU. Rev. 4.00 Feb 24, 2006 page 131 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions MAC (Multiply and ACcumulate) Multiply and Accumulate Operand Format and Number of States Required for Execution Instruction Format Addressing Mode Mnemonic Register indirect with post-increment MAC Operands 1st byte @ERn+, @ERm+ 0 1 2nd byte 6 0 3rd byte 6 D 4th byte 0 ern No. of States 0 erm 4 Notes 1. Flags (N, Z, V) indicating the result of the MAC instruction can be set in the condition-code register (CCR) by the STMAC instruction. 2. If ERn and ERm are the same register, the execution addresses are ERn and ERn + 2. After execution, the value of ERn is ERn + 4. 3. If MACS is modified during execution of a MAC instruction, the result cannot be guaranteed. It is essential to wait for at least three states after a MAC instruction before modifying MACS. Further Explanation of Instructions Using Multiplier 1. Modification of flags The multiplier has N-MULT, Z-MULT, and V-MULT flags that indicate the results of MAC instructions. These flags are separated from the condition-code register (CCR). The values of these flags can be set in the N, Z, and V flags of the CCR only by the STMAC instruction. N-MULT and Z-MULT are modified only by MAC instructions. V-MULT retains a value indicating whether an overflow has occurred in the past, until it is cleared by execution of the CLRMAC or LDMAC instruction. The setting and clearing conditions for these flags are given below. * N-MULT (negative flag) Saturating mode Set when bit 31 of register MACL is set to 1 by execution of a MAC instruction Cleared when bit 31 of register MACL is cleared to 0 by execution of a MAC instruction Non-saturating mode Set when bit 41 of register MACH is set to 1 by execution of a MAC instruction Cleared when bit 41 of register MACH is cleared to 0 by execution of a MAC instruction Rev. 4.00 Feb 24, 2006 page 132 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions MAC (Multiply and ACcumulate) * Multiply and Accumulate Z-MULT (zero flag) Saturating mode Set when register MACL is cleared to 0 by execution of a MAC instruction Cleared when register MACL is not cleared to 0 by execution of a MAC instruction Non-saturating mode Set when registers MACH and MACL are both cleared to 0 by execution of a MAC instruction Cleared when register MACH or MACL is not cleared to 0 by execution of a MAC instruction * V-MULT (overflow flag) Saturating mode Set when the result of the MAC instruction overflows the range from H'80000000 (minimum) to H'7FFFFFFF (maximum) Cleared when a CLRMAC or LDMAC instruction is executed Note: Not cleared when the result of the MAC instruction is within the above range Non-saturating mode Set when the result of the MAC instruction overflows the range from H'20000000000 (minimum) to H'1FFFFFFFFFF (maximum) Cleared when a CLRMAC or LDMAC instruction is executed Note: Not cleared when the result of the MAC instruction is within the above range The N-MULT, Z-MULT, and V-MULT flags are not modified by switching between saturating and non-saturating modes, or by execution of a multiply instruction (MULXU or MULXS). 2. Example CLRMAC MAC @ER1+,@ER2+ MAC @ER1+,@ER2+ : MAC @ER1+,@ER2+ NOP STMAC MACH,ER3 CLRMAC STMAC MACH,ER3 Overflow occurs Result = 0 CCR (N = 0, Z = 1, V = 1) CCR (N = 0, Z = 1, V = 0) Rev. 4.00 Feb 24, 2006 page 133 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.39 (1) MOV (B) MOV (MOVe data) Move Condition Code Operation Rs Rd U N Z V C -- -- -- -- I UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the transferred data is negative; otherwise cleared to 0. Z: Set to 1 if the transferred data is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format MOV.B Rs, Rd Operand Size Byte Description This instruction transfers one byte of data from an 8-bit register Rs to an 8-bit register Rd, tests the transferred data, and sets condition-code flags according to the result. Available Registers Rs: R0L to R7L, R0H to R7H Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands MOV.B Rs, Rd Notes Rev. 4.00 Feb 24, 2006 page 134 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 0 rs C rd 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions 2.2.39 (2) MOV (W) MOV (MOVe data) Move Condition Code Operation Rs Rd U N Z V C -- -- -- -- I UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the transferred data is negative; otherwise cleared to 0. Z: Set to 1 if the transferred data is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format MOV.W Rs, Rd Operand Size Word Description This instruction transfers one word of data from a 16-bit register Rs to a 16-bit register Rd, tests the transferred data, and sets condition-code flags according to the result. Available Registers Rd: R0 to R7, E0 to E7 Rs: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands MOV.W Rs, Rd Instruction Format 1st byte 2nd byte 0 rs D rd 3rd byte 4th byte No. of States 1 Notes Rev. 4.00 Feb 24, 2006 page 135 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.39 (3) MOV (L) MOV (MOVe data) Move Condition Code Operation ERs ERd U N Z V C -- -- -- -- I UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the transferred data is negative; otherwise cleared to 0. Z: Set to 1 if the transferred data is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format MOV.L ERs, ERd Operand Size Longword Description This instruction transfers one word of data from a 32-bit register ERs to a 32-bit register ERd, tests the transferred data, and sets condition-code flags according to the result. Available Registers ERd: ER0 to ER7 ERs: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands MOV.L ERs, ERd Notes Rev. 4.00 Feb 24, 2006 page 136 of 322 REJ09B0139-0400 Instruction Format 1st byte 0 F 2nd byte 1 ers 0 erd 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions 2.2.39 (4) MOV (B) MOV (MOVe data) Assembly-Language Format MOV.B <EAs>, Rd Operand Size Byte I U N Z V C -- -- -- -- (EAs) Rd Condition Code Operation Move UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the transferred data is negative; otherwise cleared to 0. Z: Set to 1 if the transferred data is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction transfers the source operand contents to an 8-bit register Rd, tests the transferred data, and sets condition-code flags according to the result. Available Registers Rd: R0L to R7L, R0H to R7H ERs: ER0 to ER7 Rev. 4.00 Feb 24, 2006 page 137 of 322 REJ09B0139-0400 MOV.B Register indirect Rev. 4.00 Feb 24, 2006 page 138 of 322 REJ09B0139-0400 @aa:16, Rd @aa:32, Rd MOV.B @aa:8, Rd MOV.B MOV.B @ERs+, Rd 6 6 2 6 7 @(d:32, ERs), Rd MOV.B MOV.B 6 @(d:16, ERs), Rd MOV.B 6 F A A rd C 8 E 8 rd 1st byte 2 0 abs 0 ers 0 ers 0 ers 0 ers IMM rd rd rd 0 rd rd 2nd byte 6 A 3rd byte abs disp 2 rd abs 5th byte Instruction Format 4th byte 6th byte disp 7th byte 8th byte 4 3 2 3 5 3 2 1 No. of States For the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. The MOV.B @ER7+, Rd instruction should never be used, because it leaves an odd value in the stack pointer (ER7). For details refer to section 3.3, Exception-Handling State, or to the relevant hardware manual. Notes Absolute address Register indirect with postincrement Register indirect with displacement #xx:8, Rd MOV.B Immediate @ERs, Rd Operands Addressing Mnemonic Mode Operand Format and Number of States Required for Execution Section 2 Instruction Descriptions MOV (MOVe data) Move Section 2 Instruction Descriptions 2.2.39 (5) MOV (W) MOV (MOVe data) Assembly-Language Format MOV.W <EAs>, Rd Operand Size Word I U N Z V C -- -- -- -- (EAs) Rd Condition Code Operation Move UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the transferred data is negative; otherwise cleared to 0. Z: Set to 1 if the transferred data is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction transfers the source operand contents to a 16-bit register Rd, tests the transferred data, and sets condition-code flags according to the result. Available Registers Rd: R0 to R7, E0 to E7 ERs: ER0 to ER7 Rev. 4.00 Feb 24, 2006 page 139 of 322 REJ09B0139-0400 MOV.W Register indirect Rev. 4.00 Feb 24, 2006 page 140 of 322 REJ09B0139-0400 1. 2. @aa:32, Rd @aa:16, Rd MOV.W MOV.W @ERs+, Rd 6 6 6 7 @(d:32, ERs), Rd MOV.W MOV.W 6 @(d:16, ERs), Rd MOV.W 6 7 B B D 8 F 9 9 1st byte 2 0 0 ers 0 ers 0 ers 0 ers 0 rd rd rd 0 rd rd rd 2nd byte 6 B abs disp 2 rd abs 5th byte Instruction Format 4th byte IMM 3rd byte The source operand <EAs> must be located at an even address. In machine language, MOV.W @ER7+, Rd is identical to POP.W Rd. Notes Absolute address Register indirect with postincrement Register indirect with displacement #xx:16, Rd MOV.W Immediate @ERs, Rd Operands Addressing Mnemonic Mode Operand Format and Number of States Required for Execution 6th byte disp 7th byte 8th byte 4 3 3 5 3 2 2 No. of States Section 2 Instruction Descriptions MOV (MOVe data) Move Section 2 Instruction Descriptions 2.2.39 (6) MOV (L) MOV (MOVe data) Move Condition Code Operation (EAs) ERd U N Z V C -- -- -- -- I UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the transferred data is negative; otherwise cleared to 0. Z: Set to 1 if the transferred data is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format MOV.L <EAs>, ERd Operand Size Longword Description This instruction transfers the source operand contents to a specified 32-bit register (ERd), tests the transferred data, and sets condition-code flags according to the result. The first memory word located at the effective address is stored in extended register Ed. The next word is stored in general register Rd. MSB EA LSB ERd Ed RdH RdL Available Registers ERs: ER0 to ER7 ERd: ER0 to ER7 Rev. 4.00 Feb 24, 2006 page 141 of 322 REJ09B0139-0400 Rev. 4.00 Feb 24, 2006 page 142 of 322 REJ09B0139-0400 1. 2. @aa:32, ERd @aa:16, ERd MOV.L MOV.L @ERs+, ERd MOV.L @(d:32, ERs), ERd MOV.L 0 0 0 0 0 0 7 1 1 1 1 1 1 A 1st byte 0 0 0 0 0 0 0 0 0 0 0 0 0 0 erd 2nd byte 6 6 6 7 6 6 B B D 8 F 9 3rd byte 0 2 0 0 erd 0 erd 0 ers 0 erd 0 ers 0 ers 0 erd 0 ers 0 erd 6 B abs disp 2 7th byte abs 0 erd 6th byte Instruction Format 5th byte IMM 4th byte The source operand <EAs> must be located at an even address. In machine language, MOV.L @R7+, ERd is identical to POP.L ERd. Notes Absolute address Register indirect with postincrement @(d:16, ERs), ERd @ERs, ERd #xx:32, Rd Operands MOV.L MOV.L Register indirect Register indirect with displacement MOV.L Immediate Addressing Mnemonic Mode Operand Format and Number of States Required for Execution 9th byte disp 8th byte 6 5 5 7 5 4 3 No. of 10th byte States Section 2 Instruction Descriptions MOV (MOVe data) Move Section 2 Instruction Descriptions 2.2.39 (7) MOV (B) MOV (MOVe data) Assembly-Language Format MOV.B Rs, <EAd> Operand Size Byte I U N Z V C -- -- -- -- Rs (EAd) Condition Code Operation Move UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the transferred data is negative; otherwise cleared to 0. Z: Set to 1 if the transferred data is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction transfers the contents of an 8-bit register Rs (source operand) to a destination location, tests the transferred data, and sets condition-code flags according to the result. Available Registers Rs: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Rev. 4.00 Feb 24, 2006 page 143 of 322 REJ09B0139-0400 Rev. 4.00 Feb 24, 2006 page 144 of 322 REJ09B0139-0400 2. 1. Rs, @aa:16 Rs, @aa:32 MOV.B Rs, @aa:8 MOV.B MOV.B Rs, @-Erd 6 6 3 6 7 Rs, @(d:32, ERd) MOV.B MOV.B 6 Rs, @(d:16, ERd) MOV.B 6 A A rs C 8 E 8 1st byte A 8 abs 1 erd 0 erd 1 erd 1 erd rs rs rs 0 rs rs 2nd byte 6 A 3rd byte abs disp A rs abs 5th byte Instruction Format 4th byte 6th byte disp 7th byte 8th byte The MOV.B Rs, @-ER7 instruction should never be used, because it leaves an odd value in the stack pointer (ER7). For details refer to section 3.3, Exception-Handling State, or to the relevant hardware manual. Execution of MOV.B RnL, @-ERn or MOV.B RnH, @-ERn first decrements ERn by one, then transfers the designated part (RnL or RnH) of the resulting ERn value. Notes Absolute address Register indirect with predecrement Register indirect with displacement Rs, @ERd Register indirect MOV.B Operands Addressing Mnemonic Mode Operand Format and Number of States Required for Execution 4 3 2 3 5 3 2 No. of States Section 2 Instruction Descriptions MOV (MOVe data) Move Section 2 Instruction Descriptions 2.2.39 (8) MOV (W) MOV (MOVe data) Assembly-Language Format MOV.W Rs, <EAd> Operand Size Word I U N Z V C -- -- -- -- Rs (EAd) Condition Code Operation Move UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the transferred data is negative; otherwise cleared to 0. Z: Set to 1 if the transferred data is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction transfers the contents of a 16-bit register Rs (source operand) to a destination location, tests the transferred data, and sets condition-code flags according to the result. Available Registers Rs: R0 to R7, E0 to E7 ERd: ER0 to ER7 Rev. 4.00 Feb 24, 2006 page 145 of 322 REJ09B0139-0400 Rev. 4.00 Feb 24, 2006 page 146 of 322 REJ09B0139-0400 1. 2. 3. Rs, @aa:32 Rs, @aa:16 MOV.W MOV.W Rs, @-ERd 6 6 6 7 Rs, @(d:32, ERd) MOV.W MOV.W 6 Rs, @(d:16, ERd) MOV.W 6 B B D 8 F 9 1st byte A 8 1 erd 0 erd 1 erd 1 erd rs rs rs 0 rs rs 2nd byte 6 B 3rd byte abs disp A rs abs 5th byte Instruction Format 4th byte 6th byte disp 7th byte 8th byte 4 3 3 5 3 2 No. of States The destination operand <EAd> must be located at an even address. In machine language, MOV.W Rs, @-ER7 is identical to PUSH.W Rs. When MOV.W Rn, @-ERn is executed, the transferred value comes from (value of ERn before execution) - 2. Notes Absolute address Register indirect with predecrement Register indirect with displacement Rs, @ERd Register indirect MOV.W Operands Addressing Mnemonic Mode Operand Format and Number of States Required for Execution Section 2 Instruction Descriptions MOV (MOVe data) Move Section 2 Instruction Descriptions 2.2.39 (9) MOV (L) MOV (MOVe data) Move Condition Code Operation ERs (EAd) U N Z V C -- -- -- -- I UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the transferred data is negative; otherwise cleared to 0. Z: Set to 1 if the transferred data is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format MOV.L ERs, <EAd> Operand Size Longword Description This instruction transfers the contents of a 32-bit register ERs (source operand) to a destination location, tests the transferred data, and sets condition-code flags according to the result. The extended register (Es) contents are stored at the first word indicated by the effective address. The general register (Rs) contents are stored at the next word. MSB EA LSB ERs Es RsH RsL Available Registers ERs: ER0 to ER7 ERd: ER0 to ER7 Rev. 4.00 Feb 24, 2006 page 147 of 322 REJ09B0139-0400 Rev. 4.00 Feb 24, 2006 page 148 of 322 REJ09B0139-0400 1. 2. 3. ERs, @aa:32 ERs, @aa:16 MOV.L MOV.L ERs, @-ERd ERs, @(d:32, ERd) MOV.L MOV.L ERs, @(d:16, ERd) MOV.L 0 0 0 0 0 0 1 1 1 1 1 1 1st byte 0 0 0 0 0 0 0 0 0 0 0 0 2nd byte 6 6 6 7 6 6 B B D 8 F 9 3rd byte 0 A 8 0 ers 0 ers 1 erd 0 ers 0 erd 1 erd 0 ers 1 erd 0 ers 4th byte 6 B abs disp A 7th byte abs 0 ers 6th byte Instruction Format 5th byte 8th byte disp 9th byte The destination operand <EAd> must be located at an even address. In machine language, MOV.L ERs, @-ER7 is identical to PUSH.L ERs. When MOV.L ERn, @-ERn is executed, the transferred value is (value of ERn before execution) - 4. Notes Absolute address Register indirect with predecrement Register indirect with displacement ERs, @ERd Register indirect MOV.L Operands Addressing Mnemonic Mode Operand Format and Number of States Required for Execution 6 5 5 7 5 4 No. of 10th byte States Section 2 Instruction Descriptions MOV (MOVe data) Move Section 2 Instruction Descriptions 2.2.40 MOVFPE MOVFPE (MOVe From Peripheral with E clock) Move Data with E Clock Condition Code Operation (EAs) Rd Synchronized with E clock Assembly-Language Format U N Z V C -- -- -- -- I UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the transferred data is negative; otherwise cleared to 0. Z: Set to 1 if the transferred data is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. MOVFPE @aa:16, Rd Operand Size Byte Description This instruction transfers memory contents specified by a 16-bit absolute address to a general register Rd in synchronization with an E clock, tests the transferred data, and sets condition-code flags according to the result. Note: Avoid using this instruction in microcontrollers without an E clock output pin, or in single-chip mode. Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Operands Absolute address MOVFPE @aa:16, Rd Instruction Format 1st byte 2nd byte 6 4 A rd 3rd byte 4th byte No. of States abs * Note: * For details, refer to the relevant microcontroller hardware manual. Notes 1. This instruction cannot be used with addressing modes other than the above, and cannot transfer word data or longword data. 2. The number of states required for execution is variable. For details, refer to the relevant microcontroller hardware manual. Rev. 4.00 Feb 24, 2006 page 149 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.41 MOVTPE MOVTPE (MOVe To Peripheral with E clock) Move Data with E Clock Condition Code Operation Rs (EAd) Synchronized with E clock Assembly-Language Format U N Z V C -- -- -- -- I UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the transferred data is negative; otherwise cleared to 0. Z: Set to 1 if the transferred data is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. MOVTPE Rs, @aa:16 Operand Size Byte Description This instruction transfers the contents of a general register Rs (source operand) to a destination location specified by a 16-bit absolute address in synchronization with an E clock, tests the transferred data, and sets condition-code flags according to the result. Note: Avoid using this instruction in microcontrollers without an E clock output pin, or in single-chip mode. Available Registers Rs: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Operands Absolute address MOVTPE Rs, @aa:16 Instruction Format 1st byte 2nd byte 6 C A rs 3rd byte 4th byte No. of States abs Note: * For details, refer to the relevant microcontroller hardware manual. Notes 1. This instruction cannot be used with addressing modes other than the above, and cannot transfer word data or longword data. 2. The number of states required for execution is variable. For details, refer to the relevant microcontroller hardware manual. Rev. 4.00 Feb 24, 2006 page 150 of 322 REJ09B0139-0400 * Section 2 Instruction Descriptions 2.2.42 (1) MULXS (B) MULXS (MULtiply eXtend as Signed) Multiply Signed Operation Condition Code Rd x Rs Rd Assembly-Language Format U N Z -- -- -- -- I UI H V C -- -- H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Previous value remains unchanged. C: Previous value remains unchanged. MULXS.B Rs, Rd Operand Size Byte Description This instruction multiplies the lower 8 bits of a 16-bit register Rd (destination operand) by the contents of an 8-bit register Rs (source operand) as signed data and stores the result in the 16-bit register Rd. If Rd is one of general registers R0 to R7, Rs can be the upper part (RdH) or lower part (RdL) of Rd. The operation performed is 8 bits x 8 bits 16 bits signed multiplication. Rd Don't care Rs Multiplicand x Rd Multiplier 8 bits Product 8 bits 16 bits Available Registers Rd: R0 to R7, E0 to E7 Rs: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Operands Register direct MULXS.B Rs, Rd Instruction Format 1st byte 2nd byte 3rd byte 4th byte 0 C 5 rs 1 0 0 rd No. of States 4* Note: * The number of states in the H8S/2000 CPU is 13. A maximum of three additional states are required for execution of this instruction within three states after execution of a MAC instruction. For example, if there is a one-state instruction (such as NOP) between the MAC instruction and this instruction, this instruction will be two states longer. The number of states may differ depending on the product. For details, refer to the relevant microcontroller hardware manual of the product in question. Notes Rev. 4.00 Feb 24, 2006 page 151 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.42 (2) MULXS (W) MULXS (MULtiply eXtend as Signed) Multiply Signed Operation Condition Code ERd x Rs ERd Assembly-Language Format U N Z -- -- -- -- I UI H V C -- -- H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Previous value remains unchanged. C: Previous value remains unchanged. MULXS.W Rs, ERd Operand Size Word Description This instruction multiplies the lower 16 bits of a 32-bit register ERd (destination operand) by the contents of a 16-bit register Rs (source operand) as signed data and stores the result in the 32-bit register ERd. Rs can be the upper part (Ed) or lower part (Rd) of ERd. The operation performed is 16 bits x 16 bits 32 bits signed multiplication. ERd Don't care Rs Multiplicand x ERd Multiplier 16 bits Product 16 bits 32 bits Available Registers ERd: ER0 to ER7 Rs: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Operands Register direct MULXS.W Rs, ERd Instruction Format 1st byte 2nd byte 3rd byte 4th byte 0 C 5 rs 1 0 2 0 erd No. of States 5* Note: * The number of states in the H8S/2000 CPU is 21. A maximum of three additional states are required for execution of this instruction within three states after execution of a MAC instruction. For example, if there is a one-state instruction (such as NOP) between the MAC instruction and this instruction, this instruction will be two states longer. The number of states may differ depending on the product. For details, refer to the relevant microcontroller hardware manual of the product in question. Notes Rev. 4.00 Feb 24, 2006 page 152 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.43 (1) MULXU (B) MULXU (MULtiply eXtend as Unsigned) Multiply Operation Condition Code Rd x Rs Rd I UI H U N Z V C -- -- -- -- -- -- -- -- Assembly-Language Format H: N: Z: V: C: MULXU.B Rs, Rd Operand Size Byte Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction multiplies the lower 8 bits of a 16-bit register Rd (destination operand) by the contents of an 8-bit register Rs (source operand) as unsigned data and stores the result in the 16-bit register Rd. If Rd is one of general registers R0 to R7, Rs can be the upper part (RdH) or lower part (RdL) of Rd. The operation performed is 8 bits x 8 bits 16 bits unsigned multiplication. Rd Don't care Rs Multiplicand x Rd Multiplier 8 bits Product 8 bits 16 bits Available Registers Rd: R0 to R7, E0 to E7 Rs: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Operands Register direct MULXU.B Rs, Rd Instruction Format 1st byte 2nd byte 5 rs 0 3rd byte 4th byte rd No. of States 3* Note: * The number of states in the H8S/2000 CPU is 12. A maximum of three additional states are required for execution of this instruction within three states after execution of a MAC instruction. For example, if there is a one-state instruction (such as NOP) between the MAC instruction and this instruction, this instruction will be two states longer. The number of states may differ depending on the product. For details, refer to the relevant microcontroller hardware manual of the product in question. Notes Rev. 4.00 Feb 24, 2006 page 153 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.43 (2) MULXU (W) MULXU (MULtiply eXtend as Unsigned) Multiply Operation Condition Code ERd x Rs ERd I UI H U N Z V C -- -- -- -- -- -- -- -- Assembly-Language Format H: N: Z: V: C: MULXU.W Rs, ERd Operand Size Word Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction multiplies the lower 16 bits of a 32-bit register ERd (destination operand) by the contents of a 16-bit register Rs (source operand) as unsigned data and stores the result in the 32-bit register ERd. Rs can be the upper part (Ed) or lower part (Rd) of ERd. The operation performed is 16 bits x 16 bits 32 bits unsigned multiplication. ERd Don't care Rs Multiplicand x ERd Multiplier 16 bits Product 16 bits 32 bits Available Registers ERd: ER0 to ER7 Rs: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Operands Register direct MULXU.W Rs, ERd Instruction Format 1st byte 2nd byte 5 rs 2 3rd byte 4th byte 0 erd No. of States 4* Note: * The number of states in the H8S/2000 CPU is 20. A maximum of three additional states are required for execution of this instruction within three states after execution of a MAC instruction. For example, if there is a one-state instruction (such as NOP) between the MAC instruction and this instruction, this instruction will be two states longer. The number of states may differ depending on the product. For details, refer to the relevant microcontroller hardware manual of the product in question. Notes Rev. 4.00 Feb 24, 2006 page 154 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions NEG (B) NEG (NEGate) Negate Binary Signed UI H U N -- -- -- I Z V C 0 - Rd Rd Condition Code Operation 2.2.44 (1) H: Set to 1 if there is a borrow at bit 3; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a borrow at bit 7; otherwise cleared to 0. Assembly-Language Format NEG.B Rd Operand Size Byte Description This instruction takes the two's complement of the contents of an 8-bit register Rd (destination operand) and stores the result in the 8-bit register Rd (subtracting the register contents from H'00). If the original contents of Rd were H'80, however, the result remains H'80. Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands NEG.B Rd Instruction Format 1st byte 2nd byte 1 8 7 rd 3rd byte 4th byte No. of States 1 Notes An overflow occurs if the original contents of Rd were H'80. Rev. 4.00 Feb 24, 2006 page 155 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions NEG (W) NEG (NEGate) Negate Binary Signed UI H U N -- -- -- I Z V C 0 - Rd Rd Condition Code Operation 2.2.44 (2) H: Set to 1 if there is a borrow at bit 11; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a borrow at bit 15; otherwise cleared to 0. Assembly-Language Format NEG.W Rd Operand Size Word Description This instruction takes the two's complement of the contents of a 16-bit register Rd (destination operand) and stores the result in the 16-bit register Rd (subtracting the register contents from H'0000). If the original contents of Rd were H'8000, however, the result remains H'8000. Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands NEG.W Rd Instruction Format 1st byte 2nd byte 1 9 7 rd Notes An overflow occurs if the original contents of Rd were H'8000. Rev. 4.00 Feb 24, 2006 page 156 of 322 REJ09B0139-0400 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions NEG (L) NEG (NEGate) Negate Binary Signed UI H U N -- -- -- I Z V C 0 - ERd ERd Condition Code Operation 2.2.44 (3) H: Set to 1 if there is a borrow at bit 27; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a borrow at bit 31; otherwise cleared to 0. Assembly-Language Format NEG.L ERd Operand Size Longword Description This instruction takes the two's complement of the contents of a 32-bit register ERd (destination operand) and stores the result in the 32-bit register ERd (subtracting the register contents from H'00000000). If the original contents of ERd were H'80000000, however, the result remains H'80000000. Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands NEG.L ERd Instruction Format 1st byte 2nd byte 1 B 7 3rd byte 0 erd 4th byte No. of States 1 Notes An overflow occurs if the original contents of ERd were H'80000000. Rev. 4.00 Feb 24, 2006 page 157 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.45 NOP NOP (No OPeration) No Operation Condition Code Operation PC + 2 PC I UI H U N Z V C -- -- -- -- -- -- -- -- H: N: Z: V: C: Assembly-Language Format NOP Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Operand Size -- Description This instruction only increments the program counter, causing the next instruction to be executed. The internal state of the CPU does not change. Operand Format and Number of States Required for Execution Addressing Mode Mnemonic -- NOP Operands Notes Rev. 4.00 Feb 24, 2006 page 158 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 0 0 0 0 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions 2.2.46 (1) NOT (B) NOT (NOT = logical complement) Logical Complement Condition Code Operation Rd Rd U N Z V C -- -- -- -- I UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format NOT.B Rd Operand Size Byte Description This instruction takes the one's complement of the contents of an 8-bit register Rd (destination operand) and stores the result in the 8-bit register Rd. Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands NOT.B Rd Instruction Format 1st byte 2nd byte 1 0 7 rd 3rd byte 4th byte No. of States 1 Notes Rev. 4.00 Feb 24, 2006 page 159 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.46 (2) NOT (W) NOT (NOT = logical complement) Logical Complement Condition Code Operation Rd Rd U N Z V C -- -- -- -- I UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format NOT.W Rd Operand Size Word Description This instruction takes the one's complement of the contents of a 16-bit register Rd (destination operand) and stores the result in the 16-bit register Rd. Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands NOT.W Rd Notes Rev. 4.00 Feb 24, 2006 page 160 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 1 1 7 rd 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions 2.2.46 (3) NOT (L) NOT (NOT = logical complement) Logical Complement Condition Code Operation ERd ERd U N Z V C -- -- -- -- I UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format NOT.L ERd Operand Size Longword Description This instruction takes the one's complement of the contents of a 32-bit register ERd (destination operand) and stores the result in the 32-bit register ERd. Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands NOT.L ERd Instruction Format 1st byte 2nd byte 1 3 7 0 erd 3rd byte 4th byte No. of States 1 Notes Rev. 4.00 Feb 24, 2006 page 161 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.47 (1) OR (B) OR (inclusive OR logical) Logical OR Condition Code Operation Rd (EAs) Rd U N Z V C -- -- -- -- I UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format OR.B <EAs>, Rd Operand Size Byte Description This instruction ORs the source operand with the contents of an 8-bit register Rd (destination operand) and stores the result in the 8-bit register Rd. Available Registers Rd: R0L to R7L, R0H to R7H Rs: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Instruction Format Mnemonic Operands Immediate OR.B #xx:8, Rd C rd Register direct OR.B Rs, Rd 1 4 Notes Rev. 4.00 Feb 24, 2006 page 162 of 322 REJ09B0139-0400 1st byte 2nd byte IMM rs 3rd byte 4th byte No. of States 1 rd 1 Section 2 Instruction Descriptions 2.2.47 (2) OR (W) OR (inclusive OR logical) Logical OR Condition Code Operation Rd (EAs) Rd U N Z V C -- -- -- -- I UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format OR.W <EAs>, Rd Operand Size Word Description This instruction ORs the source operand with the contents of a 16-bit register Rd (destination operand) and stores the result in the 16-bit register Rd. Available Registers Rd: R0 to R7, E0 to E7 Rs: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Instruction Format Mnemonic Operands Immediate OR.W #xx:16, Rd 7 9 4 rd Register direct OR.W Rs, Rd 6 4 rs rd 1st byte 2nd byte 3rd byte 4th byte IMM No. of States 2 1 Notes Rev. 4.00 Feb 24, 2006 page 163 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.47 (3) OR (L) OR (inclusive OR logical) Logical OR Condition Code Operation ERd (EAs) ERd U N Z V C -- -- -- -- I UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format OR.L <EAs>, ERd Operand Size Longword Description This instruction ORs the source operand with the contents of a 32-bit register ERd (destination operand) and stores the result in the 32-bit register ERd. Available Registers ERd: ER0 to ER7 ERs: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Instruction Format Mnemonic Operands 1st byte 2nd byte Immediate OR.L #xx:32, ERd 7 A 4 0 erd Register direct OR.L ERs, ERd 0 1 F 0 Notes Rev. 4.00 Feb 24, 2006 page 164 of 322 REJ09B0139-0400 3rd byte 4th byte 5th byte IMM 6 4 0 ers 0 erd 6th byte No. of States 3 2 Section 2 Instruction Descriptions ORC ORC (inclusive OR Control register) Logical OR with CCR I: UI: H: U: N: Z: V: C: Assembly-Language Format ORC #xx:8, CCR Operand Size Byte H U N Z V C UI I CCR #IMM CCR Condition Code Operation 2.2.48 (1) Stores the corresponding bit of the result. Stores the corresponding bit of the result. Stores the corresponding bit of the result. Stores the corresponding bit of the result. Stores the corresponding bit of the result. Stores the corresponding bit of the result. Stores the corresponding bit of the result. Stores the corresponding bit of the result. Description This instruction ORs the contents of the condition-code register (CCR) with immediate data and stores the result in the condition-code register. No interrupt requests, including NMI, are accepted immediately after execution of this instruction. Operand Format and Number of States Required for Execution Addressing Mode Immediate Mnemonic Operands ORC #xx:8, CCR Instruction Format 1st byte 0 4 2nd byte IMM 3rd byte 4th byte No. of States 1 Notes Rev. 4.00 Feb 24, 2006 page 165 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.48 (2) ORC ORC (inclusive OR Control register) Logical OR with EXR Condition Code Operation EXR #IMM EXR I UI H U N Z V C -- -- -- -- -- -- -- -- H: N: Z: V: C: Assembly-Language Format ORC #xx:8, EXR Stores the corresponding bit of the result. Stores the corresponding bit of the result. Stores the corresponding bit of the result. Stores the corresponding bit of the result. Stores the corresponding bit of the result. Operand Size Byte Description This instruction ORs the contents of the extended control register (EXR) with immediate data and stores the result in the extended control register. No interrupt requests, including NMI, are accepted for three states after execution of this instruction. Operand Format and Number of States Required for Execution Addressing Mode Immediate Mnemonic Operands ORC #xx:8, EXR Notes Rev. 4.00 Feb 24, 2006 page 166 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 3rd byte 0 4 0 1 1 4 4th byte No. of States IMM 2 Section 2 Instruction Descriptions 2.2.49 (1) POP (W) POP (POP data) Pop Data from Stack Condition Code Operation @SP+ Rn U N Z V C -- -- -- -- I UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the transferred data is negative; otherwise cleared to 0. Z: Set to 1 if the transferred data is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format POP.W Rn Operand Size Word Description This instruction restores data from the stack to a 16-bit general register Rn, tests the restored data, and sets condition-code flags according to the result. Available Registers Rn: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Operands -- POP.W Rn Instruction Format 1st byte 2nd byte 6 7 D rn 3rd byte 4th byte No. of States 3 Notes POP.W Rn is identical to MOV.W @SP+, Rn. Rev. 4.00 Feb 24, 2006 page 167 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.49 (2) POP (L) POP (POP data) Pop Data from Stack Condition Code Operation @SP+ ERn U N Z V C -- -- -- -- I UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the transferred data is negative; otherwise cleared to 0. Z: Set to 1 if the transferred data is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format POP.L ERn Operand Size Longword Description This instruction restores data from the stack to a 32-bit general register ERn, tests the restored data, and sets condition-code flags according to the result. Available Registers ERn: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Operands -- POP.L ERn Instruction Format 1st byte 2nd byte 3rd byte 4th byte 0 0 6 7 Notes POP.L ERn is identical to MOV.L @SP+, ERn. Rev. 4.00 Feb 24, 2006 page 168 of 322 REJ09B0139-0400 1 0 D 0 ern No. of States 5 Section 2 Instruction Descriptions 2.2.50 (1) PUSH (W) PUSH (PUSH data) Push Data on Stack Condition Code Operation Rn @-SP U N Z V C -- -- -- -- I UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the transferred data is negative; otherwise cleared to 0. Z: Set to 1 if the transferred data is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format PUSH.W Rn Operand Size Word Description This instruction saves data from a 16-bit register Rn onto the stack, tests the saved data, and sets condition-code flags according to the result. Available Registers Rn: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Operands -- PUSH.W Rn Instruction Format 1st byte 2nd byte 6 F D rn 3rd byte 4th byte No. of States 3 Notes 1. PUSH.W Rn is identical to MOV.W Rn, @-SP. 2. When PUSH.W R7 or PUSH.W E7 is executed, the value saved on the stack is the R7 or E7 value after effective address calculation (after ER7 is decremented by 2). Rev. 4.00 Feb 24, 2006 page 169 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.50 (2) PUSH (L) PUSH (PUSH data) Push Data on Stack Condition Code Operation ERn @-SP U N Z V C -- -- -- -- I UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the transferred data is negative; otherwise cleared to 0. Z: Set to 1 if the transferred data is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format PUSH.L ERn Operand Size Longword Description This instruction pushes data from a 32-bit register ERn onto the stack, tests the saved data, and sets condition-code flags according to the result. Available Registers ERn: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Operands -- PUSH.L ERn Instruction Format 1st byte 2nd byte 3rd byte 4th byte 0 0 6 F 1 0 D 0 ern No. of States 5 Notes 1. PUSH.L ERn is identical to MOV.L ERn, @-SP. 2. When PUSH.L ER7 is executed, the value saved on the stack is the ER7 value after effective address calculation (after ER7 is decremented by 4). Rev. 4.00 Feb 24, 2006 page 170 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.51 (1) ROTL (B) ROTL (ROTate Left) Rotate Condition Code Operation Rd (left rotation) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 7. ROTL.B Rd Operand Size Byte Description This instruction rotates the bits in an 8-bit register Rd (destination operand) one bit to the left. The most significant bit (bit 7) is rotated to the least significant bit (bit 0), and also copied to the carry flag. MSB LSB . . . . . . C b7 b0 Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands ROTL.B Rd Instruction Format 1st byte 2nd byte 1 8 2 rd 3rd byte 4th byte No. of States 1 Notes Rev. 4.00 Feb 24, 2006 page 171 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.51 (2) ROTL (B) ROTL (ROTate Left) Rotate Condition Code Operation Rd (left rotation) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 6. ROTL.B #2, Rd Operand Size Byte Description This instruction rotates the bits in an 8-bit register Rd (destination operand) two bits to the left. The most significant two bits (bits 7 and 6) are rotated to the least significant two bits (bits 1 and 0), and bit 6 is also copied to the carry flag. MSB LSB . . . . C b7 b6 b1 b0 Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands ROTL.B #2, Rd Notes Rev. 4.00 Feb 24, 2006 page 172 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 1 C 2 rd 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions 2.2.51 (3) ROTL (W) ROTL (ROTate Left) Rotate Condition Code Operation Rd (left rotation) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 15. ROTL.W Rd Operand Size Word Description This instruction rotates the bits in a 16-bit register Rd (destination operand) one bit to the left. The most significant bit (bit 15)is rotated to the least significant bit (bit 0), and also copied to the carry flag. MSB LSB . . . . . . C b15 b0 Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands ROTL.W Rd Instruction Format 1st byte 2nd byte 1 9 2 rd 3rd byte 4th byte No. of States 1 Notes Rev. 4.00 Feb 24, 2006 page 173 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.51 (4) ROTL (W) ROTL (ROTate Left) Rotate Condition Code Operation Rd (left rotation) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 14. ROTL.W #2, Rd Operand Size Word Description This instruction rotates the bits in a 16-bit register Rd (destination operand) two bits to the left. The most significant two bits (bits 15 and 14) are rotated to the least significant two bits (bits 1 and 0), and bit 14 is also copied to the carry flag. MSB LSB . . . . C b15 b14 b1 b0 Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands ROTL.W #2, Rd Notes Rev. 4.00 Feb 24, 2006 page 174 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 1 D 2 rd 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions 2.2.51 (5) ROTL (L) ROTL (ROTate Left) Rotate Condition Code Operation ERd (left rotation) ERd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 31. ROTL.L ERd Operand Size Longword Description This instruction rotates the bits in a 32-bit register ERd (destination operand) one bit to the left. The most significant bit (bit 31) is rotated to the least significant bit (bit 0), and also copied to the carry flag. MSB LSB . . . . . . C b31 b0 Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands ROTL.L ERd Instruction Format 1st byte 2nd byte 1 B 2 0 erd 3rd byte 4th byte No. of States 1 Notes Rev. 4.00 Feb 24, 2006 page 175 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.51 (6) ROTL (L) ROTL (ROTate Left) Rotate Condition Code Operation ERd (left rotation) ERd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 30. ROTL.L #2, ERd Operand Size Longword Description This instruction rotates the bits in a 32-bit register ERd (destination operand) two bits to the left. The most significant two bits (bits 31 and 30) are rotated to the least significant two bits (bits 1 and 0), and bit 30 is also copied to the carry flag. MSB LSB . . . . C b31 b30 b1 b0 Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands ROTL.L #2, ERd Notes Rev. 4.00 Feb 24, 2006 page 176 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 1 F 2 0 erd 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions 2.2.52 (1) ROTR (B) ROTR (ROTate Right) Rotate Condition Code Operation Rd (right rotation) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. ROTR.B Rd Operand Size Byte Description This instruction rotates the bits in an 8-bit register Rd (destination operand) one bit to the right. The least significant bit (bit 0) is rotated to the most significant bit (bit 7), and also copied to the carry flag. MSB LSB . . . . . . b7 b0 C Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands ROTR.B Rd Instruction Format 1st byte 2nd byte 1 8 3 rd 3rd byte 4th byte No. of States 1 Notes Rev. 4.00 Feb 24, 2006 page 177 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.52 (2) ROTR (B) ROTR (ROTate Right) Rotate Condition Code Operation Rd (right rotation) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 1. ROTR.B #2, Rd Operand Size Byte Description This instruction rotates the bits in an 8-bit register Rd (destination operand) two bits to the right. The least significant two bits (bits 1 and 0) are rotated to the most significant two bits (bits 7 and 6), and bit 1 is also copied to the carry flag. MSB LSB . . . . b7 b6 b1 b0 C Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands ROTR.B #2, Rd Notes Rev. 4.00 Feb 24, 2006 page 178 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 1 C 3 rd 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions 2.2.52 (3) ROTR (W) ROTR (ROTate Right) Rotate Condition Code Operation Rd (right rotation) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. ROTR.W Rd Operand Size Word Description This instruction rotates the bits in a 16-bit register Rd (destination operand) one bit to the right. The least significant bit (bit 0) is rotated to the most significant bit (bit 15), and also copied to the carry flag. MSB LSB . . . . . . b15 C b0 Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands ROTR.W Rd Instruction Format 1st byte 2nd byte 1 9 3 rd 3rd byte 4th byte No. of States 1 Notes Rev. 4.00 Feb 24, 2006 page 179 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.52 (4) ROTR (W) ROTR (ROTate Right) Rotate Condition Code Operation Rd (right rotation) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 1. ROTR.W #2, Rd Operand Size Word Description This instruction rotates the bits in a 16-bit register Rd (destination operand) two bits to the right. The least significant two bits (bits 1 and 0) are rotated to the most significant two bits (bits 15 and 14), and bit 1 is also copied to the carry flag. MSB LSB . . . . b15 b14 b1 b0 C Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands ROTR.W #2, Rd Notes Rev. 4.00 Feb 24, 2006 page 180 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 1 D 3 rd 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions 2.2.52 (5) ROTR (L) ROTR (ROTate Right) Rotate Condition Code Operation ERd (right rotation) ERd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. ROTR.L ERd Operand Size Longword Description This instruction rotates the bits in a 32-bit register ERd (destination operand) one bit to the right. The least significant bit (bit 0) is rotated to the most significant bit (bit 31), and also copied to the carry flag. MSB LSB . . . . . . b31 b0 C Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands ROTR.L ERd Instruction Format 1st byte 2nd byte 1 B 3 0 erd 3rd byte 4th byte No. of States 1 Notes Rev. 4.00 Feb 24, 2006 page 181 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.52 (6) ROTR (L) ROTR (ROTate Right) Rotate Condition Code Operation ERd (right rotation) ERd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 1. ROTR.L #2, ERd Operand Size Longword Description This instruction rotates the bits in a 32-bit register ERd (destination operand) two bits to the right. The least significant two bits (bits 1 and 0) are rotated to the most significant two bits (bits 31 and 30), and bit 1 is also copied to the carry flag. MSB LSB . . . . b31 b30 b1 b0 C Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands ROTR.L #2, ERd Notes Rev. 4.00 Feb 24, 2006 page 182 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 1 F 3 0 erd 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions 2.2.53 (1) ROTXL (B) ROTXL (ROTate with eXtend carry Left) Rotate through Carry Condition Code Operation Rd (left rotation through carry flag) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 7. ROTXL.B Rd Operand Size Byte Description This instruction rotates the bits in an 8-bit register Rd (destination operand) one bit to the left through the carry flag. The carry flag is rotated into the least significant bit (bit 0). The most significant bit (bit 7) rotates into the carry flag. MSB LSB . . . . . . C b7 b0 Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands ROTXL.B Rd Instruction Format 1st byte 2nd byte 1 0 2 rd 3rd byte 4th byte No. of States 1 Notes Rev. 4.00 Feb 24, 2006 page 183 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.53 (2) ROTXL (B) ROTXL (ROTate with eXtend carry Left) Rotate through Carry Condition Code Operation Rd (left rotation through carry flag) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 6. ROTXL.B #2, Rd Operand Size Byte Description This instruction rotates the bits in an 8-bit register Rd (destination operand) two bits to the left through the carry flag. The carry flag rotates into bit 1, bit 7 rotates into bit 0, and bit 6 rotates into the carry flag. MSB LSB . . . . . . C b7 b6 b1 b0 Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands ROTXL.B #2, Rd Notes Rev. 4.00 Feb 24, 2006 page 184 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 1 4 2 rd 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions 2.2.53 (3) ROTXL (W) ROTXL (ROTate with eXtend carry Left) Rotate through Carry Condition Code Operation Rd (left rotation through carry flag) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 15. ROTXL.W Rd Operand Size Word Description This instruction rotates the bits in a 16-bit register Rd (destination operand) one bit to the left through the carry flag. The carry flag is rotated into the least significant bit (bit 0). The most significant bit (bit 15) rotates into the carry flag. MSB LSB . . . . . . C b15 b0 Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Operands Register direct ROTXL.W Rd Instruction Format 1st byte 2nd byte 1 1 2 rd 3rd byte 4th byte No. of States 1 Notes Rev. 4.00 Feb 24, 2006 page 185 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.53 (4) ROTXL (W) ROTXL (ROTate with eXtend carry Left) Rotate through Carry Condition Code Operation Rd (left rotation through carry flag) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 14. ROTXL.W #2, Rd Operand Size Word Description This instruction rotates the bits in a 16-bit register Rd (destination operand) two bits to the left through the carry flag. The carry flag rotates into bit 1, bit 15 rotates into bit 0, and bit 14 rotates into the carry flag. MSB LSB . . . . . . C b15 b14 b1 b0 Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Operands Register direct ROTXL.W #2, Rd Notes Rev. 4.00 Feb 24, 2006 page 186 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 1 5 2 rd 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions 2.2.53 (5) ROTXL (L) ROTXL (ROTate with eXtend carry Left) Rotate through Carry Condition Code Operation ERd (left rotation through carry flag) ERd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 31. ROTXL.L ERd Operand Size Longword Description This instruction rotates the bits in a 32-bit register ERd (destination operand) one bit to the left through the carry flag. The carry flag is rotated into the least significant bit (bit 0). The most significant bit (bit 31) rotates into the carry flag. MSB LSB . . . . . . C b31 b0 Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands ROTXL.L ERd Instruction Format 1st byte 2nd byte 1 3 2 0 erd 3rd byte 4th byte No. of States 1 Notes Rev. 4.00 Feb 24, 2006 page 187 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.53 (6) ROTXL (L) ROTXL (ROTate with eXtend carry Left) Rotate through Carry Condition Code Operation ERd (left rotation through carry flag) ERd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 30. ROTXL.L #2, ERd Operand Size Longword Description This instruction rotates the bits in a 32-bit register ERd (destination operand) two bits to the left through the carry flag. The carry flag rotates into bit 1, bit 31 rotates into bit 0, and bit 30 rotates into into the carry flag. MSB LSB . . . . . . C b31 b30 b1 b0 Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands ROTXL.L #2, ERd Notes Rev. 4.00 Feb 24, 2006 page 188 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 1 7 2 0 erd 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions 2.2.54 (1) ROTXR (B) ROTXR (ROTate with eXtend carry Right) Rotate through Carry Condition Code Operation Rd (right rotation through carry flag) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. ROTXR.B Rd Operand Size Byte Description This instruction rotates the bits in an 8-bit register Rd (destination operand) one bit to the right through the carry flag. The carry flag is rotated into the most significant bit (bit 7). The least significant bit (bit 0) rotates into the carry flag. MSB LSB . . . . . . b7 b0 C Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Operands Register direct ROTXR.B Rd Instruction Format 1st byte 2nd byte 1 0 3 rd 3rd byte 4th byte No. of States 1 Notes Rev. 4.00 Feb 24, 2006 page 189 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.54 (2) ROTXR (B) ROTXR (ROTate with eXtend carry Right) Rotate through Carry Condition Code Operation Rd (right rotation through carry flag) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 1. ROTXR.B #2, Rd Operand Size Byte Description This instruction rotates the bits in an 8-bit register Rd (destination operand) two bits to the right through the carry flag. The carry flag rotates into bit 6, bit 0 rotates into bit 7, and bit 1 rotates into the carry flag. MSB LSB . . . . b7 C b6 b1 b0 Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Operands Register direct ROTXR.B #2, Rd Notes Rev. 4.00 Feb 24, 2006 page 190 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 1 4 3 rd 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions 2.2.54 (3) ROTXR (W) ROTXR (ROTate with eXtend carry Right) Rotate through Carry Condition Code Operation Rd (right rotation through carry flag) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. ROTXR.W Rd Operand Size Word Description This instruction rotates the bits in a 16-bit register Rd (destination operand) one bit to the right through the carry flag. The carry flag is rotated into the most significant bit (bit 15). The least significant bit (bit 0) rotates into the carry flag. MSB LSB . . . . . . b15 b0 C Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Operands Register direct ROTXR.W Rd Instruction Format 1st byte 2nd byte 1 1 3 rd 3rd byte 4th byte No. of States 1 Notes Rev. 4.00 Feb 24, 2006 page 191 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.54 (4) ROTXR (W) ROTXR (ROTate with eXtend carry Right) Rotate through Carry Condition Code Operation Rd (right rotation through carry flag) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 1. ROTXR.W #2, Rd Operand Size Word Description This instruction rotates the bits in a 16-bit register Rd (destination operand) two bits to the right through the carry flag. The carry flag rotates into bit 14, bit 0 rotates into bit 15, and bit 1 rotates into the carry flag. MSB LSB . . . . C b15 b14 b1 b0 Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Operands Register direct ROTXR.W #2, Rd Notes Rev. 4.00 Feb 24, 2006 page 192 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 1 5 3 rd 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions 2.2.54 (5) ROTXR (L) ROTXR (ROTate with eXtend carry Right) Rotate through Carry Condition Code Operation ERd (right rotation through carry flag) ERd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. ROTXR.L ERd Operand Size Longword Description This instruction rotates the bits in a 32-bit register ERd (destination operand) one bit to the right through the carry flag. The carry flag is rotated into the most significant bit (bit 31). The least significant bit (bit 0) rotates into the carry flag. MSB LSB . . . . . . b31 b0 C Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Operands Register direct ROTXR.L ERd Instruction Format 1st byte 2nd byte 1 3 3 0 erd 3rd byte 4th byte No. of States 1 Notes Rev. 4.00 Feb 24, 2006 page 193 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.54 (6) ROTXR (L) ROTXR (ROTate with eXtend carry Right) Rotate through Carry Condition Code Operation ERd (right rotation through carry flag) ERd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 1. ROTXR.L #2, ERd Operand Size Longword Description This instruction rotates the bits in a 32-bit register ERd (destination operand) two bits to the right through the carry flag. The carry flag rotates into bit 30, bit 0 rotates into bit 31, and bit 1 rotates into the carry flag. MSB LSB . . . . C b31 b30 b1 b0 Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Operands Register direct ROTXR.L #2, ERd Notes Rev. 4.00 Feb 24, 2006 page 194 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 1 7 3 0 erd 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions RTE RTE (ReTurn from Exception) Return from Exception Handling I: UI: @SP+ PC H: Assembly-Language Format U: RTE N: Z: Operand Size -- N Z V C U H Restored from the corresponding bit on the stack. Restored from the corresponding bit on the stack. Restored from the corresponding bit on the stack. Restored from the corresponding bit on the stack. Restored from the corresponding bit on the stack. Restored from the corresponding bit on the stack. Restored from the corresponding bit on the stack. Restored from the corresponding bit on the stack. @SP+ EXR @SP+ CCR UI @SP+ PC * When EXR is valid I @SP+ CCR * When EXR is invalid Condition Code Operation 2.2.55 V: C: Description This instruction returns from an exception-handling routine by restoring the EXR, condition-code register (CCR) and program counter (PC) from the stack. Program execution continues from the address restored to the program counter. The CCR and PC contents at the time of execution of this instruction are lost. If the extended control regiser (EXR) is valid, it is also restored (and the existing EXR contents are lost). Operand Format and Number of States Required for Execution Addressing Mode Mnemonic -- RTE Operands Instruction Format 1st byte 2nd byte 5 7 6 0 3rd byte 4th byte No. of States 5* Note: * Six states when EXR is valid. Rev. 4.00 Feb 24, 2006 page 195 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions RTE (ReTurn from Exception) Return from Exception Handling Notes The stack structure differs between normal mode and advanced mode. Don't care CCR PC Normal mode 23 Undet. 16 15 CCR PC 87 Rev. 4.00 Feb 24, 2006 page 196 of 322 REJ09B0139-0400 0 Advanced mode 23 16 15 87 0 Section 2 Instruction Descriptions 2.2.56 RTS RTS (ReTurn from Subroutine) Return from Subroutine Condition Code Operation @SP+ PC I UI H U N Z V C -- -- -- -- -- -- -- -- Assembly-Language Format H: N: Z: V: C: RTS Operand Size Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. -- Description This instruction returns from a subroutine by restoring the program counter (PC) from the stack. Program execution continues from the address restored to the program counter. The PC contents at the time of execution of this instruction are lost. Operand Format and Number of States Required for Execution Addressing Mode Mnemonic -- RTS Operands Instruction Format No. of States 1st byte 2nd byte 3rd byte 4th byte Normal Advanced 5 4 7 0 4 5 Notes The stack structure and number of states required for execution differ between normal mode and advanced mode. In normal mode, only the lower 16 bits of the program counter are restored. Don't care PC Normal mode 23 Undet. 16 15 PC 87 0 Advanced mode 23 16 15 87 0 Rev. 4.00 Feb 24, 2006 page 197 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions SHAL (B) SHAL (SHift Arithmetic Left) Shift Arithmetic Assembly-Language Format U N -- -- -- -- I UI H Z V C Rd (left arithmetic shift) Rd Condition Code Operation 2.2.57 (1) H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Receives the previous value in bit 7. SHAL.B Rd Operand Size Byte Description This instruction shifts the bits in an 8-bit register Rd (destination operand) one bit to the left. The most significant bit (bit 7) shifts into the carry flag. The least significant bit (bit 0) is cleared to 0. MSB LSB . . . . . . 0 b7 C b0 Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands SHAL.B Rd Instruction Format 1st byte 2nd byte 1 8 0 3rd byte 4th byte rd Notes The SHAL instruction differs from the SHLL instruction in its effect on the overflow flag. Rev. 4.00 Feb 24, 2006 page 198 of 322 REJ09B0139-0400 No. of States 1 Section 2 Instruction Descriptions SHAL (B) SHAL (SHift Arithmetic Left) Shift Arithmetic Assembly-Language Format U N -- -- -- -- I UI H Z V C Rd (left arithmetic shift) Rd Condition Code Operation 2.2.57 (2) H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Receives the previous value in bit 6. SHAL.B #2, Rd Operand Size Byte Description This instruction shifts the bits in an 8-bit register Rd (destination operand) two bits to the left. Bit 6 shifts into the carry flag. Bits 0 and 1 are cleared to 0. MSB LSB . . . . . . C b7 b6 0 0 b1 b0 0 Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands SHAL.B #2, Rd Instruction Format 1st byte 2nd byte 1 C 0 3rd byte 4th byte rd No. of States 1 Notes The SHAL instruction differs from the SHLL instruction in its effect on the overflow flag. Rev. 4.00 Feb 24, 2006 page 199 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions SHAL (W) SHAL (SHift Arithmetic Left) Shift Arithmetic Assembly-Language Format U N -- -- -- -- I UI H Z V C Rd (left arithmetic shift) Rd Condition Code Operation 2.2.57 (3) H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Receives the previous value in bit 15. SHAL.W Rd Operand Size Word Description This instruction shifts the bits in a 16-bit register Rd (destination operand) one bit to the left. The most significant bit (bit 15) shifts into the carry flag. The least significant bit (bit 0) is cleared to 0. MSB LSB . . . . . . C 0 b15 b0 Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands SHAL.W Rd Instruction Format 1st byte 2nd byte 1 9 0 3rd byte 4th byte rd Notes The SHAL instruction differs from the SHLL instruction in its effect on the overflow flag. Rev. 4.00 Feb 24, 2006 page 200 of 322 REJ09B0139-0400 No. of States 1 Section 2 Instruction Descriptions SHAL (W) SHAL (SHift Arithmetic Left) Shift Arithmetic Assembly-Language Format U N -- -- -- -- I UI H Z V C Rd (left arithmetic shift) Rd Condition Code Operation 2.2.57 (4) H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Receives the previous value in bit 14. SHAL.W #2, Rd Operand Size Word Description This instruction shifts the bits in a 16-bit register Rd (destination operand) two bits to the left. Bit 14 shifts into the carry flag. Bits 0 and 1 are cleared to 0. MSB LSB . . . . . . C b15 b14 0 0 b1 b0 0 Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands SHAL.W #2, Rd Instruction Format 1st byte 2nd byte 1 D 0 3rd byte 4th byte rd No. of States 1 Notes The SHAL instruction differs from the SHLL instruction in its effect on the overflow flag. Rev. 4.00 Feb 24, 2006 page 201 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions SHAL (L) SHAL (SHift Arithmetic Left) Shift Arithmetic Assembly-Language Format U N -- -- -- -- I UI H Z V C ERd (left arithmetic shift) ERd Condition Code Operation 2.2.57 (5) H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Receives the previous value in bit 31. SHAL.L ERd Operand Size Longword Description This instruction shifts the bits in a 32-bit register ERd (destination operand) one bit to the left. The most significant bit (bit 31) shifts into the carry flag. The least significant bit (bit 0) is cleared to 0. MSB LSB . . . . . . C 0 b31 b0 Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands SHAL.L ERd Instruction Format 1st byte 2nd byte 1 B 0 3rd byte 4th byte 0 erd Notes The SHAL instruction differs from the SHLL instruction in its effect on the overflow flag. Rev. 4.00 Feb 24, 2006 page 202 of 322 REJ09B0139-0400 No. of States 1 Section 2 Instruction Descriptions SHAL (L) SHAL (SHift Arithmetic Left) Shift Arithmetic Assembly-Language Format U N -- -- -- -- I UI H Z V C ERd (left arithmetic shift) ERd Condition Code Operation 2.2.57 (6) H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Receives the previous value in bit 30. SHAL.L #2, ERd Operand Size Longword Description This instruction shifts the bits in a 32-bit register ERd (destination operand) two bits to the left. Bit 30 shifts into the carry flag. Bits 0 and 1 are cleared to 0. MSB LSB . . . . . . C b31 b30 0 0 b1 b0 0 Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands SHAL.L #2, ERd Instruction Format 1st byte 2nd byte 1 F 0 3rd byte 4th byte 0 erd No. of States 1 Notes The SHAL instruction differs from the SHLL instruction in its effect on the overflow flag. Rev. 4.00 Feb 24, 2006 page 203 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.58 (1) SHAR (B) SHAR (SHift Arithmetic Right) Shift Arithmetic Condition Code Operation Rd (right arithmetic shift) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. SHAR.B Rd Operand Size Byte Description This instruction shifts the bits in an 8-bit register Rd (destination operand) one bit to the right. Bit 0 shifts into the carry flag. Bit 7 shifts into itself. Since bit 7 remains unaltered, the sign does not change. MSB LSB . . . . . . b7 b0 C Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands SHAR.B Rd Notes Rev. 4.00 Feb 24, 2006 page 204 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 1 8 1 rd 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions 2.2.58 (2) SHAR (B) SHAR (SHift Arithmetic Right) Shift Arithmetic Condition Code Operation Rd (right arithmetic shift) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 1. SHAR.B #2, Rd Operand Size Byte Description This instruction shifts the bits in an 8-bit register Rd (destination operand) two bits to the right. Bit 1 shifts into the carry flag. Bits 7 and 6 receive the previous value of bit 7. Since bit 7 remains unaltered, the sign does not change. MSB LSB . . . b7 b6 b5 b1 b0 C Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands SHAR.B #2, Rd Instruction Format 1st byte 2nd byte 1 C 1 rd 3rd byte 4th byte No. of States 1 Notes Rev. 4.00 Feb 24, 2006 page 205 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.58 (3) SHAR (W) SHAR (SHift Arithmetic Right) Shift Arithmetic Condition Code Operation Rd (right arithmetic shift) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. SHAR.W Rd Operand Size Word Description This instruction shifts the bits in a 16-bit register Rd (destination operand) one bit to the right. Bit 0 shifts into the carry flag. Bit 15 shifts into itself. Since bit 15 remains unaltered, the sign does not change. MSB LSB . . . . . . b15 b0 C Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands SHAR.W Rd Notes Rev. 4.00 Feb 24, 2006 page 206 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 1 9 1 rd 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions 2.2.58 (4) SHAR (W) SHAR (SHift Arithmetic Right) Shift Arithmetic Condition Code Operation Rd (right arithmetic shift) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 1. SHAR.W #2, Rd Operand Size Word Description This instruction shifts the bits in a 16-bit register Rd (destination operand) two bits to the right. Bit 1 shifts into the carry flag. Bits 15 and 14 receive the previous value of bit 15. Since bit 15 remains unaltered, the sign does not change. MSB LSB . . . b15 b14 b13 b1 b0 C Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands SHAR.W #2, Rd Instruction Format 1st byte 2nd byte 1 D 1 rd 3rd byte 4th byte No. of States 1 Notes Rev. 4.00 Feb 24, 2006 page 207 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.58 (5) SHAR (L) SHAR (SHift Arithmetic Right) Shift Arithmetic Condition Code Operation ERd (right arithmetic shift) ERd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. SHAR.L ERd Operand Size Longword Description This instruction shifts the bits in a 32-bit register ERd (destination operand) one bit to the right. Bit 0 shifts into the carry flag. Bit 31 shifts into itself. Since bit 31 remains unaltered, the sign does not change. MSB LSB . . . . . . b31 b0 C Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands SHAR.L ERd Notes Rev. 4.00 Feb 24, 2006 page 208 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 1 B 1 0 erd 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions 2.2.58 (6) SHAR (L) SHAR (SHift Arithmetic Right) Shift Arithmetic Condition Code Operation ERd (right arithmetic shift) ERd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 1. SHAR.L #2, ERd Operand Size Longword Description This instruction shifts the bits in a 32-bit register ERd (destination operand) two bits to the right. Bit 1 shifts into the carry flag. Bits 31 and 30 receive the previous value of bit 31. Since bit 31 remains unaltered, the sign does not change. MSB LSB . . . b31 b30 b29 b1 b0 C Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands SHAR.L #2, ERd Instruction Format 1st byte 2nd byte 1 F 1 0 erd 3rd byte 4th byte No. of States 1 Notes Rev. 4.00 Feb 24, 2006 page 209 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.59 (1) SHLL (B) SHLL (SHift Logical Left) Shift Logical Condition Code Operation Rd (left logical shift) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 7. SHLL.B Rd Operand Size Byte Description This instruction shifts the bits in an 8-bit register Rd (destination operand) one bit to the left. The most significant bit (bit 7) shifts into the carry flag. The least significant bit (bit 0) is cleared to 0. MSB LSB . . . . . . C 0 b7 b0 Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands SHLL.B Rd Instruction Format 1st byte 2nd byte 1 0 0 3rd byte 4th byte rd Notes The SHLL instruction differs from the SHAL instruction in its effect on the overflow flag. Rev. 4.00 Feb 24, 2006 page 210 of 322 REJ09B0139-0400 No. of States 1 Section 2 Instruction Descriptions 2.2.59 (2) SHLL (B) SHLL (SHift Logical Left) Shift Logical Condition Code Operation Rd (left logical shift) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 6. SHLL.B #2, Rd Operand Size Byte Description This instruction shifts the bits in an 8-bit register Rd (destination operand) two bits to the left. Bit 6 shifts into the carry flag. Bits 0 and 1 are cleared to 0. MSB LSB . . . . C b7 b6 0 0 b1 b0 0 Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands SHLL.B #2, Rd Instruction Format 1st byte 2nd byte 1 4 0 3rd byte 4th byte rd No. of States 1 Notes The SHLL instruction differs from the SHAL instruction in its effect on the overflow flag. Rev. 4.00 Feb 24, 2006 page 211 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.59 (3) SHLL (W) SHLL (SHift Logical Left) Shift Logical Condition Code Operation Rd (left logical shift) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 15. SHLL.W Rd Operand Size Word Description This instruction shifts the bits in a 16-bit register Rd (destination operand) one bit to the left. The most significant bit (bit 15) shifts into the carry flag. The least significant bit (bit 0) is cleared to 0. MSB LSB . . . . . . C 0 b15 b0 Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands SHLL.W Rd Instruction Format 1st byte 2nd byte 1 1 0 3rd byte 4th byte rd Notes The SHLL instruction differs from the SHAL instruction in its effect on the overflow flag. Rev. 4.00 Feb 24, 2006 page 212 of 322 REJ09B0139-0400 No. of States 1 Section 2 Instruction Descriptions 2.2.59 (4) SHLL (W) SHLL (SHift Logical Left) Shift Logical Condition Code Operation Rd (left logical shift) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 14. SHLL.W #2, Rd Operand Size Word Description This instruction shifts the bits in a 16-bit register Rd (destination operand) two bits to the left. Bit 14 shifts into the carry flag. Bits 0 and 1 are cleared to 0. MSB LSB . . . . C b15 b14 0 0 b1 b0 0 Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands SHLL.W #2, Rd Instruction Format 1st byte 2nd byte 1 5 0 3rd byte 4th byte rd No. of States 1 Notes The SHLL instruction differs from the SHAL instruction in its effect on the overflow flag. Rev. 4.00 Feb 24, 2006 page 213 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.59 (5) SHLL (L) SHLL (SHift Logical Left) Shift Logical Condition Code Operation ERd (left logical shift) ERd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 31. SHLL.L ERd Operand Size Longword Description This instruction shifts the bits in a 32-bit register ERd (destination operand) one bit to the left. The most significant bit (bit 31) shifts into the carry flag. The least significant bit (bit 0) is cleared to 0. MSB LSB . . . . . . C 0 b31 b0 Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands SHLL.L ERd Instruction Format 1st byte 2nd byte 1 3 0 3rd byte 4th byte 0 erd Notes The SHLL instruction differs from the SHAL instruction in its effect on the overflow flag. Rev. 4.00 Feb 24, 2006 page 214 of 322 REJ09B0139-0400 No. of States 1 Section 2 Instruction Descriptions 2.2.59 (6) SHLL (L) SHLL (SHift Logical Left) Shift Logical Condition Code Operation ERd (left logical shift) ERd Assembly-Language Format U N Z V C -- -- -- -- 0 I UI H H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 30. SHLL.L #2, ERd Operand Size Longword Description This instruction shifts the bits in a 32-bit register ERd (destination operand) two bits to the left. Bit 30 shifts into the carry flag. Bits 0 and 1 are cleared to 0. MSB LSB . . . . C b31 b30 0 0 b1 b0 0 Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands SHLL.L #2, ERd Instruction Format 1st byte 2nd byte 1 7 0 3rd byte 4th byte 0 erd No. of States 1 Notes The SHLL instruction differs from the SHAL instruction in its effect on the overflow flag. Rev. 4.00 Feb 24, 2006 page 215 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.60 (1) SHLR (B) SHLR (SHift Logical Right) Shift Logical Condition Code Operation Rd (right logical shift) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 0 I UI H H: Previous value remains unchanged. N: Always cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. SHLR.B Rd Operand Size Byte Description This instruction shifts the bits in an 8-bit register Rd (destination operand) one bit to the right. The least significant bit (bit 0) shifts into the carry flag. The most significant bit (bit 7) is cleared to 0. MSB LSB . . . . . . 0 b7 b0 C Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands SHLR.B Rd Notes Rev. 4.00 Feb 24, 2006 page 216 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 1 0 1 rd 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions 2.2.60 (2) SHLR (B) SHLR (SHift Logical Right) Shift Logical Condition Code Operation Rd (right logical shift) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 0 I UI H H: Previous value remains unchanged. N: Always cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 1. SHLR.B #2, Rd Operand Size Byte Description This instruction shifts the bits in an 8-bit register Rd (destination operand) two bits to the right. Bit 1 shifts into the carry flag. Bits 7 and 6 are cleared to 0. MSB LSB 0 0 b7 b6 0 . . . . . . b1 b0 C Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands SHLR.B #2, Rd Instruction Format 1st byte 2nd byte 1 4 1 rd 3rd byte 4th byte No. of States 1 Notes Rev. 4.00 Feb 24, 2006 page 217 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.60 (3) SHLR (W) SHLR (SHift Logical Right) Shift Logical Condition Code Operation Rd (right logical shift) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 0 I UI H H: Previous value remains unchanged. N: Always cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. SHLR.W Rd Operand Size Word Description This instruction shifts the bits in a 16-bit register Rd (destination operand) one bit to the right. The least significant bit (bit 0) shifts into the carry flag. The most significant bit (bit 15) is cleared to 0. MSB LSB . . . . . . 0 b15 b0 C Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands SHLR.W Rd Notes Rev. 4.00 Feb 24, 2006 page 218 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 1 1 1 rd 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions 2.2.60 (4) SHLR (W) SHLR (SHift Logical Right) Shift Logical Condition Code Operation Rd (right logical shift) Rd Assembly-Language Format U N Z V C -- -- -- -- 0 0 I UI H H: Previous value remains unchanged. N: Always cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 1. SHLR.W #2, Rd Operand Size Word Description This instruction shifts the bits in a 16-bit register Rd (destination operand) two bits to the right. Bit 1 shifts into the carry flag. Bits 15 and 14 are cleared to 0. MSB 0 0 LSB 0 . . . . . . b15 b14 b1 b0 C Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands SHLR.W #2, Rd Instruction Format 1st byte 2nd byte 1 5 1 rd 3rd byte 4th byte No. of States 1 Notes Rev. 4.00 Feb 24, 2006 page 219 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.60 (5) SHLR (L) SHLR (SHift Logical Right) Shift Logical Condition Code Operation ERd (right logical shift) ERd Assembly-Language Format U N Z V C -- -- -- -- 0 0 I UI H H: Previous value remains unchanged. N: Always cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. SHLR.L ERd Operand Size Longword Description This instruction shifts the bits in a 32-bit register ERd (destination operand) one bit to the right. The least significant bit (bit 0) shifts into the carry flag. The most significant bit (bit 31) is cleared to 0. MSB LSB . . . . . . 0 b31 b0 C Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands SHLR.L ERd Notes Rev. 4.00 Feb 24, 2006 page 220 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 1 3 1 0 erd 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions 2.2.60 (6) SHLR (L) SHLR (SHift Logical Right) Shift Logical Condition Code Operation ERd (right logical shift) ERd Assembly-Language Format U N Z V C -- -- -- -- 0 0 I UI H H: Previous value remains unchanged. N: Always cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 1. SHLR.L #2, ERd Operand Size Longword Description This instruction shifts the bits in a 32-bit register ERd (destination operand) two bits to the right. Bit 1 shifts into the carry flag. Bits 31 and 30 are cleared to 0. MSB 0 0 LSB 0 . . . . . . b31 b30 b1 b0 C Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands SHLR.L #2, ERd Instruction Format 1st byte 2nd byte 1 7 1 0 erd 3rd byte 4th byte No. of States 1 Notes Rev. 4.00 Feb 24, 2006 page 221 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.61 SLEEP SLEEP (SLEEP) Power-Down Mode Condition Code Operation Program execution state power-down mode I UI H U N Z V C -- -- -- -- -- -- -- -- Assembly-Language Format H: N: Z: V: C: SLEEP Operand Size Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. -- Description When the SLEEP instruction is executed, the CPU enters a power-down mode. Its internal state remains unchanged, but the CPU stops executing instructions and waits for an exception-handling request. When it receives an exception-handling request, the CPU exits the power-down mode and begins the exception-handling sequence. Interrupt requests other than NMI cannot end the powerdown mode if they are masked in the CPU. Available Registers -- Operand Format and Number of States Required for Execution Addressing Mode Mnemonic -- SLEEP Operands Instruction Format 1st byte 2nd byte 0 8 1 0 3rd byte 4th byte No. of States 2 Notes For information about power-down modes, see the relevant microcontroller hardware manual. Rev. 4.00 Feb 24, 2006 page 222 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.62 (1) STC (B) STC (STore from Control register) Store CCR Condition Code Operation CCR Rd I UI H U N Z V C -- -- -- -- -- -- -- -- Assembly-Language Format H: N: Z: V: C: STC.B CCR, Rd Operand Size Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Byte Description This instruction copies the CCR contents to an 8-bit register Rd. Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands STC.B CCR, Rd Instruction Format 1st byte 2nd byte 0 0 2 rd 3rd byte 4th byte No. of States 1 Notes Rev. 4.00 Feb 24, 2006 page 223 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.62 (2) STC (B) STC (STore from Control register) Store EXR Condition Code Operation EXR Rd I UI H U N Z V C -- -- -- -- -- -- -- -- Assembly-Language Format H: N: Z: V: C: STC.B EXR, Rd Operand Size Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Byte Description This instruction copies the EXR contents to an 8-bit register Rd. Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands STC.B EXR, Rd Notes Rev. 4.00 Feb 24, 2006 page 224 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 0 1 2 rd 3rd byte 4th byte No. of States 1 Section 2 Instruction Descriptions 2.2.62 (3) STC (W) STC (STore from Control register) Operation Store CCR Condition Code CCR (EAd) I UI H U N Z V C -- -- -- -- -- -- -- -- Assembly-Language Format STC.W CCR, <EAd> Operand Size H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Word Description This instruction copies the CCR contents to a destination location. Although CCR is a byte register, the destination operand is a word operand. The CCR contents are stored at the even address. Undetermined data is stored at the odd address. Available Registers ERd: ER0 to ER7 Rev. 4.00 Feb 24, 2006 page 225 of 322 REJ09B0139-0400 Rev. 4.00 Feb 24, 2006 page 226 of 322 REJ09B0139-0400 Notes Absolute address Register indirect with predecrement Register indirect with displacement Register indirect CCR, @aa:32 CCR, @aa:16 STC.W STC.W CCR, @-ERd CCR, @(d:32, ERd) STC.W STC.W CCR, @(d:16, ERd) CCR, @ERd Operands STC.W STC.W Addressing Mnemonic Mode 0 0 0 0 0 0 1 1 1 1 1 1 1st byte 4 4 4 4 4 4 0 0 0 0 0 0 2nd byte 6 6 6 7 6 6 B B D 8 F 9 3rd byte A 8 1 erd 0 erd 1 erd 1 erd 0 0 0 0 0 0 4th byte 6 B 5th byte abs disp A 0 6th byte Instruction Format Operand Format and Number of States Required for Execution abs 7th byte 9th byte disp 8th byte 5 4 4 6 4 3 No. of 10th byte States Section 2 Instruction Descriptions STC (STore from Control register) Store CCR Section 2 Instruction Descriptions 2.2.62 (4) STC (W) STC (STore from Control register) Operation Store EXR Condition Code EXR (EAd) I UI H U N Z V C -- -- -- -- -- -- -- -- Assembly-Language Format STC.W EXR, <EAd> Operand Size H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Word Description This instruction copies the EXR contents to a destination location. Although EXR is a byte register, the destination operand is a word operand. The EXR contents are stored at the even address. Undetermined data is stored at the odd address. Available Registers ERd: ER0 to ER7 Rev. 4.00 Feb 24, 2006 page 227 of 322 REJ09B0139-0400 Rev. 4.00 Feb 24, 2006 page 228 of 322 REJ09B0139-0400 Notes Absolute address Register indirect with predecrement Register indirect with displacement EXR, @ERd Register indirect EXR, @aa:32 EXR, @aa:16 STC.W STC.W EXR, @-ERd EXR, @(d:32, ERd) STC.W STC.W EXR, @(d:16, ERd) STC.W STC.W Operands Addressing Mnemonic Mode 0 0 0 0 0 0 1 1 1 1 1 1 1st byte 4 4 4 4 4 4 1 1 1 1 1 1 2nd byte 6 6 6 7 6 6 B B D 8 F 9 3rd byte A 8 1 erd 0 erd 1 erd 1 erd 0 0 0 0 0 0 4th byte 6 B 5th byte abs disp A 0 6th byte Instruction Format Operand Format and Number of States Required for Execution abs 7th byte 9th byte disp 8th byte 5 4 4 6 4 3 No. of 10th byte States Section 2 Instruction Descriptions STC (STore from Control register) Store EXR Section 2 Instruction Descriptions 2.2.63 STM STM (STore from Multiple registers) Operation Store Data on Stack Condition Code ERn (register list) @-SP I UI H U N Z V C -- -- -- -- -- -- -- -- Assembly-Language Format STM.L <register list>, @-SP H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Operand Size Longword Description This instruction saves a group of registers specified by a register list onto the stack. The registers are saved in ascending order of register number. Two, three, or four registers can be saved by one STM instruction. The following ranges can be specified in the register list. Two registers: ER0-ER1, ER2-ER3, ER4-ER5, or ER6-ER7 Three registers: ER0-ER2 or ER4-ER6 Four registers: ER0-ER3 or ER4-ER7 Available Registers ERn: ER0 to ER7 Rev. 4.00 Feb 24, 2006 page 229 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions STM (STore from Multiple registers) Store Data on Stack Operand Format and Number of States Required for Execution Addressing Mnemonic Mode Instruction Format Operands 1st byte 2nd byte 3rd byte 4th byte No. of States -- STM.L (ERn-ERn+1), @-SP 0 1 1 0 6 D F 0 ern 7 -- STM.L (ERn-ERn+2), @-SP 0 1 2 0 6 D F 0 ern 9 -- STM.L (ERn-ERn+3), @-SP 0 1 3 0 6 D F 0 ern 11 Notes When ER7 is saved, the value after effective address calculation (after ER7 is decremented by 4) is saved on the stack. Rev. 4.00 Feb 24, 2006 page 230 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions STMAC STMAC (STore from MAC register) Condition Code Assembly-Language Format STMAC MAC register, ERd Operand Size Longword I UI H U -- -- -- -- N Z V C * * * -- MACH ERd or MACL ERd Operation Store Data from MAC Register 2.2.64 H: Previous value remains unchanged. N: Set to 1 if a MAC instruction resulted in a negative MAC register value; otherwise cleared to 0. Z: Set to 1 if a MAC instruction resulted in a zero MAC register value; otherwise cleared to 0. V: Set to 1 if a MAC instruction resulted in an overflow; otherwise cleared to 0. C: Previous value remains unchanged. Note: * Execution of this instruction copies the N, Z, and V flag values from the multiplier to the condition-code register (CCR). If the STMAC instruction is executed after a CLRMAC or LDMAC instruction with no intervening MAC instruction, the V flag will be 0 and the N and Z flags will have undetermined values. Description This instruction moves the contents of a multiply-accumulate register (MACH or MACL) to a general register. If the transfer is from MACH, the upper 22 bits transferred to the general register are a sign extension. This instruction is supported by the H8S/2600 CPU only. Available Registers ERd: ER0 to ER7 Rev. 4.00 Feb 24, 2006 page 231 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions STMAC (STore from MAC register) Store Data from MAC Register Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Operands Register direct STMAC Register direct STMAC Instruction Format 3rd byte 4th byte No. of States 1st byte 2nd byte MACH, ERd 0 2 2 0 erd 1* MACL, ERd 0 2 3 0 erd 1* Note: * A maximum of three additional states are required for execution of this instruction within three states after execution of a MAC instruction. For example, if there is a one-state instruction (such as NOP) between the MAC instruction and this instruction, this instruction will be two states longer. The number of states may differ depending on the product. For details, refer to the relevant microcontroller hardware manual of the product in question. Notes Rev. 4.00 Feb 24, 2006 page 232 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions SUB (B) SUB (SUBtract binary) Subtract Binary UI H U N -- -- -- I Z V C Rd - Rs Rd Condition Code Operation 2.2.65 (1) H: Set to 1 if there is a borrow at bit 3; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a borrow at bit 7; otherwise cleared to 0. Assembly-Language Format SUB.B Rs, Rd Operand Size Byte Description This instruction subtracts the contents of an 8-bit register Rs (source operand) from the contents of an 8-bit register Rd (destination operand) and stores the result in the 8-bit register Rd. Available Registers Rd: R0L to R7L, R0H to R7H Rs: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic Operands SUB.B Rs, Rd Instruction Format 1st byte 2nd byte 1 rs 8 rd 3rd byte 4th byte No. of States 1 Rev. 4.00 Feb 24, 2006 page 233 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions SUB (SUBtract binary) Subtract Binary Notes The SUB.B instruction can operate only on general registers. Immediate data can be subtracted from general register contents by using the SUBX instruction. Before executing SUBX #xx:8, Rd, first set the Z flag to 1 and clear the C flag to 0. The following coding examples can also be used to subtract nonzero immediate data #IMM. (1) ORC SUBX (2) ADD XORC #H'05,CCR #(IMM-1),Rd #(0-IMM),Rd #H'01,CCR Rev. 4.00 Feb 24, 2006 page 234 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions SUB (W) SUB (SUBtract binary) Subtract Binary UI H U N -- -- -- I Z V C Rd - (EAs) Rd Condition Code Operation 2.2.65 (2) H: Set to 1 if there is a borrow at bit 11; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a borrow at bit 15; otherwise cleared to 0. Assembly-Language Format SUB.W <EAs>, Rd Operand Size Word Description This instruction subtracts a source operand from the contents of a 16-bit register Rd (destination operand) and stores the result in the 16-bit register Rd. Available Registers Rd: R0 to R7, E0 to E7 Rs: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Instruction Format Mnemonic Operands Immediate SUB.W #xx:16, Rd 7 9 3 rd Register direct SUB.W Rs, Rd 1 9 rs rd 1st byte 2nd byte 3rd byte 4th byte IMM No. of States 2 1 Notes Rev. 4.00 Feb 24, 2006 page 235 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions SUB (L) SUB (SUBtract binary) Subtract Binary H U -- -- -- N Z V C UI I ERd - (EAs) ERd Condition Code Operation 2.2.65 (3) H: Set to 1 if there is a borrow at bit 27; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a borrow at bit 31; otherwise cleared to 0. Assembly-Language Format SUB.L <EAs>, ERd Operand Size Longword Description This instruction subtracts a source operand from the contents of a 32-bit register ERd (destination operand) and stores the result in the 32-bit register ERd. Available Registers ERd: ER0 to ER7 ERs: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Instruction Format Mnemonic Operands 1st byte Immediate SUB.L #xx:32, ERd 7 A Register direct SUB.L ERs, ERd 1 A Notes Rev. 4.00 Feb 24, 2006 page 236 of 322 REJ09B0139-0400 2nd byte 3 0 erd 1 ers 0 erd 3rd byte 4th byte 5th byte IMM 6th byte No. of States 3 1 Section 2 Instruction Descriptions 2.2.66 SUBS SUBS (SUBtract with Sign extension) Subtract Binary Address Data Condition Code Operation Rd - 1 ERd Rd - 2 ERd Rd - 4 ERd I UI H U N Z V C -- -- -- -- -- -- -- -- H: N: Z: V: C: Assembly-Language Format SUBS #1, ERd SUBS #2, ERd SUBS #4, ERd Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Operand Size Longword Description This instruction subtracts the immediate value 1, 2, or 4 from the contents of a 32-bit register ERd (destination operand). Unlike the SUB instruction, it does not affect the condition-code flags. Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Operands Register direct SUBS Register direct SUBS Register direct SUBS Instruction Format 3rd byte 4th byte No. of States 1st byte 2nd byte #1, ERd 1 B 0 0 erd 1 #2, ERd 1 B 8 0 erd 1 #4, ERd 1 B 9 0 erd 1 Notes Rev. 4.00 Feb 24, 2006 page 237 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions SUBX SUBX (SUBtract with eXtend carry) Subtract with Borrow UI H U N -- -- -- I Z V C Rd - (EAs) - C Rd Condition Code Operation 2.2.67 H: Set to 1 if there is a borrow at bit 3; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Previous value remains unchanged when the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a borrow at bit 7; otherwise cleared to 0. Assembly-Language Format SUBX <EAs>, Rd Operand Size Byte Description This instruction subtracts the source operand and carry flag from the contents of an 8-bit register Rd (destination operand) and stores the result in the 8-bit register Rd. Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Instruction Format Mnemonic Operands Immediate SUBX #xx:8, Rd B rd Register direct SUBX Rs, Rd 1 E Notes Rev. 4.00 Feb 24, 2006 page 238 of 322 REJ09B0139-0400 1st byte 2nd byte IMM rs 3rd byte 4th byte No. of States 1 rd 1 Section 2 Instruction Descriptions 2.2.68 TAS TAS (Test And Set) Test and Set Condition Code Operation @ERd - 0 set/clear CCR 1 (<bit 7> of @ERd) U N Z V C -- -- -- -- I UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format TAS @ERd Operand Size Byte Description This instruction tests a memory operand by comparing it with zero, and sets the condition-code register according to the result. Then it sets the most significant bit (bit 7) of the operand to 1. Available Registers ERd: ER0, ER1, ER4, ER5 Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Operands Register indirect TAS @ERd Instruction Format 1st byte 2nd byte 3rd byte 0 E 7 1 0 B 4th byte 0 erd C No. of States 4 Notes Rev. 4.00 Feb 24, 2006 page 239 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.69 TRAPA TRAPA (TRAP Always) Operation Trap Unconditionally Condition Code * When EXR is invalid PC @-SP CCR @-SP <Vector> PC * When EXR is valid PC @-SP CCR @-SP EXR @-SP <Vector> PC Assembly-Language Format TRAPA #x:2 I: UI: H: N: Z: V: C: I UI H U N Z V C 1 * -- -- -- -- -- -- Always set to 1. See note. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Note: * The UI bit is set to 1 when used as an interrupt mask bit, but retains its previous value when used as a user bit. For details, see the relevant microcontroller hardware manual. Operand Size -- Description This instruction pushes the program counter (PC) and condition-code register (CCR) onto the stack, then sets the I bit to 1. If the extended control register (EXR) is valid, EXR is also saved onto the stack, but bits I2 to I0 are not modified. Next execution branches to a new address given by the contents of the vector address corresponding to the specified vector number. The PC value pushed onto the stack is the starting address of the next instruction after the TRAPA instruction. #x Vector Address Normal Mode Advanced Mode 0 H'0010 to H'0011 H'000020 to H'000023 1 H'0012 to H'0013 H'000024 to H'000027 2 H'0014 to H'0015 H'000028 to H'00002B 3 H'0016 to H'0017 H'00002C to H'00002F Rev. 4.00 Feb 24, 2006 page 240 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions TRAPA (TRAP Always) Trap Unconditionally Operand Format and Number of States Required for Execution Addressing Mode Register direct Instruction Format Mnemonic Operands 1st byte TRAPA #x:2 5 7 2nd byte 00 IMM 0 3rd byte 4th byte No. of States 7* Note: * Eight states when EXR is valid. Notes The stack and vector structure differ between normal mode and advanced mode, and depending on whether EXR is valid or invalid. Rev. 4.00 Feb 24, 2006 page 241 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.70 (1) XOR (B) XOR (eXclusive OR logical) Exclusive Logical OR Condition Code Operation Rd (EAs) Rd U N Z V C -- -- -- -- I UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format XOR.B <EAs>, Rd Operand Size Byte Description This instruction exclusively ORs the source operand with the contents of an 8-bit register Rd (destination operand) and stores the result in the 8-bit register Rd. Available Registers Rd: R0L to R7L, R0H to R7H Rs: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Instruction Format Mnemonic Operands Immediate XOR.B #xx:8, Rd D rd Register direct XOR.B Rs, Rd 1 5 Notes Rev. 4.00 Feb 24, 2006 page 242 of 322 REJ09B0139-0400 1st byte 2nd byte IMM rs 3rd byte 4th byte No. of States 1 rd 1 Section 2 Instruction Descriptions 2.2.70 (2) XOR (W) XOR (eXclusive OR logical) Exclusive Logical OR Condition Code Operation Rd (EAs) Rd U N Z V C -- -- -- -- I UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format XOR.W <EAs>, Rd Operand Size Word Description This instruction exclusively ORs the source operand with the contents of a 16-bit register Rd (destination operand) and stores the result in the 16-bit register Rd. Available Registers Rd: R0 to R7, E0 to E7 Rs: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Instruction Format Mnemonic Operands Immediate XOR.W #xx:16, Rd 7 9 5 rd Register direct XOR.W Rs, Rd 6 5 rs rd 1st byte 2nd byte 3rd byte 4th byte IMM No. of States 2 1 Notes Rev. 4.00 Feb 24, 2006 page 243 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.70 (3) XOR (L) XOR (eXclusive OR logical) Exclusive Logical OR Condition Code Operation ERd (EAs) ERd U N Z V C -- -- -- -- I UI H 0 -- H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Assembly-Language Format XOR.L <EAs>, ERd Operand Size Longword Description This instruction exclusively ORs the source operand with the contents of a 32-bit register ERd (destination operand) and stores the result in the 32-bit register ERd. Available Registers ERd: ER0 to ER7 ERs: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Instruction Format Mnemonic Operands 1st byte 2nd byte Immediate XOR.L #xx:32, ERd 7 A 5 0 erd Register direct XOR.L ERs, ERd 0 1 F 0 Notes Rev. 4.00 Feb 24, 2006 page 244 of 322 REJ09B0139-0400 3rd byte 4th byte 5th byte IMM 6 5 0 ers 0 erd 6th byte No. of States 3 2 Section 2 Instruction Descriptions XORC XORC (eXclusive OR Control register) Exclusive Logical OR with CCR I: UI: H: U: N: Z: V: C: Assembly-Language Format XORC #xx:8, CCR Operand Size Byte H U N Z V C UI I CCR #IMM CCR Condition Code Operation 2.2.71 (1) Stores the corresponding bit of the result. Stores the corresponding bit of the result. Stores the corresponding bit of the result. Stores the corresponding bit of the result. Stores the corresponding bit of the result. Stores the corresponding bit of the result. Stores the corresponding bit of the result. Stores the corresponding bit of the result. Description This instruction exclusively ORs the contents of the condition-code register (CCR) with immediate data and stores the result in the condition-code register. No interrupt requests, including NMI, are accepted immediately after execution of this instruction. Operand Format and Number of States Required for Execution Addressing Mode Immediate Mnemonic Operands XORC #xx:8, CCR Instruction Format 1st byte 0 5 2nd byte IMM 3rd byte 4th byte No. of States 1 Notes Rev. 4.00 Feb 24, 2006 page 245 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.2.71 (2) XORC XORC (eXclusive OR Control register) Exclusive Logical OR with EXR Condition Code Operation EXR #IMM EXR I UI H U N Z V C -- -- -- -- -- -- -- -- H: N: Z: V: C: Assembly-Language Format XORC #xx:8, EXR Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Operand Size Byte Description This instruction exclusively ORs the contents of the extended control register (EXR) with immediate data and stores the result in the extended control register. No interrupt requests, including NMI, are accepted for three states after execution of this instruction. Operand Format and Number of States Required for Execution Addressing Mode Immediate Mnemonic Operands XORC #xx:8, EXR Notes Rev. 4.00 Feb 24, 2006 page 246 of 322 REJ09B0139-0400 Instruction Format 1st byte 2nd byte 3rd byte 0 4 0 1 1 5 4th byte No. of States IMM 2 MOV W W W W W W W W W W W W W MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 B W MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd B B B MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd B B MOV.B Rs,@(d:16,ERd) MOV.B Rs,@aa:16 B B MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@aa:8 B B B MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd B B MOV.B @(d:16, ERs), Rd MOV.B @aa:16,Rd B MOV.B @ERs,Rd MOV.B @aa:8,Rd B B Size MOV.B #xx:8,Rd MOV.B Rs,Rd Mnemonic #xx 4 2 Rn 2 2 @ERn 2 2 2 2 @(d,ERn) 8 4 8 4 8 4 8 4 @-ERn/@ERn+ 2 2 2 2 2 @aa 4 6 6 4 6 4 2 6 4 Rs16@aa:16 Rs16@aa:32 ERd32-2ERd32,Rs16@ERd Rs16@(d:32,ERd) Rs16@ERd Rs16@(d:16,ERd) @aa:32Rd16 @ERsRd16,ERs32+2@ERs32 @aa:16Rd16 @(d:32,ERs)Rd16 @ERsRd16 @(d:16,ERs)Rd16 Rs16Rd16 Rs8@aa:32 #xx:16Rd16 Rs8@aa:16 Rs8@aa:8 Rd8@(d:32,ERd) ERd32-1ERd32,Rs8@ERd Rd8@(d:16,ERd) @aa:32Rd8 Rs8@ERd @aa:16Rd8 @aa:8Rd8 @(d:32,ERs)Rd8 @ERsRd8,ERs32+1ERs32 @(d:16,ERs)Rd8 @ERsRd8 #xx:8Rd8 Rs8Rd8 Operation I -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 V Z N Condition Code C -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 3 4 3 5 2 3 4 3 3 5 2 3 1 4 2 3 2 5 3 3 4 2 3 2 5 3 3 2 1 1 No. of States*1 Table 2.1 @@aa @(d,PC) Addressing Mode and Instruction Length (Bytes) Normal 2.3 Advanced (1) Data Transfer Instructions Section 2 Instruction Descriptions Instruction Set Instruction Set Rev. 4.00 Feb 24, 2006 page 247 of 322 REJ09B0139-0400 -- L L L MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 L L STM.L (ERm-ERn),@-SP MOVFPE@aa:16,Rd MOVTPE Rs,@aa:16 LDM STM MOVFPE MOVTPE B B L W PUSH.W Rn PUSH.L ERn LDM.L @SP+,(ERm-ERn) PUSH W L L MOV.L ERs,@(d:32,ERd) POP.W Rn POP.L ERn L L L MOV.L @aa:16,ERd MOV.L @aa:32,ERd L L MOV.L @ERs+,ERd MOV.L ERs,@(d:16,ERd) L L MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L ERs,@ERd L L L MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd POP MOV #xx 6 Rn 2 @ERn 4 4 @(d,ERn) 10 6 6 10 @-ERn/@ERn+ 4 4 @aa ERs32@(d:32,ERd) ERs32@(d:16,ERd) ERs32@ERd @aa:16ERd32 @aa:32ERd32 @ERsERd32,ERs32+4@ERs32 4 4 4 4 4 2 SP-4SP,ERn32@SP (@SPERn32,SP+4SP) Repeated for each register restored (SP-4SP,ERn32@SP) Repeated for each register saved @aa:16Rd (synchronized with E clock) Rs@aa:16 (synchronized with E clock) SP-2SP,Rn16@SP @SPRn16,SP+2SP @SPERn32,SP+4SP ERs32@aa:32 @(d,PC) 8 @@aa 6 2 4 -- ERd32-4ERd32,ERs32@ERd ERs32@aa:16 6 8 @(d:16,ERs)ERd32 @(d:32,ERs)ERd32 #xx:32ERd32 ERs32ERd32 @ERsERd32 Operation I -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- H N -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- -- 0 0 -- -- -- C -- -- -- V Z Size Mnemonic Condition Code Rev. 4.00 Feb 24, 2006 page 248 of 322 REJ09B0139-0400 Normal (1) (1) 7/9/11*3 5 7/9/11*3 3 3 5 5 6 5 7 5 4 5 6 5 5 7 3 1 4 No. of States*1 Advanced Addressing Mode and Instruction Length (Bytes) Section 2 Instruction Descriptions DEC SUBS SUBX L L DEC.L #1,ERd DEC.L #2,ERd DEC.W #2,Rd W W DEC.W #1,Rd L B SUBS #4,ERd DEC.B Rd L L B SUBX Rs,Rd SUBS #1,ERd SUBS #2,ERd B SUBX #xx:8,Rd L W L SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd B W SUB.B Rs,Rd SUB.W #xx:16,Rd B DAA Rd L L INC.L #1,ERd INC.L #2,ERd SUB W INC.W #2,Rd DAA B W L ADDS #4,ERd INC.B Rd INC.W #1,Rd L ADDS #2,ERd INC B L ADDX Rs,Rd ADDS #1,ERd ADDS ADD.L ERs,ERd B L ADD.L #xx:32,ERd ADDX #xx:8,Rd L ADD.W Rs,Rd ADDX W W ADD.W #xx:16,Rd B B ADD.B #xx:8,Rd ADD.B Rs,Rd #xx 2 6 4 2 6 4 2 Rn 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 I -- ERd32-1ERd32 ERd32-2ERd32 Rd16-1Rd16 Rd16-2Rd16 Rd8-1Rd8 ERd32-1ERd32 ERd32-2ERd32 ERd32-4ERd32 Rd8-Rs8-CRd8 Rd8-#xx:8-CRd8 ERd32-ERs32ERd32 Rd16-Rs16Rd16 ERd32-#xx:32ERd32 * -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- (3) -- (2) -- (3) (4) -- -- -- -- -- -- -- -- -- -- 1 1 1 -- -- -- -- -- -- -- -- -- 1 -- -- -- -- -- -- (4) 1 2 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 1 1 -- -- -- -- -- -- -- -- 1 1 1 1 3 1 2 1 1 No. of States*1 * -- -- -- -- -- -- -- -- -- C V (4) -- -- (4) Z N -- -- -- -- (2) Rd8 decimal adjust Rd8 -- -- -- -- -- -- -- -- -- (3) -- (3) -- (2) -- -- Rd8-Rs8Rd8 Rd16-#xx:16Rd16 H -- (2) -- -- ERd32+1ERd32 ERd32+2ERd32 Rd16+2Rd16 Rd8+1Rd8 Rd16+1Rd16 ERd32+4ERd32 ERd32+2ERd32 Rd8+Rs8+CRd8 ERd32+1ERd32 Rd8+#xx:8+CRd8 ERd32+ERs32ERd32 ERd32+#xx:32ERd32 Rd16+Rs16Rd16 Rd16+#xx:16Rd16 Rd8+#xx:8Rd8 Rd8+Rs8Rd8 ADD Operation Size Mnemonic Condition Code Normal @@aa @(d,PC) @aa @-ERn/@ERn+ @(d,ERn) @ERn Addressing Mode and Instruction Length (Bytes) Advanced (2) Arithmetic Operation Instructions Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 249 of 322 REJ09B0139-0400 -- TAS EXTS EXTU NEG CMP DIVXS DIVXU L B EXTS.L ERd *8 TAS @ERd 2 2 L W 2 2 2 L W 2 2 2 2 NEG.L ERd 6 EXTU.W Rd EXTU.L ERd EXTS.W Rd L L CMP.L #xx:32,ERd CMP.L ERs,ERd 4 2 B W W CMP.W Rs,Rd #xx 2 4 4 2 2 4 4 2 2 2 Rn NEG.B Rd NEG.W Rd B B W W DIVXS.W Rs,ERd CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd B W DIVXU.W Rs,ERd DIVXS.B Rs,Rd B W MULXS.W Rs,ERd DIVXU.B Rs,Rd B W MULXS.B Rs,Rd MULXU.W Rs,ERd MULXS B MULXU.B Rs,Rd MULXU B DAS Rd DAS @ERn 4 0(<bits 31 to 16> of ERd32) (<bit 7> of Rd16)(<bits 15 to 8> of Rd16) (<bit 15> of ERd32)(<bits 31 to 16> of ERd32) @ERd-0set CCR, 1(<bit 7> of @ERd) 0-ERd32ERd32 0(<bits 15 to 8> of Rd16) 0-Rd16Rd16 0-Rd8Rd8 ERd32-#xx:32 ERd32-ERs32 Rd16-Rs16 Rd8xRs8Rd16 (signed multiplication) Rd16xRs16ERd32 (signed multiplication) Rd16/Rs8Rd16 (RdH: remainder, RdL: quotient) (unsigned division) ERd32/Rs16ERd32 (Ed: remainder, Rd: quotient) (unsigned division) Rd16/Rs8Rd16 (RdH: remainder, RdL: quotient) (signed division) ERd32/Rs16ERd32 (Ed: remainder, Rd: quotient) (signed division) Rd8-#xx:8 Rd8-Rs8 Rd16-#xx:16 Rd16xRs16ERd32 (unsigned multiplication) Rd8xRs8Rd16 (unsigned multiplication) Rd8 decimal adjust Rd8 I H -- -- -- -- -- -- -- V -- -- -- -- * C 1 1 1 1 1 -- -- -- -- 0 0 0 -- -- -- -- -- 0 0 0 0 -- 1 1 2 4 1 1 1 3 1 1 21 13 20 3 (12*7) *4 *10 4 (20*7) *4 *10 4 (13*7) *5 *10 5 (21*7) *5 *10 12 -- -- -- -- -- -- -- -- -- No. of States*1 -- (7) (6) -- -- (7) (6) -- -- (5) (6) -- -- (3) -- (3) -- -- -- Z -- (5) (6) -- -- -- -- (2) -- -- N -- -- * -- -- -- (2) -- -- -- -- -- -- -- -- -- Condition Code Operation Size Mnemonic Normal Rev. 4.00 Feb 24, 2006 page 250 of 322 REJ09B0139-0400 Advanced @@aa @(d,PC) @aa @-ERn/@ERn+ @(d,ERn) Addressing Mode and Instruction Length (Bytes) Section 2 Instruction Descriptions -- L L L STMAC*9 LDMAC ERs,MACL STMAC MACH,ERd STMAC MACL,ERd -- -- L MAC @ERn+,@ERm+ CLRMAC*9 CLRMAC LDMAC*9 LDMAC ERs,MACH MAC*9 Size Rn 2 2 2 2 @-ERn/@ERn+ 4 -- 2 ERsMACL MACHERd MACLERd 0MACH, MACL ERsMACH @ERnx@ERm+MACMAC (signed multiplication) ERn+2ERn,ERm+2ERm Operation I -- -- -- -- -- -- H N Z V C -- -- -- -- -- -- -- -- 2*6 *10 2*6 *10 2*6 *10 1*6 *10 1*6 *10 -- -- -- -- -- -- -- 4 No. of States*1 -- -- -- -- -- -- -- -- -- (8) (8) (8) Mnemonic Condition Code Normal Advanced @@aa @(d,PC) @aa @(d,ERn) @ERn #xx Addressing Mode and Instruction Length (Bytes) Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 251 of 322 REJ09B0139-0400 Rev. 4.00 Feb 24, 2006 page 252 of 322 REJ09B0139-0400 NOT XOR OR AND W L L B W L XOR.L ERs,ERd NOT.B Rd NOT.W Rd NOT.L ERd L B OR.L ERs,ERd XOR.B #xx:8,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd L OR.L #xx:32,ERd B W OR.W Rs,Rd W B W OR.B Rs,Rd OR.W #xx:16,Rd XOR.W #xx:16,Rd W L L B AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd OR.B #xx:8,Rd XOR.B Rs,Rd B B W AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd Size #xx 6 4 2 6 4 2 6 4 2 Rn 2 2 4 2 2 2 4 2 2 4 2 2 Rd16Rd16 Rd32Rd32 ERd32ERs32ERd32 Rd8Rd8 Rd16Rs16Rd16 ERd32#xx:32ERd32 Rd16#xx:16Rd16 Rd8Rs8Rd8 ERd32ERs32ERd32 Rd8#xx:8Rd8 ERd32#xx:32ERd32 Rd16Rs16Rd16 Rd8Rs8Rd8 Rd16#xx:16Rd16 Rd16Rs16Rd16 ERd32#xx:32ERd32 ERd32ERs32ERd32 Rd8#xx:8Rd8 Rd8#xx:8Rd8 Rd8Rs8Rd8 Rd16#xx:16Rd16 Operation I -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- H -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 V Z N Mnemonic Condition Code C -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 2 1 1 3 2 1 2 1 3 1 1 2 1 3 2 1 1 1 2 No. of States*1 Normal @@aa @(d,PC) @aa @-ERn/@ERn+ @(d,ERn) @ERn Addressing Mode and Instruction Length (Bytes) Advanced (3) Logic Operation Instructions Section 2 Instruction Descriptions -- ROTXL SHLR SHLL SHAR SHAL @-ERn/@ERn+ @(d,ERn) @ERn C 0 0 C C -- -- -- -- -- -- -- W L L 2 2 2 2 W ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd 2 MSB LSB -- -- -- -- -- -- -- -- -- -- LSB LSB LSB LSB 2 2 2 MSB MSB MSB MSB -- -- -- -- -- -- 0 C C I -- 2 2 2 2 2 2 2 2 2 2 2 2 L L SHLR.L ERd SHLR.L #2,ERd #xx B B B W W SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd ROTXL.B Rd L B @aa -- -- @(d,PC) 2 2 @@aa -- -- -- -- -- 2 2 2 2 2 2 2 2 Rn ROTXL.B #2,Rd ROTXL.W Rd L SHLL.L #2,ERd SHLR.B Rd L B SHAR.L #2,ERd SHLL.B Rd SHLL.L ERd L SHAR.L ERd B B W W SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd W W L L B SHAL.L ERd SHAL.L #2,ERd SHAR.B Rd SHLL.W Rd SHLL.W #2,Rd B W W SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHLL.B #2,Rd B SHAL.B Rd Operation H -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 V Z N Size Mnemonic C Condition Code 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 No. of States*1 Normal Addressing Mode and Instruction Length (Bytes) Advanced (4) Shift Instructions Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 253 of 322 REJ09B0139-0400 Rev. 4.00 Feb 24, 2006 page 254 of 322 REJ09B0139-0400 ROTR ROTL ROTXR W L L ROTR.L #2,ERd W W L L ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR.W #2,Rd ROTR.L ERd L B B ROTXR.L #2,ERd ROTL.B Rd ROTL.B #2,Rd B B W W W L ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd B B ROTXR.B Rd ROTXR.B #2,Rd Rn 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 C MSB MSB MSB Operation LSB LSB LSB C C -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- H -- -- -- -- -- -- -- -- -- I 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 V Z N Size Mnemonic C Condition Code 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 No. of States*1 Advanced Normal @@aa @(d,PC) @aa @-ERn/@ERn+ @(d,ERn) @ERn #xx Addressing Mode and Instruction Length (Bytes) Section 2 Instruction Descriptions -- BNOT BCLR BSET B B B B B B B BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BNOT #xx:3,Rd BNOT #xx:3,@ERd B B B B BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 B B B B B B BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BNOT #xx:3,@aa:8 B B B B BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 B B B B B BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BCLR #xx:3,Rd B B B BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 B Size BSET #xx:3,Rd Mnemonic Rn 2 2 2 2 2 2 @ERn 4 4 4 4 4 4 @aa (#xx:3 of @ERd)0 (#xx:3 of @aa:8)0 (#xx:3 of @aa:16)0 (#xx:3 of Rd8)0 (Rn8 of @aa:8)1 (Rn8 of @aa:16)1 (Rn8 of @aa:32)1 (Rn8 of Rd8)1 (Rn8 of @ERd)1 8 4 6 6 8 4 8 I H N -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- (Rn8 of @ERd) [ (Rn8 of @ERd)] (Rn8 of @aa:8) [ (Rn8 of @aa:8)] (Rn8 of @aa:16) [ (Rn8 of @aa:16)] (Rn8 of @aa:32) [ (Rn8 of @aa:32)] -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- (#xx:3 of @aa:16) [ (#xx:3 of @aa:16)] -- (#xx:3 of @aa:32) [ (#xx:3 of @aa:32)] -- (Rn8 of Rd8) [ (Rn8 of Rd8)] -- (Rn8 of @aa:32)0 (#xx:3 of Rd8) [ (#xx:3 of Rd8)] (#xx:3 of @ERd) [ (#xx:3 of @ERd)] (#xx:3 of @aa:8) [ (#xx:3 of @aa:8)] (Rn8 of @aa:8)0 (Rn8 of @aa:16)0 @(d,PC) 4 6 @@aa (#xx:3 of @aa:32)0 (Rn8 of Rd8)0 (Rn8 of @ERd)0 -- 8 4 6 4 6 8 4 6 8 (#xx:3 of @ERd)1 (#xx:3 of @aa:8)1 (#xx:3 of @aa:16)1 (#xx:3 of @aa:32)1 (#xx:3 of Rd8)1 Operation -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Z -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- V Condition Code C 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 6 4 4 5 5 6 1 6 1 4 4 4 5 6 1 4 4 4 5 1 5 6 -- -- -- 1 4 4 4 4 5 6 -- -- -- -- -- -- -- -- No. of States*1 Normal @-ERn/@ERn+ @(d,ERn) #xx Addressing Mode and Instruction Length (Bytes) Advanced (5) Bit Manipulation Instructions Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 255 of 322 REJ09B0139-0400 Rev. 4.00 Feb 24, 2006 page 256 of 322 REJ09B0139-0400 BIST BST BILD BLD BTST B B B B B B B BLD #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 B B B B B B B BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 B B B BTST Rn,@aa:16 BTST Rn,@aa:32 BLD #xx:3,Rd B B B B BTST Rn,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BIST #xx:3,Rd B B BTST Rn,Rd BTST Rn,@ERd B B B B B BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 B B BTST #xx:3,Rd BTST #xx:3,@ERd Size Rn 2 2 2 2 2 2 @ERn 4 4 4 4 4 @(d,ERn) 4 @aa (Rn8 of @aa:8)Z (Rn8 of @ERd)Z (#xx:3 of @aa:8)Z (#xx:3 of @aa:16)Z (#xx:3 of @aa:32)Z (Rn8 of Rd8)Z C(#xx:3 of @aa:32) C(#xx:3 of Rd8) C(#xx:3 of @ERd24) C(#xx:3 of @aa:8) C(#xx:3 of @aa:16) C(#xx:3 of @aa:32) 4 6 8 C(#xx:3 of @ERd24) C(#xx:3 of @aa:8) C(#xx:3 of @aa:16) (#xx:3 of @aa:16)C (#xx:3 of @aa:32)C C(#xx:3 of Rd8) 8 4 6 6 8 4 (#xx:3 of Rd8)C (#xx:3 of @ERd)C (#xx:3 of @aa:8)C (#xx:3 of @aa:8)C (#xx:3 of @aa:16)C (#xx:3 of @aa:32)C @(d,PC) 4 6 8 @@aa (Rn8 of @aa:16)Z (Rn8 of @aa:32)Z (#xx:3 of Rd8)C (#xx:3 of @ERd)C -- 6 8 4 4 6 8 (#xx:3 of Rd8)Z (#xx:3 of @ERd)Z Operation I -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- H N -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- V -- -- Z Mnemonic C -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Condition Code 4 5 6 6 1 4 4 4 5 3 4 5 1 5 1 3 3 3 4 4 5 1 3 3 3 4 5 1 1 3 No. of States*1 Advanced Normal @-ERn/@ERn+ #xx Addressing Mode and Instruction Length (Bytes) Section 2 Instruction Descriptions BIXOR BXOR BIOR BOR BIAND BAND B B B B BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 B BXOR #xx:3,@aa:32 BIXOR #xx:3,@ERd B B BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 B B BXOR #xx:3,@ERd BIXOR #xx:3,Rd B BXOR #xx:3,Rd B B BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 B B BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BOR #xx:3,@aa:32 B B BOR #xx:3,@aa:16 BIOR #xx:3,Rd B B BOR #xx:3,@aa:8 B B B B BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BOR #xx:3,Rd B BIAND #xx:3,@aa:8 BOR #xx:3,@ERd B B B B BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BIAND #xx:3,Rd B B BAND #xx:3,@ERd BAND #xx:3,@aa:8 BIAND #xx:3,@ERd B Size BAND #xx:3,Rd Mnemonic Rn 2 2 2 2 2 2 @ERn 4 4 4 4 4 4 4 @aa 6 8 4 8 4 6 8 6 4 8 6 4 6 8 4 6 8 I C [ (#xx:3 of @aa:16)]C C [ (#xx:3 of @aa:32)]C -- -- -- C [ (#xx:3 of @ERd24)]C C [ (#xx:3 of @aa:8)]C C [ (#xx:3 of @aa:16)]C C[ (#xx:3 of @aa:16)]C C[ (#xx:3 of @aa:32)]C C[ (#xx:3 of @aa:8)]C C[ (#xx:3 of @ERd24)]C C[ (#xx:3 of Rd8)]C C(#xx:3 of @aa:32)C C(#xx:3 of @aa:8)C C(#xx:3 of @aa:16)C C(#xx:3 of @ERd24)C C(#xx:3 of Rd8)C -- -- -- -- -- -- -- -- -- -- -- -- C [ (#xx:3 of Rd8)]C C [ (#xx:3 of @aa:32)]C -- -- -- -- C(#xx3: of @aa:32)C C(#xx3: of @aa:16)C C(#xx3: of @aa:8)C C(#xx:3 of @ERd24)C -- -- -- -- C [ (#xx:3 of @aa:8)]C C(#xx:3 of Rd8)C -- -- C [ (#xx:3 of Rd8)]C C [ (#xx:3 of @ERd24)]C -- -- -- -- -- C(#xx:3 of @aa:16)C C(#xx:3 of @aa:32)C C(#xx:3 of @ERd24)C C(#xx:3 of @aa:8)C C(#xx:3 of Rd8)C Operation H N -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Z -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- V -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- C Condition Code 4 5 3 3 1 5 3 4 3 1 5 4 3 3 1 5 4 3 3 1 4 5 3 3 1 4 5 3 3 1 No. of States*1 Advanced Normal @@aa @(d,PC) @-ERn/@ERn+ @(d,ERn) #xx Addressing Mode and Instruction Length (Bytes) Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 257 of 322 REJ09B0139-0400 -- Bcc -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BRA d:16(BT d:16) BRN d:8(BF d:8) BRN d:16(BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8(BHS d:8) BCC d:16(BHS d:16) BCS d:8(BLO d:8) BCS d:16(BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 Size BRA d:8(BT d:8) Mnemonic @(d,PC) Rev. 4.00 Feb 24, 2006 page 258 of 322 REJ09B0139-0400 2 4 4 2 4 2 4 2 4 2 2 4 4 4 2 2 2 4 4 4 2 4 2 2 4 2 2 4 4 4 2 2 PCPC+d else next; if condition is true then Operation I Z(NV)=1 Z(NV)=0 -- NV=1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- NV=0 N=1 N=0 V=1 V=0 Z=1 Z=0 C=1 C=0 Cz=1 Cz=0 Never Always Branch Condition N -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- H -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Z -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- V Condition Code C -- -- -- -- -- -- 2 3 3 3 2 2 2 3 3 -- -- -- 2 3 2 3 3 2 2 2 3 3 3 2 3 2 2 3 2 2 3 3 3 2 2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- No. of States*1 Normal @@aa @aa @-ERn/@ERn+ @(d,ERn) @ERn Rn #xx Addressing Mode and Instruction Length (Bytes) Advanced (6) Branch Instructions Section 2 Instruction Descriptions -- RTS JSR BSR JMP -- -- -- -- -- -- -- -- -- JMP @@aa:8 BSR d:8 BSR d:16 JSR @ERn JSR @aa:24 JSR @@aa:8 RTS Size JMP @ERn JMP @aa:24 Mnemonic @ERn 2 2 @aa 4 4 @(d,PC) 2 4 @@aa 2 2 -- 2 PC@aa:8 PC@-SP,PCPC+d:8 PC@-SP,PCPC+d:16 PC@-SP,PCERn PC@-SP,PCaa:24 PC@-SP,PCaa:8 PC@SP+ PCErn PCaa:24 Operation Branch Condition I -- -- -- -- -- -- -- -- -- N -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- H -- -- -- -- -- -- -- -- -- Z -- -- -- -- -- -- -- -- -- V Condition Code C -- -- -- -- -- -- -- -- -- Normal 4 3 4 3 4 4 4 2 3 No. of States*1 5 4 5 4 5 6 5 Advanced @-ERn/@ERn+ @(d,ERn) Rn #xx Addressing Mode and Instruction Length (Bytes) Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 259 of 322 REJ09B0139-0400 B B B B W SLEEP LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR SLEEP LDC W W W W W W LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR W W LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,EXR W LDC @(d:16,ERs),EXR LDC @ERs+,CCR W W LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR -- -- RTE RTE #xx 4 2 2 Rn 2 @ERn 4 4 6 @(d,ERn) 10 10 6 4 @-ERn/@ERn+ 4 -- @ERsEXR,ERs32+2ERs32 @ERsCCR,ERs32+2ERs32 @(d:32,ERs)CCR @(d:32,ERs)EXR @(d:16,ERs)EXR @ERsEXR @(d:16,ERs)CCR Rs8EXR @ERsCCR #xx:8EXR Rs8CCR #xx:8CCR Transition to power-down state PC@-SP,CCR@-SP, EXR@-SP,<vector>PC EXR@SP+,CCR@SP+, PC@SP+ @aa:32CCR @aa:32EXR @aa 8 8 @(d,PC) @aa:16CCR @aa:16EXR @@aa 6 6 2 Z V -- N -- H -- -- I 1 C 1 2 1 -- -- -- -- -- -- 2 -- -- -- -- -- -- 5[9]*7 -- 7[9] *7 8[9]*7 1 3 3 4 -- -- -- -- -- -- -- -- -- -- -- -- 4 4 4 4 5 5 -- -- -- -- -- -- 6 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRAPA #x:2 TRAPA Operation No. of States*1 Size Rev. 4.00 Feb 24, 2006 page 260 of 322 REJ09B0139-0400 Mnemonic Condition Code Normal Addressing Mode and Instruction Length (Bytes) Advanced (7) System Control Instructions Section 2 Instruction Descriptions NOP XORC ORC ANDC STC W W W W W STC CCR,@-ERd STC EXR,@-ERd STC CCR,@aa:16 STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 XORC #xx:8,EXR NOP B -- B B ORC #xx:8,EXR XORC #xx:8,CCR B ORC #xx:8,CCR B W STC EXR,@(d:32,ERd) ANDC #xx:8,EXR W STC CCR,@(d:32,ERd) B W STC EXR,@(d:16,ERd) ANDC #xx:8,CCR W W STC CCR,@(d:16,ERd) B B W W STC CCR,Rd STC EXR,Rd STC CCR,@ERd STC EXR,@ERd Size #xx 4 2 4 2 4 2 Rn 2 2 @ERn 4 4 6 @(d,ERn) 10 10 6 @-ERn/@ERn+ 4 4 @aa 8 8 6 6 -- 2 EXR#xx:8EXR PCPC+2 CCR#xx:8CCR EXR#xx:8EXR CCR#xx:8CCR EXR#xx:8EXR CCR#xx:8CCR EXR@aa:32 CCR@aa:32 EXR@aa:16 CCR@aa:16 ERd32-2ERd32,EXR@ERd ERd32-2ERd32,CCR@ERd EXR@(d:32,ERd) CCR@(d:32,ERd) EXR@(d:16,ERd) CCR@(d:16,ERd) CCRRd8 EXRRd8 CCR@ERd EXR@ERd Operation I -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- H N -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Z -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- V -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- C -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2 1 1 -- -- -- -- -- -- -- -- -- -- -- -- 2 -- -- -- -- -- 1 2 1 5 5 4 4 4 4 6 6 4 4 1 1 3 3 -- Mnemonic No. of States*1 Normal Condition Code Advanced @@aa @(d,PC) Addressing Mode and Instruction Length (Bytes) Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 261 of 322 REJ09B0139-0400 Rev. 4.00 Feb 24, 2006 page 262 of 322 REJ09B0139-0400 7. 8. 9. 10. (1) (2) (3) (4) (5) (6) (7) (8) (9) 6. 5. Notes: 1. 2. 3. 4. EEPMOV @(d,ERn) @ERn Rn #xx if R4L 0 Repeat @ER5+@ER6+ ER5+1ER5 ER6+1ER6 R4L-1R4L Until R4L=0 else next; if R4 0 Repeat @ER5+@ER6+ ER5+1ER5 ER6+1ER6 R4-1 4 Until R4=0 else next; Operation I -- -- H N -- -- -- -- Z -- -- V -- -- C -- -- No. of States*1 4+2n*2 4+2n*2 The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. n is the initial setting of R4L or R4. Seven states for saving or restoring two registers, nine states for three registers, or eleven states for four registers. One additional state is required for execution immediately after a MULXU, MULXS, or STMAC instruction. Also, a maximum of three additional states are required for execution of a MULXU instruction within three states after execution of a MAC instruction. For example, if there is a one-state instruction (such as NOP) between a MAC instruction and a MULXU instruction, the MULXU instruction will be two states longer. A maximum of two additional states are required for execution of a MULXS instruction within two states after execution of a MAC instruction. For example, if there is a one-state instruction (such as NOP) between a MAC instruction and a MULXS instruction, the MULXS instruction will be one state longer. A maximum of three additional states are required for execution of one of these instructions within three states after execution of a MAC instruction. For example, if there is a one-state instruction (such as NOP) between a MAC instruction and one of these instructions, that instruction will be two states longer. Values in parentheses ( ) are for the H8S/2000 CPU. Values in square brackets [ ] apply to interrupt control modes 2 and 3. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. These instructions are supported only by the H8S/2600 CPU. The number of states may differ depending on the product. For details, refer to the relevant microcontroller hardware manual of the product in question. The number of states required for execution of an instruction that transfers data in synchronization with the E clock is variable. Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. Retains its previous value when the result is zero; otherwise cleared to 0. Set to 1 when the divisor is negative; otherwise cleared to 0. Set to 1 when the divisor is zero; otherwise cleared to 0. Set to 1 when the quotient is negative; otherwise cleared to 0. MAC instruction results are indicated in the flags when the STMAC instruction is executed. One additional state is required for execution when EXR is valid. 4 @-ERn/@ERn+ -- @aa EEPMOV.W @(d,PC) 4 @@aa -- Size -- EEPMOV.B Mnemonic Condition Code Normal Addressing Mode and Instruction Length (Bytes) Advanced (8) Block Transfer Instructions Section 2 Instruction Descriptions Bcc BAND ANDC AND ADDX AND.L ERs,ERd -- -- -- -- -- -- -- -- BRN d:16 (BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) B BAND #xx:3,@aa:32 BRN d:8 (BF d:8) B BAND #xx:3,@aa:16 BRA d:16 (BT d:16) B BAND #xx:3,@aa:8 -- B BAND #xx:3,@ERd BRA d:8 (BT d:8) B BAND #xx:3,Rd B AND.L #xx:32,ERd B L L AND.W Rs,Rd ANDC #xx:8,EXR W AND.W #xx:16,Rd ANDC #xx:8,CCR B W AND.B Rs,Rd B B ADDX Rs,Rd AND.B #xx:8,Rd B ADDX #xx:8,Rd L ADDS #4,ERd ADD.L ERs,ERd L ADD.L #xx:32,ERd L L L ADD.W Rs,Rd ADDS #2,ERd W ADD.W #xx:16,Rd 4 8 5 4 3 8 2 8 1 8 0 A A E C 6 1 6 1 A 6 9 6 rd E rd B B B A A 9 9 8 rd 4 5 4 5 4 5 4 6 6 7 7 7 0 0 0 7 6 7 1 E 0 9 0 0 0 0 7 0 7 0 8 1st byte 0 erd rd rd rd IMM 3 2 1 0 3 1 disp disp disp disp disp abs 0 erd rd rd rd 0 0 0 0 0 0 0 rd 1 0 0 erd IMM rd 0 erd 0 erd 0 erd IMM 0 IMM 4 F 6 rs 6 rs rs 9 8 0 1 ers 0 erd 1 rs 1 rs IMM 2nd byte 7 7 0 6 6 6 6 6 3rd byte IMM IMM disp disp disp disp abs 0 IMM 0 IMM IMM 0 0 abs 0 ers 0 erd IMM IMM 4th byte 7 6 0 IMM 0 6th byte Instruction Format 5th byte 7 6 7th byte 0 IMM 0 8th byte 9th byte 10th byte Table 2.2 ADDS #1,ERd B W ADD.B Rs,Rd B Size ADD.B #xx:8,Rd Mnemonic 2.4 ADDS ADD Instruction Section 2 Instruction Descriptions Instruction Code Instruction Codes Rev. 4.00 Feb 24, 2006 page 263 of 322 REJ09B0139-0400 Rev. 4.00 Feb 24, 2006 page 264 of 322 REJ09B0139-0400 BCLR Bcc Instruction -- BLE d:16 B -- BLE d:8 BCLR Rn,@aa:32 -- BGT d:16 B -- BGT d:8 BCLR Rn,@aa:16 -- BLT d:16 B -- BLT d:8 B -- BGE d:16 BCLR Rn,@aa:8 -- BGE d:8 BCLR Rn,@ERd -- BMI d:16 B -- BMI d:8 BCLR Rn,Rd -- BPL d:16 B -- BPL d:8 BCLR #xx:3,@aa:32 -- BVS d:16 B -- BVS d:8 BCLR #xx:3,@aa:16 -- BVC d:16 B -- BVC d:8 B -- BEQ d:16 BCLR #xx:3,@aa:8 -- BEQ d:8 BCLR #xx:3,@ERd -- BNE d:16 B 4 -- BNE d:8 BCLR #xx:3,Rd 5 -- BCS d:16 (BLO d:16) 8 6 6 7 7 6 6 6 7 7 7 5 4 5 4 5 4 5 4 5 A A F D 2 A A F D 2 8 F 8 E 8 D 8 C 8 B 8 A 5 4 9 8 8 8 7 8 6 8 5 8 4 5 4 5 4 5 4 5 4 -- BCS d:8 (BLO d:8) 5 1st byte -- Size BCC d:16 (BHS d:16) Mnemonic disp disp disp disp disp disp disp disp disp disp disp 3 1 abs 0 erd rn 3 1 abs 0 erd 0 IMM F E D C B A 9 8 7 6 5 4 8 8 0 rd 8 8 0 rd 0 0 0 0 0 0 0 0 0 0 0 0 2nd byte 6 6 7 7 2 2 2 2 3rd byte abs abs rn rn 0 IMM 0 IMM disp disp disp disp disp disp disp disp disp disp disp disp 0 0 0 0 4th byte abs abs 6 7 2 2 rn 0 IMM 0 0 6th byte Instruction Format 5th byte 6 7 2 2 7th byte rn 0 IMM 0 0 8th byte 9th byte 10th byte Section 2 Instruction Descriptions BNOT BLD BIXOR BIST BIOR BILD BIAND Instruction B B B B B BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd B BLD #xx:3,@aa:32 BNOT #xx:3,@ERd B BLD #xx:3,@aa:16 B B BNOT #xx:3,Rd B BLD #xx:3,@aa:8 B BIXOR #xx:3,@aa:32 BLD #xx:3,@ERd B BIXOR #xx:3,@aa:16 B B BLD #xx:3,Rd B BIXOR #xx:3,@aa:8 B BIST #xx:3,@aa:32 BIXOR #xx:3,@ERd B BIST #xx:3,@aa:16 B B BIXOR #xx:3,Rd B BIST #xx:3,@aa:8 B BIOR #xx:3,@aa:32 BIST #xx:3,@ERd B BIOR #xx:3,@aa:16 B B BIST #xx:3,Rd B BIOR #xx:3,@aa:8 B BILD #xx:3,@aa:32 BIOR #xx:3,@ERd B BILD #xx:3,@aa:16 B B BIOR #xx:3,Rd B B BIAND #xx:3,@aa:32 BILD #xx:3,@aa:8 B BIAND #xx:3,@aa:16 BILD #xx:3,@ERd B BIAND #xx:3,@aa:8 B B BIAND #xx:3,@ERd BILD #xx:3,Rd B Size BIAND #xx:3,Rd Mnemonic 6 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 6 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 1 A A F D 1 A A E C 7 A A E C 5 A A F D 7 A A E C 4 A A E C 7 A A E C 6 1st byte rn rd 8 8 1 0 rd 0 0 0 rd 0 0 0 rd 8 8 0 rd 0 0 0 rd 0 0 0 rd 0 0 0 rd 3 abs 0 erd 0 IMM 3 1 abs 0 erd 0 IMM 3 1 abs 0 erd 1 IMM 3 1 abs 0 erd 1 IMM 3 1 abs 0 erd 1 IMM 3 1 abs 0 erd 1 IMM 3 1 abs 0 erd 1 IMM 2nd byte 7 7 7 7 7 7 6 6 7 7 7 7 7 7 1 1 7 7 5 5 7 7 4 4 7 7 6 6 3rd byte abs 0 IMM 0 IMM abs 0 IMM 0 IMM abs 1 IMM 1 IMM abs 1 IMM 1 IMM abs 1 IMM 1 IMM abs 1 IMM 1 IMM abs 1 IMM 1 IMM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4th byte abs abs abs abs abs abs abs 7 7 7 6 7 7 7 1 7 5 7 4 7 6 0 IMM 0 IMM 1 IMM 1 IMM 1 IMM 1 IMM 1 IMM 0 0 0 0 0 0 0 6th byte Instruction Format 5th byte 7 7 7 6 7 7 7 1 7 5 7 4 7 6 7th byte 0 IMM 0 IMM 1 IMM 1 IMM 1 IMM 1 IMM 1 IMM 0 0 0 0 0 0 0 8th byte 9th byte 10th byte Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 265 of 322 REJ09B0139-0400 Rev. 4.00 Feb 24, 2006 page 266 of 322 REJ09B0139-0400 BTST BST BSR BSET BOR BNOT Instruction B B B B B BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 B B B B B B B B B BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 B BST #xx:3,@aa:32 BTST #xx:3,@aa:8 B BST #xx:3,@aa:16 BTST #xx:3,@ERd B BST #xx:3,@aa:8 B B BST #xx:3,@ERd BTST #xx:3,Rd B BST #xx:3,Rd -- B BSET #xx:3,@aa:32 BSR d:16 B BSET #xx:3,@aa:16 -- B BSR d:8 B BSET #xx:3,@aa:8 B BOR #xx:3,@aa:32 BSET #xx:3,@ERd B BOR #xx:3,@aa:16 B B BSET #xx:3,Rd B BOR #xx:3,@aa:8 B BNOT Rn,@aa:32 BOR #xx:3,@ERd B BNOT Rn,@aa:16 B B BNOT Rn,@aa:8 BOR #xx:3,Rd B Size BNOT Rn,@ERd Mnemonic 6 6 7 7 6 6 6 7 7 7 6 6 A A E C 3 A A E C 3 A A F D 7 7 7 C 5 A A F D 0 A A F D 0 A A E C 4 A A F D 6 5 5 6 6 7 7 6 6 6 7 7 7 6 6 7 7 7 6 6 7 7 1st byte abs disp 3 1 abs 0 erd rn 3 1 abs 0 erd 0 IMM 3 1 abs 0 erd 0 IMM 0 3 1 abs 0 erd rn 3 1 0 0 0 rd 0 0 0 rd 8 8 0 rd 0 8 8 0 rd 8 8 0 0 erd abs rd 0 0 0 rd 8 8 0 0 IMM 3 1 abs 0 erd 0 IMM 3 1 0 erd 2nd byte 6 6 7 7 6 6 6 6 7 7 7 7 6 6 3 3 3 3 7 7 0 0 0 0 4 4 1 1 3rd byte rn rn rn abs abs rn rn 0 IMM 0 IMM abs 0 IMM 0 IMM disp abs abs 0 IMM 0 IMM abs *1 0 IMM 0 IMM abs rn 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4th byte abs abs abs abs abs abs abs 6 7 6 6 7 7 6 3 3 7 0 0 4 1 rn 0 IMM 0 IMM rn 0 IMM 0 IMM rn 0 0 0 0 0 0 0 6th byte Instruction Format 5th byte 6 7 6 6 7 7 6 3 3 7 0 0 4 1 7th byte rn 0 IMM 0 IMM rn 0 IMM 0 IMM rn 0 0 0 0 0 0 0 8th byte 9th byte 10th byte Section 2 Instruction Descriptions B B B BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 INC EXTU EXTS EEPMOV DIVXU DIVXS B DEC.B Rd DEC B W W L L INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd L EXTU.L ERd INC.B Rd L W EXTS.L ERd EXTU.W Rd W -- EXTS.W Rd -- EEPMOV.B EEPMOV.W B W DIVXU.W Rs,ERd 0 0 0 0 0 1 1 1 1 7 7 5 5 0 DIVXU.B Rs,Rd 0 1 1 B DEC.L #2,ERd W L DEC.L #1,ERd 1 1 DIVXS.W Rs,ERd L DEC.W #2,Rd 1 1 0 1 7 DIVXS.B Rs,Rd W W DEC.W #1,Rd B B DAS Rd CMP.L ERs,ERd DAA Rd L L CMP.L #xx:32,ERd DAS W CMP.W Rd,Rd DAA 7 1 W CMP.W #xx:16,Rd 1 A B B CMP.B Rs,Rd 0 6 6 7 7 7 B B B B A 7 7 7 7 B B 3 1 1 1 B B B B A F F F A D 9 C rd 1 A A E C 5 1st byte CMP.B #xx:8,Rd CMP B BXOR #xx:3,@ERd -- B Size BXOR #xx:3,Rd Mnemonic CLRMAC*1 CLRMAC BXOR Instruction 0 erd rd 7 F 7 D 5 0 7 5 F D D 5 rs rs D D F 0 erd 0 erd rd rd rd 0 erd rd 0 erd rd 4 C 0 erd rd 0 0 0 erd 0 erd rd 5 D rd rd rd 0 0 0 1 ers 0 erd 2 rd rd rs rd 2 IMM 0 0 0 0 rd rs A 3 1 abs 0 erd 0 IMM 2nd byte 5 5 5 5 7 7 9 9 3 1 5 5 3rd byte IMM abs 8 8 rs rs 0 IMM 0 IMM IMM abs F F 0 erd rd 0 0 4th byte 7 5 0 IMM 0 6th byte Instruction Format 5th byte 7 5 7th byte 0 IMM 0 8th byte 9th byte 10th byte Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 267 of 322 REJ09B0139-0400 Rev. 4.00 Feb 24, 2006 page 268 of 322 REJ09B0139-0400 W W W W W W W W W W W LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR B B B B B B B MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd B MOV.B #xx:8,Rd MOV L -- MAC @ERn+,@ERm+ LDMAC ERs,MACL 6 2 6 7 6 6 0 F 0 0 0 0 LDM.L @SP+,(ERn-ERn+3) L L 0 LDM.L @SP+,(ERn-ERn+2) L LDMAC ERS,MACH 0 LDM.L @SP+,(ERn-ERn+1) L 0 0 0 A rd C 8 E 8 C rd 1 3 3 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 3 3 1 7 F E D B A 9 0 0 0 0 0 0 0 0 B W 0 LDC @ERs,CCR B LDC Rs,CCR 0 0 5 5 5 5 5 5 1st byte LDC Rs,EXR B B -- JSR @@aa:8 LDC #xx:8,CCR -- LDC #xx:8,EXR -- -- JMP @aa:8 JSR @ERn -- JMP @aa:24 JSR @aa:24 -- Size JMP @ERn Mnemonic MAC*1 LDMAC*1 LDM LDC JSR JMP Instruction 0 abs 0 ers 0 ers rd rd 0 rd rd rd 0 0 ers IMM 0 ers 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 rs rs 1 0 0 0 ers IMM 0 ers rs 6 3 2 3 2 1 4 4 4 4 4 4 4 4 4 4 4 4 1 0 4 abs 0 ern abs 0 ern 2nd byte 6 6 6 6 6 6 6 6 6 6 6 7 7 6 6 6 6 0 abs abs A D D D D B B B B D D 8 8 F F 9 9 7 3rd byte 0 0 ern+3 0 ern+2 0 ern+1 0 0 0 0 0 0 0 0 0 0 0 abs disp 2 rd 0 ern 0 erm 7 7 7 2 2 0 0 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers IMM 4th byte 6 6 B B abs abs disp disp 2 2 0 0 6th byte Instruction Format 5th byte disp abs abs 7th byte 8th byte disp disp 9th byte 10th byte Section 2 Instruction Descriptions MOV Instruction 0 0 L L L L L L L L MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd)*2 MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 0 0 0 0 0 0 0 0 0 0 0 7 L L MOV.L #xx:32,Rd 6 6 MOV.L @ERs+,ERd W MOV.W Rs,@aa:32 L W MOV.W Rs,@aa:16 6 MOV.L @(d:32,ERs),ERd W MOV.W Rs,@-ERd 7 6 L W MOV.W Rs,@(d:32,ERd) MOV.L @(d:16,ERs),ERd W MOV.W Rs,@(d:16,ERd) 6 L W MOV.W Rs,@ERd 6 6 L W MOV.W @aa:32,Rd MOV.L @ERs,ERd W MOV.W @aa:16,Rd 6 7 6 6 0 7 6 6 3 6 7 6 6 6 rd rs rs rs 0 rs rs rd rd rd 0 rd 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ers 0 erd 0 A 8 1 erd 0 erd 1 erd 1 erd 2 0 0 ers 0 ers 0 ers rd rd rs rs rs 0 rs rs rd 0 erd abs 0 ers rs 0 A 8 1 erd 0 erd 1 erd 1 erd 2 2nd byte 1 1 1 1 1 1 1 1 1 F A B B D 8 F 9 B B D 8 F 9 D 9 A A rs C 8 E 8 A 1st byte MOV.L ERs,ERd W MOV.W @ERs+,Rd W MOV.W #xx:16,Rd W B MOV.B Rs,@aa:32 MOV.W @(d:32,ERs),Rd B MOV.B Rs,@aa:16 W B MOV.B Rs,@aa:8 MOV.W @(d:16,ERs),Rd B MOV.B Rs,@-ERd W B MOV.B Rs,@(d:32,ERd) W B MOV.B Rs,@(d:16,ERd) MOV.W @ERs,Rd B MOV.B Rs,@ERd MOV.W Rs,Rd B Size MOV.B @aa:32,Rd Mnemonic 6 6 6 7 B B D 8 F 9 6 6 B B D 8 F 9 B B A 6 6 6 7 6 6 6 6 6 3rd byte A 2 A rs rd rs IMM abs abs abs abs 0 0 erd 0 erd 0 A 8 0 ers 0 ers 1 erd 0 ers 0 erd 1 erd 0 ers 1 erd 0 ers 2 0 0 ers 0 erd 0 ers 0 ers 0 erd 0 ers 0 erd abs disp abs disp IMM abs disp 4th byte 6 6 B B abs disp abs disp A 2 disp disp disp abs 0 ers abs 0 erd 6th byte Instruction Format 5th byte 7th byte 8th byte disp disp 9th byte 10th byte Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 269 of 322 REJ09B0139-0400 Rev. 4.00 Feb 24, 2006 page 270 of 322 REJ09B0139-0400 ROTR ROTL PUSH POP ORC OR.L ERs,ERd L W W ROTR.W Rd ROTR.W #2,Rd ROTL.L #2,ERd B L ROTL.L ERd B L ROTL.W #2,Rd ROTR.B #2,Rd W ROTL.W Rd ROTR.B Rd B W ROTL.B #2,Rd B ROTL.B Rd PUSH.L ERn L W POP.L ERn PUSH.W Rn W POP.W Rn B OR.L #xx:32,ERd B L L OR.W Rs,Rd ORC #xx:8,CCR W OR.W #xx:16,Rd ORC #xx:8,EXR W OR.B Rs,Rd C B B OR.B #xx:8,Rd L NOT.L ERd OR 1 W NOT.W Rd 0 1 1 1 1 1 1 1 1 1 1 0 6 0 6 3 3 3 3 2 2 2 2 2 2 1 D 1 D 4 1 0 1 A 4 9 4 rd 7 7 7 0 7 7 7 2 0 1 1 A A 0 0 7 6 7 1 1 1 B -- NOP 1 NOT.B Rd L NEG.L ERd 1 1 5 5 NOT B W NEG.W Rd MULXU.W Rs,ERd NEG.B Rd B W MULXU.B Rs,Rd 0 0 6 6 1st byte NOP NEG MULXU W MULXS.W Rs,ERd MULXS B B MOVTPE Rs,@aa:16 MULXS.B Rs,Rd MOVTPE B Size MOVFPE @aa:16,Rd Mnemonic MOVFPE Instruction D 9 C 8 F B D 9 C 8 0 F 0 7 4 F 4 rs 4 rs 3 1 0 0 B 9 8 rs rs C C C 4 rd rd rd 1 rd rd rd rd 0 rn 0 rn rd rd rd rd 0 erd 0 erd IMM 0 0 erd IMM 0 erd rd rd 0 0 erd rd rd 0 erd rd 0 0 rs rd 2nd byte 6 6 0 6 5 5 D D 4 4 2 0 3rd byte rs rs rd IMM 0 erd F 7 0 ern 0 ern IMM 0 ers 0 erd IMM abs abs 4th byte 6th byte Instruction Format 5th byte 7th byte 8th byte 9th byte 10th byte Section 2 Instruction Descriptions SHLR SHLL SHAR B L SHLL.L #2,ERd SHLR.B #2,Rd L SHLL.L ERd B W SHLL.W #2,Rd SHLR.B Rd W SHLL.W Rd L SHAR.L #2,ERd B L SHAR.L ERd SHLL.B #2,Rd W SHAR.W #2,Rd B W SHAR.W Rd SHLL.B Rd B L SHAL.L #2,ERd SHAR.B #2,Rd L SHAL.L ERd B W SHAL.W #2,Rd SHAR.B Rd B W B SHAL.B Rd SHAL SHAL.W Rd -- RTS RTS SHAL.B #2,Rd -- L RTE L ROTXR.L #2,ERd ROTXR.B #2,Rd ROTXR.L ERd B ROTXR.B Rd W B ROTXL.L #2,ERd W L ROTXL.L ERd ROTXR.W #2,Rd L ROTXL.W #2,Rd ROTXR.W Rd W W ROTXL.W Rd B ROTXL.B #2,Rd L B ROTR.L #2,ERd ROTXL.B Rd L Size ROTR.L ERd Mnemonic RTE ROTXR ROTXL ROTR Instruction 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 4 6 3 3 3 3 3 3 2 2 2 2 2 2 3 3 1st byte 4 0 7 3 5 1 4 0 F B D 9 C 8 F B D 9 C 8 7 7 7 3 5 1 4 0 7 3 5 1 4 0 F B rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 0 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd 2nd byte 3rd byte 4th byte 6th byte Instruction Format 5th byte 7th byte 8th byte 9th byte 10th byte Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 271 of 322 REJ09B0139-0400 Rev. 4.00 Feb 24, 2006 page 272 of 322 REJ09B0139-0400 W W W W W STC.W CCR,@-ERd STC.W EXR,@-ERd STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 TRAPA #x:2 TRAPA -- B B SUBX Rs,Rd TAS @ERd*3 TAS L B SUBS #4,ERd SUBX #xx:8,Rd L SUB.L ERs,ERd L L L SUB.L #xx:32,ERd SUBS #1,ERd W SUB.W Rs,Rd SUBS #2,ERd W SUB.W #xx:16,Rd L B STMAC MACL,ERd SUB.B Rs,Rd L STMAC MACH,ERd L W STC.W EXR,@(d:32,ERd) L W STC.W CCR,@(d:32,ERd) STM.L (ERn-ERn+3),@-SP W STC.W EXR,@(d:16,ERd) STM.L (ERn-ERn+2),@-SP W STC.W CCR,@(d:16,ERd) L W STC.W EXR,@ERd STM.L (ERn-ERn+1),@-SP W STC.W CCR,@ERd SUBX SUBS SUB STMAC*1 STM B W STC.B EXR,Rd B STC.B CCR,Rd L SHLR.L #2,ERd STC L SHLR.L ERd -- W SHLR.W #2,Rd SLEEP W Size SHLR.W Rd Mnemonic SLEEP SHLR Instruction 5 0 1 B 1 1 1 1 7 1 7 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 7 1 E rd B B B A A 9 9 8 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1st byte 0 erd rd rd rd 0 ers 0 ers 0 0 0 1 0 1 0 1 0 1 0 erd 0 0 00 IMM rd E IMM 0 erd 0 erd rs 9 8 0 1 ers 0 erd 3 rs 3 rs 3 2 3 2 1 4 4 4 4 4 4 4 0 1 4 4 0 1 0 rd rd 0 0 erd 0 erd rd rd 4 4 4 1 0 8 7 3 5 1 2nd byte 7 6 6 6 6 6 6 6 6 6 7 7 6 6 6 6 B D D D B B B B D D 8 8 F F 9 9 3rd byte 0 erd IMM F F F A A 8 8 1 erd 1 erd 0 erd 0 erd 1 erd 1 erd 1 erd 1 erd C IMM 0 ern 0 ern 0 ern 0 0 0 0 0 0 0 0 0 0 0 0 4th byte 6 6 B B disp abs abs disp A A 0 0 6th byte Instruction Format 5th byte abs abs 7th byte 8th byte disp disp 9th byte 10th byte Section 2 Instruction Descriptions XOR.L ERs,ERd B XOR.L #xx:32,ERd B L L XOR.W Rs,Rd XORC #xx:8,EXR W XOR.W #xx:16,Rd XORC #xx:8,CCR B W XOR.B Rs,Rd B Size XOR.B #xx:8,Rd Mnemonic 0 0 0 7 6 7 1 D 1 5 1 A 5 9 5 rd 1st byte 4 F 5 rs 5 rs rd rd rd IMM 1 0 0 erd IMM 2nd byte 0 6 5 5 3rd byte IMM IMM 0 ers 0 erd IMM 4th byte 7th byte 8th byte 9th byte 10th byte General Register ER0 ER1 * * * ER7 Register Field 000 001 * * * 111 Address Register 32-Bit Register 0000 0001 * * * 0111 1000 1001 * * * 1111 Register Field R0 R1 * * * R7 E0 E1 * * * E7 General Register 16-Bit Register The register fields specify general registers as follows. 0000 0001 * * * 0111 1000 1001 * * * 1111 Register Field R0H R1H * * * R7H R0L R1L * * * R7L General Register 8-Bit Register Immediate data (2, 3, 8, 16, or 32 bits) Absolute address (8, 16, 24, or 32 bits) Displacement (8, 16, or 32 bits) Register field (4 bits specifying an 8-bit or 16-bit register. The symbols rs, rd, and rn correspond to operand symbols Rs, Rd, and Rn.) ers, erd, ern, erm: Register field (3 bits specifying an address register or 32-bit register. The symbols ers, erd, ern, and erm correspond to operand symbols ERs, ERd, ERn, and ERm.) Legend: IMM: abs: disp: rs, rd, rn: 6th byte Instruction Format 5th byte Notes: 1. These instructions are supported by the H8S/2600 CPU only. 2. Bit 7 of the 4th byte of the MOV.L ERs, @(d:32,ERd) instruction can be either 1 or 0. 3. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. XORC XOR Instruction Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 273 of 322 REJ09B0139-0400 Rev. 4.00 Feb 24, 2006 page 274 of 322 REJ09B0139-0400 STC STMAC* 2 LDC LDMAC* 3 BL BST TRAPA BEQ XOR AND E MOV OR D MOV C F SUB ADD BVS 9 B Table 2.3 (2) JMP BPL BMI Table 2.3 (2) Table 2.3 (2) Table 2.3 (2) Table 2.3 (2) A Table 2.3 (2) Table 2.3 (2) EEPMOV MOV Table 2.3 (2) SUBX Note: * These instructions are supported by the H8S/2600 CPU only. 8 BVC CMP BIST BLD BXOR BAND BILD BIXOR BIAND AND RTE BNE B BIOR XOR BSR BCS A BOR OR RTS BCC MOV.B Table 2.3 (2) LDC 7 ADDX BTST DIVXU BLS AND ANDC 6 9 BCLR MULXU BHI XOR XORC 5 ADD BNOT DIVXU BRN OR ORC 4 Instruction when most significant bit of BH is 1. Instruction when most significant bit of BH is 0. 8 7 BSET MULXU 5 6 BRA 4 3 2 Table 2.3 (2) 1 BH Table 2.3 (2) Table 2.3 (2) Table 2.3 (2) Table 2.3 (2) NOP 0 AL 2nd byte BSR BGE C CMP MOV JSR BGT SUBX ADDX E Table 2.3 (3) MOV BLT D BLE Table 2.3 (2) Table 2.3 (2) F Table 2.3 1 0 AL AH 1st byte 2.5 AH Operation Code: Section 2 Instruction Descriptions Operation Code Map Table 2.3 shows an operation code map. Operation Code Map (1) ADDS DAA 0B 0F CMP CMP ADD ADD MOV MOV 79 7A EXTU INC BNE MAC* 6 INC 7 BCC OR OR SUB SUB AND AND XOR XOR BCS BEQ DEC BVC MOV NEG EXTU DEC ROTR ROTXR ROTXR SUBS ROTL SHAR SHLR ROTXL SHLR SHAL ADDS SLEEP 8 ROTXL SHLL STC 5 SHLL LDC 4 Table 2.3 (4) MOVFPE BLS NOT STM 3 Note: * These instructions are supported by the H8S/2600 CPU only. BHI MOV BRN Table 2.3 (4) BRA MOV 2 BL 2nd byte BH 58 DAS 1F AL 6A SUBS NOT 17 1B ROTXR 13 1A SHLR ROTXL 12 DEC 1 LDM 11 SHLL INC 0A 10 MOV 0 01 BH AH 1st byte BVS 9 MOV BPL CLRMAC* A BMI NEG B D BGE MOVTPE CMP SUB ROTL SHAR SHAL ROTR MOV ADD BLT DEC EXTS INC Table 2.3 (3) Table 2.3 (3) C BGT TAS E BLE DEC EXTS ROTR ROTL SHAR SHAL INC Table 2.3 (3) F Table 2.3 AH AL Operation Code: Section 2 Instruction Descriptions Operation Code Map (2) Rev. 4.00 Feb 24, 2006 page 275 of 322 REJ09B0139-0400 Rev. 4.00 Feb 24, 2006 page 276 of 322 REJ09B0139-0400 *2 *1 BSET BNOT BNOT BNOT BNOT DIVXS 1 AL BCLR BCLR BCLR BCLR MULXS 2 BH 3 BTST BTST BTST BTST BOR BOR BIOR BIOR OR 4 CL 3rd byte CH DIVXS BL 2nd byte Notes: 1. The letter "r" indicates a register field. 2. The letters "aa" indicate an absolute address field. BSET 7Faa7*2 BSET BSET MULXS 0 7Faa6*2 7Eaa7 *2 7Eaa6 7Dr07 7Dr06 *1 7Cr07 *1 7Cr06 *1 01F06 01D05 CL AH 1st byte AND 6 DL 7 BXOR BAND BLD BILD BIXOR BIAND BST BIST BXOR BAND BLD BILD BIXOR BIAND BST BIST XOR 5 DH 4th byte 8 9 A B C D E F Instruction when most significant bit of DH is 0. Instruction when most significant bit of DH is 1. Table 2.3 01C05 AHALBHBLCH Operation Code: Section 2 Instruction Descriptions Operation Code Map (3) AH BSET 0 BNOT BNOT 1 AL 1st byte BSET 1 0 BL BCLR 2 BH BL 2nd byte BCLR 2 BH 2nd byte BTST 3 BTST 3 CL CL BIOR 4 BOR CH 3rd byte BIOR 4 BOR CH 3rd byte Note: * The letters "aa" indicate an absolute address field. 6A38aaaaaaaa7* 6A38aaaaaaaa6* 6A30aaaaaaaa7* 6A30aaaaaaaa6* AHALBHBL ... FHFLGH EL Operation Code: 6A18aaaa7* 6A18aaaa6* 6A10aaaa7* 6A10aaaa6* AHALBHBLCHCLDHDLEH AL AH 1st byte 6 DL EH 7 6 DL EH 7 EL 5th byte BXOR BAND BLD BILD BIXOR BIAND BST BIST 5 DH 4th byte EL 5th byte BXOR BAND BLD BILD BIXOR BIAND BST BIST 5 DH 4th byte 8 8 9 FL FH 9 FL 6th byte FH 6th byte A B HH HL 8th byte C D E F B C D E F Instruction when most significant bit of HH is 0. Instruction when most significant bit of HH is 1. GL 7th byte GH A Instruction when most significant bit of FH is 0. Instruction when most significant bit of FH is 1. Table 2.3 EL Operation Code: Section 2 Instruction Descriptions Operation Code Map (4) Rev. 4.00 Feb 24, 2006 page 277 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.6 Number of States Required for Instruction Execution The tables in this section can be used to calculate the number of states required for instruction execution by the CPU. Table 2.5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table 2.4 indicates the number of states required for each cycle, depending on its size. The number of states required for each cycle depends on the product. See the hardware manual named for the relevant product for details. The number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I x SI + J x SJ + K x SK + L x SL + M x SM + N x SN Examples: Advanced mode, program code and stack located in external memory, on-chip supporting modules accessed in two states with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. 1. BSET #0, @FFFFC7:8 From table 2.5: I = L = 2, J = K = M = N= 0 From table 2.4: SI = 4, SL = 2 Number of states required for execution = 2 x 4 + 2 x 2 = 12 2. JSR @@30 From table 2.5: I = J = K = 2, L=M=N=0 From table 2.4: SI = SJ = SK = 4 Number of states required for execution = 2 x 4 + 2 x 4 + 2 x 4 = 24 Rev. 4.00 Feb 24, 2006 page 278 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions Table 2.4 Number of States per Cycle Access Conditions External Device On-Chip Supporting Module Cycle Instruction fetch SI 8-Bit Bus 16-Bit Bus On-Chip Memory 8-Bit Bus 16-Bit Bus 2-State Access 3-State Access 2-State Access 3-State Access 1 2n n 4 6 + 2m 2 3 + m* 2 3+m 4 6 + 2m 1 1 1 1 Branch address read SJ Stack operation SK Byte data access SL Word data access SM Internal operation SN n 2n 1 1 1 Note: * For the MOVFPE and MOVTPE instructions, refer to the relevant microcontroller hardware manual. Legend: m: Number of wait states inserted into external device access n: Number of states required for access to an on-chip supporting module. For the specific number, refer to the relevant microcontroller hardware manual. Rev. 4.00 Feb 24, 2006 page 279 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions Table 2.5 Number of Cycles in Instruction Execution Instruction Fetch Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation J K L M N Instruction Mnemonic I ADD ADD.B #xx:8,Rd 1 ADD.B Rs,Rd 1 ADD.W #xx:16,Rd 2 ADD.W Rs,Rd 1 ADD.L #xx:32,ERd 3 ADD.L ERs,ERd 1 ADDS ADDS #1/2/4,ERd 1 ADDX ADDX #xx:8,Rd 1 ADDX Rs,Rd 1 AND AND.B #xx:8,Rd 1 AND.B Rs,Rd 1 AND.W #xx:16,Rd 2 AND.L #xx:32,ERd 3 AND.L ERs,ERd 2 ANDC ANDC #xx:8,CCR 1 ANDC #xx:8,EXR 2 BAND BAND #xx:3,Rd 1 BAND #xx:3,@ERd 2 BAND #xx:3,@aa:8 2 1 BAND #xx:3,@aa:16 3 1 BAND #xx:3,@aa:32 4 1 BRA d:8 (BT d:8) 2 Bcc BRN d:8 (BF d:8) 2 BHI d:8 2 BLS d:8 2 BCC d:8 (BHS d:8) 2 BCS d:8 (BLO d:8) 2 BNE d:8 2 BEQ d:8 2 BVC d:8 2 BVS d:8 2 BPL d:8 2 BMI d:8 2 BGE d:8 2 BLT d:8 2 BGT d:8 2 Rev. 4.00 Feb 24, 2006 page 280 of 322 REJ09B0139-0400 1 Section 2 Instruction Descriptions Instruction Fetch Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation J K L M N Instruction Mnemonic I Bcc BLE d:8 2 BCLR BIAND BILD BRA d:16 (BT d:16) 2 1 BRN d:16 (BF d:16) 2 1 BHI d:16 2 1 BLS d:16 2 1 BCC d:16 (BHS d:16) 2 1 BCS d:16 (BLO d:16) 2 1 BNE d:16 2 1 BEQ d:16 2 1 BVC d:16 2 1 BVS d:16 2 1 BPL d:16 2 1 BMI d:16 2 1 BGE d:16 2 1 BLT d:16 2 1 BGT d:16 2 1 BLE d:16 2 1 BCLR #xx:3,Rd 1 BCLR #xx:3,@ERd 2 2 BCLR #xx:3,@aa:8 2 2 BCLR #xx:3,@aa:16 3 2 BCLR #xx:3,@aa:32 4 2 BCLR Rn,Rd 1 BCLR Rn,@ERd 2 2 BCLR Rn,@aa:8 2 2 BCLR Rn,@aa:16 3 2 BCLR Rn,@aa:32 4 2 BIAND #xx:3,Rd 1 BIAND #xx:3,@ERd 2 BIAND #xx:3,@aa:8 2 1 BIAND #xx:3,@aa:16 3 1 BIAND #xx:3,@aa:32 4 1 BILD #xx:3,Rd 1 1 BILD #xx:3,@ERd 2 1 BILD #xx:3,@aa:8 2 1 BILD #xx:3,@aa:16 3 1 BILD #xx:3,@aa:32 4 1 Rev. 4.00 Feb 24, 2006 page 281 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions Instruction Fetch Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation J K L M N Instruction Mnemonic I BIOR BIOR #xx:8,Rd 1 BIOR #xx:8,@ERd 2 1 BIOR #xx:8,@aa:8 2 1 BIOR #xx:8,@aa:16 3 1 BIOR #xx:8,@aa:32 4 1 BIST #xx:3,Rd 1 BIST BIXOR BLD BNOT BOR BSET BIST #xx:3,@ERd 2 2 BIST #xx:3,@aa:8 2 2 BIST #xx:3,@aa:16 3 2 BIST #xx:3,@aa:32 4 2 BIXOR #xx:3,Rd 1 BIXOR #xx:3,@ERd 2 1 BIXOR #xx:3,@aa:8 2 1 BIXOR #xx:3,@aa:16 3 1 BIXOR #xx:3,@aa:32 4 1 BLD #xx:3,Rd 1 BLD #xx:3,@ERd 2 BLD #xx:3,@aa:8 2 1 BLD #xx:3,@aa:16 3 1 BLD #xx:3,@aa:32 4 1 BNOT #xx:3,Rd 1 1 BNOT #xx:3,@ERd 2 2 BNOT #xx:3,@aa:8 2 2 BNOT #xx:3,@aa:16 3 2 BNOT #xx:3,@aa:32 4 2 BNOT Rn,Rd 1 BNOT Rn,@ERd 2 BNOT Rn,@aa:8 2 2 BNOT Rn,@aa:16 3 2 BNOT Rn,@aa:32 4 2 BOR #xx:3,Rd 1 BOR #xx:3,@ERd 2 BOR #xx:3,@aa:8 2 1 BOR #xx:3,@aa:16 3 1 BOR #xx:3,@aa:32 4 1 BSET #xx:3,Rd 1 2 1 BSET #xx:3,@ERd 2 2 BSET #xx:3,@aa:8 2 2 Rev. 4.00 Feb 24, 2006 page 282 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions Instruction Fetch Branch Address Read Stack Operation J K Byte Data Access Word Data Access Internal Operation L M N Instruction Mnemonic I BSET BSET #xx:3,@aa:16 3 2 BSET #xx:3,@aa:32 4 2 BSET Rn,Rd 1 BSR BSET Rn,@ERd 2 2 BSET Rn,@aa:8 2 2 BSET Rn,@aa:16 3 2 BSET Rn,@aa:32 4 2 BSR d:8 BSR d:16 BST BTST BXOR Normal 2 1 Advanced 2 2 Normal 2 1 1 Advanced 2 2 1 BST #xx:3,Rd 1 BST #xx:3,@ERd 2 BST #xx:3,@aa:8 2 2 BST #xx:3,@aa:16 3 2 BST #xx:3,@aa:32 4 2 BTST #xx:3,Rd 1 2 BTST #xx:3,@ERd 2 1 BTST #xx:3,@aa:8 2 1 BTST #xx:3,@aa:16 3 1 BTST #xx:3,@aa:32 4 1 BTST Rn,Rd 1 BTST Rn,@ERd 2 1 BTST Rn,@aa:8 2 1 BTST Rn,@aa:16 3 1 BTST Rn,@aa:32 4 1 BXOR #xx:3,Rd 1 BXOR #xx:3,@ERd 2 1 BXOR #xx:3,@aa:8 2 1 BXOR #xx:3,@aa:16 3 1 BXOR #xx:3,@aa:32 4 1 CLRMAC*5 CLRMAC 1 CMP CMP.B #xx:8,Rd 1 CMP.B Rs,Rd 1 CMP.W #xx:16,Rd 2 CMP.W Rs,Rd 1 CMP.L #xx:32,ERd 3 CMP.L ERs,ERd 1 3 6 1* * Rev. 4.00 Feb 24, 2006 page 283 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions Instruction Fetch Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation J K L M N Instruction Mnemonic I DAA DAA Rd 1 DAS DAS Rd 1 DEC DEC.B Rd 1 DEC.W #1/2,Rd 1 DEC.L #1/2,ERd 1 DIVXS.B Rs,Rd 2 DIVXS.W Rs,ERd 2 19 DIVXU DIVXU.B Rs,Rd 1 11 DIVXU.W Rs,ERd 1 EEPMOV EEPMOV.B 2 2n + 2*1 EEPMOV.W 2 1 2n + 2* EXTS.W Rd 1 DIVXS EXTS EXTU INC JMP EXTS.L ERd 1 EXTU.W Rd 1 EXTU.L ERd 1 INC.B Rd 1 INC.W #1/2,Rd 1 INC.L #1/2,ERd 1 JMP @ERn 2 JMP @aa:24 JSR 19 2 1 JMP @@aa:8 Normal JSR @ERn Advanced 2 2 JSR @aa:24 Normal 2 1 1 Advanced 2 2 1 Normal 2 1 1 Advanced 2 2 2 JSR @@aa:8 LDC 11 2 1 Advanced 2 2 Normal 2 LDC #xx:8,CCR 1 1 1 1 LDC #xx:8,EXR 2 LDC Rs,CCR 1 LDC Rs,EXR 1 LDC @ERs,CCR 2 LDC @ERs,EXR 2 1 LDC @(d:16,ERs),CCR 3 1 1 LDC @(d:16,ERs),EXR 3 1 LDC @(d:32,ERs),CCR 5 1 LDC @(d:32,ERs),EXR 5 1 Rev. 4.00 Feb 24, 2006 page 284 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions Instruction Fetch Branch Address Read Stack Operation Byte Data Access J K L Instruction Mnemonic I LDC LDC @ERs+,CCR 2 LDM LDMAC*5 Word Data Access Internal Operation M N 1 1 1 LDC @ERs+,EXR 2 1 LDC @aa:16,CCR 3 1 LDC @aa:16,EXR 3 1 LDC @aa:32,CCR 4 1 LDC @aa:32,EXR 4 1 LDM.L @SP+,(ERn-ERn+1) 2 4 1 LDM.L @SP+,(ERn-ERn+2) 2 6 1 LDM.L @SP+,(ERn-ERn+3) 2 8 1 LDMAC ERs,MACH 1 LDMAC ERs,MACL 1 MAC*5 MAC @ERn+,@ERm+ 2 MOV MOV.B #xx:8,Rd 1 MOV.B Rs,Rd 1 3 6 1* * 3 6 * 1 * 2 MOV.B @ERs,Rd 1 1 MOV.B @(d:16,ERs),Rd 2 1 MOV.B @(d:32,ERs),Rd 4 1 MOV.B @ERs+,Rd 1 1 MOV.B @aa:8,Rd 1 1 MOV.B @aa:16,Rd 2 1 MOV.B @aa:32,Rd 3 1 MOV.B Rs,@ERd 1 1 MOV.B Rs,@(d:16,ERd) 2 1 MOV.B Rs,@(d:32,ERd) 4 1 MOV.B Rs,@-ERd 1 1 MOV.B Rs,@aa:8 1 1 MOV.B Rs,@aa:16 2 1 MOV.B Rs,@aa:32 3 1 MOV.W #xx:16,Rd 2 MOV.W Rs,Rd 1 1 1 MOV.W @ERs,Rd 1 1 MOV.W @(d:16,ERs),Rd 2 1 MOV.W @(d:32,ERs),Rd 4 1 MOV.W @ERs+,Rd 1 1 MOV.W @aa:16,Rd 2 1 MOV.W @aa:32,Rd 3 1 MOV.W Rs,@ERd 1 1 1 Rev. 4.00 Feb 24, 2006 page 285 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions Instruction Fetch Branch Address Read Stack Operation Byte Data Access J K L Instruction Mnemonic I MOV MOV.W Rs,@(d:16,ERd) 2 Word Data Access Internal Operation M N 1 MOV.W Rs,@(d:32,ERd) 4 1 MOV.W Rs,@-ERd 1 1 MOV.W Rs,@aa:16 2 1 MOV.W Rs,@aa:32 3 1 MOV.L #xx:32,ERd 3 MOV.L ERs,ERd 1 MOV.L @ERs,ERd 2 2 MOV.L @(d:16,ERs),ERd 3 2 MOV.L @(d:32,ERs),ERd 5 2 MOV.L @ERs+,ERd 2 2 MOV.L @aa:16,ERd 3 2 MOV.L @aa:32,ERd 4 2 MOV.L ERs,@ERd 2 2 MOV.L ERs,@(d:16,ERd) 3 2 MOV.L ERs,@(d:32,ERd) 5 2 MOV.L ERs,@-ERd 2 2 MOV.L ERs,@aa:16 3 2 MOV.L ERs,@aa:32 4 1 1 1 2 MOVFPE MOVFPE @:aa:16,Rd 2 1*2 MOVTPE MOVTPE Rs,@:aa:16 2 1*2 MULXS MULXS.B Rs,Rd H8S/2600 2 2*3 *6 H8S/2000 2 11 MULXS.W Rs,ERd H8S/2600 2 3 6 3* * MULXU NEG MULXU.B Rs,Rd H8S/2000 2 19 H8S/2600 1 2*3 *6 H8S/2000 1 11 MULXU.W Rs,ERd H8S/2600 1 3*3 *6 H8S/2000 1 19 NEG.B Rd 1 NEG.W Rd 1 NEG.L ERd 1 NOP NOP 1 NOT NOT.B Rd 1 NOT.W Rd 1 NOT.L ERd 1 Rev. 4.00 Feb 24, 2006 page 286 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions Instruction Fetch Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation J K L M N Instruction Mnemonic I OR OR.B #xx:8,Rd 1 OR.B Rs,Rd 1 OR.W #xx:16,Rd 2 OR.W Rs,Rd 1 ORC POP PUSH ROTL ROTR ROTXL ROTXR OR.L #xx:32,ERd 3 OR.L ERs,ERd 2 ORC #xx:8,CCR 1 ORC #xx:8,EXR 2 POP.W Rn 1 1 1 POP.L ERn 2 2 1 PUSH.W Rn 1 1 1 PUSH.L ERn 2 2 1 ROTL.B Rd 1 ROTL.B #2,Rd 1 ROTL.W Rd 1 ROTL.W #2,Rd 1 ROTL.L ERd 1 ROTL.L #2,ERd 1 ROTR.B Rd 1 ROTR.B #2,Rd 1 ROTR.W Rd 1 ROTR.W #2,Rd 1 ROTR.L ERd 1 ROTR.L #2,ERd 1 ROTXL.B Rd 1 ROTXL.B #2,Rd 1 ROTXL.W Rd 1 ROTXL.W #2,Rd 1 ROTXL.L ERd 1 ROTXL.L #2,ERd 1 ROTXR.B Rd 1 ROTXR.B #2,Rd 1 ROTXR.W Rd 1 ROTXR.W #2,Rd 1 ROTXR.L ERd 1 ROTXR.L #2,ERd 1 RTE RTE 2 2/3*1 1 RTS RTS Normal 2 1 1 Advanced 2 2 1 Rev. 4.00 Feb 24, 2006 page 287 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions Instruction Fetch Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation J K L M N Instruction Mnemonic I SHAL SHAL.B Rd 1 SHAL.B #2,Rd 1 SHAR SHLL SHLR SHAL.W Rd 1 SHAL.W #2,Rd 1 SHAL.L ERd 1 SHAL.L #2,ERd 1 SHAR.B Rd 1 SHAR.B #2,Rd 1 SHAR.W Rd 1 SHAR.W #2,Rd 1 SHAR.L ERd 1 SHAR.L #2,ERd 1 SHLL.B Rd 1 SHLL.B #2,Rd 1 SHLL.W Rd 1 SHLL.W #2,Rd 1 SHLL.L ERd 1 SHLL.L #2,ERd 1 SHLR.B Rd 1 SHLR.B #2,Rd 1 SHLR.W Rd 1 SHLR.W #2,Rd 1 SHLR.L ERd 1 SHLR.L #2,ERd 1 SLEEP SLEEP 1 STC STC.B CCR,Rd 1 STC.B EXR,Rd 1 1 STC.W CCR,@ERd 2 1 STC.W EXR,@ERd 2 1 STC.W CCR,@(d:16,ERd) 3 1 STC.W EXR,@(d:16,ERd) 3 1 STC.W CCR,@(d:32,ERd) 5 1 STC.W EXR,@(d:32,ERd) 5 1 STC.W CCR,@-ERd 2 1 1 STC.W EXR,@-ERd 2 1 1 STC.W CCR,@aa:16 3 1 STC.W EXR,@aa:16 3 1 STC.W CCR,@aa:32 4 1 STC.W EXR,@aa:32 4 1 Rev. 4.00 Feb 24, 2006 page 288 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions Instruction Fetch Branch Address Read J Stack Operation Byte Data Access Word Data Access K L M Internal Operation Instruction Mnemonic I STM STM.L (ERn-ERn+1),@-SP 2 4 1 STM.L(ERn-ERn+2),@-SP 2 6 1 STM.L(ERn-ERn+3),@-SP 2 8 1 STMAC MACH,ERd 1 0*3 *6 STMAC MACL,ERd 1 0*3 *6 SUB.B Rs,Rd 1 STMAC*5 SUB SUB.W #xx:16,Rd 2 SUB.W Rs,Rd 1 SUB.L #xx:32,ERd 3 SUB.L ERs,ERd 1 SUBS SUBS #1/2/4,ERd 1 SUBX SUBX #xx:8,Rd 1 SUBX Rs,Rd 1 TAS TAS @ERd*4 TRAPA TRAPA #x:2 XOR 2 N 2 Normal 2 1 2/3*1 2 Advanced 2 2 2/3*1 2 XOR.B #xx:8,Rd 1 XOR.B Rs,Rd 1 XOR.W #xx:16,Rd 2 XOR.W Rs,Rd 1 XOR.L #xx:32,ERd 3 XOR.L ERs,ERd 2 XORC XORC #xx:8,CCR 1 XORC XORC #xx:8,EXR 2 Notes: 1. 2 when EXR is invalid, 3 when EXR is valid. 2. 5 for concatenated execution, 4 otherwise. 3. An internal operation may require between 0 and 3 additional states, depending on the preceding instruction. 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 5. These instructions are supported by the H8S/2600 CPU only. 6. The number of states may differ depending on the product. For details, refer to the relevant microcontroller hardware manual of the product in question. Rev. 4.00 Feb 24, 2006 page 289 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.7 Bus States During Instruction Execution Table 2.6 indicates the types of cycles that occur during instruction execution by the CPU. See table 2.4 for the number of states per cycle. How to Read the Table: Order of execution Instruction JMP @aa:24 1 R:W 2nd 2 Internal operation, 1 state 3 4 5 6 7 8 R:W EA End of instruction Read effective address (word-size read) No read or write Read 2nd word of current instruction (word-size read) Legend R:B Byte-size read R:W Word-size read W:B Byte-size write W:W Word-size write 2nd Address of 2nd word (3rd and 4th bytes) 3rd Address of 3rd word (5th and 6th bytes) 4th Address of 4th word (7th and 8th bytes) 5th Address of 5th word (9th and 10th bytes) NEXT Address of next instruction EA Effective address VEC Vector address Rev. 4.00 Feb 24, 2006 page 290 of 322 REJ09B0139-0400 9 Section 2 Instruction Descriptions Figure 2.1 shows timing waveforms for the address bus and the RD and WR (HWR or LWR) signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. Address bus RD WR (HWR or LWR) High level R:W 2nd Fetching 3rd byte of instruction Internal operation Fetching 4th byte of instruction R:W EA Fetching 1st byte of instruction at jump address Fetching 2nd byte of instruction at jump address Figure 2.1 Address Bus, RD, HWR or LWR) RD and WR (HWR LWR Timing (8-Bit Bus, Three-State Access, No Wait States) Rev. 4.00 Feb 24, 2006 page 291 of 322 REJ09B0139-0400 1 R:W NEXT R:W NEXT ADD.L ERs,ERd ADDS #1/2/4,ERd ADDX #xx:8,Rd Rev. 4.00 Feb 24, 2006 page 292 of 322 REJ09B0139-0400 R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BRA d:8 (BT d:8) R:W NEXT R:W NEXT BAND #xx:3,@aa:32 R:W NEXT R:W 2nd BAND #xx:3,@aa:16 BHI d:8 R:W 2nd BAND #xx:3,@aa:8 BRN d:8 (BF d:8) R:W 2nd R:W 2nd BAND #xx:3,@ERd R:W NEXT BAND #xx:3,Rd AND.L ERs,ERd R:W NEXT R:W 2nd AND.L #xx:32,ERd R:W 2nd R:W 2nd AND.W Rs,Rd ANDC #xx:8,EXR R:W NEXT AND.W #xx:16,Rd ANDC #xx:8,CCR R:W NEXT R:W 2nd AND.B Rs,Rd R:W NEXT R:W NEXT ADD.L #xx:32,ERd R:W NEXT R:W 2nd ADD.W Rs,Rd AND.B #xx:8,Rd R:W NEXT ADD.W #xx:16,Rd R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W 3rd R:W 3rd R:B EA R:B EA R:W NEXT R:W NEXT R:W 3rd R:W NEXT R:W 3rd R:W NEXT 2 R:W 4th R:B EA R:W NEXT R:W NEXT R:W NEXT R:W NEXT 3 R:B EA R:W NEXT 4 R:W NEXT 5 6 7 8 9 Table 2.6 ADDX Rs,Rd R:W NEXT R:W 2nd ADD.B Rs,Rd R:W NEXT Instruction ADD.B #xx:8,Rd Section 2 Instruction Descriptions Instruction Execution Cycles R:W 2nd R:W 2nd R:W 2nd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 R:W NEXT BCLR #xx:3,@ERd BCLR #xx:3,Rd R:W 2nd BPL d:16 R:W 2nd R:W 2nd BVS d:16 BLE d:16 R:W 2nd BVC d:16 R:W 2nd R:W 2nd BEQ d:16 BGT d:16 R:W 2nd BNE d:16 R:W 2nd R:W 2nd BCS d:16 (BLO d:16) BLT d:16 R:W 2nd BCC d:16 (BHS d:16) R:W 2nd R:W 2nd BLS d:16 BGE d:16 R:W 2nd BHI d:16 R:W 2nd R:W 2nd BRN d:16 (BF d:16) BMI d:16 R:W 2nd BRA d:16 (BT d:16) 1 R:W NEXT Instruction BLE d:8 2 3 R:W 3rd R:B EA R:B EA R:B EA R:W NEXT R:W NEXT Internal operation, R:W EA 1 state Internal operation, R:W EA 1 state Internal operation, R:W EA 1 state Internal operation, R:W EA 1 state Internal operation, R:W EA 1 state Internal operation, R:W EA 1 state Internal operation, R:W EA 1 state Internal operation, R:W EA 1 state Internal operation, R:W EA 1 state Internal operation, R:W EA 1 state Internal operation, R:W EA 1 state Internal operation, R:W EA 1 state Internal operation, R:W EA 1 state Internal operation, R:W EA 1 state Internal operation, R:W EA 1 state Internal operation, R:W EA 1 state R:W EA W:B EA R:W NEXT W:B EA 4 W:B EA 5 6 7 8 9 Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 293 of 322 REJ09B0139-0400 Rev. 4.00 Feb 24, 2006 page 294 of 322 REJ09B0139-0400 R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT #xx:3,Rd R:W NEXT BLD #xx:3,Rd BLD #xx:3,@aa:8 R:W 2nd BIXOR #xx:3,@aa:32 BLD #xx:3,@ERd R:W 3rd R:W 2nd BIXOR #xx:3,@aa:16 R:B EA R:W 3rd R:W 3rd R:B EA R:W 4th R:B EA R:W NEXT R:W NEXT R:W 4th R:B EA R:W NEXT R:B EA R:W 3rd R:W NEXT R:B EA R:W 4th R:B EA R:W NEXT R:W NEXT R:W 4th R:B EA R:W NEXT R:W NEXT R:W 4th R:B EA R:W NEXT R:W NEXT R:W 4th R:B EA R:W NEXT R:W NEXT R:W 4th R:B EA R:W 2nd R:W NEXT BIXOR #xx:3,Rd R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:W NEXT R:W NEXT R:W 2nd R:W 2nd BIST #xx:3,@aa:32 R:B EA R:B EA 3 R:W 4th BIXOR #xx:3,@aa:8 R:W 2nd BIST #xx:3,@aa:16 2 R:W 3rd BIXOR #xx:3,@ERd R:W 2nd R:W NEXT BIST #xx:3,Rd R:W 2nd R:W 2nd BIOR #xx:3,@aa:32 BIST #xx:3,@aa:8 R:W 2nd BIOR #xx:3,@aa:16 BIST #xx:3,@ERd R:W 2nd R:W NEXT BIOR #xx:3,Rd R:W 2nd R:W 2nd BILD #xx:3,@aa:32 BIOR #xx:3,@aa:8 R:W 2nd BILD #xx:3,@aa:16 BIOR #xx:3,@ERd R:W 2nd R:W NEXT BILD #xx:3,Rd R:W 2nd R:W 2nd BIAND #xx:3,@aa:32 BILD #xx:3,@aa:8 R:W 2nd BIAND #xx:3,@aa:16 BILD #xx:3,@ERd R:W 2nd R:W NEXT BIAND #xx:3,Rd R:W 2nd R:W 2nd BCLR Rn,@aa:32 BIAND #xx:3,@aa:8 R:W 2nd BCLR Rn,@aa:16 BIAND #xx:3,@ERd R:W 2nd R:W 2nd BCLR Rn,@aa:8 R:W NEXT BCLR Rn,Rd BCLR Rn,@ERd 1 R:W 2nd Instruction BCLR #xx:3,@aa:32 4 R:B EA R:W NEXT R:B EA R:W NEXT R:B EA R:W NEXT W:B EA W:B EA R:B EA R:W NEXT R:B EA R:W NEXT R:B EA R:W NEXT R:B EA R:W NEXT W:B EA W:B EA R:B EA 5 R:W NEXT R:W NEXT R:W NEXT W:B EA R:W NEXT R:W NEXT R:W NEXT R:W NEXT W:B EA R:W NEXT W:B EA W:B EA W:B EA 6 7 8 9 Section 2 Instruction Descriptions Normal R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST #xx:3,Rd BTST #xx:3,@ERd R:W NEXT BST #xx:3,@ERd BST #xx:3,Rd R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W NEXT R:W 4th R:B EA R:W NEXT R:W NEXT Internal operation, R:W EA 1 state Advanced R:W 2nd W:W stack (H) W:W stack R:W 4th R:B EA R:W NEXT R:W NEXT R:W 4th R:B EA R:W NEXT R:W NEXT R:W 4th R:B EA R:W NEXT R:W NEXT R:W 4th R:B EA R:W NEXT R:W NEXT R:W 4th R:B EA Internal operation, R:W EA 1 state R:W EA 3 R:W NEXT R:W 2nd Normal Advanced R:W NEXT BSR d:16 R:W EA R:W NEXT BSR d:8 R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 2nd R:W 2nd BSET Rn,@aa:16 2 R:W 3rd R:B EA R:B EA BSET Rn,@aa:32 R:W 2nd R:W NEXT BSET Rn,Rd R:W 2nd R:W 2nd BSET #xx:3,@aa:32 BSET Rn,@aa:8 R:W 2nd BSET #xx:3,@aa:16 BSET Rn,@ERd R:W 2nd R:W NEXT BSET #xx:3,Rd R:W 2nd R:W 2nd BOR #xx:3,@aa:32 BSET #xx:3,@aa:8 R:W 2nd BOR #xx:3,@aa:16 BSET #xx:3,@ERd R:W 2nd R:W NEXT BOR #xx:3,Rd R:W 2nd R:W 2nd BNOT Rn,@aa:32 BOR #xx:3,@aa:8 R:W 2nd BNOT Rn,@aa:16 BOR #xx:3,@ERd R:W 2nd R:W NEXT BNOT Rn,Rd R:W 2nd R:W 2nd BNOT #xx:3,@aa:32 BNOT Rn,@aa:8 R:W 2nd BNOT #xx:3,@aa:16 BNOT Rn,@ERd R:W 2nd BNOT #xx:3,@aa:8 1 R:W 2nd Instruction BNOT #xx:3,@ERd 4 R:B EA R:W NEXT W:B EA W:B EA W:W stack (H) W:W stack W:W stack (L) R:B EA R:W NEXT W:B EA W:B EA R:B EA R:W NEXT W:B EA W:B EA R:B EA R:W NEXT R:B EA R:W NEXT W:B EA W:B EA R:B EA R:W NEXT W:B EA W:B EA W:B EA R:W NEXT W:B EA W:W stack (L) R:W NEXT W:B EA R:W NEXT W:B EA R:W NEXT R:W NEXT W:B EA R:W NEXT 5 W:B EA W:B EA W:B EA W:B EA W:B EA 6 7 8 9 Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 295 of 322 REJ09B0139-0400 Rev. 4.00 Feb 24, 2006 page 296 of 322 REJ09B0139-0400 R:W NEXT DAS Rd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT DEC.L #1/2,ERd DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV.B EEPMOV.W EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd INC.B Rd R:W NEXT R:W NEXT DAA Rd R:W NEXT R:W NEXT CMP.L ERs,ERd DEC.W #1/2,Rd R:W 2nd CMP.L #xx:32,ERd DEC.B Rd R:W NEXT CMP.W Rs,Rd R:W NEXT CMP.B #xx:8,Rd R:W NEXT R:W NEXT CLRMAC* R:W 2nd R:W 2nd BXOR #xx:3,@aa:32 CMP.W #xx:16,Rd R:W 2nd BXOR #xx:3,@aa:16 CMP.B Rs,Rd R:W 2nd R:W NEXT BXOR #xx:3,Rd R:W 2nd R:W 2nd BTST Rn,@aa:32 BXOR #xx:3,@aa:8 R:W 2nd BTST Rn,@aa:16 BXOR #xx:3,@ERd R:W 2nd R:W 2nd R:W NEXT BTST Rn,Rd BTST Rn,@aa:8 R:W 2nd BTST #xx:3,@aa:32 BTST Rn,@ERd R:W 2nd BTST #xx:3,@aa:16 1 R:W 2nd Instruction BTST #xx:3,@aa:8 2 3 R:B EA R:W NEXT R:B EA R:W NEXT R:B EA R:W NEXT 4 R:B EAd *1 R:B EAd *1 R:B EAs *1 R:B EAs *1 Internal operation, 19 states W:B EAd *2 W:B EAd *2 R:W NEXT R:W NEXT R:W NEXT 5 Repeated n times*3 R:B EAs *2 R:B EAs *2 Internal operation, 19 states Internal operation, 11 states R:W NEXT R:W 4th R:B EA R:W NEXT R:W NEXT R:W 4th R:B EA R:W NEXT R:W NEXT R:W 4th R:B EA R:W NEXT Internal operation, 11 states R:W NEXT R:W NEXT R:W 3rd R:W NEXT Internal operation, 1 state*9 R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:W NEXT R:W NEXT 6 7 8 9 Section 2 Instruction Descriptions Normal R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR LDM.L @SP+,(ERn-ERn+1) R:W NEXT R:W 3rd R:W 3rd R:W 3rd R:W 3rd R:W NEXT R:W NEXT R:W 3rd R:W 3rd R:W 3rd R:W 3rd LDC @ERs,EXR R:W 2nd R:W 2nd R:W 2nd LDC @ERs,CCR R:W 2nd R:W NEXT LDC Rs,EXR LDC @(d:16,ERs),EXR R:W NEXT LDC Rs,CCR LDC @(d:16,ERs),CCR R:W NEXT R:W NEXT R:W 2nd LDC #xx:8,EXR R:W NEXT R:W NEXT R:W aa:8 (H) R:W aa:8 W:W stack (L) R:W 5th R:W 5th R:W EA R:W EA W:W stack (H) R:W EA W:W stack (H) W:W stack R:W EA R:W NEXT R:W NEXT Internal operation, R:W stack (H)*3 1 state R:W 4th R:W 4th R:W NEXT R:W EA Internal operation, R:W EA 1 state R:W NEXT 5 R:W stack (L)*3 R:W EA R:W EA R:W NEXT R:W NEXT W:W stack (L) W:W stack (L) Internal operation, R:W EA 1 state Internal operation, R:W EA 1 state R:W 4th R:W 4th R:W NEXT R:W NEXT R:W EA R:W EA R:W aa:8 (L) W:W stack Internal operation, R:W EA 1 state Advanced R:W 2nd W:W stack (H) W:W stack R:W aa:8 (L) Internal operation, R:W EA 1 state Advanced R:W NEXT 4 Internal operation, R:W EA 1 state R:W 2nd Normal R:W EA R:W EA R:W NEXT R:W aa:8 (H) R:W aa:8 Advanced R:W NEXT Normal 3 Internal operation, R:W EA 1 state R:W EA 2 LDC #xx:8,CCR JSR @@aa:8 JSR @aa:24 JSR @ERn Advanced R:W NEXT R:W NEXT JMP @@aa:8 Normal R:W NEXT R:W 2nd JMP @aa:24 R:W NEXT JMP @ERn INC.L #1/2,ERd 1 R:W NEXT Instruction INC.W #1/2,Rd R:W EA R:W EA R:W EA 6 7 8 9 Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 297 of 322 REJ09B0139-0400 Rev. 4.00 Feb 24, 2006 page 298 of 322 REJ09B0139-0400 R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+, Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.B Rs,@-ERd R:W NEXT R:W NEXT MOV.B Rs,@(d:32,ERd) MOV.W @ERs,Rd R:W 2nd MOV.B Rs,@(d:16,ERd) MOV.W Rs,Rd R:W 2nd MOV.B Rs,@ERd R:W 2nd R:W NEXT MOV.B @aa:32,Rd MOV.W #xx:16,Rd R:W 2nd MOV.B @aa:16,Rd R:W 2nd R:W 2nd MOV.B @aa:8,Rd MOV.B Rs,@aa:32 R:W NEXT MOV.B @ERs+,Rd R:W NEXT R:W NEXT MOV.B @(d:32,ERs),Rd R:W 2nd R:W 2nd MOV.B @(d:16,ERs),Rd MOV.B Rs,@aa:16 R:W 2nd MOV.B @ERs,Rd MOV.B Rs,@aa:8 R:W NEXT R:W NEXT MOV.B Rs,Rd R:W 2nd R:W NEXT R:W NEXT LDMAC ERs,MACL*11 MOV.B #xx:8,Rd R:W NEXT LDMAC ERs,MACH*11 MAC @ERn+,@ERm+*11 R:W 2nd LDM.L @SP+,(ERn-ERn+3) 1 R:W 2nd Instruction LDM.L @SP+,(ERn-ERn+2) 2 R:W 4th R:B EA R:W EAn R:B EA R:W 4th W:B EA R:W NEXT W:B EA R:W 4th R:W EA R:W NEXT W:W EA R:W 3rd R:W NEXT R:W NEXT R:W EA Internal operation, R:W EA 1 state R:W 3rd R:W NEXT R:W EA R:W NEXT R:W 3rd R:W NEXT W:B EA Internal operation, W:B EA 1 state R:W 3rd R:W NEXT W:B EA R:W 3rd R:W NEXT R:B EA R:B EA R:W NEXT W:B EA R:W NEXT R:B EA R:W NEXT R:W EAm R:W EA W:B EA R:B EA Repeated n times*3 R:W stack (L)*3 5 Internal operation, R:W stack (H)*3 1 state 4 R:W stack (L)*3 3 Internal operation, R:W stack (H)*3 1 state Internal operation, R:B EA 1 state R:W 3rd R:W NEXT R:B EA R:W NEXT Internal operation, 1 state*9 Internal operation, 1 state*9 R:W NEXT R:W NEXT 6 7 8 9 Section 2 Instruction Descriptions R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE @aa:16,Rd R:W NEXT W:W EA R:E 4th Internal operation, 11 states Internal operation, 19 states R:W NEXT R:W NEXT R:W NEXT R:W NEXT NOP NOT.B Rd Internal operation, 19 states H8S/2000 R:W NEXT NEG.L ERd Internal operation, 11 states Internal operation, 3 states*9 NEG.W Rd W:W EA R:W NEXT Internal operation, 3 states*9 H8S/2000 R:W NEXT R:W NEXT R:W 5th W:W EA W:W EA+2 Internal operation, 2 states*9 W:B *4 EA R:W *4 EA R:W 4th R:W NEXT MULXU.W Rs,ERd H8S/2600 R:W NEXT NEG.B Rd R:W EA R:W NEXT Internal operation, W:W EA 1 state R:W 4th R:W NEXT W:W EA R:W 4th R:W NEXT Internal operation, 2 states*9 R:W NEXT R:W 5th R:W EA R:W EA+2 W:W EA R:W NEXT 4 Internal operation, R:W EA 1 state R:W 4th R:W NEXT R:W EA R:W NEXT H8S/2600 R:W NEXT H8S/2000 R:W 2nd MULXU.B Rs,Rd R:W NEXT R:W NEXT H8S/2000 R:W 2nd R:W NEXT H8S/2600 R:W 2nd R:W NEXT R:W NEXT R:W 3rd R:W 3rd R:W NEXT R:W 3rd R:W 3rd R:W NEXT R:W 3rd R:W 3rd MULXS.W Rs,ERd H8S/2600 R:W 2nd MULXS.B Rs,Rd R:W 2nd R:W 3rd R:W 2nd MOV.L @(d:32,ERs),ERd R:W NEXT R:W 3rd R:W 2nd R:W NEXT R:W 3rd R:W 2nd MOVTPE Rs,@aa:16 3 W:W EA Internal operation, W:W EA 1 state R:W 3rd R:W NEXT R:W 3rd MOV.L @(d:16,ERs),ERd MOV.L ERs,ERd 2 R:W NEXT MOV.L @ERs,ERd R:W 2nd R:W NEXT MOV.L #xx:32,ERd R:W 2nd R:W NEXT MOV.W Rs,@-ERd R:W 2nd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 R:W 2nd MOV.W Rs,@(d:32,ERd) 1 R:W 2nd Instruction MOV.W Rs,@(d:16,ERd) W:W EA W:W EA+2 W:W EA+2 R:W NEXT W:W EA+2 R:W EA R:W EA+2 R:W EA+2 R:W NEXT R:W EA+2 W:W EA 5 W:W EA+2 W:W EA R:W EA+2 R:W EA 6 W:W EA+2 R:W EA+2 7 8 9 Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 299 of 322 REJ09B0139-0400 1 Rev. 4.00 Feb 24, 2006 page 300 of 322 REJ09B0139-0400 R:W 2nd PUSH.L ERn R:W NEXT R:W NEXT R:W NEXT ROTXL.L #2,ERd ROTXR.B Rd ROTXL.W #2,Rd ROTXL.L ERd R:W NEXT R:W NEXT ROTXL.W Rd R:W NEXT R:W NEXT ROTXL.B #2,Rd ROTR.L #2,ERd ROTXL.B Rd R:W NEXT R:W NEXT ROTR.L ERd R:W NEXT R:W NEXT R:W NEXT ROTR.B #2,Rd ROTR.W #2,Rd R:W NEXT ROTR.B Rd ROTR.W Rd R:W NEXT R:W NEXT ROTL.L #2,ERd ROTL.W #2,Rd ROTL.L ERd R:W NEXT R:W NEXT ROTL.W Rd R:W NEXT R:W NEXT PUSH.W Rn R:W NEXT R:W 2nd POP.L ERn ROTL.B #2,Rd R:W NEXT POP.W Rn ROTL.B Rd R:W NEXT R:W 2nd OR.L ERs,ERd R:W 2nd R:W 2nd OR.L #xx:32,ERd ORC #xx:8,EXR R:W NEXT OR.W Rs,Rd ORC #xx:8,CCR R:W NEXT R:W 2nd OR.W #xx:16,Rd OR.B #xx:8,Rd OR.B Rs,Rd R:W NEXT R:W NEXT NOT.L ERd R:W NEXT Instruction NOT.W Rd R:W NEXT 3 R:W NEXT 4 Internal operation, R:W EA 1 state Internal operation W:W EA Internal operation, W:W EA 1 state R:W NEXT Internal operation, R:W EA 1 state R:W NEXT R:W NEXT R:W 3rd R:W NEXT 2 W:W EA+2 R:W EA+2 5 6 7 8 9 Section 2 Instruction Descriptions R:W NEXT R:W NEXT RTE RTS R:W NEXT R:W NEXT R:W NEXT R:W NEXT SHLR.L ERd SHLR.L #2,ERd SLEEP STC CCR,Rd R:W NEXT R:W NEXT SHLR.W #2,Rd SHLR.B #2,Rd SHLR.W Rd R:W NEXT R:W NEXT SHLR.B Rd R:W NEXT R:W NEXT SHLL.L #2,ERd SHLL.W #2,Rd SHLL.L ERd R:W NEXT R:W NEXT SHLL.W Rd R:W NEXT SHAR.L #2,ERd R:W NEXT SHAR.L ERd SHLL.B #2,Rd R:W NEXT R:W NEXT SHAR.W #2,Rd SHLL.B Rd R:W NEXT R:W NEXT SHAR.W Rd R:W NEXT R:W NEXT SHAR.B #2,Rd SHAL.L #2,ERd SHAR.B Rd R:W NEXT R:W NEXT SHAL.L ERd R:W NEXT R:W NEXT SHAL.W #2,Rd SHAL.B #2,Rd SHAL.W Rd R:W NEXT R:W NEXT SHAL.B Rd Advanced R:W NEXT R:W NEXT R:W NEXT ROTXR.L #2,ERd ROTXR.W #2,Rd ROTXR.L ERd R:W NEXT R:W NEXT ROTXR.W Rd Normal 1 R:W NEXT Instruction ROTXR.B #2,Rd 3 Internal operation, 1 state R:W stack (H) R:W stack R:W stack (L) 4 R:W stack (L) 5 Internal operation, R:W *5 1 state Internal operation, R:W *5 1 state Internal operation, R:W *5 1 state R:W stack (EXR) R:W stack (H) 2 6 7 8 9 Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 301 of 322 REJ09B0139-0400 R:W 2nd R:W 2nd R:W 2nd R:W 2nd STC CCR,@(d:32,ERd) STC EXR,@(d:32,ERd) STC CCR,@-ERd STC EXR,@-ERd Rev. 4.00 Feb 24, 2006 page 302 of 322 REJ09B0139-0400 R:W NEXT Advanced R:W NEXT TRAPA #x:2 R:W NEXT R:W 2nd TAS @ERd*10 XOR.B #xx8,Rd Internal operation, W:W stack (L) 1 state R:W NEXT SUBX Rs,Rd R:W NEXT R:B EA Internal operation, W:W stack (L) 1 state R:W NEXT SUBX #xx:8,Rd Normal R:W NEXT SUBS #1/2/4,ERd R:W NEXT R:W NEXT R:W 3rd R:W 2nd W:W stack (H) W:W stack (H) W:B EA W:W EA W:W EA 6 W:W stack (EXR) R:W VEC W:W stack (EXR) R:W VEC Repeated n times*3 W:W stack (L)*3 Internal operation, W:W stack (H)*3 1 state SUB.L ERs,ERd R:W NEXT *9 *9 W:W stack (L)*3 SUB.L #xx:32,ERd STMAC MACL,ERd*11 W:W EA W:W EA Internal operation, W:W stack (H)*3 1 state R:W NEXT R:W NEXT STMAC MACH,ERd*11 R:W NEXT R:W NEXT R:W NEXT W:W stack (L)*3 SUB.W Rs,Rd R:W NEXT STM.L(ERn-ERn+3),@-SP R:W NEXT W:W EA W:W EA R:W NEXT R:W NEXT 5 Internal operation, W:W stack (H)*3 1 state R:W NEXT R:W 2nd STM.L(ERn-ERn+2),@-SP R:W NEXT R:W 4th R:W 4th R:W NEXT R:W NEXT Internal operation, W:W EA 1 state R:W 2nd R:W 2nd STM.L(ERn-ERn+1),@-SP R:W 3rd R:W 3rd R:W 5th R:W 5th W:W EA W:W EA 4 Internal operation, W:W EA 1 state R:W 4th R:W 4th R:W NEXT R:W NEXT W:W EA W:W EA 3 SUB.W #xx:16,Rd R:W 2nd STC EXR,@aa:32 R:W 3rd R:W 3rd R:W NEXT R:W NEXT R:W 3rd R:W 3rd R:W 3rd R:W 3rd R:W NEXT R:W NEXT 2 SUB.B Rs,Rd R:W 2nd R:W 2nd STC CCR,@aa:32 R:W 2nd R:W 2nd STC EXR,@(d:16,ERd) R:W 2nd R:W 2nd STC CCR,@(d:16,ERd) STC EXR,@aa:16 R:W 2nd STC EXR,@ERd STC CCR,@aa:16 R:W 2nd STC CCR,@ERd 1 R:W NEXT Instruction STC EXR,Rd R:W VEC+2 8 Internal operation, R:W *8 1 state Internal operation, R:W *8 1 state 7 9 Section 2 Instruction Descriptions Internal operation, W:W stack (L) 1 state Advanced R:W *7 Normal Internal operation, W:W stack (L) 1 state 4 W:W stack (H) W:W stack (H) Internal operation, R:W *6 1 state R:W *7 R:W VEC+2 3 R:W NEXT Internal operation, R:W *6 1 state R:W NEXT R:W NEXT R:W 3rd R:W NEXT 2 6 W:W stack (EXR) R:W:M VEC W:W stack (EXR) R:W VEC 5 R:W VEC+2 8 Internal operation, R:W *8 1 state Internal operation, R:W *8 1 state 7 9 Notes: 1. EAs is the contents of ER5. EAd is the contents of ER6. 2. EAs is the contents of ER5. EAd is the contents of ER6. Both registers are incremented by 1 after execution of the instruction. n is the initial value of R4L or R4. If n = 0, these bus cycles are not executed. 3. Repeated two times to save or restore two registers, three times for three registers, or four times for four registers. 4. For the number of states required for byte-size read or write, refer to the relevant microcontroller hardware manual. 5. Start address after return. 6. Start address of the program. 7. Prefetch address, equal to two plus the PC value pushed onto the stack. In recovery from sleep mode or software standby mode the read operation is replaced by an internal operation. 8. Start address of the interrupt-handling routine. 9. An internal operation may require between 0 and 3 additional states, depending on the preceding instruction. 10. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 11. These instructions are supported by the H8S/2600 CPU only. Interrupt exception handling Advanced R:W VEC R:W VEC Reset exception handling Normal R:W NEXT R:W 2nd XOR.L ERs,ERd R:W 2nd R:W 2nd XOR.L #xx:32,ERd XORC #xx:8,EXR R:W NEXT XOR.W Rs,Rd XORC #xx:8,CCR R:W 2nd XOR.W #xx:16,Rd 1 R:W NEXT Instruction XOR.B Rs,Rd Section 2 Instruction Descriptions Rev. 4.00 Feb 24, 2006 page 303 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions 2.8 Condition Code Modification This section indicates the effect of each CPU instruction on the condition code. The notation used in the table is defined below. m= 31 for longword operands 15 for word operands 7 for byte operands The i-th bit of the source operand Di The i-th bit of the destination operand Ri The i-th bit of the result Dn The specified bit in the destination operand -- Not affected Si Modified according to the result of the instruction (see definition) 0 Always cleared to 0 1 Always set to 1 * Undetermined (no guaranteed value) Z' Z flag before instruction execution C' C flag before instruction execution Rev. 4.00 Feb 24, 2006 page 304 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions V C Z N ADD H Instruction Condition Code Modification Table 2.7 Definition H = Sm-4 * Dm-4 + Dm-4 * Rm-4 + Sm-4 * Rm-4 N = Rm Z = Rm * Rm-1 * ...... * R0 V = Sm * Dm * Rm + Sm * Dm * Rm C = Sm * Dm + Dm * Rm + Sm * Rm -- -- ADDX -- -- -- ADDS H = Sm-4 * Dm-4 + Dm-4 * Rm-4 + Sm-4 * Rm-4 N = Rm Z = Z' * Rm * ...... * R0 V = Sm * Dm * Rm + Sm * Dm * Rm -- C = Sm * Dm + Dm * Rm + Sm * Rm AND 0 -- N = Rm Z = Rm * Rm-1 * ...... * R0 ANDC Stores the corresponding bits of the result. BCLR -- -- -- -- -- BIAND -- -- -- -- BILD -- -- -- -- BIOR -- -- -- -- BIST -- -- -- -- -- BIXOR -- -- -- -- BLD -- -- -- -- BNOT -- -- -- -- -- BOR -- -- -- -- BSET -- -- -- -- -- BSR -- -- -- -- -- BST -- -- -- -- -- BTST -- -- -- -- BXOR -- -- -- -- CLRMAC* -- -- -- -- -- CMP -- -- -- -- -- Bcc -- -- -- -- No flags change when the operand is EXR. BAND C = C' * Dn C = C' * Dn C = Dn C = C' + Dn C = C' * Dn + C' * Dn C = Dn C = C' + Dn Z = Dn C = C' * Dn + C' * Dn H = Sm-4 * Dm-4 + Dm-4 * Rm-4 + Sm-4 * Rm-4 N = Rm Z = Rm * Rm-1 * ... * R0 V = Sm * Dm * Rm + Sm * Dm * Rm C = Sm * Dm + Dm * Rm + Sm * Rm Rev. 4.00 Feb 24, 2006 page 305 of 322 REJ09B0139-0400 Instruction H N Z V C DAA * * Section 2 Instruction Descriptions Definition N = Rm Z = Rm * Rm-1 * ...... * R0 * * DAS C: decimal arithmetic carry N = Rm Z = Rm * Rm-1 * ...... * R0 -- C: decimal arithmetic borrow DEC -- N = Rm Z = Rm * Rm-1 * ...... * R0 -- V = Dm * Rm DIVXS -- -- N = Sm * Dm + Sm * Dm -- DIVXU Z = Sm * Sm-1 * ...... * S0 -- -- N = Sm Z = Sm * Sm-1 * ...... * S0 EXTS -- -- -- -- EEPMOV -- -- 0 -- N = Rm 0 -- Z = Rm * Rm-1 * ...... * R0 -- 0 -- EXTU INC Z = Rm * Rm-1 * ...... * R0 -- N = Rm Z = Rm * Rm-1 * ...... * R0 V = Dm * Rm -- -- LDC -- -- -- JSR -- -- -- -- -- JMP Stores the corresponding bits of the result. -- -- -- -- -- MAC* -- -- -- -- -- MOV -- MOVFPE -- MOVTPE -- -- -- 0 -- -- -- -- LDMAC* 0 -- LDM No flags change when the operand is EXR. 0 -- N = Rm Z = Rm * Rm-1 * ...... * R0 N = Rm Z = Rm * Rm-1 * ...... * R0 N = Rm -- MULXS Z = Rm * Rm-1 * ...... * R0 -- -- N = R2m Z = R2m * R2m-1 * ...... * R0 Rev. 4.00 Feb 24, 2006 page 306 of 322 REJ09B0139-0400 Section 2 Instruction Descriptions C Definition -- -- -- -- -- V Z MULXU NEG N H Instruction H = Dm-4 + Rm-4 N = Rm Z = Rm * Rm-1 * ...... * R0 V = Dm * Rm -- OR -- NOT -- -- 0 -- -- -- -- C = Dm + Rm NOP 0 -- N = Rm Z = Rm * Rm-1 * ...... * R0 N = Rm -- ROTL -- PUSH -- 0 -- POP 0 -- ORC Z = Rm * Rm-1 * ...... * R0 0 Stores the corresponding bits of the result. No flags change when the operand is EXR. N = Rm Z = Rm * Rm-1 * ...... * R0 N = Rm Z = Rm * Rm-1 * ...... * R0 N = Rm Z = Rm * Rm-1 * ...... * R0 0 -- C = Dm (1-bit shift) or C = Dm-1 (2-bit shift) ROTR N = Rm Z = Rm * Rm-1 * ...... * R0 0 -- C = D0 (1-bit shift) or C = D1 (2-bit shift) ROTXL N = Rm Z = Rm * Rm-1 * ...... * R0 0 -- C = Dm (1-bit shift) or C = Dm-1 (2-bit shift) ROTXR N = Rm Z = Rm * Rm-1 * ...... * R0 Stores the corresponding bits of the result. -- -- -- -- -- -- SHAL RTS C = D0 (1-bit shift) or C = D1 (2-bit shift) RTE N = Rm Z = Rm * Rm-1 * ...... * R0 V = Dm * Dm-1 + Dm * Dm-1 (1-bit shift) V = Dm * Dm-1 * Dm-2 + Dm * Dm-1 * Dm-2 (2-bit shift) C = Dm (1-bit shift) or C = Dm-1 (2-bit shift) Rev. 4.00 Feb 24, 2006 page 307 of 322 REJ09B0139-0400 Instruction H N Z V C SHAR -- 0 Section 2 Instruction Descriptions Definition N = Rm Z = Rm * Rm-1 * ...... * R0 0 -- C = D0 (1-bit shift) or C = D1 (2-bit shift) SHLL N = Rm Z = Rm * Rm-1 * ...... * R0 0 0 -- C = Dm (1-bit shift) or C = Dm-1 (2-bit shift) SHLR N = Rm Z = Rm * Rm-1 * ...... * R0 -- -- -- -- -- STC -- -- -- -- -- STM -- -- -- -- -- STMAC* -- C = D0 (1-bit shift) or C = D1 (2-bit shift) SLEEP -- N = 1 if MAC instruction resulted in negative value in MAC register Z = 1 if MAC instruction resulted in zero value in MAC register V = 1 if MAC instruction resulted in overflow SUB H = Sm-4 * Dm-4 + Dm-4 * Rm-4 + Sm-4 * Rm-4 N = Rm Z = Rm * Rm-1 * ...... * R0 V = Sm * Dm * Rm + Sm * Dm * Rm C = Sm * Dm + Dm * Rm + Sm * Rm -- -- -- -- SUBX -- SUBS H = Sm-4 * Dm-4 + Dm-4 * Rm-4 + Sm-4 * Rm-4 N = Rm Z = Z' * Rm * ...... * R0 V = Sm * Dm * Rm + Sm * Dm * Rm -- C = Sm * Dm + Dm * Rm + Sm * Rm TAS 0 -- N = Dm TRAPA -- -- -- XOR -- Z = Dm * Dm-1 * ...... * D0 -- -- 0 -- N = Rm XORC Z = Rm * Rm-1 * ...... * R0 Stores the corresponding bits of the result. No flags change when the operand is EXR. Note: * These instructions are supported by the H8S/2600 CPU only. Rev. 4.00 Feb 24, 2006 page 308 of 322 REJ09B0139-0400 Section 3 Processing States Section 3 Processing States 3.1 Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 3.1 shows a diagram of the processing states. Figure 3.2 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped. Exception-handling state A transient state in which the CPU changes the normal processing flow in response to a reset, interrupt, or trap instruction. Processing states Program execution state The CPU executes program instructions in sequence. Bus-released state The external bus has been released in response to a bus request signal from a bus master other than the CPU. Sleep mode Software standby mode Power-down state CPU operation is stopped to conserve power.* Hardware standby mode Note: * The power-down state also includes a medium-speed mode, module stop mode, etc. Figure 3.1 Processing States Rev. 4.00 Feb 24, 2006 page 309 of 322 REJ09B0139-0400 Section 3 Processing States End of bus request Bus request Program execution state End of bus request Bus request SLEEP instruction with SSBY = 1 Bus-released state End of exception handling SLEEP instruction with SSBY = 0 Request for exception handling Sleep mode Interrupt request Exception-handling state External interrupt Software standby mode RES = high Reset state*1 STBY = high, RES = low Hardware standby mode*2 Power-down state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. 2. From any state, a transition to hardware standby mode occurs when STBY goes low. Figure 3.2 State Transitions 3.2 Reset State When the RES input goes low all current processing stops and the CPU enters the reset state. Reset exception handling starts when the RES signal changes from low to high. The reset state can also be entered by a watchdog timer overflow. For details, refer to the relevant microcontroller hardware manual. Rev. 4.00 Feb 24, 2006 page 310 of 322 REJ09B0139-0400 Section 3 Processing States 3.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. 3.3.1 Types of Exception Handling and Their Priority Exception handling is performed for traces, resets, interrupts, and trap instructions. Table 3.1 indicates the types of exception handling and their priority. Trap instruction exception handling is always accepted, in the program execution state. Exception handling and the stack structure differ according to the interrupt control mode set in SYSCR. Table 3.1 Exception Handling Types and Priority Priority Type of Exception Detection Timing Start of Exception Handling High Reset Synchronized with clock Exception handling starts immediately when RES changes from low to high Trace End of instruction execution or end of exception-handling 1 sequence* When the trace (T) bit is set to 1, the trace starts at the end of the current instruction or current exceptionhandling sequence Interrupt End of instruction execution or end of exception-handling 2 sequence* When an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence Trap instruction When TRAPA instruction is executed Exception handling starts when a trap (TRAPA) instruction is 3 executed* Low Notes: 1. Traces are enabled only in interrupt control modes 2 and 3. Trace exception-handling is not executed at the end of the RTE instruction. 2. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after reset exception handling. 3. Trap instruction exception handling is always accepted, in the program execution state. For details on interrupt control modes, exception sources, and exception handling, refer to the relevant microcontroller hardware manual. Rev. 4.00 Feb 24, 2006 page 311 of 322 REJ09B0139-0400 Section 3 Processing States 3.3.2 Reset Exception Handling After the RES pin has gone low and the reset state has been entered, reset exception handling starts when RES goes high again. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during reset exception handling and after it ends. 3.3.3 Trace Traces are enabled only in interrupt control modes 2 and 3. Trace mode is entered when the T bit of EXR is set to 1. When trace mode is established, trace exception handling starts at the end of each instruction. At the end of a trace exception-handling sequence, the T bit of EXR is cleared to 0 and trace mode is cleared. Interrupt masks are not affected. The T bit saved on the stack retains its value of 1, and when the RTE instruction is executed to return from the trace exception-handling routine, trace mode is entered again. Trace exceptionhandling is not executed at the end of the RTE instruction. Trace mode is not entered in interrupt control modes 0 and 1, regardless of the state of the T bit. 3.3.4 Interrupt Exception Handling and Trap Instruction Exception Handling When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer (ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start address (vector) from the exception vector table and execution branches to that address. Figure 3.3 shows the stack after exception handling ends, for the case of interrupt mode 1 in advanced mode. 3.3.5 Usage Notes (1) Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an interrupt is generated during execution of the instruction, the interrupt concerned will still be Rev. 4.00 Feb 24, 2006 page 312 of 322 REJ09B0139-0400 Section 3 Processing States enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked by the CPU. (2) Instructions that Disable Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. (3) Interrupts during Execution of EEPMOV Instructions Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the transfer is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at the next break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W R4,R4 BNE L1 Rev. 4.00 Feb 24, 2006 page 313 of 322 REJ09B0139-0400 Section 3 Processing States Normal mode SP SP EXR Reserved* CCR CCR* CCR CCR* PC (16 bits) PC (16 bits) (a) Interrupt control modes 0 & 1 (b) Interrupt control modes 2 & 3 Advanced mode SP SP EXR Reserved* CCR CCR PC (24 bits) PC (24 bits) (c) Interrupt control modes 0 & 1 (d) Interrupt control modes 2 & 3 Note: * Ignored when returning. Figure 3.3 Stack Structure after Exception Handling (Example) 3.4 Program Execution State In this state the CPU executes program instructions in sequence. Rev. 4.00 Feb 24, 2006 page 314 of 322 REJ09B0139-0400 Section 3 Processing States 3.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts except for internal operations. Bus masters other than the CPU may include the direct memory access controller (DMAC) and data transfer controller (DTC). For further details, refer to the relevant microcontroller hardware manual. 3.6 Power-Down State The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are three modes in which the CPU stops operating: sleep mode, software standby mode, and hardware standby mode. There are also two other power-down modes: medium-speed mode and module stop mode. In medium-speed mode the CPU and other bus masters operate on a medium-speed clock. Module stop mode permits halting of the operation of individual modules, other than the CPU. For details, refer to the relevant microcontroller hardware manual. 3.6.1 Sleep Mode A transition to sleep mode is made if the SLEEP instruction is executed while the software standby bit (SSBY) in the system control register (SYSCR) is cleared to 0. In sleep mode, CPU operations stop immediately after execution of the SLEEP instruction. The contents of CPU registers are retained. 3.6.2 Software Standby Mode A transition to software standby mode is made if the SLEEP instruction is executed while the SSBY bit in SYSCR is set to 1. In software standby mode, the CPU and clock halt and all on-chip operations stop. The on-chip supporting modules are reset, but as long as a specified voltage is supplied, the contents of CPU registers and on-chip RAM are retained. The I/O ports also remain in their existing states. Rev. 4.00 Feb 24, 2006 page 315 of 322 REJ09B0139-0400 Section 3 Processing States 3.6.3 Hardware Standby Mode A transition to hardware standby mode is made when the STBY pin goes low. In hardware standby mode, the CPU and clock halt and all on-chip operations stop. The on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are retained. Rev. 4.00 Feb 24, 2006 page 316 of 322 REJ09B0139-0400 Section 4 Basic Timing Section 4 Basic Timing 4.1 Overview The CPU is driven by a system clock, denoted by the symbol . The period from one rising edge of to the next is referred to as a "state." The memory cycle or bus cycle consists of one, two, or three states. Different methods are used to access on-chip memory, on-chip supporting modules, and the external address space. Refer to the relevant microcontroller hardware manual for details. 4.2 On-Chip Memory (ROM, RAM) On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word access. Figure 4.1 shows the on-chip memory access cycle. Figure 4.2 shows the pin states. Bus cycle T1 Internal address bus Read access Address Internal read signal Internal data bus Read data Internal write signal Write access Internal data bus Write data Figure 4.1 On-Chip Memory Access Cycle Rev. 4.00 Feb 24, 2006 page 317 of 322 REJ09B0139-0400 Section 4 Basic Timing Bus cycle T1 Address bus Unchanged AS High RD High HWR, LWR High Data bus High-impedance state Figure 4.2 Pin States during On-Chip Memory Access Rev. 4.00 Feb 24, 2006 page 318 of 322 REJ09B0139-0400 Section 4 Basic Timing 4.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular on-chip register being accessed. Figure 4.3 shows the access timing for the on-chip supporting modules. Figure 4.4 shows the pin states. Bus cycle T1 T2 Internal address bus Address Internal read signal Read access Internal data bus Read data Internal write signal Write access Internal data bus Write data Figure 4.3 On-Chip Supporting Module Access Timing Rev. 4.00 Feb 24, 2006 page 319 of 322 REJ09B0139-0400 Section 4 Basic Timing Bus cycle T1 T2 Address bus Unchanged AS High RD High HWR, LWR High Data bus High-impedance state Figure 4.4 Pin States during On-Chip Supporting Module Access 4.4 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. Figure 4.5 shows the read timing for two-state and three-state access. Figure 4.6 shows the write timing for two-state and three-state access. In three-state access, wait states can be inserted. For further details, refer to the relevant microcontroller hardware manual. Rev. 4.00 Feb 24, 2006 page 320 of 322 REJ09B0139-0400 Section 4 Basic Timing Read cycle T1 T2 Address bus Address AS RD Data bus Read data (a) Two-State Access Read cycle T1 T2 T3 Address bus Address AS RD Data bus Read data (b) Three-State Access Figure 4.5 External Device Access Timing (Read Timing) Rev. 4.00 Feb 24, 2006 page 321 of 322 REJ09B0139-0400 Section 4 Basic Timing Write cycle T1 T2 Address bus Address AS HWR, LWR Data bus Write data (a) Two-State Access Write cycle T1 T2 T3 Address bus Address AS HWR, LWR Data bus Write data (b) Three-State Access Figure 4.6 External Device Access Timing (Write Timing) Rev. 4.00 Feb 24, 2006 page 322 of 322 REJ09B0139-0400 Renesas 16-Bit Single-Chip Microcomputer Software Manual H8S/2600 Series, H8S/2000 Series Publication Date: 1st Edition, March 1995 Rev.4.00, February 24, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. 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