DF2238BTE13V - Renesas Electronics

To our customers,

Old Company Name in Catalogs and Other Documents

On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corporation took over all the business of both

companies. Therefore, although the old company name remains in this document, it is a valid

Renesas Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1st, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

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H8S/2600 Series,

H8S/2000 Series

Software Manual

User’s Manual

Rev.4.00 2006.02

Renesas 16-Bit Single-Chip

Microcomputer

H8S Family

Rev. 4.00 Feb 24, 2006 page ii of xiv

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circuit application examples contained in these materials.

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subject to change by Renesas Technology Corp. without notice due to product improvements or

other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or

an authorized Renesas Technology Corp. product distributor for the latest product information

before purchasing a product listed herein.

The information described here may contain technical inaccuracies or typographical errors.

Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising

from these inaccuracies or errors.

Please also pay attention to information published by Renesas Technology Corp. by various means,

including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).

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contained therein.

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and

more reliable, but there is always the possibility that trouble may occur with them. Trouble with

semiconductors may lead to personal injury, fire or property damage.

Remember to give due consideration to safety when making your circuit designs, with appropriate

measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or

(iii) prevention against any malfunction or mishap.

Keep safety first in your circuit designs!

Notes regarding these materials

Rev. 4.00 Feb 24, 2006 page iii of xiv

Preface

The H8S/2600 Series and the H8S/2000 Series are built around an H8S/2000 CPU core.

The H8S/2600 and H8S/2000 CPUs have the same internal 32-bit architecture. Both CPUs

execute basic instructions in one state, have sixteen 16-bit registers, and have a concise, optimized

instruction set. They can address a 16-Mbyte linear address space.Programs coded in the high-

level language C can be compiled to high-sp eed executable code.

For easy migration, the instruction set is upward-compatible with the H8/300H, H8/300, and

H8/300L Series at the object-code level.

The H8S/2600 CPU is upward-compatible with the H8S/2000 CPU at the object-code level, and

supports sum of products instructions.

This manual gives details of the H8S/2600 and H8S/2000 instructions and can be sued with all

microcontrollers in the H8S/2600 Series and the H8S/2000 Series.

For hard war e details, r ef e r to the r e levant microcontroller hard war e manuals.

Rev. 4.00 Feb 24, 2006 page iv of xiv

Rev. 4.00 Feb 24, 2006 page v of xiv

Main Revisions for This Edition

Item Page Revisions (See Manual for Details)

1.1.1 Features 2 Note * added

— Maximum clock frequency: 20 MHz*

Note: * The maximum operating frequency and instruction

execution time differ depending on the product.

2.2.22 CLRMAC

Operand Format and

Number of States

Required for Execution

90 Further explanation added to note

The number of states may differ depending on the prod uct.

For details, refer to the hardware manual of the product in

question.

2.2.24 DAA

Description 94 Table amended

C Flag

before

Adjustment

Upper 4 Bits

before

Adjustment

H Flag

before

Adjustment

Lower 4 Bits

before

Adjustment

Value

Added

(Hexadecimal)

C Flag

after

Adjustment

0 A to F 1 0 to 3 66 1

10 to 2 0 0 to 9 60 1

10 to 2 0 A to F 66 1

10 to 3 1 0 to 3 6 6 1

2.2.37 LDMAC

Operand Format and

Number of States

Required for Execution

130

2.2.42 (1) MULXS (B)

Operand Format and

Number of States

Required for Execution

151

Further explanation added to note

The number of states may differ depending on the prod uct.

For details, refer to the hardware manual of the product in

question.

2.2.42 (2) MULXS (W)

Operand Format and

Number of States

Required for Execution

152

2.2.43 (1) MULXU (B)

Operand Format and

Number of States

Required for Execution

153

2.2.43 (2) MULXU (W)

Operand Format and

Number of States

Required for Execution

154

Rev. 4.00 Feb 24, 2006 page vi of xiv

Item Page Revisions (See Manual for Details)

2.2.64 STMAC

Operand Format and

Number of States

Required for Execution

232 Table amended

Instruction Format

1st byte 2nd byte 3rd byte 4th byte

0220erd

0230erd

Further explanation added to note

The number of states may differ depending on the prod uct.

For details, refer to the hardware manual of the product in

question.

2.3 Instruction Set

Table 2.1 Instruction

Set

250,

251,

260,

262

Note 7 amended and note 10 added

Mnemonic

DAS DAS Rd 1

MULXU MULXU.B Rs,Rd 3 (12*7)

MULXU.W Rs,ERd 4 (20*7)

*4 *10

MULXS MULXS.B Rs,Rd 4 (13*7)

MULXS.W Rs,ERd 5 (21*7)

No. of

States*

Normal

Advanced

*5 *10

Mnemonic

MAC*

MAC @ERn+,@ERm+ 4

CLRMAC

CLRMAC 2*

LDMAC*

LDMAC ERs,MACH 2*

LDMAC ERs,MACL 2*

STMAC*

STMAC MACH,ERd 1*

STMAC MACL,ERd 1*

No. of

States*

Normal

Advanced

Mnemonic

No. of

States*

Normal

Advanced

TRAPA TRAPA #x:2 7[9] 8[9]

RTE RTE 5[9]

*7*7

Notes: 7. Values in parentheses ( ) are for the H8S/2000

CPU. Values in square brackets [ ] apply to interrupt control

modes 2 and 3.

10. The number of states may differ depending on the product.

For details, refer to the hardware manual of the product in

question.

Rev. 4.00 Feb 24, 2006 page vii of xiv

Item Page Revisions (See Manual for Details)

Note 6 added

Instruction

Fetch

Branch

Address

Read Stack

Operation Byte Data

Access Word Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

CLRMAC*

CLRMAC 1 1 *

2.6 Number of States

Required for Instruction

Execution

Table 2.5 Number of

Cycles in Instruction

Execution

283,

285,

286,

288

Instruction

Fetch

Branch

Address

Read Stack

Operation Byte Data

Access Word Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

LDMAC*5LDMAC E Rs,MACH 1 *3 *6

LDMAC ERs,MACL 1

1*3 *6

Instruction

Fetch

Branch

Address

Read Stack

Operation Byte Data

Access Word Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

MULXS MULXS.B Rs,Rd H8S/2600 2 *

H8S/2000 2 1

MULXS.W Rs,ERd H8S/2600 2 *

H8S/2000 2 9

MULXU MULXU.B Rs,Rd H8S/2600 1 *

H8S/2000 1 1

MULXU.W Rs,ERd H8S/2600 1 *

H8S/2000 1

Instruction

Fetch

Branch

Address

Read Stack

Operation Byte Data

Access Word Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

STMAC*

STMAC MACH,ERd 1 0*

STMAC MACL,ERd 1 0*

Notes: 6. The number of states may differ depending on the

product. For details, refer to the hardware manual of the

product in question.

2.7 Bus States During

Instruction Execution 290 :M deleted from legend

Table 2.6 Instruction

Execution Cycles 293 to

302 All instances of :M deleted from table

3.3.5 Usage Notes 312,

313 Newly added

Rev. 4.00 Feb 24, 2006 page viii of xiv

Rev. 4.00 Feb 24, 2006 page ix of xiv

Contents

Section 1 CPU...................................................................................................................... 1

1.1 Overview........................................................................................................................... 1

1.1.1 Features................................................................................................................ 1

1.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU.................................. 2

1.1.3 Differences from H8/300 CPU ............................................................................ 3

1.1.4 Differences from H8/300H CPU.......................................................................... 4

1.2 CPU Operating Modes...................................................................................................... 5

1.3 Address Space................................................................................................................... 10

1.4 Register Configuration...................................................................................................... 11

1.4.1 Overview.............................................................................................................. 11

1.4.2 General Registers................................................................................................. 12

1.4.3 Control Registers ................................................................................................. 13

1.4.4 Initial Register Values.......................................................................................... 15

1.5 Data Formats..................................................................................................................... 16

1.5.1 General Register Data Formats............................................................................ 16

1.5.2 Memory Data Formats......................................................................................... 18

1.6 Instruction Set................................................................................................................... 19

1.6.1 Overview.............................................................................................................. 19

1.6.2 Instructions and Addressing Modes..................................................................... 20

1.6.3 Table of Instructions Classified by Function....................................................... 22

1.6.4 Basic Instruction Formats.................................................................................... 32

1.7 Addressing Modes and Effective Address Calculation..................................................... 33

Section 2 Instruction Descriptions.................................................................................. 41

2.1 Tables and Symbols.......................................................................................................... 41

2.1.1 Assembly-Language Format................................................................................ 42

2.1.2 Operation ............................................................................................................. 43

2.1.3 Condition Code.................................................................................................... 44

2.1.4 Instruction Format................................................................................................ 44

2.1.5 Register Specification.......................................................................................... 45

2.1.6 Bit Data Access in Bit Manipulation Instructions................................................ 46

2.2 Instruction Descriptions.................................................................................................... 47

2.2.1 (1) ADD (B).......................................................................................................... 48

2.2.1 (2) ADD (W)......................................................................................................... 49

2.2.1 (3) ADD (L).......................................................................................................... 50

2.2.2 ADDS.............................................................................................................. 51

2.2.3 ADDX............................................................................................................. 52

2.2.4 (1) AND (B).......................................................................................................... 53

Rev. 4.00 Feb 24, 2006 page x of xiv

2.2.4 (2) AND (W)......................................................................................................... 54

2.2.4 (3) AND (L).......................................................................................................... 55

2.2.5 (1) ANDC ............................................................................................................. 56

2.2.5 (2) ANDC ............................................................................................................. 57

2.2.6 BAND ............................................................................................................. 58

2.2.7 Bcc .................................................................................................................. 60

2.2.8 BCLR.............................................................................................................. 62

2.2.9 BIAND............................................................................................................ 64

2.2.10 BILD ............................................................................................................... 66

2.2.11 BIOR............................................................................................................... 68

2.2.12 BIST................................................................................................................ 70

2.2.13 BIXOR............................................................................................................ 72

2.2.14 BLD................................................................................................................. 74

2.2.15 BNOT.............................................................................................................. 76

2.2.16 BOR ................................................................................................................ 78

2.2.17 BSET............................................................................................................... 80

2.2.18 BSR................................................................................................................. 82

2.2.19 BST ................................................................................................................. 84

2.2.20 BTST............................................................................................................... 86

2.2.21 BXOR.............................................................................................................. 88

2.2.22 CLRMAC........................................................................................................ 90

2.2.23 (1) CMP (B).......................................................................................................... 91

2.2.23 (2) CMP (W)......................................................................................................... 92

2.2.23 (3) CMP (L).......................................................................................................... 93

2.2.24 DAA................................................................................................................ 94

2.2.25 DAS................................................................................................................. 96

2.2.26 (1) DEC (B) .......................................................................................................... 98

2.2.26 (2) DEC (W) ......................................................................................................... 99

2.2.26 (3) DEC (L)........................................................................................................... 100

2.2.27 (1) DIVXS (B)...................................................................................................... 101

2.2.27 (2) DIVXS (W)..................................................................................................... 103

2.2.28 (1) DIVXU (B) ..................................................................................................... 105

2.2.28 (2) DIVXU (W) .................................................................................................... 107

2.2.29 (1) EEPMOV (B).................................................................................................. 109

2.2.29 (2) EEPMOV (W)................................................................................................. 110

2.2.30 (1) EXTS (W) ....................................................................................................... 112

2.2.30 (2) EXTS (L)......................................................................................................... 113

2.2.31 (1) EXTU (W)....................................................................................................... 114

2.2.31 (2) EXTU (L)........................................................................................................ 115

2.2.32 (1) INC (B) ........................................................................................................... 116

2.2.32 (2) INC (W) .......................................................................................................... 117

Rev. 4.00 Feb 24, 2006 page xi of xiv

2.2.32 (3) INC (L)............................................................................................................ 118

2.2.33 JMP ................................................................................................................. 119

2.2.34 JSR.................................................................................................................. 120

2.2.35 (1) LDC (B) .......................................................................................................... 122

2.2.35 (2) LDC (B) .......................................................................................................... 123

2.2.35 (3) LDC (W) ......................................................................................................... 124

2.2.35 (4) LDC (W) ......................................................................................................... 126

2.2.36 LDM................................................................................................................ 128

2.2.37 LDMAC.......................................................................................................... 130

2.2.38 MAC................................................................................................................ 131

2.2.39 (1) MOV (B)......................................................................................................... 134

2.2.39 (2) MOV (W)........................................................................................................ 135

2.2.39 (3) MOV (L) ......................................................................................................... 136

2.2.39 (4) MOV (B)......................................................................................................... 137

2.2.39 (5) MOV (W)........................................................................................................ 139

2.2.39 (6) MOV (L) ......................................................................................................... 141

2.2.39 (7) MOV (B)......................................................................................................... 143

2.2.39 (8) MOV (W)........................................................................................................ 145

2.2.39 (9) MOV (L) ......................................................................................................... 147

2.2.40 MOVFPE ........................................................................................................ 149

2.2.41 MOVTPE........................................................................................................ 150

2.2.42 (1) MULXS (B) .................................................................................................... 151

2.2.42 (2) MULXS (W) ................................................................................................... 152

2.2.43 (1) MULXU (B).................................................................................................... 153

2.2.43 (2) MULXU (W)................................................................................................... 154

2.2.44 (1) NEG (B).......................................................................................................... 155

2.2.44 (2) NEG (W)......................................................................................................... 156

2.2.44 (3) NEG (L) .......................................................................................................... 157

2.2.45 NOP................................................................................................................. 158

2.2.46 (1) NOT (B).......................................................................................................... 159

2.2.46 (2) NOT (W)......................................................................................................... 160

2.2.46 (3) NOT (L) .......................................................................................................... 161

2.2.47 (1) OR (B)............................................................................................................. 162

2.2.47 (2) OR (W)............................................................................................................ 163

2.2.47 (3) OR (L)............................................................................................................. 164

2.2.48 (1) ORC ................................................................................................................ 165

2.2.48 (2) ORC ................................................................................................................ 166

2.2.49 (1) POP (W).......................................................................................................... 167

2.2.49 (2) POP (L) ........................................................................................................... 168

2.2.50 (1) PUSH (W)....................................................................................................... 169

2.2.50 (2) PUSH (L) ........................................................................................................ 170

Rev. 4.00 Feb 24, 2006 page xii of xiv

2.2.51 (1) ROTL (B)........................................................................................................ 171

2.2.51 (2) ROTL (B)........................................................................................................ 172

2.2.51 (3) ROTL (W)....................................................................................................... 173

2.2.51 (4) ROTL (W)....................................................................................................... 174

2.2.51 (5) ROTL (L)........................................................................................................ 175

2.2.51 (6) ROTL (L)........................................................................................................ 176

2.2.52 (1) ROTR (B)........................................................................................................ 177

2.2.52 (2) ROTR (B)........................................................................................................ 178

2.2.52 (3) ROTR (W)....................................................................................................... 179

2.2.52 (4) ROTR (W)....................................................................................................... 180

2.2.52 (5) ROTR (L)........................................................................................................ 181

2.2.52 (6) ROTR (L)........................................................................................................ 182

2.2.53 (1) ROTXL (B)..................................................................................................... 183

2.2.53 (2) ROTXL (B)..................................................................................................... 184

2.2.53 (3) ROTXL (W).................................................................................................... 185

2.2.53 (4) ROTXL (W).................................................................................................... 186

2.2.53 (5) ROTXL (L) ..................................................................................................... 187

2.2.53 (6) ROTXL (L) ..................................................................................................... 188

2.2.54 (1) ROTXR (B)..................................................................................................... 189

2.2.54 (2) ROTXR (B)..................................................................................................... 190

2.2.54 (3) ROTXR (W).................................................................................................... 191

2.2.54 (4) ROTXR (W).................................................................................................... 192

2.2.54 (5) ROTXR (L)..................................................................................................... 193

2.2.54 (6) ROTXR (L)..................................................................................................... 194

2.2.55 RTE................................................................................................................. 195

2.2.56 RTS ................................................................................................................. 197

2.2.57 (1) SHAL (B)........................................................................................................ 198

2.2.57 (2) SHAL (B)........................................................................................................ 199

2.2.57 (3) SHAL (W)....................................................................................................... 200

2.2.57 (4) SHAL (W)....................................................................................................... 201

2.2.57 (5) SHAL (L)........................................................................................................ 202

2.2.57 (6) SHAL (L)........................................................................................................ 203

2.2.58 (1) SHAR (B)........................................................................................................ 204

2.2.58 (2) SHAR (B)........................................................................................................ 205

2.2.58 (3) SHAR (W) ....................................................................................................... 206

2.2.58 (4) SHAR (W) ....................................................................................................... 207

2.2.58 (5) SHAR (L)........................................................................................................ 208

2.2.58 (6) SHAR (L)........................................................................................................ 209

2.2.59 (1) SHLL (B) ........................................................................................................ 210

2.2.59 (2) SHLL (B) ........................................................................................................ 211

2.2.59 (3) SHLL (W) ....................................................................................................... 212

Rev. 4.00 Feb 24, 2006 page xiii of xiv

2.2.59 (4) SHLL (W) ....................................................................................................... 213

2.2.59 (5) SHLL (L)......................................................................................................... 214

2.2.59 (6) SHLL (L)......................................................................................................... 215

2.2.60 (1) SHLR (B)........................................................................................................ 216

2.2.60 (2) SHLR (B)........................................................................................................ 217

2.2.60 (3) SHLR (W)....................................................................................................... 218

2.2.60 (4) SHLR (W)....................................................................................................... 219

2.2.60 (5) SHLR (L) ........................................................................................................ 220

2.2.60 (6) SHLR (L) ........................................................................................................ 221

2.2.61 SLEEP............................................................................................................. 222

2.2.62 (1) STC (B)........................................................................................................... 223

2.2.62 (2) STC (B)........................................................................................................... 224

2.2.62 (3) STC (W).......................................................................................................... 225

2.2.62 (4) STC (W).......................................................................................................... 227

2.2.63 STM ................................................................................................................ 229

2.2.64 STMAC........................................................................................................... 231

2.2.65 (1) SUB (B)........................................................................................................... 233

2.2.65 (2) SUB (W) ......................................................................................................... 235

2.2.65 (3) SUB (L)........................................................................................................... 236

2.2.66 SUBS............................................................................................................... 237

2.2.67 SUBX.............................................................................................................. 238

2.2.68 TAS................................................................................................................. 239

2.2.69 TRAPA............................................................................................................ 240

2.2.70 (1) XOR (B).......................................................................................................... 242

2.2.70 (2) XOR (W)......................................................................................................... 243

2.2.70 (3) XOR (L).......................................................................................................... 244

2.2.71 (1) XORC.............................................................................................................. 245

2.2.71 (2) XORC.............................................................................................................. 246

2.3 Instruction Set................................................................................................................... 247

2.4 Instruction Code................................................................................................................ 263

2.5 Operation Code Map......................................................................................................... 274

2.6 Number of States Required for Instruction Execution...................................................... 278

2.7 Bus States During Instruction Execution.......................................................................... 290

2.8 Condition Code Modification ........................................................................................... 304

Section 3 Processing States .............................................................................................. 309

3.1 Overview........................................................................................................................... 309

3.2 Reset State......................................................................................................................... 310

3.3 Exception-Handling State................................................................................................. 311

3.3.1 Types of Exception Handling and Their Priority................................................. 311

3.3.2 Reset Exception Handling.................................................................................... 312

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3.3.3 Trace.................................................................................................................... 312

3.3.4 Interrupt Exception Handling and Trap Instruction Exception Handling............ 312

3.3.5 Usage Notes......................................................................................................... 312

3.4 Program Execution State................................................................................................... 314

3.5 Bus-Released State............................................................................................................ 315

3.6 Power-Down State ............................................................................................................ 315

3.6.1 Sleep Mode.......................................................................................................... 315

3.6.2 Software Standby Mode....................................................................................... 315

3.6.3 Hardware Standby Mode ..................................................................................... 316

Section 4 Basic Timing...................................................................................................... 317

4.1 Overview........................................................................................................................... 317

4.2 On-Chip Memory (ROM, RAM)...................................................................................... 317

4.3 On-Chip Supporting Module Access Timing.................................................................... 319

4.4 External Address Space Access Timing............................................................................ 320

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Section 1 CPU

1.1 Overview

The H8S/2600 CPU and the H8S/2000 CPU are high-speed central processing units with a

common an intern al 32-bit architecture. Each CPU is upward-compatible with the H8/300 and

H8/300H CPUs. The H8S/2600 CPU and H8S/2000 CPU have sixteen 16-bit general registers,

can address a 4- Gbyte linear addr ess sp ace, and are ideal for realtime control.

1.1.1 Features

The H8S/2600 CPU and H8S/2000 CPU have the following features.

• Upward-compatible with H8 /300 and H8/300H CPUs

 Can execute H8/300 and H8/300 H object programs

• General-register architecture

 Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit

registers)

• Sixty-nine basic instructions (H8S/2000 CPU has sixty-five)

 8/16/32-b it ar ithmetic and logic in str uctions

 Multiply and divide instructio ns

 Powerful bit-manipulation instructions

 Multiply-and-accumulate instruction (H8S/2600 CPU only)

• Eight addressing modes

 Register direct [Rn]

 Register indirect [@ERn]

 Register indirect with displacement [@(d:16,ERn) or @( d:32,ERn)]

 Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]

 Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]

 Immediate [#xx:8, #xx: 16, or #xx: 3 2]

 Program-counter relative [@(d:8,PC) or @(d:16,PC)]

 Memory indirect [@@aa:8]

• 4-Gbyte address space

 Program: 16 Mbytes

 Data: 4 Gb ytes

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• High-speed operation

 All frequently-u sed instructions execute in one or two states

 Maximum clock frequency: 20 MHz*

 8/16/32-bit register-register add/subtract: 50 ns

 8 × 8-bit register-register multiply: 150 ns (H8S/2000 CPU: 600 ns)

 16 ÷ 8-bit register-register divide: 600 ns

 16 × 16-bit register-register multiply: 200 ns (H8S/2000 CPU: 1000 ns)

 32 ÷ 16-bit regis t er-regis t er divide: 1000 ns

• Two CPU operating modes

 Normal mode

 Advanced mode

• Power-down modes

 Transition to power-down state by SLEEP instruction

 CPU clock speed selection

Note: * The maximum operating frequency and instruction execution time differ depending on

the product.

1.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU

Differences between the H8S/2600 CPU and the H8S/2000 CPU are as follows.

• Register configuration

 The MAC register is supported only by the H8S/2600 CPU.

For details, see section 1.4, Register Configuration.

• Basic instructions

 The MAC, CLRMAC, LDMAC, and STMAC instructions are supported only by the

H8S/2600 CPU.

For details, see section 1.6, Instruction Set, and Section 2, Instruction Descriptions.

• Number of states required for execution

 The number of states required for execution of the MULXU and MULXS instructions.

For details, see section 2.6, Number of States Required for Execution.

In addition, there may be defferences in address spaces, EXR register fu nctions, power-down

states, and so on. For details, refer to th e relevant microcontroller hardware manual.

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1.1.3 Differences from H8/300 CPU

In comparison with the H8/300 CPU, the H8S/2600 CPU and H8S/2000 CPU have the following

enhancements.

• More general registers and control registers

 Eight 16-bit registers, one 8-bit and two 32-bit control registers have been added.

• Expanded address space

 Normal mode supports the same 64-kbyte address space as the H8/300 CPU.

 Advanced mode supports a maximum 4-Gbyte address space.

• Enhanced addressing

 The addressing modes have been enhanced to make effective use of the 4-Gbyte address

space.

• Enhanced instructions

 Addressing modes of bit-manipulation instructions have been enhanced.

 Signed multiply and divide in structions have be en added.

 A multiply-and-accumulate instruction has been added. (H8S/2600CPU only)

 Two-bit shift and rotate instructions have been added.

 Instructio ns for saving and restoring multiple registers have been added.

 A test and set instruction has been added.

• Higher speed

 Basic instructions execute twice as fast.

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1.1.4 Differences from H8/300H CPU

In comparison with the H8/300H CPU, the H8S/2600 CPU and H8S/2000 CPU have the following

enhancements.

• Additional control register

 One 8-bit and two 32-bit control registers have been added.

• Expanded address space

 Advanced mode supports a maximum 4-Gbyte data address space.

• Enhanced instructions

 Addressing modes of bit-manipulation instructions have been enhanced.

 A multiply-and-accumulate instruction has been added (H8S/2600 CPU only).

 Two-bit shift and rotate instructions have been added.

 Instructio ns for saving and r e storing multiple registers have be en added.

 A test and set instruction has been added.

• Higher speed

 Basic instructions execute twice as fast.

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1.2 CPU Operating Modes

Like the H8/300H CPU, the H8S/2600 CPU has two operating modes: normal and advanced.

Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum

4-Gbyte total address space, of which up to 16 Mbytes can be used for prog ram code and up to 4

Gbytes for data. The mode is selected with the mode pins of the microcontroller. For further

informatio n, re f er to th e relevant microcontroller hardware manual.

CPU operating modes

Normal mode

Advanced mode

Maximum 64 kbytes, program

and data areas combined

Maximum 16-Mbyte program

area and 4-Gbyte data area,

maximum 4 Gbytes for program

and data areas combined

Figure 1.1 CPU Operating Modes

(1) Normal Mode

The exception vector table and stack have the same structure as in the H8/300 CPU.

Address Space: A maximum address space of 64 kbytes can be accessed, as in the H8/300 CPU.

Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as

the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain

any value, even when the corresponding general register (R0 to R7) is used as an address register.

If the general register is referenced in the register indirect addressing mode with pre-decrement

(@–Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the

correspo ndin g exten d ed register will be affected.

Instruction Set: All additional instr uctions and addressing mo des not found in the H8/300 CPU

can be used. Only the lo wer 16 bits of effective addresses (EA) are valid.

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Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area

starting at H'0000 is allocated to the exception vector table. One branch address is stored per

16 bits (figure 1.2). The exception vector table differs depending on the microcontroller. Refer to

the relevant microcontroller hardware manual for further information.

H'0000

H'0001

H'0002

H'0003

H'0004

H'0005

H'0006

H'0007

H'0008

H'0009

H'000A

H'000B

Power-on reset exception vector

Manual reset exception vector

Exception vector 1

Exception vector 2

Exception

vector table

(Reserved for system use)

Figure 1.2 Exception Vector Table (Normal Mode)

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses

an 8-bit absolute address included in th e instruction code to specify a memory operand that

contains a branch address. In normal mode the operand is a 16-bit word operand, providing a

16-bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF.

Note that this area is also used for th e exception vector table.

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Stack Structure: When the program counter (PC) is pushed onto the stack in a subrou tine call,

and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto

the stack in exception handling, they are stored as shown in figure 1.3. When EXR is invalid, it is

not pushed onto the stack. For details, see the relevant hardware manual.

(a) Subroutine Branch (b) Exception Handling

(16 bits) EXR*1

Reserved*1 *3

CCR

CCR*3

(16 bits)

SP SP

Notes: 1.

When EXR is not used it is not stored on the stack.

SP when EXR is not used.

Ignored on return.

(SP )

Figure 1.3 Stack Structure in Normal Mode

(2) Advanced Mode

In advanced mode the data address space is larger than for the H8/300H CPU.

Address Space: The 4-Gbyte maximum address space provides linear access to a maximum

16 Mbytes of program code and maximum 4 Gbytes of data.

Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as

the upper 16-bit segments of 32-bit registers or address registers.

Instruction Set: All instructions and addressing modes can be used.

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Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top

area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each

32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 1.4).

The exception vector table differs depend ing on the microcontroller. Refer to the relevant

microcontroller hardware manual for further information.

H'00000000

H'00000003

H'00000004

H'0000000B

H'0000000C

Exception vector table

Reserved

Power-on reset exception vector

(Reserved for system use)

Reserved

Exception vector 1

Reserved

Manual reset exception vector

H'00000010

H'00000008

H'00000007

Figure 1.4 Exception Vector Table (Advanced Mode)

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses

an 8-bit absolute address included in th e instruction code to specify a memory operand that

contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing

a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area th at is regarded as

H'00. Branch addresses can be stored in the top area from H'00000000 to H'000000FF. Note that

this area is also used for the exception vector table.

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Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a

subroutine call, and the PC, condition- co de register (CCR), and ex te nded control register (EXR)

are pushed onto the stack in exception handling, they are stored as shown in figure 1.5. When

EXR is invalid, it is not pushed onto the stack. For details, see the relevant hardware manual.

(a) Subroutine Branch (b) Exception Handling

(24 bits)

EXR*1

Reserved*1 *3

CCR

(24 bits)

SP SP

Notes: 1.

When EXR is not used it is not stored on the stack.

SP when EXR is not used.

Ignored on return.

(SP )

Reserved

Figure 1.5 Stack Structure in Advanced Mode

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1.3 Address Space

Figure 1.6 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear

access to a maximum 64-kbyte address space in normal mode, and a maximum 4-Gbyte address

space in advanced mode. The address space differs depending on the operating mode. For details,

refer to th e releva nt microcontroller hardware m anu al.

(b) Advanced Mode

H'0000

H'FFFF

H'00000000

H'FFFFFFFF

H'00FFFFFF

(a) Normal Mode

Data area

Program area

Figure 1.6 Memory Map

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1.4 Register Configuration

1.4.1 Overview

The CPUs have the internal registers shown in figure 1.7. There are two types of registers: general

registers and control registers. The H8S/2000 CPU does not support the MAC register.

————

I2 I1 I0EXR 76543210

23 0

15 07 07 0

R0H

R1H

R2H

R3H

R4H

R5H

R6H

R7H

R0L

R1L

R2L

R3L

R4L

R5L

R6L

R7L

General Registers (Rn) and Extended Registers (En)

Control Registers (CR)

Legend: Stack pointer

Program counter

Extended control register

Trace bit

Interrupt mask bits

Condition-code register

Interrupt mask bit

User bit or interrupt mask bit

SP:

PC:

EXR:

I2 to I0:

CCR:

UI:

ER0

ER1

ER2

ER3

ER4

ER5

ER6

ER7 (SP)

HUNZVCCCR 76543210

Sign extension

63 32

031

MAC MACL

Half-carry flag

User bit

Negative flag

Zero flag

Overflow flag

Carry flag

Multiply-accumulate register

MAC:

MACH

Figure 1.7 CPU Registers

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1.4.2 General Registers

The CPUs have eight 32-bit general registers. These general registers are all functionally alike and

can be used as both address registers and data registers. When a general register is used as a data

as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).

The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R

(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit

registers. The E registers (E0 to E7) are also referred to as extended registers.

The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and

RL (R0L to R7L). These registers are functionally equivalent, prov iding a maximum sixteen 8-bit

registers.

Figure 1.8 illustrates the usage of the general registers. The usage of each register can be selected

independently.

• Address registers

• 32-bit registers • 16-bit registers • 8-bit registers

ER registers

(ER0 to ER7)

E registers (extended registers)

(E0 to E7)

R registers

(R0 to R7)

RH registers

(R0H to R7H)

RL registers

(R0L to R7L)

Figure 1.8 Usage of General Registers

General register ER7 has the function of stack pointer (SP) in addition to its general-register

function, and is used implicitly in exception handling and subroutine calls. Figure 1.9 shows the

stack.

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Free area

Stack area

SP (ER7)

Figure 1.9 Stack

1.4.3 Control Registers

The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR),

8-bit condition-code register (CCR), and 64-bit multiply-accumulate register (MAC: H8S/2600

CPU only).

(1) Program Counter (PC)

This 24-b it coun ter indicates th e address of the next instruction the CPU will execute. Th e length

of all CPU instru ctions is 16 bits ( one word) or a multiple of 16 bits, so the least significant PC bit

is ignored. When an instruction is fetched, the least significant PC bit is regarded as 0.

(2) Extended Control Register (EXR)

This 8-bit register contains the trace bit (T) and three interrupt mask bits (I2 to I0).

Bit 7—Trace Bit (T): Selects trace mode. When this bit is cleared to 0, instructions are executed

in sequence. When this bit is set to 1, a trace exception is generated each time an instruction is

executed.

Bits 6 to 3—Reserved: These bits are reserved, always read as 1.

Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate th e interrupt mask level (0 to

7). For details refer to the relevant microcontroller hardware manual.

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Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC

instruction s. All in ter r upts, including NMI , are disabled for three states after one of th ese

instructions is executed, except for STC.

(3) Condition-Code Register (CCR)

This 8-bit r egister contains internal CPU statu s information , including an interrupt ma sk bit (I ) and

half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.

Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted

regardless of the I bit setting.) The I bit is set to 1 by hardware at the start o f an exception-

handling sequence.

Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by sof twar e using the

LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask

bit. For details r e f er to the relevant microcontro ller hardware manual.

Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B

instruction is ex ecuted, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0

otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is ex ecuted, the H flag is

set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L,

SUB.L, CMP.L, or NEG.L in struction is executed, th e H flag is set to 1 if there is a carry or

borrow at bit 27, and cleared to 0 otherwise.

Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and

XORC instru ctions.

Bit 3—Negative Flag (N): Stores the value of the most significant bit (sign bit) of data.

Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.

Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other

times.

Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:

• Add instructions, to indicate a carry

• Subtract instructions, to indicate a borrow

• Shift and rotate instructions, to sto re the value shifted out of th e end bit

The carry flag is also used as a bit accumulator by bit manipulation instructions.

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Some instructions leave some or all of the flag bits unchanged. For the action of each instruction

on the flag bits, refer to the detailed descriptions of the instructions starting in section 2.2.1.

Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC

instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch

(Bcc) instructions.

(4) Multiply - A ccumulate Register (MAC)

The MAC register is supported only by the H8S/2600 CPU. This 64-bit register stores the results

of multip ly -and-accumulate operations. It consists of two 32-bit registers d enoted MACH and

MACL. The lower 10 bits of MACH are valid; the upper bits are a sign extension.

1.4.4 Initial Register Values

Reset exception handling loads the CPU’s program counter (PC) from the vector table, clears the

trace bit in EXR to 0, and sets the inter r upt mask bits in CCR and EXR to 1 . The other CCR bits

and the genera l r egisters ar e not initialized. In par ticular, the stack pointer (ER7 ) is not initialized.

The stack pointer should therefore be initialized by an MOV.L instruction executed immediately

after a reset.

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1.5 Data Formats

The CPUs can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data.

Bit-manipulation instructions op erate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte

operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-b it

BCD data.

1.5.1 General Register Data Formats

Figure 1.10 shows the data formats in general registers.

76543210 Don’t care

Don’t care 76543210

Don’t careUpper Lower

LSB

MSB LSB

Data Type Register Number Data Format

1-bit data

4-bit BCD data

Byte data

RnH

RnL

RnH

RnL

RnH

RnL

MSB

Don’t care Upper Lower

Don’t care

Don’t care 70

Figure 1.10 General Register Data Formats

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MSB LSB

Word data

LSB

MSB

En Rn

General register ER

General register E

General register R

General register RH

General register RL

Most significant bit

Least significant bit

Legend:

ERn:

En:

Rn:

RnH:

RnL:

MSB:

LSB:

MSB LSB

Longword data ERn

Figure 1.10 General Register Data Formats (cont)

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1.5.2 Memory Data Formats

Figure 1.11 shows the data formats in memory. The CPU can access word data and longwor d data

in memory, but word or longword data must begin at an even address. If an attempt is made to

access word or longword data at an odd address, no address error occurs bu t the least significant

bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to

instructio n fetches.

76543210

MSB LSB

MSB

LSB

MSB

LSB

Data Type Data Format

1-bit data

Byte data

Word data

Longword data

Address

Address L

Address 2M

Address 2M + 1

Address 2N

Address 2N + 1

Address 2N + 2

Address 2N + 3

Figure 1.11 Memory Data Formats

When the stack pointer (ER7) is used as an address register to access the stack, the operand size

should be word size or longword size.

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1.6 Instruction Set

1.6.1 Overview

The H8S/2600 CPU has 69types of instructions, while the H8S/2000 CPU has 65 types. The

instructions are classified by function as shown in table 1.1. For a detailed description of each

instruction, see section 2.2, Instruction Descriptions.

Table 1.1 Instruction Classification

Function Instructions Size Types

MOV BWL

POP*2, PUSH*2WL

LDM, STM L

Data transfer

MOVFPE, MOVTPE B

ADD, SUB, CMP, NEG BWL

ADDX, SUBX, DAA, DAS B

INC, DEC BWL

ADDS, SUBS L

MULXU, DIVXU, MULXS, DIVXS BW

EXTU, EXTS WL

TAS*4B

Arithmetic

operations

MAC, LDMAC, STMAC, CLRMAC*1— 4*1

Logic operations AND, OR, XOR, NOT BWL 4

Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL 8

Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,

BIAND, BOR, BIOR, BXOR, BIXOR B14

Branch Bcc*3, JMP, BSR, JSR, RTS — 5

System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP — 9

Block data transfer EEPMOV — 1

H8S/2600 CPU: Total 69 types H8S/2000 CPU: Total 65 types

Legend: B: Byte size

W: Word size

L: Longword size

Notes: 1. The MAC, LDMAC, STMAC, and CLRMAC instructions are supported only by the

H8S/2600 CPU.

2. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,

@–SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L

ERn, @–SP.

3. Bcc is the generic designation of a conditional branch instruction.

4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

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1.6.2 Instructions and Addressing Mo des

Table 1.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU

and H8S/2000 CPU can use.

Table 1.2 Combinations of Instructions and Ad dressing Modes

Addressing Modes

Function Instruction

Data MOV BWL BWL BWL BWL BWL BWL B BWL — BWL ————

transfer POP, PUSH —————————————WL

LDM, STM ————————————— L

MOVEPE, ———————B——————

MOVTPE

Arithmetic ADD, CMP BWL BWL ————————————

operations SUB WL BWL ————————————

ADDX, SUBX B B ————————————

ADDS, SUBS — L ————————————

INC, DEC — BWL ————————————

DAA, DAS — B ————————————

MULXU, — BW ————————————

DIVXU

MULXS, — BW ————————————

DIVXS

NEG — BWL ————————————

EXTU, EXTS — WL ————————————

TAS*2——B———————————

MAC*1————— ————————

CLRMAC*1—————————————

LDMAC*1, — L ————————————

STMAC*1

#xx

@ERn

@(d:16,ERn)

@(d:32,ERn)

@–ERn/@ERn+

@aa:8

@aa:16

@aa:24

@aa:32

@(d:8,PC)

@(d:16,PC)

@@aa:8

—

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Addressing Modes

Function Instruction

Logic AND, OR, BWL BWL ————————————

operations XOR

NOT — BWL ————————————

Shift — BWL ————————————

Bit manipulation — BB———BB— B ————

Branch Bcc, BSR —————————— ——

JMP, JSR ———————— ——— —

RTS —————————————

System TRAPA —————————————

control RTE —————————————

SLEEP —————————————

LDC B BWWWW— W — W ————

STC — BWWWW— W — W ————

ANDC, B —————————————

ORC, XORC

NOP —————————————

Block data transfer —————————————BW

Legend:

B: Byte

W: Word

L: Longword

Notes: 1. Supported only by the H8S/2600 CPU

2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

#xx

@ERn

@(d:16,ERn)

@(d:32,ERn)

@–ERn/@ERn+

@aa:8

@aa:16

@aa:24

@aa:32

@(d:8,PC)

@(d:16,PC)

@@aa:8

—

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1.6.3 Table of Instructions Classified by Function

Table 1.3 summarizes the instructions in each functional category. The no tation used in table 1.3

is defined next.

Operation Notation

Rd General register (destination)*

Rs General register (source)*

Rn General register*

ERn General register (32-bit register)

MAC Multiply-accumulate register (32-bit register)

(EAd) Destination operand

(EAs) Source operand

EXR Extended control r egi ster

CCR Condition-code register

N N (negative) flag in CCR

Z Z (zero) flag in CCR

V V (overflow) flag in CCR

C C (carry) flag in CCR

PC Program counter

SP Stack pointer

#IMM Immediate data

disp Displacement

+ Addition

–Subtraction

×Multiplication

÷Division

∧Logical AND

∨Logical OR

⊕Logical exclusive OR

→Move

¬Logical not (logical complement)

:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length

Note: *General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0

to R7, E0 to E7), and 32-bit registers (ER0 to ER7).

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Table 1.3 Instructions Classified by Function

Type Instruction Size*1Function

MOV B/W/L (EAs) → Rd, Rs → (EAd)

Moves data between two general registers or between

a general register and memory, or moves immediate

data to a general register.

MOVFPE B (EAs) → Rd

Moves external memory contents (addressed by

@aa:16) to a general register in synchronization with

an E clock.

MOVTPE B Rs → (EAs)

Moves general register contents to an external memory

location (addressed by @aa:16) in synchronization with

an E clock.

POP W/L @SP+ → Rn

Pops a register from the stack. POP.W Rn is identical

to MOV.W @SP+, Rn. POP.L ERn is identical to

MOV.L @SP+, ERn.

PUSH W/L Rn → @–SP

Pushes a register onto the stack. PUSH.W Rn is

identical to MOV.W Rn, @–SP. PUSH.L ERn is

identical to MOV.L ERn, @–SP.

LDM L @SP+ → Rn (register list)

Pops two or more general registers from the stack.

Data transfer

STM L Rn (register list) → @–SP

Pushes two or more general registers onto the stack.

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Type Instruction Size*1Function

ADD

SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd

Performs addition or subtraction on data in two general

registers, or on immediate data and data in a general

from byte data in a general register. Use the SUBX or

ADD instruction.)

ADDX

SUBX BRd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd

Performs addition or subtraction with carry or borrow

on byte data in two general registers, or on immediate

data and data in a general register.

INC

DEC B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd

Increments or decrements a general register by 1 or 2.

(Byte operands can be incremented or decremented by

1 only.)

ADDS

SUBS LRd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd

Adds or subtracts the value 1, 2, or 4 to or from data in

a 32-bit register.

DAA

DAS B Rd decimal adjust → Rd

Decimal-a dju st s an additi on or subtrac t io n result in a

general register by referring to the CCR to produce 4-

bit BCD data.

MULXU B/W Rd × Rs → Rd

Performs unsigned multiplication on data in two general

registers: either 8 bits × 8 bits → 16 bits or 16 bits ×

16 bits → 32 bits.

MULXS B/W Rd × Rs → Rd

Performs signed multiplication on data in two general

registers: either 8 bits × 8 bits → 16 bits or 16 bits ×

16 bits → 32 bits.

DIVXU B/W Rd ÷ Rs → Rd

Performs unsigned division on data in two general

registers: either 16 bits ÷ 8 bits → 8-bit quotient and

8-bit remainde r or 32 bits ÷ 16 bits → 16-bit quotient

and 16-bit remainder.

Arithmetic

operations

DIVXS B/W Rd ÷ Rs → Rd

Performs signed division on data in two general

registers: either 16 bits ÷ 8 bits → 8-bit quotient and

8-bit remainde r or 32 bits ÷ 16 bits → 16-bit quotient

and 16-bit remainder.

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Type Instruction Size*1Function

CMP B/W/L Rd – Rs, Rd – #IMM

Compares data in a general register with data in

another general register or with immediate data, and

sets CCR bits according to the result.

NEG B/W/L 0 – Rd → Rd

Takes the two’s complement (arithmetic complement)

of data in a general register.

EXTU W/L Rd (zero extension) → Rd

Extends the lower 8 bits of a 16-bit register to word

size, or the lower 16 bits of a 32-bit register to longword

size, by padding with zeros on the left.

EXTS W/L Rd (sign extension) → Rd

Extends the lower 8 bits of a 16-bit register to word

size, or the lower 16 bits of a 32-bit register to longword

size, by extending the sign bit.

TAS B @ERd – 0, 1 → (<bit 7> of @ERd)*2

Tests memory contents, and sets the most significant

bit (bit 7) to 1.

MAC — (EAs) × (EAd) + MAC → MAC

Performs signed mu ltiplication on memory contents

and adds the result to the multiply-accumulate register.

The following oper atio ns can be perform ed :

16 bits × 16 bits +32 bits → 32 bits, satur ati ng

16 bits × 16 bits + 42 bits → 42 bits, non-saturating

Supported by H8S/2600 CPU only.

CLRMAC —0 → MAC

Clears the multiply-accumulate register to zero.

Supported by H8S/2600 CPU only.

Arithmetic

operations

LDMAC

STMAC LRs → MAC, MAC → Rd

Transfers data between a general register and the

multiply-a ccum u late regi ster .

Supported by H8S/2600 CPU only.

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Type Instruction Size*1Function

AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd

Performs a logical AND operation on a general register

and another general register or immediate data.

OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd

Performs a logical OR operation on a general register

and another general register or immediate data.

XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logical exclusive OR operation on a general

data.

Logic operations

NOT B/W/L ¬ (Rd) → (Rd)

Takes the one’s complement of general register

contents.

SHAL

SHAR B/W/L Rd (shift) → Rd

Performs an arithmetic shift on general register

contents.

1-bit or 2-bit shift is possible.

SHLL

SHLR B/W/L Rd (shift) → Rd

Performs a logical shift on general register contents.

1-bit or 2-bit shift is possible.

ROTL

ROTR B/W/L Rd (rotate) → Rd

Rotates general register contents.

1-bit or 2-bit rotation is possible.

Shift operations

ROTXL

ROTXR B/W/L Rd (rotate) → Rd

Rotates general register contents through the carry bit.

1-bit or 2-bit rotation is possible.

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Type Instruction Size*1Function

BSET B 1 → (<bit-No.> of <EAd>)

Sets a specified bit in a general register or memory

operand to 1. The bit number is specified by 3-bit

immediate data or the lower three bits of a general

BCLR B 0 → (<bit-No.> of <EAd>)

Clears a specified bit in a general register or memory

operand to 0. The bit number is specified by 3-bit

immediate data or the lower three bits of a general

BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)

Inverts a specified bit in a general register or memory

operand. The bit number is specified by 3-bit

immediate data or the lower three bits of a general

BTST B ¬ (<bit-No.> of <EAd>) → Z

Tests a specified bit in a general register or memory

operand and sets or clears the Z flag accordingly. The

bit number is specified by 3-bit immediate data or the

lower three bits of a general register.

BAND B C ∧ (<bit-No.> of <EAd>) → C

ANDs the carry flag with a specified bit in a general

carry flag.

BIAND B C ∧ ¬ (<bit-No.> of <EAd>) → C

ANDs the carry flag with the inverse of a specified bit in

a general register or memory operand and stores the

result in the carry flag.

The bit number is specified by 3-bit immediate data.

BOR B C ∨ (<bit-No.> of <EAd>) → C

ORs the carry flag with a specified bit in a general

carry flag.

Bit-manipulation

instructions

BIOR B C ∨ ¬ (<bit-No.> of <EAd>) → C

ORs the carry flag with the inverse of a specified bit in

a general register or memory operand and stores the

result in the carry flag.

The bit number is specified by 3-bit immediate data.

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Type Instruction Size*1Function

BXOR B C ⊕ (<bit-No.> of <EAd>) → C

Exclusive-O Rs the carry flag with a specif ied bit in a

general register or memory operand and stores the

result in the carry flag.

BIXOR B C ⊕ ¬ (<bit-No.> of <EAd>) → C

Exclusive-ORs the carry flag with the inverse of a

specified bit in a general register or memory operand

and stores the result in the carry flag.

The bit number is specified by 3-bit immediate data.

BLD B (<bit-No.> of <EAd>) → C

Transfers a specified bit in a general register or

memory operand to the carry flag.

BILD B ¬ (<bit-No.> of <EAd>) → C

Transfers the inverse of a specified bit in a general

The bit number is specified by 3-bit immediate data.

BST B C → (<bit-No.> of <EAd>)

Transfers the carry flag value to a specified bit in a

general register or memory operand.

Bit-manipulation

instructions

BIST B ¬ C → (<bit-No.> of <EAd>)

Transfers the inverse of the carry flag value to a

specified bit in a general register or memory operand.

The bit number is specified by 3-bit immediate data.

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Type Instruction Size*1Function

Branches to a specified address if a specified condition

is true. The branching conditions are listed below.

Mnemonic Description Condition

BRA(BT) Always (true) Always

BRN(BF) Never (false) Never

BHI High C ∨ Z = 0

BLS Low or same C ∨ Z = 1

BCC(BHS) Carry clear

(high or same) C = 0

BCS(BLO) Carry set (low) C = 1

BNE Not equal Z = 0

BEQ Equal Z = 1

BVC Overflow clear V = 0

BVS Overflow set V = 1

BPL Plus N = 0

BMI Minus N = 1

BGE Greater or equal N ⊕ V = 0

BLT Less than N ⊕ V = 1

BGT Greater than Z ∨ (N ⊕ V) = 0

BLE Less or equal Z ∨ (N ⊕ V) = 1

Bcc —

JMP —Branches unconditionally to a specified address.

BSR —Branches to a subroutine at a specified address.

JSR —Branches to a subroutine at a specified address.

Branch

instructions

RTS —Returns from a subroutine

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Type Instruction Size*1Function

TRAPA —Starts trap-instruction exception handling.

RTE —Returns from an exception-handling routine.

SLEEP —Causes a transition to a power-down state.

LDC B/W (EAs) → CCR, (EAs) → EXR

Moves the sour ce opera nd cont ents or immediate data

to CCR or EXR. Although CCR and EXR are 8-bit

registers, word-size transfers are performed between

them and memory. The upper 8 bits are valid.

STC B/W CCR → (EAd), EXR → (EAd)

Transfers CCR or EXR contents to a general regis ter or

memory. Although CCR and EXR are 8-bit registers,

word-size transfers are performed between them and

memory. The upper 8 bits are valid.

ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR

Logically ANDs the CCR or EXR contents with

immediate data.

ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR

Logically ORs the CCR or EXR contents with

immediate data.

XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR

Logically exclusive-ORs the CCR or EXR contents with

immediate data.

System control

instructions

NOP —PC + 2 → PC

Only increments the program counter.

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Type Instruction Size*1Function

EEPMOV.B —if R4L ≠ 0 then

Repeat @ER5+ → @ER6+

R4L – 1 → R4 L

Until R4L = 0

else next;

EEPMOV.W —if R4 ≠ 0 then

Repeat @ER5+ → @ER6+

R4 – 1 → R4

Until R4 = 0

else next;

Block data

transfer

instruction

Transfers a data block according to parameters set in

general registers R4L or R4, ER5, and ER6.

R4L or R4: size of block (bytes)

ER5: starting source address

ER6: starting destination address

Execution of the next instruction begins as soon as the

transfer is completed.

Notes: 1. Size refers to the operand size.

B: Byte

W: Word

L: Longword

2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

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1.6.4 Basic Instruction Formats

The H8S/2600 or H8S/2000 instructions consist of 2-byte (1-word) units. An instruction consists

of an operation field (op field), a register field (r field), an effective address extension (EA field),

and a condition field (cc).

Operation Field: Indicates the function of the instruction, the addressing mode, and the operation

to be carried out on the operand. The operation field always includes the first four bits of the

instruction. Some instructions have two operation fields.

by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field.

Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute

address, or a displacement.

Condition Field: Specifies the branch ing condition of Bcc instructions.

Figure 1.12 shows examples of instruction formats.

op rn rm

NOP, RTS, etc.

ADD.B Rn, Rm, etc.

MOV.B @(d:16, Rn), Rm, etc.

(1) Operation field only

(2) Operation field and register fields

(3) Operation field, register fields, and effective address extension

rn rm

EA (disp)

(4) Operation field, effective address extension, and condition field

op cc EA (disp) BRA d:8, etc

Figure 1.12 Instruction Formats

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1.7 Addressing Modes and Effective Address Calculation

(1) Addressing Modes

The CPUs support the eight addressing modes listed in table 1.4. Each instruction uses a subset of

these addressing modes. Arithmetic and logic instructions can use the register direct and

immediate modes. Data transfer instructions can use all addressing modes except program-coun ter

relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or

absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and

BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.

Table 1.4 Addressing Mo des

No. Addressing Mode Symbol

1 Register direct Rn

2 Register indirect @ERn

3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn)

5 Absol ute addr es s @aa:8/@aa:16/@aa:24/@aa:32

6 Immediate #xx:8/#xx:16/#xx:32

7 Program-counter relative @(d:8,PC)/@(d:16,PC)

8 Memory indirect @@aa:8

1. Register Direct—Rn: The register field of the instruction specifies an 8-, 16-, or 32-bit general

R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit

registers.

2. Register Indirect—@ERn: The register field of the instruction code specifies an address

instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00).

3. Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn): A 16-bit or 32-bit

displacement contained in the instruction is added to an address register (ERn) specified by the

displacement is sign-extended when added.

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4. Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn:

• Register indirect with post-increment—@ERn+

The register field of the instruction code specifies an address register (ERn) which contains the

address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address

access, 2 for word access, or 4 for longword access. For word or longword access, the register

value should be even.

• Register indirect with pre-decrem ent—@–ERn

The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field

in the instru ction code, and the result becomes the address of a memory operand. The result is

also stored in the address register. The value subtracted is 1 for byte access, 2 for word access,

or 4 for longword access. For word or longword access, the register value should be even.

5. Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32: The instruction code contains the

absolute address of a memory operand. The ab solute address may be 8 bits long (@aa:8), 16 bits

long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32).

To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits

(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1

(H'FFFFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute

address can access the entire addr ess space.

A 24-bit absolute address (@aa:24) indicates the address of a prog ram instruction. The upper 8

bits are all assumed to be 0 (H'00).

Table 1.5 indicates the accessible absolute address ranges.

Table 1.5 Absolute Address Access Ranges

Absolute Address Normal Mode Advanced Mode

8 bits (@aa:8) H'FF00 to H'FFFF H'FFFFFF00 to H'FFFFFFFF

16 bits (@aa:16) H'00000000 to H'00007FFF,

H'FFFF8000 to H'FFFFFFFF

Data address

32 bits (@aa:32) H'00000000 to H'FFFFFFFF

Program instruction

address 24 bits (@aa:24)

H'0000 to H'FFFF

H'00000000 to H'00FFFFFF

For further details on the accessible range, refer to the relevant micr ocontroller hardware manual.

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6. Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16),

or 32-bit (#xx:32) immediate data as an operand.

The ADDS, SUBS, INC, and DEC instructions con tain immediate data implicitly. Some bit

manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit

number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a

vector address.

7. Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and

BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and

added to the 24-bit PC contents to generate a b ranch address. Only the lower 24 bits of this branch

address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the

displacement is added is the address of the first byte of the next instruction, so the possible

branching range is –126 to +128 bytes (–63 to +64 wor ds) or –32766 to +32768 bytes (–16383 to

+16384 words) from the branch instruction. The resulting value should be an even number.

8. Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The

second byte of the instruction specifies a memory operand by an 8-bit absolute address. This

memory operand contains a branch address. The upper bits of the ab solute address are all assumed

to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'00000000 to

H'000000FF in advanced mode). In normal mode the memory operand is a word operand and the

branch address is 16 bits long. In advanced mode the memory operand is a longword operand, the

first byte of which is assumed to be all 0 (H'00).

Note that the first part of the address range is also the exception vector area. For further details

refer to th e releva nt microcontroller hardware m anu al.

(a) Normal Mode (b) Advanced Mode

Branch address

Specified

by @aa:8 Specified

by @aa:8 Reserved

Branch address

Figure 1.13 Branch Address Specification in Memory Indirect Mode

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If an odd address is specified in word or longword memory access, or as a branch address, the

least significant bit is regarded as 0, causing data to be accessed or an instruction code to be

fetched at the address preceding the specified address. (For further information, see section 1.5.2,

Memory Data Formats.)

(2) Effective Address Calculation

Table 1.6 indicates how effective addresses are calculated in each addressing mode. In normal

mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.

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Table 1.6 Effective Address Calculation

pre-decrement

• Register indirect with post-increment @ERn+

No. Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)

1 Register direct (Rn)

op rm rn Operand is general register contents.

@(d:16, ERn) or @(d:32, ERn)

• Register indirect with pre-decrement @–ERn

General register contents

Sign extension disp

General register contents

1, 2, or 4

General register contents

1, 2, or 4

Byte

Word

Longword

Operand Size Value added

31 0

31 0 31 0

31 0

op r

rop

disp

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@aa:8

Absolute address

@aa:16

@aa:32

6Immediate #xx:8/#xx:16/#xx:32

31 08 7

Operand is immediate data.

No. Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)

@aa:24

31 0

16 15

31 0

24 23

31 0

op abs

abs

op IMM

H'FFFFFF

Sign extension

H'00

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7Program-counter relative

@(d:8, PC)/@(d:16, PC)

8Memory indirect @@aa:8

• Normal mode

• Advanced mode

No. Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)

31 8 7

disp

H'000000

abs

H'000000

31 0

24 23

31 0

16 15

31 0

24 23

op disp

op abs

Sign

extension

PC contents

abs

Memory contents

Reserved H'00

H'0000

H'00

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Section 2 Instruction Descriptions

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Section 2 Instruction Descriptions

2.1 Tables and Symbols

This section explains how to read the tables in section 2.2, describing each instruction. Note that

the descriptions of some instructions extend over more than one page.

[1] Mnemonic (Full Name) [2] Type

[3] Operati on

[4] Assembly-Language Format

[5] Operand Size

[6] Condition Code

[7] Descripti on

[8] Availab le Registers

[9] Operand Format an d Number of Stat es Required for Execution

[10] Notes

[1] Mnemonic (Full Name): Gives the full and mnemonic names of the instruction.

[2] Type: Indicates the type of instruction.

[3] Operation: Describes the instruction in symbolic notation. (See section 2.1.2, Operation.)

[4] Assembly-Language Format: Indicates the assembly-language format of the instruction.

(See section 2.1.1, Assembler Format.)

[5] Operand Size: Indicates the available operand sizes.

[6] Condition Code: Indicates the effect of instruction execution on the flag bits in the CCR.

(See section 2.1.3, Condition Code.)

[7] Description: Describes the operation of the instruction in detail.

[8] Available Registers: Indicates which registers can be specified in the register field of the

instruction.

[9] Operand Format and Number of States Required for Execution: Shows the addressing

modes and instruction format together with the number of states required for execution.

[10] Notes: Gives notes concerni ng exe cut ion of the instru cti on.

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2.1.1 Assembly-Language Format

Example: ADD. B <EAs>, Rd

Destination operand

Source operand

Size

Mnemonic

The operand size is byte (B), word (W), or longword (L). Some instructions are restricted to a

limited set of operand sizes.

The symbol <EA> indicates that two or more addressing modes can be used. The H8S/2600 CPU

supports the eight addressing modes listed next. Effective address calculation is described in

section 1.7, Addressing Modes and Effective Address Calculation.

Symbol Addressing Mode

Rn Register direct

@ERn Register indirect

@(d:16, ERn)/@(d:32, ERn) Register indirect with displacement (16-bit or 32-bit)

@ERn+/@–ERn Register indirect wi th post-increment or pre-decrement

@aa:8/@aa:16/@aa:24/@aa:32 Absolute address (8-bit, 16-bit, 24-bit, or 32-bit)

#xx:8/#xx:16/#xx:32 Immediate (8-bit, 16-bit, or 32-bit)

@(d:8, PC)/@(d:16, PC) Program-counter relative (8-bit or 16-bi t)

@@aa:8 Memory indirect

The suffixes :8, :16, :24, and :32 may be omitted. In particular, if the :8, :16, :24, or :32

designatio n is omitted in an abso lute address or disp lacement, the assembler will optimize the

length according to the valu e range. For details, refer to the H8S, H8/300 Series cross assembler

user’s manual.

Note: “:2” and “:3” in “#xx (:2)” and “#xx (:3)” indicate the specifiable bit length. Do not

include (:2) or (:3) in the assembler notation.

Example: TRAPA #3

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2.1.2 Operation

The symbols used in the operation descriptions are defined as follows.

Rd General register (destination)*

Rs General register (source)*

Rn General register*

ERn General register (32-bit register)

MAC Multiply-accumulate register (32-bit register)

(EAd) Destination operand

(EAs) Source operand

EXR Extended control register

CCR Condition-code register

N N (negative) flag in CCR

Z Z (zero) flag in CCR

V V (overflow) flag in CCR

C C (carry) flag in CCR

PC Program counter

SP Stack pointer

#IMM Immediate data

disp Displacement

+Add

– Subtract

×Multiply

÷Divide

∧Logical AND

∨Logical OR

⊕Logical exclusive OR

→Transfer from the operand on the left to the operand on the right, or transition from

the state on the left to the state on the right

¬Logical NOT (logical complement)

( ) < > Contents of effective address of the operand

:8/:16/

:24/:32 8-, 16-, 24-, or 32-bit length

Note: *General registers include 8-bit registers (R0H to R7H and R0L to R7L), 16-bit registers

(R0 to R7 and E0 to E7), and 32-bit registers (ER0 to ER7).

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2.1.3 Condition Code

The symbols used in the condition-code description are defined as follows.

Symbol Meaning

↔

Changes according to the result of instruction execution

*Undetermined (no guaranteed value)

0 Always cleared to 0

1 Always set to 1

— Not affected by execution of the instruction

∆Varies depending on conditions; see the notes

For details on changes of the condition code, see section 2.8, Condition Code Modification.

2.1.4 Instruction Format

The symbols used in the instruction format descriptions are listed below.

Symbol Meaning

IMM Immediate data (2, 3, 8, 16, or 32 bi ts)

abs Absolute address (8, 16, 24, or 32 bits)

disp Displacement (8, 16, or 32 bits)

rs, rd, rn Register field (4 bits). The symbols rs, rd, and rn correspond to operand symbols

Rs, Rd, and Rn.

ers, erd, ern Register field (3 bits). The symbols ers, erd, and ern correspond to operand

symbols ERs, ERd, and ERn.

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2.1.5 Register Specification

Address Register Specification: When a general register is used as an address register [@ERn,

@(d:16, ERn), @(d:32, ERn), @ERn+, or @–ERn], the register is specified by a 3-bit register

field (ers or er d).

Data Register Specification: A general register can be used as a 32-bit, 16-bit, or 8-bit data

When used as a 32-bit register, it is specified by a 3-bit register field (ers, erd, or ern).

When used as a 16-bit register, it is specified by a 4-bit register field (rs, rd, or rn). The lower 3

bits specify the register number. The upper bit is set to 1 to specify an extended register (En) or

cleared to 0 to specify a general register (Rn).

When used as an 8-bit register, it is specified by a 4-bit register field (rs, rd, or rn). The lower 3

bits specify the register number. The upper bit is set to 1 to specify a low register (RnL) or cleared

to 0 to specify a high register (RnH). This is shown next.

Address Register

32-Bit Register 16-Bit Register 8-Bit Register

Field General

000

001

111

ER0

ER1

ER7

0000

0001

0111

1000

1001

1111

0000

0001

0111

1000

1001

1111

R0H

R1H

R7H

R0L

R1L

R7L

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2.1.6 Bit Data Access in Bit Manipulation Instructions

Bit data is accessed as the n-th bit (n = 0, 1, 2, 3, …, 7) of a byte operand in a general register or

memory. The bit number is given by 3-bit immediate data, or by the lower 3 bits of a general

Example 1: To set bit 3 in R2H to 1

BSET R1L, R2H

R1L 011

Don’t care

001

R2H 10110

Bit number

Set to 1

Example 2: To load bit 5 at addr ess H'FFFF02 into the bit accumulator

BLD #5, @H'FFFF02

H'FFFF02 110

00101

Load

The operand size and addressing mode are as indicated fo r register or memory operand data.

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2.2 Instruction Descriptions

The instructions are described starting in section 2.2.1.

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2.2.1 (1) ADD (B)

ADD (ADD Binary) Add Binary

Operation

Rd + (EAs) → Rd

Assembly-Language Format

ADD.B <EAs>, Rd

Operand Size

Byte

Condition Code

↔

———

UIHUNZVC

H: Set to 1 if th er e is a carry at bit 3;

otherwise cleared to 0.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a carry at bit 7;

otherwise cleared to 0.

Description

This instructio n adds the source operand to the contents of an 8-bit reg ister Rd (destination

operand) and stores the re sult in the 8-bit register Rd.

Available Registers

Rd: R0L to R7L, R0H to R7H

Rs: R0L to R7L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Immedi ate ADD.B #xx: 8 , Rd 8 rd IMM 1

Notes

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2.2.1 (2) ADD (W)

ADD (ADD Binary) Add Binary

Operation

Rd + (EAs) → Rd

Assembly-Language Format

ADD.W <EAs>, Rd

Operand Size

Word

Condition Code

↔

———

UIHUNZVC

H: Set to 1 if th er e is a carry at bit 11;

otherwise cleared to 0.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a carry at bit 15;

otherwise cleared to 0.

Description

This instructio n adds the source operand to the contents of a 16-bit reg ister Rd (destination

operand) and stores the re sult in the 16-bit register Rd.

Available Registers

Rd: R0 to R7, E0 to E7

Rs: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Immedi ate ADD.W #xx: 16, Rd 7 9 1 rd IMM 2

Notes

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2.2.1 (3) ADD (L)

ADD (ADD Binary) Add Binary

Operation

ERd + (EAs) → ERd

Assembly-Language Format

ADD.L <EAs>, ERd

Operand Size

Longword

Condition Code

↔

———

UIHUNZVC

H: Set to 1 if th er e is a carry at bit 27;

otherwise cleared to 0.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a carry at bit 31;

otherwise cleared to 0.

Description

This instructio n adds the source operand to the contents of a 32-bit register ERd (destination

operand) and stores the result in the 32-bit register ERd.

Available Registers

ERd: ER0 to ER7

ERs: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte

No. of

States

Immediate ADD.L #xx:32, ERd 7 A 1 0 erd IMM 3

Notes

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2.2.2 ADDS

ADDS (ADD with Sign extension) Add Binary Address Data

Operation

Rd + 1 → ERd

Rd + 2 → ERd

Rd + 4 → ERd

Assembly-Language Format

ADDS #1, ERd

ADDS #2, ERd

ADDS #4, ERd

Operand Size

Longword

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction adds the immediate value 1, 2, or 4 to the contents of a 32-bit register ERd

(destination o perand). Unlike the ADD instruction, it d o e s not affect th e condition code flags.

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Notes

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2.2.3 ADDX

ADDX (ADD with eXtend carry) Add with Carry

Operation

Rd + (EAs) + C → Rd

Assembly-Language Format

ADDX <EAs>, Rd

Operand Size

Byte

Condition Code

↔

———

UIHUNZVC

H: Set to 1 if th er e is a carry at bit 3;

otherwise cleared to 0.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a carry at bit 7;

otherwise cleared to 0.

Description

This instruction adds the source operand and carry flag to th e contents of an 8-bit register Rd

(destination operand) and stores the result in the 8-bit reg ister Rd.

Available Registers

Rd: R0L to R7 L, R0H to R7H

Rs: R0L to R7L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Immedi ate ADDX #xx:8, Rd 9 rd IMM 1

Notes

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2.2.4 (1) AND (B)

AND (AND logical) Logical AND

Operation

Rd ∧ (EAs) → Rd

Assembly-Language Format

AND.B <EAs>, Rd

Operand Size

Byte

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction ANDs the source operand with the contents o f an 8- bit register Rd (destination

operand) and stores the re sult in the 8-bit register Rd.

Available Registers

Rd: R0L to R7 L, R0H to R7H

Rs: R0L to R7L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Immedi ate AND.B #xx: 8 , Rd E rd I M M 1

Notes

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2.2.4 (2) AND (W)

AND (AND logical) Logical AND

Operation

Rd ∧ (EAs) → Rd

Assembly-Language Format

AND.W <EAs>, Rd

Operand Size

Word

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction ANDs the source operand with the contents of a 16-bit register Rd (destination

operand) and stores the re sult in the 16-bit register Rd.

Available Registers

Rd: R0 to R7, E0 to E7

Rs: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Immedi ate AND.W #xx: 16, Rd 7 9 6 rd IMM 2

Notes

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2.2.4 (3) AND (L)

AND (AND logical) Logical AND

Operation

ERd ∧ (EAs) → ERd

Assembly-Language Format

AND.L <EAs>, ERd

Operand Size

Longword

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction ANDs the source operand with the contents o f a 32- bit register ERd (destination

operand) and stores the result in the 32-bit register ERd.

Available Registers

ERd: ER0 to ER7

ERs: ER0 to ER7

Operand Format and Number of States Required for Execution

Inst ruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte

No. of

States

Immediate AND.L #xx:32, ERd 7 A 6 0 erd IMM 3

Notes

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2.2.5 (1) ANDC

ANDC (AND Control register) Logical AND with CCR

Operation

CCR ∧ #IMM → CCR

Assembly-Language Format

ANDC #xx:8, CCR

Operand Size

Byte

Condition Code

↔

UIHUNZVC

I: Stores the corresponding bit of the result.

UI: Stores the corresponding bit of the result.

H: Stores the corresponding bit of the result.

U: Stores the corresponding bit of the result.

N: Stores the corresponding bit of the result.

Z: Stores the corresponding bit of the result.

V: Stores the corresponding bit of the result.

C: Stores the corresponding bit of the result.

Description

This instru ction ANDs the contents of the condition-code register (CCR) with imme diate data and

stores the result in the condition-code register. No interrupt requests, including NMI, are accepted

immediately af ter execution of this instru ction.

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Immedi ate ANDC #xx:8, CCR 0 6 IMM 1

Notes

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2.2.5 (2) ANDC

ANDC (AND Control register) Logical AND with EXR

Operation

EXR ∧ #IMM → EXR

Assembly-Language Format

ANDC #xx:8, EXR

Operand Size

Byte

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction ANDs the contents of the extended control register (EXR) with immediate data

and stores th e result in the extend ed contro l r e gister. No interrupt requests, inclu ding NMI, are

accepted for three states after execution of this instruction.

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

Immediate ANDC#xx:8, EXR014106 IMM 2

Notes

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2.2.6 BAND

BAND (Bit AND) Bit Logical AND

Operation

C ∧ (<bit No.> of <EAd>) → C

Assembly-Language Format

BAND #xx:3, <EAd>

Operand Size

Byte

Condition Code

↔

———————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Stores the re sult of the oper a tion.

Description

This instruction ANDs a specified bit in the d e stin ation operand with the carry flag and stores the

result in the car r y flag . The bit number is specified by 3-b it immediate data. The destination

operand contents remain unchanged.

∧

Specified by #xx:3

Bit No.

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7 H

ERd: ER0 to ER7

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BAND (Bit AND) Bit Logical AND

Operand Format and Number of States Required for Execution

Note: *The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8/@aa:16 access ran

e, refer to the relevant microcontroller hardware manual.

Addressing Mnemonic Operands Instruction Format No. of

Mode*1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte States

IMM

rd 1

direct

IMM

indirect

Absolute BAND #xx:3, @aa:8 7 E abs 7 6 0

IMM

address

Absolute BAND #xx:3, @aa:16 6 A 1 0 abs 7 6 0

IMM

address

Absolute BAND #xx:3, @aa:32 6 A 3 0 abs 7 6 0

IMM

address

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2.2.7 Bcc

Bcc (Branch conditiona lly) Conditional Bra nch

Operation

If condition is tr ue, then

PC + disp → PC

else next;

Assembly-Language Format

Bcc disp

Condition field

Operand Size

—

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

If the condition specified in th e cond ition field (cc) is true, a displacement is added to the program

counter (PC) and execution br anches to the resulting address. If the condition is false, the next

instruction is executed. The PC value used in the address calculation is the starting address of the

instruction immediately following the Bcc instruction. The displacement is a signed 8-bit or 16-bit

value. The branch destination address can be located in the range from −126 to +128 bytes or

−32766 to +32768 bytes from the Bcc instruction.

Mnemonic Meaning cc Condition Signed/Unsigned*

BRA (BT) Always (true) 0000 True

BRN (BF) Never (f als e) 0001 Fals e

BHI HIgh 0010 C∨Z = 0 X > Y (unsigned)

BLS Low or Same 0011 C∨Z = 1 X ≤ Y (unsi gned)

BCC (BHS) Carry Clear (High or Same) 0100 C = 0 X ≥ Y (unsigned)

BCS (BLO) Carry Set (LOw) 0101 C = 1 X < Y (unsigned)

BNE Not Equal 0110 Z = 0 X ≠ Y (unsigned or signed)

BEQ EQual 0111 Z = 1 X = Y (unsigned or signed)

BVC oVerflow Cl ear 1000 V = 0

BVS oVerflow Set 1001 V = 1

BPL PLus 1010 N = 0

BMI MInus 1011 N = 1

BGE Greater or Equal 1100 N⊕V = 0 X ≥ Y (signed)

BLT Less Than 1101 N⊕V = 1 X < Y (signed)

BGT Greater Than 1110 Z∨(N⊕V) = 0 X > Y (signed)

BLE Less or Equal 1111 Z∨(N⊕V) = 1 X ≤ Y (signed)

Note: *If the immediately preceding instruction is a CMP instruction, X is the general regist er cont ents

(destination operand) and Y is the source operand.

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Bcc (Branch conditiona lly) Conditional Bra nch

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. of

States

d:8 4 0 disp 2

Program-counter

relative BRA (BT) d:16 5800 disp 3

d:8 4 1 disp 2

Program-counter

relative BRN (BF) d:16 5810 disp 3

d:8 4 2 disp 2

Program-counter

relative BHI d:16 5820 disp 3

d:8 4 3 disp 2

Program-counter

relative BLS d:16 5830 disp 3

d:8 4 4 disp 2

Program-counter

relative Bcc (BHS) d:16 5840 disp 3

d:8 4 5 disp 2

Program-counter

relative BCS (BLO) d:16 5850 disp 3

d:8 4 6 disp 2

Program-counter

relative BNE d:16 5860 disp 3

d:8 4 7 disp 2

Program-counter

relative BEQ d:16 5870 disp 3

d:8 4 8 disp 2

Program-counter

relative BVC d:16 5880 disp 3

d:8 4 9 disp 2

Program-counter

relative BVS d:16 5890 disp 3

d:8 4 A disp 2

Program-counter

relative BPL d:16 5 8 A 0 disp 3

d:8 4 B disp 2

Program-counter

relative BMI d:16 5 8 B 0 disp 3

d:8 4 C disp 2

Program-counter

relative BGE d:16 5 8 C 0 disp 3

d:8 4 D disp 2

Program-counter

relative BLT d:16 5 8 D 0 disp 3

d:8 4 E disp 2

Program-counter

relative BGT d:16 5 8 E 0 disp 3

d:8 4 F disp 2

Program-counter

relative BLE d:16 5 8 F 0 disp 3

Notes

1. The branch destination address must be even.

2. In machine language BRA, BRN, BCC, and BCS are identical to BT, BF, BHS, and BLO,

respectively.

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2.2.8 BCLR

BCLR (Bit CLeaR) Bit Clear

Operation

0 → (<bit No.> of <EAd>)

Assembly-Language Format

BCLR #xx:3, <EAd>

BCLR Rn, <EAd>

Operand Size

Byte

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction clears a specified bit in the destination operand to 0. The bit number can be

specified by 3-bit immediate data, or by the lower three bits of an 8-bit register Rn. The specified

bit is not tested. The condition-code flags are not altered.

Specified by #xx:3 or Rn

Bit No.

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7 H

ERd: ER0 to ER7

Rn: R0L to R7L, R0H to R7 H

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BCLR (Bit CLeaR) Bit Clear

Operand Format and Number of States Required for Execution

Note: *The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual.

Addressing Mnemonic Operands Instruction Format No. of

Mode*1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte States

IMM

rd 1

direct

IMM

indirect

Absolute BCLR #xx:3, @aa:8 7 F abs 7 2 0

IMM

address

Absolute BCLR #xx:3, @aa:16 6 A 1 8 abs 7 2 0

IMM

address

Absolute BCLR #xx:3, @aa:32 6 A 3 8 abs 7 2 0

IMM

address

direct

indirect

Absolute BCLR Rn, @aa:8 7 F abs 6 2 rn 0 4

address

Absolute BCLR Rn, @aa:16 6 A 1 8 abs 6 2 rn 0 5

address

Absolute BCLR Rn, @aa:32 6 A 3 8 abs 6 2 rn 0 6

address

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2.2.9 BIAND

BIAND (Bit Invert AND) Bit Logical AND

Operation

C ∧ [¬ (<bit No.> of <EAd>)] → C

Assembly-Language Format

BIAND #xx:3, <EAd>

Operand Size

Byte

Condition Code

↔

———————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Stores the re sult of the oper a tion.

Description

This instruction ANDs the inverse of a specified b it in the destin ation operand with the carry flag

and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. The

destination operand contents remain unchanged.

∧

Specified by #xx:3

Bit No.

Invert

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7 H

ERd: ER0 to ER7

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BIAND (Bit Invert AND) Bit Logical AND

Operand Format and Number of States Required for Execution

Note: *The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8/@aa:16 access ran

e, refer to the relevant microcontroller hardware manual.

Addressing Mnemonic Operands Instruction Format No. of

Mode*1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte States

IMM

rd 1

direct

IMM

indirect

Absolute BIAND #xx:3, @aa:8 7 E abs 7 6 1

IMM

address

Absolute BIAND #xx:3, @aa:16 6 A 1 0 abs 7 6 1

IMM

address

Absolute BIAND #xx:3, @aa:32 6 A 3 0 abs 7 6 1

IMM

address

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2.2.10 BILD

BILD (Bit Invert LoaD) Bit Load

Operation

¬ (<bit No.> of <EAd>) → C

Assembly-Language Format

BILD #xx:3, <EAd>

Operand Size

Byte

Condition Code

↔

———————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Loaded with the inverse of the specified

bit.

Description

This instructio n loads the inverse o f a specified bit from the destin ation operand into th e carry

flag. The bit number is specified by 3-bit immediate data. The destination operand contents

remain unchanged.

Specified by #xx:3

Bit No.

Invert

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7 H

ERd: ER0 to ER7

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BILD (Bit Invert LoaD) Bit Load

Operand Format and Number of States Required for Execution

Note: *The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8/@aa:16 access ran

e, refer to the relevant microcontroller hardware manual.

Addressing Mnemonic Operands Instruction Format No. of

Mode*1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte States

IMM

rd 1

direct

IMM

indirect

Absolute BILD #xx:3, @aa:8 7 E abs 7 7 1

IMM

address

Absolute BILD #xx:3, @aa:16 6 A 1 0 abs 7 7 1

IMM

address

Absolute BILD #xx:3, @aa:32 6 A 3 0 abs 7 7 1

IMM

address

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2.2.11 BIOR

BIOR (Bit Invert inclusive OR) Bit Logical OR

Operation

C ∨ [¬ (<bit No.> of <EAd>)] → C

Assembly-Language Format

BIOR #xx:3, <EAd>

Operand Size

Byte

Condition Code

↔

———————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Stores the re sult of the oper a tion.

Description

This instructio n ORs the inverse of a specified bit in the destinatio n operand with the carry flag

and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. The

destination operand contents remain unchanged.

C∨C

Specified by #xx:3

Bit No.

Invert

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7 H

ERd: ER0 to ER7

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BIOR (Bit Invert inclusive OR) Bit Logical OR

Operand Format and Number of States Required for Execution

Note: *The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual.

Addressing Mnemonic Operands Instruction Format No. of

Mode*1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte States

IMM

rd 1

direct

IMM

indirect

Absolute BIOR #xx:3, @aa:8 7 E abs 7 4 1

IMM

address

Absolute BIOR #xx:3, @aa:16 6 A 1 0 abs 7 4 1

IMM

address

Absolute BIOR #xx:3, @aa:32 6 A 3 0 abs 7 4 1

IMM

address

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2.2.12 BIST

BIST (Bit Invert STore) Bit Store

Operation

¬ C → (<bit No.> of <EAd>)

Assembly-Language Format

BIST #xx:3, <EAd>

Operand Size

Byte

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instructio n stores the inv e r se of the carry f lag in a specified bit location in the de stination

erand. The bit number is s

ecified b

3-bit immediate d ata. Other bits in the destination o

erand

remain unchanged.

Specified by #xx:3

Bit No.

Invert

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7 H

ERd: ER0 to ER7

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BIST (Bit Invert STore) Bit Store

Operand Format and Number of States Required for Execution

Note: *The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8/@aa:16 access ran

e, refer to the relevant microcontroller hardware manual.

Addressing Mnemonic Operands Instruction Format No. of

Mode*1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte States

IMM

rd 1

direct

IMM

indirect

Absolute BIST #xx:3, @aa:8 7 F abs 6 7 1

IMM

address

Absolute BIST #xx:3, @aa:16 6 A 1 8 abs 6 7 1

IMM

address

Absolute BIST #xx:3, @aa:32 6 A 3 8 abs 6 7 1

IMM

address

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2.2.13 BIXOR

BIXOR (Bit Invert eXclusive OR) Bit Exclusive Logical OR

Operation

C ⊕ [¬ (<bit No.> of <EAd>)] → C

Assembly-Language Format

BIXOR #xx:3, <EAd>

Operand Size

Byte

Condition Code

↔

———————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Stores the re sult of the oper a tion.

Description

This instruction exclusively ORs the inverse of a specified bit in the destinatio n operand with the

carry flag and stores the result in the carry flag. The bit number is specified by 3-bit immediate

data. The destination operand contents remain unchanged.

Specified by #xx:3

⊕

Invert C

Bit No.

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7 H

ERd: ER0 to ER7

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BIXOR (Bit Invert eXclusive OR) Bit Exclusive Logical OR

Operand Format and Number of States Required for Execution

Note: *The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8/@aa:16 access ran

e, refer to the relevant microcontroller hardware manual.

Addressing Mnemonic Operands Instruction Format No. of

Mode*1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte States

IMM

rd 1

direct

IMM

indirect

Absolute BIXOR #xx:3, @aa:8 7 E abs 7 5 1

IMM

address

Absolute BIXOR #xx:3, @aa:16 6 A 1 0 abs 7 5 1

IMM

address

Absolute BIXOR #xx:3, @aa:32 6 A 3 0 abs 7 5 1

IMM

address

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2.2.14 BLD

BLD (Bit LoaD) Bit Load

Operation

(<Bit No.> of <EAd>) → C

Assembly-Language Format

BLD #xx:3, <EAd>

Operand Size

Byte

Condition Code

↔

———————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Loaded from the specified bit.

Description

This instructio n loads a specified bit from the destination operand into the carry flag. The bit

number is specified by 3-bit immediate data. The destination operand contents remain unchanged.

Specified by #xx:3

07Bit No.

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7 H

ERd: ER0 to ER7

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BLD (Bit LoaD) Bit Load

Operand Format and Number of States Required for Execution

Note: *The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8/@aa:16 access ran

e, refer to the relevant microcontroller hardware manual.

Addressing Mnemonic Operands Instruction Format No. of

Mode*1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte States

IMM

rd 1

direct

IMM

indirect

Absolute BLD #xx:3, @aa:8 7 E abs 7 7 0

IMM

address

Absolute BLD #xx:3, @aa:16 6 A 1 0 abs 7 7 0

IMM

address

Absolute BLD #xx:3, @aa:32 6 A 3 0 abs 7 7 0

IMM

address

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2.2.15 BNOT

BNOT (Bit NOT) Bit NOT

Operation

¬ (<bit No.> of <EAd>) → (bit No. of

<EAd>)

Assembly-Language Format

BNOT #xx:3, <EAd>

BNOT Rn, <EAd>

Operand Size

Byte

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction inverts a specified bit in the destination operand. The bit number is specified by 3-

bit immediate data or by th e lower 3 bits of an 8-bit register Rn. The specified bit is not tested.

The condition code remains unchanged.

70Bit No. Specified by #xx:3 or Rn

Invert

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7 H

ERd: ER0 to ER7

Rn: R0L to R7L, R0H to R7 H

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BNOT (Bit NOT) Bit NOT

Operand Format and Number of States Required for Execution

Note: *The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual.

Addressing Mnemonic Operands Instruction Format No. of

Mode*1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte States

IMM

rd 1

direct

IMM

indirect

Absolute BNOT #xx:3, @aa:8 7 F abs 7 1 0

IMM

address

Absolute BNOT #xx:3, @aa:16 6 A 1 8 abs 7 1 0

IMM

address

Absolute BNOT #xx:3, @aa:32 6 A 3 8 abs 7 1 0

IMM

address

direct

indirect

Absolute BNOT Rn, @aa:8 7 F abs 6 1 rn 0 4

address

Absolute BNOT Rn, @aa:16 6 A 1 8 abs 6 1 rn 0 5

address

Absolute BNOT Rn, @aa:32 6 A 3 8 abs 6 1 rn 0 6

address

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2.2.16 BOR

BOR (Bit inclusive OR) Bit Logical OR

Operation

C ∨ (<bit No.> of <EAd>) → C

Assembly-Language Format

BOR #xx:3, <EAd>

Operand Size

Byte

Condition Code

↔

———————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Stores the re sult of the oper a tion.

Description

This instruction ORs a specified b it in the destinatio n operand with the carry flag and sto res the

result in the car r y flag . The bit number is specified by 3-b it immediate data. The destination

operand contents remain unchanged.

Specified by #xx:3

Bit No.

∨

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7 H

ERd: ER0 to ER7

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BOR (Bit inclusive OR) Bit Logical OR

Operand Format and Number of States Required for Execution

Note: *The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8/@aa:16 access ran

e, refer to the relevant microcontroller hardware manual.

Addressing Mnemonic Operands Instruction Format No. of

Mode*1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte States

IMM

rd 1

direct

IMM

indirect

Absolute BOR #xx:3, @aa:8 7 E abs 7 4 0

IMM

address

Absolute BOR #xx:3, @aa:16 6 A 1 0 abs 7 4 0

IMM

address

Absolute BOR #xx:3, @aa:32 6 A 3 0 abs 7 4 0

IMM

address

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2.2.17 BSET

BSET (Bit SET) Bit Set

Operation

1 → (<bit No.> of <EAd>)

Assembly-Language Format

BSET #xx:3, <EAd>

BSET Rn, <EAd>

Operand Size

Byte

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instructio n sets a specified bit in the destination operand to 1. The bit number can be

specified by 3-bit immediate data, or by the lower three bits of an 8-bit register Rn. The specified

bit is not tested. The condition code flags are not altered.

70Bit No.

Specified by #xx:3 or Rn

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7 H

ERd: ER0 to ER7

Rn: R0L to R7L, R0H to R7 H

Section 2 Instruction Descriptions

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BSET (Bit SET) Bit Set

Operand Format and Number of States Required for Execution

Note: *The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual.

Addressing Mnemonic Operands Instruction Format No. of

Mode*1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte States

IMM

rd 1

direct

IMM

indirect

Absolute BSET #xx:3, @aa:8 7 F abs 7 0 0

IMM

address

Absolute BSET #xx:3, @aa:16 6 A 1 8 abs 7 0 0

IMM

address

Absolute BSET #xx:3, @aa:32 6 A 3 8 abs 7 0 0

IMM

address

direct

indirect

Absolute BSET Rn, @aa:8 7 F abs 6 0 rn 0 4

address

Absolute BSET Rn, @aa:16 6 A 1 8 abs 6 0 rn 0 5

address

Absolute BSET Rn, @aa:32 6 A 3 8 abs 6 0 rn 0 6

address

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2.2.18 BSR

BSR (Branch t o SubRoutine) Branch to Subroutine

Operation

PC → @–SP

PC + disp → PC

Assembly-Language Format

BSR disp

Operand Size

—

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction branches to a subroutine at a specified address. It pushes the program counter

(PC) value onto the stack as a restart address, then adds a specified displacement to the PC value

and branches to the resulting address. The PC value pushed onto the stack is the address of the

instruction following the BSR instruction. The displacement is a signed 8-bit or 16-bit value, so

the possible branching range is –126 to +128 bytes or –32766 to +32768 bytes from the address of

the BSR instru ction.

Operand Format and Number of States Required for Execution

Instruction Format No. of States

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte Normal Advanced

d:8 5 5 disp 3 4

Program-counter

relative BSR d:16 5 C 0 0 disp 4 5

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BSR (Branch t o SubRoutine) Branch to Subroutine

Notes

The stack structure differs between normal mode and advanced mode. In normal mode only the

lower 16 bits of the program counter are pushed onto the stack.

Ensure that the branch destination address is even.

PC 23 16 15 8 7 0 Normal mode

PC 23 16 15 8 7 0 Advanced mode

Reserved

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2.2.19 BST

BST (Bit STore) Bit Stor e

Operation

C → (<bit No.> of <EAd>)

Assembly-Language Format

BST #xx:3, <EAd>

Operand Size

Byte

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instructio n stores the carry flag in a specif ied bit location in the destination operand. The bit

number is sp ecified by 3-bit immediate data.

Specified by #xx:3

Bit No.

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7 H

ERd: ER0 to ER7

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BST (Bit STore) Bit Stor e

Operand Format and Number of States Required for Execution

Note: *The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8/@aa:16 access ran

e, refer to the relevant microcontroller hardware manual.

Addressing Mnemonic Operands Instruction Format No. of

Mode*1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte States

IMM

rd 1

direct

IMM

indirect

Absolute BST #xx:3, @aa:8 7 F abs 6 7 0

IMM

address

Absolute BST #xx:3, @aa:16 6 A 1 8 abs 6 7 0

IMM

address

Absolute BST #xx:3, @aa:32 6 A 3 8 abs 6 7 0

IMM

address

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2.2.20 BTST

BTST (Bit TeST) Bit Test

Operation

¬ (<Bit No.> of <EAd>) → Z

Assembly-Language Format

BTST #xx:3, <EAd>

BTST Rn, <EAd>

Operand Size

Byte

Condition Code

↔

———————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Set to 1 if the specified bit is zero ;

otherwise cleared to 0.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction tests a specified bit in the destination operand and sets or clears the zero flag

according to the result. The bit number can be specified by 3-bit immediate data, or by the lower

three bits of an 8-bit register Rn. The destination operand contents remain unchanged.

70Bit No.

Test

Specified by #xx:3 or Rn

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7 H

ERd: ER0 to ER7

Rn: R0L to R7L, R0H to R7 H

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BTST (Bit TeST) Bit Test

Operand Format and Number of States Required for Execution

Note: *The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual.

Addressing Mnemonic Operands Instruction Format No. of

Mode*1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte States

IMM

rd 1

direct

IMM

indirect

Absolute BTST #xx:3, @aa:8 7 E abs 7 3 0

IMM

address

Absolute BTST #xx:3, @aa:16 6 A 1 0 abs 7 3 0

IMM

address

Absolute BTST #xx:3, @aa:32 6 A 3 0 abs 7 3 0

IMM

address

direct

indirect

Absolute BTST Rn, @aa:8 7 E abs 6 3 rn 0 3

address

Absolute BTST Rn, @aa:16 6 A 1 0 abs 6 3 rn 0 4

address

Absolute BTST Rn, @aa:32 6 A 3 0 abs 6 3 rn 0 5

address

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2.2.21 BXOR

BXOR (Bit eXclusive OR) Bit Exclusive Logical OR

Operation

C ⊕ (<bit No.> of <EAd>) → C

Assembly-Language Format

BXOR #xx:3, <EAd>

Operand Size

Byte

Condition Code

↔

———————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Stores the re sult of the oper a tion.

Description

This instruction exclusively ORs a specified bit in the destination operand with the carry flag an d

stores the result in the carry flag. The bit number is specified by 3-bit immediate data. The

destination operand contents remain unchanged.

Specified by #xx:3

Bit No.

⊕

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7 H

ERd: ER0 to ER7

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BXOR (Bit eXclusive OR) Bit Exclusive Logical OR

Operand Format and Number of States Required for Execution

Note: *The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8/@aa:16 access ran

e, refer to the relevant microcontroller hardware manual.

Addressing Mnemonic Operands Instruction Format No. of

Mode*1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte States

IMM

rd 1

direct

IMM

indirect

Absolute BXOR #xx:3, @aa:8 7 E abs 7 5 0

IMM

address

Absolute BXOR #xx:3, @aa:16 6 A 1 0 abs 7 5 0

IMM

address

Absolute BXOR #xx:3, @aa:32 6 A 3 0 abs 7 5 0

IMM

address

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2.2.22 CLRMAC

CLRMAC (CLeaR MAC register) Initialize Multiply- A ccumulate Regist er

Operation

0 → MACH, MACL

Assembly-Language Format

CLRMAC

Operand Size

—

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction simultaneously clears registers MACH and MACL.

It is supported only by the H8S/2600 CPU.

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

—CLRMAC—01A0 2*

Note: *A maximum of three additional states are required for executi on of this inst ruct i on withi n three st ates

after execution of a MAC instruct i on. For example, if there is a one-state i nst ruction (such as NOP)

between the MAC instruct i on and this i nst ruction, this instructi on will be two stat es longer.

The number of states may differ depending on the product. For details, refer to the relevant

microcontrol l er hardware manual of the product in question.

Notes

Execution of th is instruction also clears the overflow flag in the mu ltiplier to 0.

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2.2.23 (1) CMP (B)

CMP (CoMPare) Compare

Operation

Rd – (EAs), set/clear CCR

Assembly-Language Format

CMP.B <EAs>, Rd

Operand Size

Byte

Condition Code

↔

———

UIHUNZVC

H: Set to 1 if th er e is a bor row at b it 3;

otherwise cleared to 0.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a borrow at bit 7;

otherwise cleared to 0.

Description

This instruction subtracts the source operand from the contents of an 8-bit register Rd (destination

operand) and sets or clears the condition code bits according to the result. The contents of the 8-bit

Available Registers

Rd: R0L to R7 L, R0H to R7H

Rs: R0L to R7L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Immedi ate CMP.B #xx:8, Rd A rd IMM 1

Notes

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2.2.23 (2) CMP (W)

CMP (CoMPare) Compare

Operation

Rd – (EAs), set/clear CCR

Assembly-Language Format

CMP.W <EAs>, Rd

Operand Size

Word

Condition Code

↔

———

UIHUNZVC

H: Set to 1 if th er e is a bor row at b it 11;

otherwise cleared to 0.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a borrow at bit 15;

otherwise cleared to 0.

Description

This instruction subtracts the source operand from the contents of a 16-bit register Rd (destination

operand) and sets or clears the condition code bits according to the result. The contents of the 16-

bit register Rd remain unchanged.

Available Registers

Rd: R0 to R7, E0 to E7

Rs: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Immedi ate CMP.W #xx: 16, Rd 7 9 2 rd IMM 2

Notes

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2.2.23 (3) CMP (L)

CMP (CoMPare) Compare

Operation

ERd – (EAs), set/clear CCR

Assembly-Language Format

CMP.L <EAs>, ERd

Operand Size

Longword

Condition Code

↔

———

UIHUNZVC

H: Set to 1 if th er e is a bor row at b it 27;

otherwise cleared to 0.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a borrow at bit 31;

otherwise cleared to 0.

Description

This instruction subtracts the source operand from the contents of a 32 -bit register ERd

(destination o perand) and sets or clears the condition co de bits according to the result. The

contents of the 32-bit register ERd remain unchanged.

Available Registers

ERd: ER0 to ER7

ERs: ER0 to ER7

Operand Format and Number of States Required for Execution

Inst ruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte

No. of

States

Immediate CMP.L #xx:32, ERd 7 A 2 0 erd IMM 3

Notes

Section 2 Instruction Descriptions

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2.2.24 DAA

DAA (Decimal Adjust Add) Decimal Adjust

Operation

Rd (decimal adjust) → Rd

Assembly-Language Format

DAA Rd

Operand Size

Byte

Condition Code

↔

—*—— *

UIHUNZVC

H: Undetermined (no guara nt eed value).

N: Set to 1 if the adjusted result is negative;

otherwise cleared to 0.

Z: Set to 1 if the adjusted result is zero;

otherwise cleared to 0.

V: Undetermined (no guara nt eed value).

C: Set to 1 if there is a carry at bit 7;

otherwise left unchanged.

Description

Given that the resu lt of an addition operation performed by an ADD.B or ADDX instruction on

4-bit BCD data is contained in an 8-bit register Rd and the carry and half-carry flags, the DAA

instruction ad

usts the contents of th e 8-b it re

ister Rd (destinatio n o

erand) b

addin

H'00, H'06,

H'60, or H'66 according to the table below.

C Flag

before

Adjustment

Upper 4 Bits

before

Adjustment

H Flag

before

Adjustment

Lower 4 Bits

before

Adjustment

Value

Added

(Hexadecimal)

C Flag

after

Adjustment

0 0 to 9 0 0 to 9 00 0

0 0 to 8 0 A to F 06 0

0 0 to 9 1 0 to 3 06 0

0 A to F 0 0 to 9 60 1

0 9 to F 0 A to F 66 1

0 A to F 1 0 to 3 66 1

1 0 to 2 0 0 to 9 60 1

1 0 to 2 0 A to F 66 1

1 0 to 3 1 0 to 3 66 1

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 95 of 322

REJ09B0139-0400

DAA (Decimal Adjust Add) Decimal Adjust

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Valid results (8 -bit register Rd contents and C, V, Z, N, and H flags) are not assu red if this

instruction is executed under conditions other than those described above.

Section 2 Instruction Descriptions

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2.2.25 DAS

DAS (Decimal Adju st Subtract) Decimal Adjust

Operation

Rd (decimal adjust) → Rd

Assembly-Language Format

DAS Rd

Operand Size

Byte

Condition Code

↔

—*—— *0

UIHUNZVC

H: Undetermined (no guara nt eed value).

N: Set to 1 if the adjusted result is negative;

otherwise cleared to 0.

Z: Set to 1 if the adjusted result is zero;

otherwise cleared to 0.

V: Undetermined (no guara nt eed value).

C: Previous value remains unchanged.

Description

Given that the result of a subtraction operation performed by a SUB.B, SUBX.B, or NEG.B

instruction on 4-bit BCD data is contained in an 8-bit register Rd and the carry and half-carry

flags, the DAS instruction adjusts the contents of the 8-bit register Rd (destination operand) by

adding H'00, H'FA, H'A0, or H'9A according to the table below.

C Flag

before

Adjustment

Upper 4 Bits

before

Adjustment

H Flag

before

Adjustment

Lower 4 Bits

before

Adjustment

Value

Added

(Hexadecimal)

C Flag

after

Adjustment

0 0 to 9 0 0 to 9 00 0

0 0 to 8 1 6 to F FA 0

1 7 to F 0 0 to 9 A0 1

1 6 to F 1 6 to F 9A 1

Available Registers

Rd: R0L to R7 L, R0H to R7H

Section 2 Instruction Descriptions

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REJ09B0139-0400

DAS (Decimal Adju st Subtract) Decimal Adjust

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Valid results (8 -bit register Rd contents and C, V, Z, N, and H flags) are not assu red if this

instruction is executed under conditions other than those described above.

Section 2 Instruction Descriptions

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REJ09B0139-0400

2.2.26 (1) DEC (B)

DEC (DECrement) Decrement

Operation

Rd – 1 → Rd

Assembly-Language Format

DEC.B Rd

Operand Size

Byte

Condition Code

↔

—————

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Previous value remains unchanged.

Description

This instruction decrements an 8-bit register Rd (destination operand) and stores the result in the

8-bit register Rd.

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

An overflow is caused by the operation H'80 – 1 → H'7F.

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 99 of 322

REJ09B0139-0400

2.2.26 (2) DEC (W)

DEC (DECrement) Decrement

Operation

Rd – 1 → Rd

Rd – 2 → Rd

Assembly-Language Format

DEC.W #1, Rd

DEC.W #2, Rd

Operand Size

Word

Condition Code

↔

—————

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Previous value remains unchanged.

Description

This instruction subtracts the immediate value 1 or 2 from the contents of a 16-bit register Rd

(destination operand) and stores the result in the 16-bit register Rd.

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

An overflow is caused by the operations H'8000 – 1 → H'7FFF, H'8000 – 2 → H'7FFE, and

H'8001 – 2 → H'7FFF.

Section 2 Instruction Descriptions

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2.2.26 (3) DEC (L)

DEC (DECrement) Decrement

Operation

ERd – 1 → ERd

ERd – 2 → ERd

Assembly-Language Format

DEC.L #1, ERd

DEC.L #2, ERd

Operand Size

Longword

Condition Code

↔

—————

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Previous value remains unchanged.

Description

This instruction subtracts the immediate value 1 or 2 from the contents of a 32-bit register ERd

(destination operand) and stores the result in the 32-bit register ERd.

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

An overflow is caused by the operations H'80000000 – 1 → H'7FFFFFFF, H'80000000 – 2 →

H'7FFFFFFE, an d H'80000001 – 2 → H'7FFFFFFF.

Section 2 Instruction Descriptions

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2.2.27 (1) DIVXS (B)

DIVXS (DIVide eXtend as Signed) Divide Signed

Operation

Rd ÷ Rs → Rd

Assembly-Language Format

DIVXS.B Rs, Rd

Operand Size

Byte

Condition Code

↔

——————

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if th e quotient is negativ e;

otherwise cleared to 0.

Z: Set to 1 if the divisor is zero; otherwise

cleared to 0.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction divides the contents of a 16-bit register Rd (destination operand) by the contents

of an 8-bit register Rs (source operand) and stores the result in the 16-bit register Rd. The division

is signed. The operation performed is 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder. The

quotient is placed in the lower 8 bits of Rd. The remainder is placed in the upper 8 bits of Rd. The

sign of the remainder matches the sign of the dividend.

Rd Rs Rd

Dividend ÷Divisor →Remainder Quotient

16 bits 8 bits 8 bits 8 bits

Valid results are not assured if division by zero is attempted or an overflow occurs.

Available Registers

Rd: R0 to R7, E0 to E7

Rs: R0L to R7L, R0H to R7H

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 102 of 322

REJ09B0139-0400

DIVXS (DIVide eXtend as Signed) Divide Signed

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

The N flag is set to 1 if the dividend and divisor have different signs, and cleared to 0 if they have

the same sign. The N flag may therefore be set to 1 when the quotient is zero.

Section 2 Instruction Descriptions

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2.2.27 (2) DIVXS (W)

DIVXS (DIVide eXtend as Signed) Divide Signed

Operation

ERd ÷ Rs → ERd

Assembly-Language Format

DIVXS.W Rs, ERd

Operand Size

Word

Condition Code

↔

——————

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if th e quotient is negativ e;

otherwise cleared to 0.

Z: Set to 1 if the divisor is zero; otherwise

cleared to 0.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction divides the contents of a 32-bit register ERd (destination operand) by the contents

of a 16-bit register Rs (source operand) and stores the result in the 32-bit register ERd. The

division is signed. The operation performed is 32 bits ÷ 16 bits → 16-bit quotient and 16 -bit

remainder. The quotient is placed in the lower 16 bits (Rd) of the 32-bit register ERd. The

remainder is placed in the upper 16 bits (Ed). The sign of the remainder matches the sign of the

dividend.

ERd Rs ERd

Dividend ÷Divisor →Remainder Quotient

32 bits 16 bits 16 bits 16 bits

Valid results are not assured if division by zero is attempted or an overflow occurs.

Available Registers

ERd: ER0 to ER7

Rs: R0 to R7, E0 to E7

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 104 of 322

REJ09B0139-0400

DIVXS (DIVide eXtend as Signed) Divide Signed

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

The N flag is set to 1 if the dividend and divisor have different signs, and cleared to 0 if they have

the same sign. The N flag may therefore be set to 1 when the quotient is zero.

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 105 of 322

REJ09B0139-0400

2.2.28 (1) DIVXU (B)

DIVXU (DIVide eXtend as Unsigned) Divide

Operation

Rd ÷ Rs → Rd

Assembly-Language Format

DIVXU.B Rs, Rd

Operand Size

Byte

Condition Code

↔

——————

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the divisor is negative;

otherwise cleared to 0.

Z: Set to 1 if the divisor is zero; otherwise

cleared to 0.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction divides the contents of a 16-bit register Rd (destination operand) by the contents

of an 8-bit register Rs (source operand) and stores the result in the 16-bit register Rd. The division

is unsigned. The operation performed is 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder. The

quotient is placed in the lower 8 bits of Rd. The remainder is placed in the upper 8 bits of Rd.

Rd Rs Rd

Dividend ÷Divisor →Remainder Quotient

16 bits 8 bits 8 bits 8 bits

Valid results are not assured if division by zero is attempted or an overflow occurs.

Available Registers

Rd: R0 to R7, E0 to E7

Rs: R0L to R7L, R0H to R7H

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 106 of 322

REJ09B0139-0400

DIVXU (DIVide eXtend as Unsigned) Divide

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 107 of 322

REJ09B0139-0400

2.2.28 (2) DIVXU (W)

DIVXU (DIVide eXtend as Unsigned) Divide

Operation

ERd ÷ Rs → ERd

Assembly-Language Format

DIVXU.W Rs, ERd

Operand Size

Word

Condition Code

↔

——————

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the divisor is negative;

otherwise cleared to 0.

Z: Set to 1 if the divisor is zero; otherwise

cleared to 0.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction divides the contents of a 32-bit register ERd (destination operand) by the contents

of a 16-bit register Rs (source register) and stores the result in the 32-bit register ERd. The

division is unsigned. The operation performed is 32 bits ÷ 16 bits → 16-bit quotient and 16-bit

remainder. The quotient is placed in the lower 16 bits (Rd) of the 32-bit register ERd. The

remainder is placed in the upper 16 bits of (Ed).

ERd Rs ERd

Dividend ÷Divisor →Remainder Quotient

32 bits 16 bits 16 bits 16 bits

Valid results are not assured if division by zero is attempted or an overflow occurs.

Available Registers

ERd: ER0 to ER7

Rs: R0 to R7, E0 to E7

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 108 of 322

REJ09B0139-0400

DIVXU (DIVide eXtend as Unsigned) Divide

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 109 of 322

REJ09B0139-0400

2.2.29 (1) EEPMOV (B)

EEPMOV (MOVe data to EEPROM) Block Data Transfer

Operation

if R4L ≠ 0 then

repeat @ER5+ → @ER6 +

R4L – 1 → R4L

until R4L = 0

else next;

Assembly-Language Format

EEPMOV.B

Operand Size

—

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction performs a block data transfer. It moves data from the memory location specified

in ER5 to the memory location specified in ER6, incremen ts ER5 and ER6, decrements R4L, and

repeats these operatio ns until R4L reaches zero. Execution then proceeds to the n ext instru ction.

The data transfer is performed a byte at a time, with R4L indicating the number of bytes to be

transferred. The byte symbol in the assembly-language format designates the size of R4L (and

limits the maxim um number of bytes that can be transferred to 255). No in ter rup ts ar e detected

while the bloc k transfer is in prog ress.

When the EEPMOV.B instruction ends, R4L contains 0 (zero), and ER5 and ER6 contain the last

transfer address + 1.

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

— EEPMOV.B 7B5C598F4 + 2n

Note: *n is the initial value of R4L. Although n bytes of data are transferred, 2(n + 1) data accesses are

performed, requi ri ng 2(n + 1) states. (n = 0, 1, 2, …, 255).

Notes

This instructio n first reads the memo r y locations indicated by ER5 and ER6, then carries out the

block data tran sfer.

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 110 of 322

REJ09B0139-0400

2.2.29 (2) EEPMOV (W)

EEPMOV (MOVe data to EEPROM) Block Data Transfer

Operation

if R4 ≠ 0 then

repeat @ER5+ → @ER6 +

R4 – 1 → R4

until R4 = 0

else next;

Assembly-Language Format

EEPMOV.W

Operand Size

—

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction performs a block data transfer. It moves data from the memory location specified

in ER5 to the memory location specified in ER6, incremen ts ER5 and ER6, decrements R4, and

repeats these operatio ns until R4 reaches zero. Execution then proceeds to the next instruction.

The data transfer is performed a byte at a time, with R4 indicating the number of bytes to be

transferred. The word symbol in the assembly-language format designates the size of R4 (allowing

a maximum 65535 bytes to be transferred ). All interrupts are detected while th e block transfer is

in pr ogress.

If no interrupt occurs while the EEPMOV.W in str uction is executin g , when the EEPMOV.W

instruction ends, R4 contains 0 (zero), and ER5 and ER6 contain the last transfer address + 1.

If an interrupt occurs, interrupt exception handling begins after the current byte has been

transferred. R4 indicates the number of bytes remaining to be transferred. ER5 and ER6 indicate

the next transfer addresses. The program counter value pushed onto the stack in interrupt

exception handling is the address of the next instruction after the EEPMOV.W instruction.

See the note on EEPMOV.W instruction and interrupt.

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 111 of 322

REJ09B0139-0400

EEPMOV (MOVe data to EEPROM) Block Data Transfer

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

— EEPMOV.W 7BD4598F4 + 2n

Note: *n is the initial value of R4. Alt hough n bytes of data are transf erred, 2(n + 1) data accesses are

performed, requi ri ng 2(n + 1) states. (n = 0, 1, 2, …, 65535).

Notes

This instruction first reads memory at the addresses indicated by ER5 and ER6, then carries out

the block data transfer.

EEPMOV.W Instruction a nd Interrupt

If an interrupt requ est occurs while the EEPMOV.W instruction is being executed, in terru p t

exception handling is carried out after the curren t byte has been transferred. Register contents are

then as follo ws:

ER5: address of the next byte to be transferred

ER6: destination address of the next byte

R4: number of bytes remaining to be transferred

The program counter value pushed on the stack in interrupt exception handling is the address of

the next in str uction after the EEPMOV.W instructio n. Programs should be coded as follows to

allow for interrupts during execution of the EEPMOV.W instruction.

Example:

L1: EEPMOV.W

MOV.W R4,R4

BNE L1

Interrupt requests other than NMI are not accepted if they are masked in the CPU.

During execution of the EEPMOV.B instruction no interrupts are accepted, includ ing NMI.

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 112 of 322

REJ09B0139-0400

2.2.30 (1) EXTS (W)

EXTS (EXTend as Signed) Sign Extension

Operation

(<Bit 7> of Rd) → (<bits 15 to 8> of Rd)

Assembly-Language Format

EXTS.W Rd

Operand Size

Word

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction copies the sign of the lower 8 bits in a 16-b it r e gister Rd in the upward d irection

(copies Rd bit 7 to bits 15 to 8) to extend the data to signed word data.

Don’t care

8 bits

Sign bit

8 bits

Sign extension

8 bits 8 bits

70Bit 15 Rd

70Bit 15

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 113 of 322

REJ09B0139-0400

2.2.30 (2) EXTS (L)

EXTS (EXTend as Signed) Sign Extension

Operation

(<Bit 15> of ERd) → (<bits 31 to 16> of ERd)

Assembly-Language Format

EXTS.L ERd

Operand Size

Longword

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instructio n copies the sign of the lower 16 bits in a 32-bit r egister ERd in the upward

direction (copies ERd bit 15 to bits 31 to 16) to extend the data to signed longword data.

Don’t care

16 bits

Sign bit

16 bits

Sign extension

16 bits 16 bits

0Bit 31 ERd 15 0Bit 31 ERd

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 114 of 322

REJ09B0139-0400

2.2.31 (1) EXTU (W)

EXTU (EXTend as Unsigned) Zero Extension

Operation

0 → (<bits 15 to 8> of Rd)

Assembly-Language Format

EXTU.W Rd

Operand Size

Word

Condition Code

↔

0———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Always cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instructio n extends the lower 8 bits in a 16-bit register Rd to word data by padding with

zeros. That is, it clears the u pper 8 bits of Rd (bits 15 to 8) to 0.

Don’t care

8 bits 8 bits

Zero extension

8 bits 8 bits

70Bit 15 Rd

70Bit 15

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 115 of 322

REJ09B0139-0400

2.2.31 (2) EXTU (L)

EXTU (EXTend as Unsigned) Zero Extension

Operation

0 → (<bits 31 to 16> of ERd)

Assembly-Language Format

EXTU.L ERd

Operand Size

Longword

Condition Code

↔

0———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Always cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instructio n extends the lower 16 b its ( general register Rd) in a 32-bit register ERd to

longword data by padding with zeros. That is, it clears the upper 16 bits of ERd (bits 31 to 16) to

Don’t care

16 bits 16 bits

Zero extension

16 bits 16 bits

15 0Bit 31 ERd 15 0Bit 31 ERd

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

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2.2.32 (1) INC (B)

INC (INCrement) Increment

Operation

Rd + 1 → Rd

Assembly-Language Format

INC.B Rd

Operand Size

Byte

Condition Code

↔

—————

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Previous value remains unchanged.

Description

This instruction increments an 8-bit register Rd (destination operand) and stores the result in the

8-bit register Rd.

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

An overflow is caused by the operation H'7F + 1 → H'80.

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 117 of 322

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2.2.32 (2) INC (W)

INC (INCrement) Increment

Operation

Rd + 1 → Rd

Rd + 2 → Rd

Assembly-Language Format

INC.W #1, Rd

INC.W #2, Rd

Operand Size

Word

Condition Code

↔

—————

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Previous value remains unchanged.

Description

This instructio n adds the immediate value 1 or 2 to the contents of a 16-bit register Rd ( destination

operand) and stores the re sult in the 16-bit register Rd.

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

An overflow is caused by the operations H'7FFF + 1 → H'8000, H'7 FFF + 2 → H'8001, and

H'7FFE + 2 → H'8000.

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2.2.32 (3) INC (L)

INC (INCrement) Increment

Operation

ERd + 1 → ERd

ERd + 2 → ERd

Assembly-Language Format

INC.L #1, ERd

INC.L #2, ERd

Operand Size

Longword

Condition Code

↔

—————

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Previous value remains unchanged.

Description

This instruction adds the immediate value 1 or 2 to the contents of a 32-bit register ERd

(destination operand) and stores the result in the 32-bit register ERd.

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

An overf low is caused by the operations H'7FFFFFFF + 1 → H'80000000, H'7FFFFFFF + 2 →

H'80000001, and H'7FFFFFFE + 2 → H'80000000.

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2.2.33 JMP

JMP (JuMP) Unconditional Branch

Operation

Effective address → PC

Assembly-Language Format

JMP <EA>

Operand Size

—

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction branches unconditionally to a specified effective address.

Available Registers

ERn: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format No. of States

Addressing

Mode Mnemonic Operands 1st byte 2nd byt e 3rd byte 4t h byt e Norm al A dv an ce d

Absolute ad dress JMP @aa: 24 5 A abs 3

Memory indirect JMP @@aa:8 5 B abs 4 5

Notes

The structure of the branch address and the number of states required for execution differ between

normal mode and advanced mode.

Ensure that the branch destination address is even.

Section 2 Instruction Descriptions

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2.2.34 JSR

JSR (Jump to SubRoutine) Jump to Subroutine

Operation

PC → @–SP

Effective address → PC

Assembly-Language Format

JSR <EA>

Operand Size

—

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction pushes the program counter onto the stack as a return address, then branches to a

specified effective address. The program counter value pushed onto the stack is the address of the

instructio n following the JSR instructio n.

Available Registers

ERn: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format No. of States

Addressing

Mode Mnemonic Operands 1st byte 2nd byt e 3rd byte 4t h byt e Norm al A dv an ce d

Absolute ad dress JS R @ aa: 24 5 E abs 4 5

Memory indirect JSR @@aa:8 5 F abs 4 6

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JSR (Jump to SubRoutine) Jump to Subroutine

Notes

The stack structure differs between normal mode and advanced mode. In normal mode only the

lower 16 bits of the program counter are pushed onto the stack.

Ensure that the branch destination address is even.

PC 23 16 15 8 7 0 Normal mode

PC 23 16 15 8 7 0 Advanced mode

Reserved

Section 2 Instruction Descriptions

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2.2.35 (1) LDC (B)

LDC (LoaD to Control register) Load CCR

Operation

<EAs> → CCR

Assembly-Language Format

LDC.B <EAs>, CCR

Operand Size

Byte

Condition Code

↔

UIHUNZVC

I: Loaded from the corresponding bit in the

source operand.

H: Loaded from the corresponding bit in the

source operand.

N: Loaded from the corresponding bit in the

source operand.

Z: Loaded from the corresponding bit in the

source operand.

V: Loaded from the corresponding bit in the

source operand.

C: Loaded from the corresponding bit in the

source operand.

Description

This instruction load s the sourc e opera nd cont e nts into the conditio n-code register (CCR).

No interrupt requests, including NMI, are accepted immediately after execution of this instruction.

Available Registers

Rs: R0L to R7L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Immedi ate LDC.B #xx:8, CCR 0 7 IMM 1

Notes

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2.2.35 (2) LDC (B)

LDC (LoaD to Control register) Load EXR

Operation

<EAs> → EXR

Assembly-Language Format

LDC.B <EAs>, EXR

Operand Size

Byte

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction loads the source operand contents into the extended control register (EXR).

No interrupt requests, including NMI, are accepted for three states after execution of this

instruction.

Available Registers

Rs: R0L to R7L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Immediate LDC.B#xx:8, EXR014107 IMM 2

Notes

Section 2 Instruction Descriptions

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REJ09B0139-0400

2.2.35 (3) LDC (W)

LDC (LoaD to Control register) Load CCR

Operation

(EAs) → CCR

Assembly-Language Format

LDC.W <EAs>, CCR

Operand Size

Word

Condition Code

↔

UIHUNZVC

I: Loaded from the corresponding bit in the

source operand.

H: Loaded from the corresponding bit in the

source operand.

N: Loaded from the corresponding bit in the

source operand.

Z: Loaded from the corresponding bit in the

source operand.

V: Loaded from the corresponding bit in the

source operand.

C: Loaded from the corresponding bit in the

source operand.

Description

This instruction load s the sourc e opera nd cont e nts into the conditio n-code register (CCR).

Although CCR is a byte register, the source operand is word size. The contents of the even address

are loaded into CCR.

No interrupt requests, including NMI, are accepted immediately after execution of this instruction.

Available Registers

ERs: ER0 to ER7

Section 2 Instruction Descriptions

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LDC (LoaD to Control register) Load CCR

Operand Format and Number of States Required for Execution

Notes

Addressing Mnemonic Operands Instruction Format No. of

Mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte States

LDC.W @ERs, CCR 0140690ers0 3

LDC.W @(d:16, ERs), CCR 01406F0ers0 disp 4

LDC.W @(d:32, ERs), CCR 0140780ers06B20 disp 6

LDC.W @ERs+, CCR 01406D0ers0 4

LDC.W @aa:16, CCR 01406B00 abs 4

LDC.W @aa:32, CCR 01406B20 abs 5

indirect

indirect with

displace-

ment

indirect with

post-

increment

Absolute

address

Section 2 Instruction Descriptions

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REJ09B0139-0400

2.2.35 (4) LDC (W)

LDC (LoaD to Control register) Load EXR

Operation

(EAs) → EXR

Assembly-Language Format

LDC.W <EAs>, EXR

Operand Size

Word

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction loads the source operand contents into the extended control register (EXR).

Although EXR is a byte register, the source operand is word size. The contents of the even address

are loaded into EXR.

No interrupt requests, including NMI, are accepted for three states after execution of this

instruction.

Available Registers

ERs: ER0 to ER7

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LDC (LoaD to Control register) Load EXR

Operand Format and Number of States Required for Execution

Notes

Addressing Mnemonic Operands Instruction Format No. of

Mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte States

LDC.W @ERs, EXR 0141690ers0 3

LDC.W @(d:16, ERs), EXR 01416F0ers0 disp 4

LDC.W @(d:32, ERs), EXR 0141780ers06B20 disp 6

LDC.W @ERs+, EXR 01416D0ers0 4

LDC.W @aa:16, EXR 01416B00 abs 4

LDC.W @aa:32, EXR 01416B20 abs 5

indirect

indirect with

displace-

ment

indirect with

post-

increment

Absolute

address

Section 2 Instruction Descriptions

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REJ09B0139-0400

2.2.36 LDM

LDM (LoaD to Multiple registers) Restore Data from Stack

Operation

@SP+ → ERn ( register list)

Assembly-Language Format

LDM.L @SP+, <register li st>

Operand Size

Longword

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction restores data saved on the stack to a specified list of registers. Registers are

restored in descending order of register number.

Two, three, or four registers can be restored by one LDM instruction. The following ranges can be

specified in the register list.

Two registers: ER0–ER1, ER2–ER3, ER4–ER5, or ER6–ER7

Three registers: ER0–ER2 or ER4 –ER6

Four registers: ER0–ER3 or ER4–ER7

Available Registers

ERn: ER0 to ER7

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LDM (LoaD to Multiple registers) Restore Data from Stack

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3r d byt e 4th byte

No. of

States

—LDM.L @SP+,

(ERn–ERn+1) 01106D70ern+17

—LDM.L @SP+,

(ERn–ERn+2) 01206D70ern+29

—LDM.L @SP+,

(ERn–ERn+3) 01306D70ern+311

Notes

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REJ09B0139-0400

2.2.37 LDMAC

LDMAC (LoaD to MAC register) Load MAC Register

Operation

ERs → MACH

ERs → MACL

Assembly-Language Format

LDMAC ERs, MAC register

Operand Size

Longword

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instructio n moves the con ten ts of a general register to a multip ly-accumulate register (MACH

or MACL). If the transfer is to MACH, only the lowest 10 bits of the general register are

transferred.

Supported only by the H8S/2600 CPU.

Available Registers

ERs: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Note: *A maximum of three additional states are required for executi on of this instruction within three states

after execution of a MAC instruct i on. For example, if there is a one-state i nst ruction (such as NOP)

between the MAC instruct i on and this i nst ruction, this instructi on will be two stat es longer.

The number of states may differ depending on the product. For details, refer to the relevant

microcontrol l er hardware manual of the product in question.

Notes

Execution of th is instruction clear s the overflow flag in the multiplier to 0.

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2.2.38 MAC

MAC (Multiply and ACcumulate) Multiply and Accumulate

Operation

(EAn) × (EAm) + MAC register →

MAC register

ERn + 2 → ERn

ERm + 2 → ERm

Assembly-Language Format

MAC @ERn+ , @ERm+

Operand Size

—

Condition Code

—*—*—————* —

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction performs sig ned multiplication on two 16-bit operands at addr esses given by the

contents of general registers ERn and ERm, adds the 32-bit product to the contents of the MAC

incremented by 2.

The operation can be carried out in saturating or non-saturating mode, depending on the MACS

bit in a system control register. (SYSCR)

See the relevant hardware manual for further information.

In non-saturating mode, MACH and MACL are concatenated to store a 42-bit result. The value of

bit 41 is copied into the upper 22 bits of MACH as a sign extension.

In saturating mode, only MACL is valid, and the result is limited to the range from H'80000000

(minimum value) to H'7FFFFFF F ( maximum value). If the result overflows in the negative

direction, H'80000000 (the minimum value) is stored in MACL. If the result overflows in the

positive direction, H'7FFFFFFF (the maximum v a lue) is stored in MACL. The LSB of the MACH

their previous contents.

This instruction is supported only by the H8S/2600 CPU.

Section 2 Instruction Descriptions

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MAC (Multiply and ACcumulate) Multiply and Accumulate

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4t h byt e

No. of

States

indirect with

post-increment MAC @ERn+,

@ERm+ 01606D0ern0erm4

Notes

1. Flags (N, Z, V) indicating the result of the MAC instruction can be set in the condition-code

2. If ERn and ERm are the same register, the execution addresses are ERn and ERn + 2. After

execution, the value of ERn is ERn + 4.

3. If MACS is modified during execution of a MAC instruction, the result cannot be guaranteed.

It is essential to wait fo r at least three states after a MAC instruction b e f ore modifying MACS.

Further Explanation of Instruct ions Using M ult iplier

1. Modification of flags

The multiplier h a s N- MULT, Z-MULT, and V-MULT flag s th at indicate th e r esults of MAC

instructions. These fl a gs are se parated from the conditio n-code register (CCR). The values of

these flags can be set in the N, Z, and V flags of the CCR only by the STMAC instruction.

N-MULT and Z-MULT are modified only by MAC instru ctions. V-MULT retains a value

indicating whether an overflow has occurred in the past, until it is cleared by execution of the

CLRMAC or LDMAC instruction.

The setting and clearing conditions for these flags are given below.

•N-MULT (negative flag)

Saturating mode Set when bit 31 of register MACL is set to 1 by execution of a

MAC instruction

Cleared when bit 31 of register MACL is cleared to 0 by execution

of a MAC instruction

Non-saturati ng mode Set when bit 41 of register MACH is set to 1 by execution of a

MAC instruction

Cleared when bit 41 of register MACH is cleared to 0 by execution

of a MAC instruction

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MAC (Multiply and ACcumulate) Multiply and Accumulate

•Z-MULT (zero flag)

Saturating mode Set when register MACL is cleared to 0 by execution of a MAC

instruction

Cleared when register MACL is not cleared to 0 by execution of a

MAC instruction

Non-saturati ng mode Set when registers MACH and MACL are both cleared to 0 by

execution of a MAC instruction

Cleared when register MACH or MACL is not cleared to 0 by

execution of a MAC instruction

•V-MULT (overflow flag)

Saturating mode Set when the result of the MAC instruction overflows the range

from H'80000000 (minimum) to H'7FFFFFFF (maximum)

Cleared when a CLRMAC or LDMAC instruction is executed

Note: Not cleared when the result of the MAC instruction is within

the above rang e

Non-saturati ng mode Set when the result of the MAC instruction overflows the range

from H'20000000000 (minimum) to H'1FFFFFFFFFF (maximum)

Cleared when a CLRMAC or LDMAC instruction is executed

Note: Not cleared when the result of the MAC instruction is within

the above rang e

The N-MULT, Z-MULT, and V-MULT flags are not modified by switching between

saturating and non-saturating mod es, or by execution of a multiply instruction (MULXU or

MULXS).

2. Example

CLRMAC

MAC @ER1+,@ER2+

MAC @ER1+,@ER2+ ← Overflow occurs

MAC @ER1+,@ER2+ ← Result = 0

NOP

STMAC MACH,ER3 ← CCR (N = 0 , Z = 1, V = 1)

CLRMAC

STMAC MACH,ER3 ← CCR (N = 0 , Z = 1, V = 0)

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 134 of 322

REJ09B0139-0400

2.2.39 (1) MOV (B)

MOV (MOVe data) Move

Operation

Rs → Rd

Assembly-Language Format

MOV.B Rs, Rd

Operand Size

Byte

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if th e transferred data is nega tive;

otherwise cleared to 0.

Z: Set to 1 if the transferred data is zero;

otherwise cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction transfers one byte of data from an 8-bit register Rs to an 8-bit re gister Rd, tests the

transferred data, and sets condition-code flags according to the result.

Available Registers

Rs: R0L to R7L, R0H to R7H

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 135 of 322

REJ09B0139-0400

2.2.39 (2) MOV (W)

MOV (MOVe data) Move

Operation

Rs → Rd

Assembly-Language Format

MOV.W Rs, Rd

Operand Size

Word

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if th e transferred data is nega tive;

otherwise cleared to 0.

Z: Set to 1 if the transferred data is zero;

otherwise cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction transfers one word of data from a 16-bit r egister Rs to a 16-bit r e gister Rd, tests

the transferred data, and sets condition-code flag s according to the result.

Available Registers

Rd: R0 to R7, E0 to E7

Rs: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

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REJ09B0139-0400

2.2.39 (3) MOV (L)

MOV (MOVe data) Move

Operation

ERs → ERd

Assembly-Language Format

MOV.L ERs, ERd

Operand Size

Longword

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if th e transferred data is nega tive;

otherwise cleared to 0.

Z: Set to 1 if the transferred data is zero;

otherwise cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instructio n transfers one wo r d of data from a 32-bit register ERs to a 32-bit register ERd,

tests the transferred data, and sets condition-code flags according to the result.

Available Registers

ERd: ER0 to ER7

ERs: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 137 of 322

REJ09B0139-0400

2.2.39 (4) MOV (B)

MOV (MOVe data) Move

Operation

(EAs) → Rd

Assembly-Language Format

MOV.B <EAs>, Rd

Operand Size

Byte

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if th e transferred data is nega tive;

otherwise cleared to 0.

Z: Set to 1 if the transferred data is zero;

otherwise cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction transfers the source operand contents to an 8-bit register Rd, tests the transferred

data, and sets condition-code flags according to the result.

Available Registers

Rd: R0L to R7L, R0H to R7 H

ERs: ER0 to ER7

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Rev. 4.00 Feb 24, 2006 page 138 of 322

REJ09B0139-0400

MOV (MOVe data) Move

Operand Format and Number of States Required for Execution

Notes

The MOV.B @ER7+, Rd instruction should never be used, because it leaves an odd value in the stack pointer (ER7).

For details refer to section 3.3, Exception-Handling State, or to the relevant hardware manual.

For the @aa:8/@aa:16 access ran

e, refer to the relevant microcontroller hardware manual.

Addressing Mnemonic Operands Instruction Format No. of

Mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte States

Immediate MOV.B #xx:8, Rd F rd IMM 1

MOV.B @ERs, Rd 6 8 0 ers rd 2

MOV.B 6 E 0 ers rd disp 3

MOV.B 7 8 0 ers 0 6 A 2 rd disp 5

MOV.B @ERs+, Rd 6 C 0 ers rd 3

MOV.B @aa:8, Rd 2 rd abs 2

MOV.B @aa:16, Rd 6 A 0 rd abs 3

MOV.B @aa:32, Rd 6 A 2 rd abs 4

Absolute

address

indirect

with

displace-

ment

indirect

with post-

increment

indirect

@(d:16, ERs),

@(d:32, ERs),

Section 2 Instruction Descriptions

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REJ09B0139-0400

2.2.39 (5) MOV (W)

MOV (MOVe data) Move

Operation

(EAs) → Rd

Assembly-Language Format

MOV.W <EAs>, Rd

Operand Size

Word

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if th e transferred data is nega tive;

otherwise cleared to 0.

Z: Set to 1 if the transferred data is zero;

otherwise cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction transfers the source operand contents to a 16-bit register Rd, tests the transferred

data, and sets condition-code flags according to the result.

Available Registers

Rd: R0 to R7, E0 to E7

ERs: ER0 to ER7

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 140 of 322

REJ09B0139-0400

MOV (MOVe data) Move

Operand Format and Number of States Required for Execution

Notes

1. The source operand <EAs> must be located at an even address.

2. In machine lan

e, MOV.W @ER7+, Rd is identical to POP.W Rd.

Addressing Mnemonic Operands Instruction Format No. of

Mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte States

Immediate MOV.W #xx:16, Rd 7 9 0 rd IMM 2

MOV.W @ERs, Rd 6 9 0 ers rd 2

MOV.W 6 F 0 ers rd disp 3

MOV.W 7 8 0 ers 0 6 B 2 rd disp 5

MOV.W @ERs+, Rd 6 D 0 ers rd 3

MOV.W @aa:16, Rd 6 B 0 rd abs 3

MOV.W @aa:32, Rd 6 B 2 rd abs 4

Absolute

address

indirect

with

displace-

ment

indirect

with post-

increment

indirect

@(d:16, ERs),

@(d:32, ERs),

Section 2 Instruction Descriptions

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REJ09B0139-0400

2.2.39 (6) MOV (L)

MOV (MOVe data) Move

Operation

(EAs) → ERd

Assembly-Language Format

MOV.L <EAs>, ERd

Operand Size

Longword

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if th e transferred data is nega tive;

otherwise cleared to 0.

Z: Set to 1 if the transferred data is zero;

otherwise cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction transfers the source operand contents to a specified 32-bit register (ERd), tests the

transferred data, and sets condition-code flags according to the result. The first memory word

located at the effective address is stored in extended register Ed. Th e next word is stored in

general register Rd.

ERd Ed RdH RdL

MSB

LSB

Available Registers

ERs: ER0 to ER7

ERd: ER0 to ER7

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 142 of 322

REJ09B0139-0400

MOV (MOVe data) Move

Operand Format and Number of States Required for Execution

Notes

1. The source operand <EAs> must be located at an even address.

2. In machine lan

e, MOV.L @R7+, ERd is identical to POP.L ERd.

Addressing Mnemonic Operands Instruction Format No. of

Mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte States

MOV.L #xx:32, Rd 7 A 0 0 erd IMM 3

MOV.L @ERs, ERd 0100690ers0erd 4

MOV.L @(d:16, ERs), ERd 01006F0ers0erd disp 5

MOV.L @(d:32, ERs), ERd 0100780ers06B20erd disp 7

MOV.L @ERs+, ERd 01006D0ers0erd 5

MOV.L @aa:16, ERd 01006B00erd abs 5

MOV.L @aa:32, ERd 01006B20erd abs 6

indirect

Immediate

indirect with

displace-

ment

indirect

with post-

increment

Absolute

address

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 143 of 322

REJ09B0139-0400

2.2.39 (7) MOV (B)

MOV (MOVe data) Move

Operation

Rs → (EAd)

Assembly-Language Format

MOV.B Rs, <EA d>

Operand Size

Byte

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if th e transferred data is nega tive;

otherwise cleared to 0.

Z: Set to 1 if the transferred data is zero;

otherwise cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instructio n transfers the contents of an 8-bit register Rs ( so urce operand) to a destination

location, tests th e transferred data, and sets condition-cod e flags according to the result.

Available Registers

Rs: R0L to R7L, R0H to R7 H

ERd: ER0 to ER7

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 144 of 322

REJ09B0139-0400

MOV (MOVe data) Move

Operand Format and Number of States Required for Execution

Notes

1. The MOV.B Rs, @–ER7 instruction should never be used, because it leaves an odd value in the stack pointer

(ER7). For details refer to section 3.3, Exception-Handling State, or to the relevant hardware manual.

2. Execution of MOV.B RnL, @–ERn or MOV.B RnH, @–ERn first decrements ERn by one, then transfers the

designated part (RnL or RnH) of the resulting ERn value.

Addressing Mnemonic Operands Instruction Format No. of

Mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte States

MOV.B Rs, @ERd 6 8 1 erd rs 2

MOV.B 6 E 1 erd rs disp 3

MOV.B 7 8 0 erd 0 6 A A rs disp 5

MOV.B Rs, @–Erd 6 C 1 erd rs 3

MOV.B Rs, @aa:8 3 rs abs 2

MOV.B Rs, @aa:16 6 A 8 rs abs 3

MOV.B Rs, @aa:32 6 A A rs abs 4

Absolute

address

indirect

with

displace-

ment

indirect

with pre-

decrement

indirect

Rs,

@(d:16, ERd)

Rs,

@(d:32, ERd)

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 145 of 322

REJ09B0139-0400

2.2.39 (8) MOV (W)

MOV (MOVe data) Move

Operation

Rs → (EAd)

Assembly-Language Format

MOV.W Rs, <EA d>

Operand Size

Word

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if th e transferred data is nega tive;

otherwise cleared to 0.

Z: Set to 1 if the transferred data is zero;

otherwise cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction transfers the contents of a 16-bit register Rs (source operand) to a destination

location, tests th e transferred data, and sets condition-cod e flags according to the result.

Available Registers

Rs: R0 to R7, E0 to E7

ERd: ER0 to ER7

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 146 of 322

REJ09B0139-0400

MOV (MOVe data) Move

Operand Format and Number of States Required for Execution

Notes

1. The destination operand <EAd> must be located at an even address.

2. In machine language, MOV.W Rs, @–ER7 is identical to PUSH.W Rs.

3. When MOV.W Rn, @–ERn is executed, the transferred value comes from (value of ERn before execution) – 2.

Addressing Mnemonic Operands Instruction Format No. of

Mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte States

MOV.W Rs, @ERd 6 9 1 erd rs 2

MOV.W 6 F 1 erd rs disp 3

MOV.W 7 8 0 erd 0 6 B A rs disp 5

MOV.W Rs, @–ERd 6 D 1 erd rs 3

MOV.W Rs, @aa:16 6 B 8 rs abs 3

MOV.W Rs, @aa:32 6 B A rs abs 4

Absolute

address

indirect

with

displace-

ment

indirect

with pre-

decrement

indirect

Rs,

@(d:16, ERd)

Rs,

@(d:32, ERd)

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 147 of 322

REJ09B0139-0400

2.2.39 (9) MOV (L)

MOV (MOVe data) Move

Operation

ERs → (EAd)

Assembly-Language Format

MOV.L ERs, <EAd>

Operand Size

Longword

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if th e transferred data is nega tive;

otherwise cleared to 0.

Z: Set to 1 if the transferred data is zero;

otherwise cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction transfers the contents of a 32-bit register ERs (source operand) to a destination

location, tests th e tr ansferred data, and sets con dition-code flag s according to the result. The

extended register (Es) contents are stored at the first word indicated by the effective address. The

general register (Rs) contents are stored at the next word.

ERs Es RsH RsL

MSB

LSB

Available Registers

ERs: ER0 to ER7

ERd: ER0 to ER7

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 148 of 322

REJ09B0139-0400

MOV (MOVe data) Move

Operand Format and Number of States Required for Execution

Notes

1. The destination operand <EAd> must be located at an even address.

2. In machine language, MOV.L ERs, @–ER7 is identical to PUSH.L ERs.

3. When MOV.L ERn, @–ERn is executed, the transferred value is (value of ERn before execution) – 4.

Addressing Mnemonic Operands Instruction Format No. of

Mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte States

MOV.L ERs, @ERd 0100691erd0ers 4

MOV.L ERs, @(d:16, ERd) 01006F1erd0ers disp 5

MOV.L ERs, @(d:32, ERd) 0100780erd06BA0ers disp 7

MOV.L ERs, @–ERd 01006D1erd0ers 5

MOV.L ERs, @aa:16 01006B80ers abs 5

MOV.L ERs, @aa:32 01006BA0ers abs 6

indirect

indirect with

displace-

ment

indirect

with pre-

decrement

Absolute

address

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 149 of 322

REJ09B0139-0400

2.2.40 MOVFPE

MOVFPE (MOVe From Peripheral with E clock) Move Data with E Clock

Operation

(EAs) → Rd

Synchronized with E clock

Assembly-Language Format

MOVFPE @aa:16, Rd

Operand Size

Byte

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if th e transferred data is nega tive;

otherwise cleared to 0.

Z: Set to 1 if the transferred data is zero;

otherwise cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction transfers memory contents sp ecif ied by a 16-bit absolute address to a general

flags according to the result.

Note: Avoid using this instruction in microcontrollers without an E clock output pin, or in

single-chip mode.

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Absolute address MOVFPE @aa:16, Rd 6 A 4 rd abs *

Note: *For details, refer to the relevant microcontrol l er hardware manual.

Notes

1. This instruction cannot be used with addressing modes other than the above, and cannot

transfer word data or longword data.

2. The number of states required for execution is variable. For details, refer to the relevant

microcontroller hardware manual.

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 150 of 322

REJ09B0139-0400

2.2.41 MOVTPE

MOVTPE (MOVe To Peripheral with E clock) Move Data with E Clock

Operation

Rs → (EAd)

Synchronized with E clock

Assembly-Language Format

MOVTPE Rs, @aa:16

Operand Size

Byte

Condition Code

↔

————0—

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if th e transferred data is nega tive;

otherwise cleared to 0.

Z: Set to 1 if the transferred data is zero;

otherwise cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction transfers the contents of a general register Rs (source operand) to a destination

location specified by a 16-bit absolute address in synchronization with an E clock, tests the

transferred data, and sets condition-code flags according to the result.

Note: Avoid using this instruction in microcontrollers without an E clock output pin, or in

single-chip mode.

Available Registers

Rs: R0L to R7L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Absolute address MOVTPE Rs, @aa:16 6 A C rs abs *

Note: *For details, refer to the relevant microcontrol l er hardware manual.

Notes

1. This instruction cannot be used with addressing modes other than the above, and cannot

transfer word data or longword data.

2. The number of states required for execution is variable. For details, refer to the relevant

microcontroller hardware manual.

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 151 of 322

REJ09B0139-0400

2.2.42 (1) MULXS (B)

MULXS (MU Ltiply eXtend as Signed) Multiply Signed

Operation

Rd × Rs → Rd

Assembly-Language Format

MULXS.B Rs, Rd

Operand Size

Byte

Condition Code

↔

——————

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction multiplies the lower 8 bits of a 16- bit register Rd (destin ation operand) by the

contents of an 8-bit register Rs (source operand) as signed data and stores the result in the 16-bit

part (RdL) of Rd . The operation performed is 8 bits × 8 bits → 16 bits signed multiplication.

Rd Rs Rd

Don’t care Multiplicand ×Multiplier →Product

8 bits 8 bits 16 bits

Available Registers

Rd: R0 to R7, E0 to E7

Rs: R0L to R7L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Note: *The number of states in the H8S/2000 CPU is 13.

A maximum of three additional states are required for execution of this instruction with i n three states

after execution of a MAC instruct i on. For example, if there is a one-state i nst ruction (such as NOP)

between the MAC instruct i on and this i nst ruction, this instructi on will be two stat es longer.

The number of states may differ depending on the product. For details, refer to the relevant

microcontrol l er hardware manual of the product in question.

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 152 of 322

REJ09B0139-0400

2.2.42 (2) MULXS (W)

MULXS (MU Ltiply eXtend as Signed) Multiply Signed

Operation

ERd × Rs → ERd

Assembly-Language Format

MULXS.W Rs, ERd

Operand Size

Word

Condition Code

↔

——————

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction multiplies the lower 16 bits of a 32-bit register ERd (destination ope r and ) by the

contents of a 16-bit register Rs (source operand) as signed data and stores the result in the 32-bit

16 bits × 16 bits → 32 bits signe d multiplicatio n.

ERd Rs ERd

Don’t care Multiplicand ×Multiplier →Product

16 bits 16 bits 32 bits

Available Registers

ERd: ER0 to ER7

Rs: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Note: *The number of states in the H8S/2000 CPU is 21.

A maximum of three additional states are required for execution of this instruction with i n three states

after execution of a MAC instruct i on. For example, if there is a one-state i nst ruction (such as NOP)

between the MAC instruct i on and this i nst ruction, this instruction will be two st ates longer.

The number of states may differ depending on the product. For details, refer to the relevant

microcontrol l er hardware manual of the product in question.

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 153 of 322

REJ09B0139-0400

2.2.43 (1) MULXU (B)

MULXU (MULtiply eXtend as U nsigned) Multiply

Operation

Rd × Rs → Rd

Assembly-Language Format

MULXU.B Rs, Rd

Operand Size

Byte

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction multiplies the lower 8 bits of a 16- bit register Rd (destin ation operand) by the

contents of an 8-bit register Rs (source o

erand) as unsi

ned data and stores the result in the 16-bi

part (RdL) of Rd . The operation performed is 8 bits × 8 bits → 16 bits unsigned multiplication.

Rd Rs Rd

Don’t care Multiplicand ×Multiplier →Product

8 bits 8 bits 16 bits

Available Registers

Rd: R0 to R7, E0 to E7

Rs: R0L to R7L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Note: *The number of states in the H8S/2000 CPU is 12.

A maximum of three additional states are required for execution of this instruction with i n three states

after execution of a MAC instruct i on. For example, if there is a one-state i nst ruction (such as NOP)

between the MAC instruct i on and this i nst ruction, this instructi on will be two stat es longer.

The number of states may differ depending on the product. For details, refer to the relevant

microcontrol l er hardware manual of the product in question.

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 154 of 322

REJ09B0139-0400

2.2.43 (2) MULXU (W)

MULXU (MULtiply eXtend as U nsigned) Multiply

Operation

ERd × Rs → ERd

Assembly-Language Format

MULXU.W Rs, ERd

Operand Size

Word

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction multiplies the lower 16 bits of a 32-bit register ERd (destination ope r and ) by the

contents of a 16-bit register Rs (source o

erand) as unsi

ned data and stores the result in the 32-bi

16 bits × 16 bits → 32 bits unsig ned multiplication .

ERd Rs ERd

Don’t care Multiplicand ×Multiplier →Product

16 bits 16 bits 32 bits

Available Registers

ERd: ER0 to ER7

Rs: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Note: *The number of states in the H8S/2000 CPU is 20.

A maximum of three additional states are required for execution of this instruction with i n three states

after execution of a MAC instruct i on. For example, if there is a one-state i nst ruction (such as NOP)

between the MAC instruct i on and this i nst ruction, this instructi on will be two stat es longer.

The number of states may differ depending on the product. For details, refer to the relevant

microcontrol l er hardware manual of the product in question.

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 155 of 322

REJ09B0139-0400

2.2.44 (1) NEG (B)

NEG (NEGate) Negate Binary Signed

Operation

0 – Rd → Rd

Assembly-Language Format

NEG.B Rd

Operand Size

Byte

Condition Code

↔

———

UIHUNZVC

H: Set to 1 if th er e is a bor row at b it 3;

otherwise cleared to 0.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a borrow at bit 7;

otherwise cleared to 0.

Description

This instruction takes the two’s com plement of the contents o f an 8 - bit register Rd (destin ation

operand) and stores the result in the 8-bit register Rd (subtracting the register contents from H'00).

If the original conten ts of Rd were H'80, however , the result remains H'80.

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

An overflow occurs if the orig inal contents of Rd were H'80.

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 156 of 322

REJ09B0139-0400

2.2.44 (2) NEG (W)

NEG (NEGate) Negate Binary Signed

Operation

0 – Rd → Rd

Assembly-Language Format

NEG.W Rd

Operand Size

Word

Condition Code

↔

———

UIHUNZVC

H: Set to 1 if th er e is a bor row at b it 11;

otherwise cleared to 0.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a borrow at bit 15;

otherwise cleared to 0.

Description

This instruction takes the two’s complement of the contents of a 16-bit register Rd (destination

operand) and stores the result in the 16-bit register Rd (subtracting the register contents from

H'0000). If the original contents of Rd were H'8000, however, the result remains H'8000.

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

An overflow occurs if the original contents of Rd were H'8000.

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 157 of 322

REJ09B0139-0400

2.2.44 (3) NEG (L)

NEG (NEGate) Negate Binary Signed

Operation

0 – ERd → ERd

Assembly-Language Format

NEG.L ERd

Operand Size

Longword

Condition Code

↔

———

UIHUNZVC

H: Set to 1 if th er e is a bor row at b it 27;

otherwise cleared to 0.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a borrow at bit 31;

otherwise cleared to 0.

Description

This instruction takes the two’s complement of the contents of a 32-bit register ERd (destination

operand) and stores the result in the 32-bit register ERd (subtracting the register contents from

H'00000000). If the original contents of ERd were H'80000000, however, the result remains

H'80000000.

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

An overflow occurs if the original contents of ERd were H'80000000.

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 158 of 322

REJ09B0139-0400

2.2.45 NOP

NOP (No OPeration) No Operation

Operation

PC + 2 → PC

Assembly-Language Format

NOP

Operand Size

—

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction only increments the program counter, causing the next instruction to be executed.

The internal state of the CPU does not change.

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

— NOP 0000 1

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 159 of 322

REJ09B0139-0400

2.2.46 (1) NOT (B)

NOT (NOT = log ical complement ) Logical Complement

Operation

¬ Rd → Rd

Assembly-Language Format

NOT.B Rd

Operand Size

Byte

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction takes the one’s complement of the contents of an 8-bit register Rd (destination

operand) and stores the re sult in the 8-bit register Rd.

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 160 of 322

REJ09B0139-0400

2.2.46 (2) NOT (W)

NOT (NOT = log ical complement ) Logical Complement

Operation

¬ Rd → Rd

Assembly-Language Format

NOT.W Rd

Operand Size

Word

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction takes the one’s comp lement of the contents of a 16- bit register Rd (destin ation

operand) and stores the re sult in the 16-bit register Rd.

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 161 of 322

REJ09B0139-0400

2.2.46 (3) NOT (L)

NOT (NOT = log ical complement ) Logical Complement

Operation

¬ ERd → ERd

Assembly-Language Format

NOT.L ERd

Operand Size

Longword

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction takes the one’s complement of the contents of a 32-bit register ERd (destination

operand) and stores the result in the 32-bit register ERd.

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 162 of 322

REJ09B0139-0400

2.2.47 (1) OR (B)

OR (inclusive OR logical) Logical OR

Operation

Rd ∨ (EAs) → Rd

Assembly-Language Format

OR.B <EAs>, Rd

Operand Size

Byte

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction ORs the source operand with the contents of an 8-bit register Rd ( destination

operand) and stores the re sult in the 8-bit register Rd.

Available Registers

Rd: R0L to R7 L, R0H to R7H

Rs: R0L to R7L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Immedi ate OR.B #xx:8, Rd C rd IMM 1

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 163 of 322

REJ09B0139-0400

2.2.47 (2) OR (W)

OR (inclusive OR logical) Logical OR

Operation

Rd ∨ (EAs) → Rd

Assembly-Language Format

OR.W <EAs>, Rd

Operand Size

Word

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction ORs the source operand with the contents of a 16-bit register Rd ( destination

operand) and stores the re sult in the 16-bit register Rd.

Available Registers

Rd: R0 to R7, E0 to E7

Rs: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Immedi ate OR.W #xx:16, Rd 7 9 4 rd IMM 2

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 164 of 322

REJ09B0139-0400

2.2.47 (3) OR (L)

OR (inclusive OR logical) Logical OR

Operation

ERd ∨ (EAs) → ERd

Assembly-Language Format

OR.L <EAs>, ERd

Operand Size

Longword

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction ORs the source operand with the contents of a 32-bit register ERd (destination

operand) and stores the result in the 32-bit register ERd.

Available Registers

ERd: ER0 to ER7

ERs: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte

No. of

States

Immediate OR.L #xx:32, ERd 7 A 4 0 erd IMM 3

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 165 of 322

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2.2.48 (1) ORC

ORC (inclusive OR Control register) Logical OR with CCR

Operation

CCR ∨ #IMM → CCR

Assembly-Language Format

ORC #xx:8, CCR

Operand Size

Byte

Condition Code

↔

UIHUNZVC

I: Stores the corresponding bit of the result.

UI: Stor e s the corresp onding bit of the resu lt.

H: Stores the corresponding bit of the result.

U: Stores the corresponding bit of the result.

N: Stores the corresponding bit of the result.

Z: Stores the corresponding bit of the result.

V: Stores the corresponding bit of the result.

C: Stores the corresponding bit of the result.

Description

This instruction ORs the co ntents of th e con dition-cod e register (CCR) with im mediate data and

stores the result in the condition-code register. No interrupt requests, including NMI, are accepted

immediately af ter execution of this instru ction.

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Immedi ate ORC #xx:8, CCR 0 4 IMM 1

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 166 of 322

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2.2.48 (2) ORC

ORC (inclusive OR Control register) Logical OR with EXR

Operation

EXR ∨ #IMM → EXR

Assembly-Language Format

ORC #xx:8, EXR

Operand Size

Byte

Condition Code

————————

UIHUNZVC

H: Stores the corresponding bit of the result.

N: Stores the corresponding bit of the result.

Z: Stores the corresponding bit of the result.

V: Stores the corresponding bit of the result.

C: Stores the corresponding bit of the result.

Description

This instruction ORs the contents of the extended control register (EXR) with immediate data and

stores the resu lt in the extended control r egister. No interrupt requests, including NMI, are

accepted for three states after execution of this instruction.

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Immediate ORC#xx:8, EXR014104 IMM 2

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 167 of 322

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2.2.49 (1) POP (W)

POP (POP data) Pop Data from Stack

Operation

@SP+ → Rn

Assembly-Language Format

POP.W Rn

Operand Size

Word

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if th e transferred data is nega tive;

otherwise cleared to 0.

Z: Set to 1 if the transferred data is zero;

otherwise cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction restores d a ta f rom the stack to a 16-bit general r egister Rn, tests the restored data,

and sets condition-code flags according to the result.

Available Registers

Rn: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

—POP.WRn6D7rn 3

Notes

POP.W Rn is identical to MOV.W @SP+, Rn .

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 168 of 322

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2.2.49 (2) POP (L)

POP (POP data) Pop Data from Stack

Operation

@SP+ → ERn

Assembly-Language Format

POP.L ERn

Operand Size

Longword

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if th e transferred data is nega tive;

otherwise cleared to 0.

Z: Set to 1 if the transferred data is zero;

otherwise cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instructio n restores da ta f rom the stack to a 32-bit general register ERn, tests the re stored

data, and sets condition-code flags according to the result.

Available Registers

ERn: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

— POP.L ERn 01006D70ern5

Notes

POP.L ERn is identical to MOV.L @SP+, ERn.

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 169 of 322

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2.2.50 (1) PUSH (W)

PUSH (PUSH data) Push Data on Stack

Operation

Rn → @–SP

Assembly-Language Format

PUSH.W Rn

Operand Size

Word

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if th e transferred data is nega tive;

otherwise cleared to 0.

Z: Set to 1 if the transferred data is zero;

otherwise cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction saves data from a 16-bit register Rn onto the stack, tests the saved data, and sets

condition-code flags according to the result.

Available Registers

Rn: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

— PUSH.W Rn 6 D F rn 3

Notes

1. PUSH.W Rn is identical to MOV.W Rn, @–SP.

2. When PUSH.W R7 or PUSH.W E7 is executed, the value saved on the stack is the R7 or E7

value after effective address calculation (after ER7 is decremented by 2).

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 170 of 322

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2.2.50 (2) PUSH (L)

PUSH (PUSH data) Push Data on Stack

Operation

ERn → @–SP

Assembly-Language Format

PUSH.L ERn

Operand Size

Longword

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if th e transferred data is nega tive;

otherwise cleared to 0.

Z: Set to 1 if the transferred data is zero;

otherwise cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction pushes data from a 32-bit register ERn onto the stack, tests the saved data, and

sets condition-code flags according to the result.

Available Registers

ERn: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

— PUSH.L ERn 01006DF0ern5

Notes

1. PUSH.L ERn is identical to MOV.L ERn, @–SP.

2. When PUSH.L ER7 is executed, the value saved on the stack is the ER7 value after effective

address calculation (after ER7 is decremented by 4).

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 171 of 322

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2.2.51 (1) ROTL (B)

ROTL (ROTate Left) Rotate

Operation

Rd (left ro tation) → Rd

Assembly-Language Format

ROTL.B Rd

Operand Size

Byte

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 7.

Description

This instructio n rotates the bits in an 8- bit register Rd (destination operand) one bit to the left. The

most signif ican t bit (bit 7) is rotated to the least significant bit (bit 0), and also copied to the carry

flag.

MSB LSB

C b7 b0

. . . . . .

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 172 of 322

REJ09B0139-0400

2.2.51 (2) ROTL (B)

ROTL (ROTate Left) Rotate

Operation

Rd (left ro tation) → Rd

Assembly-Language Format

ROTL.B #2, Rd

Operand Size

Byte

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 6.

Description

This instruction rotates the b its in an 8-bit register Rd ( destination operand) two bits to the left.

The most sign if icant two bits (bits 7 and 6) ar e rotated to the least significant two bits ( bits 1 and

0), and bit 6 is also copied to the carry flag.

MSB LSB

C b7 b0

. . . .

b6 b1

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 173 of 322

REJ09B0139-0400

2.2.51 (3) ROTL (W)

ROTL (ROTate Left) Rotate

Operation

Rd (left ro tation) → Rd

Assembly-Language Format

ROTL.W Rd

Operand Size

Word

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 15.

Description

This instructio n rotates the bits in a 16- bit register Rd (destination operand) one bit to the left. The

most signif icant bit (bit 15)is rotated to the least significan t bit (bit 0), and also cop ied to the carry

flag.

MSB LSB

C b15 b0

. . . . . .

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 174 of 322

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2.2.51 (4) ROTL (W)

ROTL (ROTate Left) Rotate

Operation

Rd (left ro tation) → Rd

Assembly-Language Format

ROTL.W #2, Rd

Operand Size

Word

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 14.

Description

This instruction rotates the b its in a 16-bit register Rd ( destination operand) two bits to the left.

The most sign if icant two bits (bits 15 an d 14) are rotated to the least significant two bits (bits 1

and 0), and bit 14 is also copied to the carry flag.

MSB LSB

C b15 b0

. . . .

b14 b1

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 175 of 322

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2.2.51 (5) ROTL (L)

ROTL (ROTate Left) Rotate

Operation

ERd (left rotation) → ERd

Assembly-Language Format

ROTL.L ERd

Operand Size

Longword

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 31.

Description

This instructio n rotates the bits in a 32-bit register ERd (destination operand) one bit to the left.

The most sign if icant bit (bit 31) is rotated to the least significant bit (bit 0), and also copied to the

carry flag.

MSB LSB

C b31 b0

. . . . . .

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 176 of 322

REJ09B0139-0400

2.2.51 (6) ROTL (L)

ROTL (ROTate Left) Rotate

Operation

ERd (left rotation) → ERd

Assembly-Language Format

ROTL.L #2, ERd

Operand Size

Longword

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 30.

Description

This instructio n rotates the bits in a 32-bit register ERd (destination operand) two bits to the left.

The most sign if icant two bits (bits 31 an d 30) are rotated to the least significant two bits (bits 1

and 0), and bit 30 is also copied to the carry flag.

MSB LSB

C b31 b0

. . . .

b30 b1

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 177 of 322

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2.2.52 (1) ROTR (B)

ROTR (ROTate Right) Rotate

Operation

Rd (right rotation) → Rd

Assembly-Language Format

ROTR.B Rd

Operand Size

Byte

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 0.

Description

This instructio n rotates the bits in an 8-bit register Rd (destination operand) one bit to the right.

The least significan t bit (bit 0) is rotated to the most significan t bit (bit 7), and also copied to the

carry flag.

MSB LSB

b7 b0

. . . . . .

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 178 of 322

REJ09B0139-0400

2.2.52 (2) ROTR (B)

ROTR (ROTate Right) Rotate

Operation

Rd (right rotation) → Rd

Assembly-Language Format

ROTR.B #2, Rd

Operand Size

Byte

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 1.

Description

This instruction rotates the b its in an 8-bit register Rd ( destination operand) two bits to the right.

The least significant two bits (bits 1 an d 0) are rotated to the most significant two bits (bits 7 an d

6), and bit 1 is also copied to the carry flag.

MSB LSB

b7 b0

. . . .

Cb1b6

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 179 of 322

REJ09B0139-0400

2.2.52 (3) ROTR (W)

ROTR (ROTate Right) Rotate

Operation

Rd (right rotation) → Rd

Assembly-Language Format

ROTR.W Rd

Operand Size

Word

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 0.

Description

This instructio n rotates the bits in a 16-bit register Rd (destination operand) one bit to the right.

The least significant bit (bit 0) is rotated to the most significant bit (bit 15), and also copied to the

carry flag.

MSB LSB

b15 b0

. . . . . .

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 180 of 322

REJ09B0139-0400

2.2.52 (4) ROTR (W)

ROTR (ROTate Right) Rotate

Operation

Rd (right rotation) → Rd

Assembly-Language Format

ROTR.W #2, Rd

Operand Size

Word

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 1.

Description

This instruction rotates the b its in a 16-bit register Rd ( destination operand) two bits to the right.

The least significant two bits (bits 1 an d 0) are rotated to the most significant two bits (bits 15 and

14), and bit 1 is also copied to the carry flag.

MSB LSB

b15 b0

. . . .

Cb1b14

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 181 of 322

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2.2.52 (5) ROTR (L)

ROTR (ROTate Right) Rotate

Operation

ERd (right rotation) → ERd

Assembly-Language Format

ROTR.L ERd

Operand Size

Longword

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 0.

Description

This instructio n rotates the bits in a 32-bit register ERd (destination operand) one bit to the right.

The least significant bit (bit 0) is rotated to the most significant bit (bit 31), and also copied to the

carry flag.

MSB LSB

b31 b0

. . . . . .

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 182 of 322

REJ09B0139-0400

2.2.52 (6) ROTR (L)

ROTR (ROTate Right) Rotate

Operation

ERd (right rotation) → ERd

Assembly-Language Format

ROTR.L #2, ERd

Operand Size

Longword

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 1.

Description

This instructio n rotates the bits in a 32-bit register ERd (destination operand) two bits to the right.

The least significant two bits (bits 1 an d 0) are rotated to the most significant two bits (bits 31 and

30), and bit 1 is also copied to the carry flag.

MSB LSB

b31 b0

. . . .

Cb1b30

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 183 of 322

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2.2.53 (1) ROTXL (B)

ROTXL (ROTate with eXtend carry Left) Rotate through Carry

Operation

Rd (left rotatio n through carry flag) → Rd

Assembly-Language Format

ROTXL.B Rd

Operand Size

Byte

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 7.

Description

This instructio n rotates the bits in an 8-bit register Rd (destination operand) one bit to the left

through the carry flag. The carry flag is rotated into the least signif ican t bit (bit 0). The most

significant b it ( bit 7) rotates into the carry flag.

MSB LSB

Cb7 b0

. . . . . .

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 184 of 322

REJ09B0139-0400

2.2.53 (2) ROTXL (B)

ROTXL (ROTate with eXtend carry Left) Rotate through Carry

Operation

Rd (left rotation through carry flag) → Rd

Assembly-Language Format

ROTXL.B #2, Rd

Operand Size

Byte

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 6.

Description

This instruction rotates the b its in an 8-bit register Rd ( destination operand) two bits to the left

through th e carry flag. The carry flag rotates into bit 1, bit 7 r otates into bit 0, and bit 6 ro tates into

the carry flag.

MSB LSB

Cb7 b0

. . . . . .

b1b6

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 185 of 322

REJ09B0139-0400

2.2.53 (3) ROTXL (W)

ROTXL (ROTate with eXtend carry Left) Rotate through Carry

Operation

Rd (left rotatio n through carry flag) → Rd

Assembly-Language Format

ROTXL.W Rd

Operand Size

Word

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 15.

Description

This instructio n rotates the bits in a 16-bit register Rd (destination operand) one bit to the left

through the carry flag. The carry flag is rotated into the least signif ican t bit (bit 0). The most

significant b it ( bit 15) rotates into the carry f lag.

MSB LSB

C b15 b0

. . . . . .

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 186 of 322

REJ09B0139-0400

2.2.53 (4) ROTXL (W)

ROTXL (ROTate with eXtend carry Left) Rotate through Carry

Operation

Rd (left rotation through carry flag) → Rd

Assembly-Language Format

ROTXL.W #2, Rd

Operand Size

Word

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 14.

Description

This instruction rotates the b its in a 16-bit register Rd ( destination operand) two bits to the left

through th e carry f lag. The carry flag rotates in to bit 1, bit 15 rotates into bit 0, and bit 14 rotates

into the carry flag.

MSB LSB

C b15 b0

. . . . . .

b1b14

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 187 of 322

REJ09B0139-0400

2.2.53 (5) ROTXL (L)

ROTXL (ROTate with eXtend carry Left) Rotate through Carry

Operation

ERd (left rotatio n through carry flag) → ERd

Assembly-Language Format

ROTXL.L ERd

Operand Size

Longword

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 31.

Description

This instructio n rotates the bits in a 32-bit register ERd (destination operand) one bit to the left

through the carry flag. The carry flag is rotated into the least signif ican t bit (bit 0). The most

significant b it ( bit 31) rotates into the carry f lag.

MSB LSB

C b31 b0

. . . . . .

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 188 of 322

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2.2.53 (6) ROTXL (L)

ROTXL (ROTate with eXtend carry Left) Rotate through Carry

Operation

ERd (left rotation through carry flag) → ERd

Assembly-Language Format

ROTXL.L #2, ERd

Operand Size

Longword

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 30.

Description

This instructio n rotates the bits in a 32-bit register ERd (destination operand) two bits to the left

through th e carry f lag. The carry flag rotates in to bit 1, bit 31 rotates into bit 0, and bit 30 rotates

into into th e carry flag.

MSB LSB

C b31 b0

. . . . . .

b1b30

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 189 of 322

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2.2.54 (1) ROTXR (B)

ROTXR (ROTate with eXtend carry Right) Rotate through Carry

Operation

Rd (right rotation through carry flag) → Rd

Assembly-Language Format

ROTXR.B Rd

Operand Size

Byte

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 0.

Description

This instructio n rotates the bits in an 8-bit register Rd (destination operand) one bit to the right

through the carry f lag. The carry flag is rotated into the most significant b it ( bit 7). The least

significant b it ( bit 0) rotates into the carry flag.

LSBMSB

b7 b0

. . . . . .

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 190 of 322

REJ09B0139-0400

2.2.54 (2) ROTXR (B)

ROTXR (ROTate with eXtend carry Right) Rotate through Carry

Operation

Rd (right rotation through carry flag) → Rd

Assembly-Language Format

ROTXR.B #2, Rd

Operand Size

Byte

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 1.

Description

This instruction rotates the b its in an 8-bit register Rd ( destination operand) two bits to the right

through th e carry flag. The carry flag rotates into bit 6, bit 0 r otates into bit 7, and bit 1 ro tates into

the carry flag.

LSBMSB

b7 b0

. . . .

C b1b6

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 191 of 322

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2.2.54 (3) ROTXR (W)

ROTXR (ROTate with eXtend carry Right) Rotate through Carry

Operation

Rd (right rotation through carry flag) → Rd

Assembly-Language Format

ROTXR.W Rd

Operand Size

Word

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 0.

Description

This instructio n rotates the bits in a 16-bit register Rd (destination operand) one bit to the right

through the carry f lag. The carry flag is ro tated into th e most sig nificant bit (bit 15). The least

significant b it ( bit 0) rotates into the carry flag.

LSBMSB

b15 b0

. . . . . .

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 192 of 322

REJ09B0139-0400

2.2.54 (4) ROTXR (W)

ROTXR (ROTate with eXtend carry Right) Rotate through Carry

Operation

Rd (right rotation through carry flag) → Rd

Assembly-Language Format

ROTXR.W #2, Rd

Operand Size

Word

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 1.

Description

This instruction rotates the b its in a 16-bit register Rd ( destination operand) two bits to the right

through the carry f lag. The carry flag rotates into bit 14, bit 0 rotates into bit 15, and bit 1 rotates

into the carry flag.

LSBMSB

b15 b0

. . . .

C b1b14

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 193 of 322

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2.2.54 (5) ROTXR (L)

ROTXR (ROTate with eXtend carry Right) Rotate through Carry

Operation

ERd (right ro tation through carry flag) → ERd

Assembly-Language Format

ROTXR.L ERd

Operand Size

Longword

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 0.

Description

This instructio n rotates the bits in a 32-bit register ERd (destination operand) one bit to the right

through the carry f lag. The carry flag is ro tated into th e most sig nificant bit (bit 31). The least

significant b it ( bit 0) rotates into the carry flag.

LSBMSB

b31 b0

. . . . . .

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 194 of 322

REJ09B0139-0400

2.2.54 (6) ROTXR (L)

ROTXR (ROTate with eXtend carry Right) Rotate through Carry

Operation

ERd (right ro tation through carry flag) → ERd

Assembly-Language Format

ROTXR.L #2, ERd

Operand Size

Longword

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 1.

Description

This instructio n rotates the bits in a 32-bit register ERd (destination operand) two bits to the right

through the carry f lag. The carry flag rotates into bit 30, bit 0 rotates into bit 31, and bit 1 rotates

into the carry flag.

LSBMSB

b31 b0

. . . .

C b1b30

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 195 of 322

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2.2.55 RTE

RTE (ReTurn fr om Exception) Return from Exception Handling

Operation

• When EXR is inva lid

@SP+ → CCR

@SP+ → PC

• When EXR is valid

@SP+ → EXR

@SP+ → CCR

@SP+ → PC

Assembly-Language Format

RTE

Operand Size

—

Condition Code

↔

UIHUNZVC

I: Restored from the corresponding bit on

the stack.

UI: Restored from the corresponding bit on

the stack.

H: Restored from the corresponding bit on

the stack.

U: Restored from the corresponding bit on

the stack.

N: Restored from the corresponding bit on

the stack.

Z: Restored from the corresponding bit on

the stack.

V: Restored from the corresponding bit on

the stack.

C: Restored from the corresponding bit on

the stack.

Description

This instructio n returns fro m an ex ceptio n-handling routine b y restoring the EXR, cond ition-code

address restored to the program counter. The CCR and PC contents at the time of execution of this

instruction are lost. If the extended control regiser (EXR) is valid, it is also restored (and the

existing EXR contents are lost).

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

—RTE 5670 5*

Note: *Six states when EXR is valid.

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 196 of 322

REJ09B0139-0400

RTE (ReTurn fr om Exception) Return from Exception Handling

Notes

The stack structure differs between normal mode and advanced mode.

PC 23 16 15 8 7 0

Normal mode

Don’t care CCR

PC 23 16 15 8 7 0

Advanced mode

CCR

Undet.

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 197 of 322

REJ09B0139-0400

2.2.56 RTS

RTS (ReTurn fro m Subroutine) Return from Subrout ine

Operation

@SP+ → PC

Assembly-Language Format

RTS

Operand Size

—

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction returns from a subroutine by restoring the program counter (PC) from the stack.

Program execution continues from the address restored to the program counter. The PC contents at

the time of ex ecutio n of this instruction are lost.

Operand Format and Number of States Required for Execution

Instruction Format No. of States

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte Normal Advanced

— RTS 5470 4 5

Notes

The stack structure and number of states required for execution differ between normal mode an d

advanced mode. In normal mode, only the lower 16 bits of the program counter are restored.

PC 23 16 15 8 7 0

Normal mode PC 23 16 15 8 7 0

Advanced mode

Undet.

Don’t care

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 198 of 322

REJ09B0139-0400

2.2.57 (1) SHAL (B)

SHAL (SHift Arithmetic Left) Shift Arithmetic

Operation

Rd (left arith metic shift) → Rd

Assembly-Language Format

SHAL.B Rd

Operand Size

Byte

Condition Code

↔

————

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Receives the previous value in bit 7.

Description

This instruction shifts the b its in an 8-bit register Rd (destination operand) one bit to the left. The

most significant bit (bit 7) shifts into the carry flag. The least sign if ican t bit (bit 0) is cleared to 0.

LSBMSB

b7 b0

. . . . . .

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

The SHAL instruction differs from the SHLL instruction in its effect on th e overflow flag.

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 199 of 322

REJ09B0139-0400

2.2.57 (2) SHAL (B)

SHAL (SHift Arithmetic Left) Shift Arithmetic

Operation

Rd (left arith metic shift) → Rd

Assembly-Language Format

SHAL.B #2, Rd

Operand Size

Byte

Condition Code

↔

————

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Receives the previous value in bit 6.

Description

This instruction shifts the bits in an 8-bit register Rd (destination operand) two bits to the left. Bit

6 shifts into the carry flag. Bits 0 and 1 are cleared to 0.

LSBMSB

b7 b0

. . . . . .

b1b6

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

The SHAL instruction differs from the SHLL instruction in its effect on th e overflow flag.

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 200 of 322

REJ09B0139-0400

2.2.57 (3) SHAL (W)

SHAL (SHift Arithmetic Left) Shift Arithmetic

Operation

Rd (left arith metic shift) → Rd

Assembly-Language Format

SHAL.W Rd

Operand Size

Word

Condition Code

↔

————

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Receives the previous value in bit 15.

Description

This instruction shifts the b its in a 16-bit register Rd (destination operand) one bit to the left. The

most signif ican t bit (bit 15) shif ts into the carry flag. The least significant bit (bit 0) is cleared to 0.

LSBMSB

b15 b0

. . . . . .

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

The SHAL instruction differs from the SHLL instruction in its effect on th e overflow flag.

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 201 of 322

REJ09B0139-0400

2.2.57 (4) SHAL (W)

SHAL (SHift Arithmetic Left) Shift Arithmetic

Operation

Rd (left arith metic shift) → Rd

Assembly-Language Format

SHAL.W #2, Rd

Operand Size

Word

Condition Code

↔

————

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Receives the previous value in bit 14.

Description

This instruction shifts the bits in a 16-bit register Rd (destination operand) two b its to the left. Bit

14 shifts into the carry flag . Bits 0 and 1 are cleared to 0.

LSBMSB

b15 b0

. . . . . .

b1b14

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

The SHAL instruction differs from the SHLL instruction in its effect on th e overflow flag.

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 202 of 322

REJ09B0139-0400

2.2.57 (5) SHAL (L)

SHAL (SHift Arithmetic Left) Shift Arithmetic

Operation

ERd (left arith metic shift) → ERd

Assembly-Language Format

SHAL.L ERd

Operand Size

Longword

Condition Code

↔

————

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Receives the previous value in bit 31.

Description

This instruction shifts the b its in a 32-bit register ERd (destination operand) one bit to the left. The

most signif ican t bit (bit 31) shif ts into the carry flag. The least significant bit (bit 0) is cleared to 0.

LSBMSB

b31 b0

. . . . . .

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

The SHAL instruction differs from the SHLL instruction in its effect on th e overflow flag.

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 203 of 322

REJ09B0139-0400

2.2.57 (6) SHAL (L)

SHAL (SHift Arithmetic Left) Shift Arithmetic

Operation

ERd (left arith metic shift) → ERd

Assembly-Language Format

SHAL.L #2, ERd

Operand Size

Longword

Condition Code

↔

————

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Receives the previous value in bit 30.

Description

This instruction shifts the bits in a 32-bit register ERd (destination operand) two b its to the left.

Bit 30 shifts in to the carry flag. Bits 0 an d 1 are cleared to 0.

LSBMSB

b31 b0

. . . . . .

b1b30

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

The SHAL instruction differs from the SHLL instruction in its effect on th e overflow flag.

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 204 of 322

REJ09B0139-0400

2.2.58 (1) SHAR (B)

SHAR (SHift Arithmetic Right) Shift Arithmetic

Operation

Rd (right arithmetic shift) → Rd

Assembly-Language Format

SHAR.B Rd

Operand Size

Byte

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 0.

Description

This instruction shifts the bits in an 8-bit register Rd (destination operand) one bit to th e righ t. Bit

0 shifts into the carry flag. Bit 7 sh ifts into itself. Since bit 7 rema ins unaltered, th e sign does not

change.

LSB

b7 b0

. . . . . .

MSB

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 205 of 322

REJ09B0139-0400

2.2.58 (2) SHAR (B)

SHAR (SHift Arithmetic Right) Shift Arithmetic

Operation

Rd (right arithmetic shift) → Rd

Assembly-Language Format

SHAR.B #2, Rd

Operand Size

Byte

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 1.

Description

This instruction shifts the bits in an 8-bit register Rd (destination operand) two bits to the right. Bit

1 shifts into the carry flag. Bits 7 and 6 receive the previous value of bit 7. Since bit 7 remains

unaltered, the sign does not change.

LSB

b7 b0

. . .

MSB

b1b5b6

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 206 of 322

REJ09B0139-0400

2.2.58 (3) SHAR (W)

SHAR (SHift Arithmetic Right) Shift Arithmetic

Operation

Rd (right arithmetic shift) → Rd

Assembly-Language Format

SHAR.W Rd

Operand Size

Word

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 0.

Description

This instruction shifts the bits in a 16-bit register Rd (destination operand) on e bit to the right. Bit

0 shifts into the carry flag. Bit 15 shifts into itself. Since bit 15 remains unaltered, th e sign does

not change.

LSB

b15 b0

. . . . . .

MSB

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 207 of 322

REJ09B0139-0400

2.2.58 (4) SHAR (W)

SHAR (SHift Arithmetic Right) Shift Arithmetic

Operation

Rd (right arithmetic shift) → Rd

Assembly-Language Format

SHAR.W #2, Rd

Operand Size

Word

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 1.

Description

This instruction shifts the bits in a 16-bit register Rd (destination operand) two b its to the right. Bit

1 shifts into the carry flag. Bits 15 and 14 receive the previous value of bit 15. Since bit 15

remains unaltered, the sign does not change.

LSB

b15 b0

. . .

MSB

b1b13b14

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 208 of 322

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2.2.58 (5) SHAR (L)

SHAR (SHift Arithmetic Right) Shift Arithmetic

Operation

ERd (righ t arithmetic shift) → ERd

Assembly-Language Format

SHAR.L ERd

Operand Size

Longword

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 0.

Description

This instruction shifts the bits in a 32-bit register ERd (destination operand) one bit to th e righ t.

Bit 0 shifts into the carry f lag. Bit 3 1 shifts into itself . Since bit 31 remains unaltered, the sign

does not change.

LSB

b31 b0

. . . . . .

MSB

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 209 of 322

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2.2.58 (6) SHAR (L)

SHAR (SHift Arithmetic Right) Shift Arithmetic

Operation

ERd (righ t arithmetic shift) → ERd

Assembly-Language Format

SHAR.L #2, ERd

Operand Size

Longword

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 1.

Description

This instruction shifts the bits in a 32-bit register ERd (destination operand) two b its to the right.

Bit 1 shifts into the carry flag. Bits 31 and 30 receive the previous value of bit 31. Since bit 31

remains unaltered, the sign does not change.

LSB

b31 b0

. . .

MSB

b1b29b30

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

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2.2.59 (1) SHLL (B)

SHLL (SHift Logical Left) Shift Logical

Operation

Rd (left logical shift) → Rd

Assembly-Language Format

SHLL.B Rd

Operand Size

Byte

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 7.

Description

This instruction shifts the b its in an 8-bit register Rd (destination operand) one bit to the left. The

most significant bit (bit 7) shifts into the carry flag. The least sign if ican t bit (bit 0) is cleared to 0.

LSBMSB

b7 b0

. . . . . .

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

The SHLL instruction differs from the SHAL instruction in its effect on the overflow flag.

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2.2.59 (2) SHLL (B)

SHLL (SHift Logical Left) Shift Logical

Operation

Rd (left logical shift) → Rd

Assembly-Language Format

SHLL.B #2, Rd

Operand Size

Byte

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 6.

Description

This instruction shifts the bits in an 8-bit register Rd (destination operand) two bits to the left. Bit

6 shifts into the carry flag. Bits 0 and 1 are cleared to 0.

LSBMSB

b7 b0

. . . .

b6 b1

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

The SHLL instruction differs from the SHAL instruction in its effect on the overflow flag.

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2.2.59 (3) SHLL (W)

SHLL (SHift Logical Left) Shift Logical

Operation

Rd (left logical shift) → Rd

Assembly-Language Format

SHLL.W Rd

Operand Size

Word

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 15.

Description

This instruction shifts the b its in a 16-bit register Rd (destination operand) one bit to the left. The

most signif ican t bit (bit 15) shif ts into the carry flag. The least significant bit (bit 0) is cleared to 0.

LSBMSB

b15 b0

. . . . . .

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

The SHLL instruction differs from the SHAL instruction in its effect on the overflow flag.

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2.2.59 (4) SHLL (W)

SHLL (SHift Logical Left) Shift Logical

Operation

Rd (left logical shift) → Rd

Assembly-Language Format

SHLL.W #2, Rd

Operand Size

Word

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 14.

Description

This instruction shifts the bits in a 16-bit register Rd (destination operand) two b its to the left. Bit

14 shifts into the carry flag . Bits 0 and 1 are cleared to 0.

LSBMSB

b15 b0

. . . .

b14 b1

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

The SHLL instruction differs from the SHAL instruction in its effect on the overflow flag.

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2.2.59 (5) SHLL (L)

SHLL (SHift Logical Left) Shift Logical

Operation

ERd (left log ical shift) → ERd

Assembly-Language Format

SHLL.L ERd

Operand Size

Longword

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 31.

Description

This instruction shifts the b its in a 32-bit register ERd (destination operand) one bit to the left. The

most signif ican t bit (bit 31) shif ts into the carry flag. The least significant bit (bit 0) is cleared to 0.

LSBMSB

b31 b0

. . . . . .

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

The SHLL instruction differs from the SHAL instruction in its effect on the overflow flag.

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2.2.59 (6) SHLL (L)

SHLL (SHift Logical Left) Shift Logical

Operation

ERd (left log ical shift) → ERd

Assembly-Language Format

SHLL.L #2, ERd

Operand Size

Longword

Condition Code

↔

———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 30.

Description

This instruction shifts the bits in a 32-bit register ERd (destination operand) two b its to the left.

Bit 30 shifts in to the carry flag. Bits 0 an d 1 are cleared to 0.

LSBMSB

b31 b0

. . . .

b30 b1

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

The SHLL instruction differs from the SHAL instruction in its effect on the overflow flag.

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2.2.60 (1) SHLR (B)

SHLR (SHift Logical Right) Shift Logical

Operation

Rd (right logical shift) → Rd

Assembly-Language Format

SHLR.B Rd

Operand Size

Byte

Condition Code

↔

0———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Always cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 0.

Description

This instruction shifts the bits in an 8-bit register Rd (destination operand) one bit to th e righ t. The

least significant b it ( bit 0) shifts in to the carry flag. The most sign if icant bit (bit 7) is cleared to 0.

. . . . . .

LSBMSB

b7 b0

0. . . . . .

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

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2.2.60 (2) SHLR (B)

SHLR (SHift Logical Right) Shift Logical

Operation

Rd (right logical shift) → Rd

Assembly-Language Format

SHLR.B #2, Rd

Operand Size

Byte

Condition Code

↔

0———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Always cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 1.

Description

This instruction shifts the bits in an 8-bit register Rd (destination operand) two bits to the right. Bit

1 shifts into the carry flag. Bits 7 and 6 are cleared to 0.

. . . . . .

LSBMSB

b7 b0

0. . . . . .

Cb6 b1

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

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2.2.60 (3) SHLR (W)

SHLR (SHift Logical Right) Shift Logical

Operation

Rd (right logical shift) → Rd

Assembly-Language Format

SHLR.W Rd

Operand Size

Word

Condition Code

↔

0———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Always cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 0.

Description

This instruction shifts the bits in a 16-bit register Rd (destination operand) one bit to th e righ t. The

least significant b it ( bit 0) shifts in to the carry flag. The most sign if icant bit (bit 15) is cleared to 0.

. . . . . .

LSBMSB

b15 b0

0. . . . . .

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

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2.2.60 (4) SHLR (W)

SHLR (SHift Logical Right) Shift Logical

Operation

Rd (right logical shift) → Rd

Assembly-Language Format

SHLR.W #2, Rd

Operand Size

Word

Condition Code

↔

0———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Always cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 1.

Description

This instruction shifts the bits in a 16-bit register Rd (destination operand) two b its to the right. Bit

1 shifts into the carry flag. Bits 15 and 14 are cleared to 0.

. . . . . .

LSBMSB

b15 b0

0. . . . . .

Cb14 b1

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

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2.2.60 (5) SHLR (L)

SHLR (SHift Logical Right) Shift Logical

Operation

ERd (right logical shift) → ERd

Assembly-Language Format

SHLR.L ERd

Operand Size

Longword

Condition Code

↔

0———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Always cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 0.

Description

This instruction shifts the bits in a 32-bit register ERd (destination operand) one bit to th e righ t.

The least significant bit (bit 0) shifts into th e carry flag. The most significant bit (bit 31) is cleared

to 0.

. . . . . .

LSBMSB

b31 b0

0. . . . . .

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

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2.2.60 (6) SHLR (L)

SHLR (SHift Logical Right) Shift Logical

Operation

ERd (right logical shift) → ERd

Assembly-Language Format

SHLR.L #2, ERd

Operand Size

Longword

Condition Code

↔

0———— 0

UIHUNZVC

H: Previous value remains unchanged.

N: Always cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Receives the previous value in bit 1.

Description

This instruction shifts the bits in a 32-bit register ERd (destination operand) two b its to the right.

Bit 1 shifts into the carry flag. Bits 31 and 30 are cleared to 0.

. . . . . .

LSBMSB

b31 b0

0. . . . . .

Cb30 b1

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

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2.2.61 SLEEP

SLEEP ( SLEEP ) Powe r-Dow n Mode

Operation

Program execution state → power-down mode

Assembly-Language Format

SLEEP

Operand Size

—

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

When the SLEEP instruction is executed, the CPU enters a power-down mode. Its internal state

remains unchanged, but the CPU stops executing instructions and waits for an exception-handling

request. When it receives an exception-handling request, the CPU exits the power-down mode and

begins the exception-handling sequence. Interrupt requests other than NMI cannot end the power-

down mode if they are masked in the CPU.

Available Registers

—

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

—SLEEP 0180 2

Notes

For information about power-down modes, see the relevant microcontroller hardware manual.

Section 2 Instruction Descriptions

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2.2.62 (1) STC (B)

STC (STore from Control register) Store CCR

Operation

CCR → Rd

Assembly-Language Format

STC.B CCR, Rd

Operand Size

Byte

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction copie s the CCR con te nts to an 8-bit register Rd.

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

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2.2.62 (2) STC (B)

STC (STore from Control register) Store EXR

Operation

EXR → Rd

Assembly-Language Format

STC.B EXR, Rd

Operand Size

Byte

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction copies the EXR contents to an 8-bit register Rd.

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

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2.2.62 (3) STC (W)

STC (STore from Control register) Store CCR

Operation

CCR → (EAd)

Assembly-Language Format

STC.W CCR, < EAd>

Operand Size

Word

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction copies the CCR contents to a destination locatio n. Although CCR is a byte

address. Undetermined data is stored at the odd address.

Available Registers

ERd: ER0 to ER7

Section 2 Instruction Descriptions

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STC (STore from Control register) Store CCR

Operand Format and Number of States Required for Execution

Notes

Addressing Mnemonic Operands Instruction Format No. of

Mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte States

STC.W CCR, @ERd 0140691erd0 3

STC.W CCR, @(d:16, ERd) 01406F1erd0 disp 4

STC.W CCR, @(d:32, ERd) 0140780erd06BA0 disp 6

STC.W CCR, @–ERd 01406D1erd0 4

STC.W CCR, @aa:16 01406B80 abs 4

STC.W CCR, @aa:32 01406BA0 abs 5

indirect

indirect with

displace-

ment

indirect

with pre-

decrement

Absolute

address

Section 2 Instruction Descriptions

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2.2.62 (4) STC (W)

STC (STore from Control register) Store EXR

Operation

EXR → (EAd)

Assembly-Language Format

STC.W EXR, <EAd>

Operand Size

Word

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction copies the EXR contents to a destinatio n location. Although EXR is a byte

address. Undetermined data is stored at the odd address.

Available Registers

ERd: ER0 to ER7

Section 2 Instruction Descriptions

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STC (STore from Control register) Store EXR

Operand Format and Number of States Required for Execution

Notes

Addressing Mnemonic Operands Instruction Format No. of

Mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte States

STC.W EXR, @ERd 0141691erd0 3

STC.W EXR, @(d:16, ERd) 01416F1erd0 disp 4

STC.W EXR, @(d:32, ERd) 0141780erd06BA0 disp 6

STC.W EXR, @–ERd 01416D1erd0 4

STC.W EXR, @aa:16 01416B80 abs 4

STC.W EXR, @aa:32 01416BA0 abs 5

indirect

indirect with

displace-

ment

indirect

with pre-

decrement

Absolute

address

Section 2 Instruction Descriptions

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2.2.63 STM

STM (STore from Multiple registers) Store Data on Stack

Operation

ERn (register list) → @–SP

Assembly-Language Format

STM.L <register list>, @–SP

Operand Size

Longword

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction saves a group of registers specified by a register list onto the stack. The registers

are saved in ascending order of register number.

Two, three, or four registers can be saved by one STM instruction. The following ranges can be

specified in the register list.

Two registers: ER0–ER1, ER2–ER3, ER4–ER5, or ER6–ER7

Three registers: ER0–ER2 or ER4–ER6

Four registers: ER0–ER3 or ER4–ER7

Available Registers

ERn: ER0 to ER7

Section 2 Instruction Descriptions

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STM (STore from Multiple registers) Store Data on Stack

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3r d byt e 4th byte

No. of

States

—STM.L (ERn–ERn+1),

@–SP 01106DF0ern7

—STM.L (ERn–ERn+2),

@–SP 01206DF0ern9

—STM.L (ERn–ERn+3),

@–SP 01306DF0ern11

Notes

When ER7 is saved, the value after effective address calculation (after ER7 is decremented by 4)

is saved on the stack.

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2.2.64 STMAC

STMAC (STore from MAC register) Store Data from MAC Register

Operation

MACH → ERd

MACL → ERd

Assembly-Language Format

STMAC MAC register, ERd

Operand Size

Longword

Condition Code

↔

***

—————

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if a MAC instruction resulted in a

negative MAC register value; otherwise

cleared to 0.

Z: Set to 1 if a MAC instruction resulted in a

zero MAC register value; otherwise

cleared to 0.

V: Set to 1 if a MAC instruction r e sulted in

an overflow; otherwise cleared to 0.

C: Previous value remains unchanged.

Note: * E xecution of this instru ction copies the N, Z,

and V flag values from the multiplier to the

condition-code register (CCR). If the STMAC

instr u cti o n is exe cuted after a CLRMAC or

LDMAC instruction with no intervening MAC

instr u cti o n, the V flag w ill be 0 and the N an d Z

flags will have undetermined values.

Description

This instruction moves the contents of a multiply-accumulate register (MACH or MACL) to a

general register. If the transfer is from MACH, the upper 22 bits transferred to the general register

are a sign extension.

This instruction is supported by the H8S/2600 CPU only.

Available Registers

ERd: ER0 to ER7

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STMAC (STore from MAC register) Store Data from MAC Register

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Note: *A maximum of three additional states are required for executi on of this inst ruct i on withi n three st ates

after execution of a MAC instruct i on. For example, if there is a one-state i nst ruction (such as NOP)

between the MAC instruct i on and this i nst ruction, this instructi on will be two stat es longer.

The number of states may differ depending on the product. For details, refer to the relevant

microcontrol l er hardware manual of the product in question.

Notes

Section 2 Instruction Descriptions

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2.2.65 (1) SUB (B)

SUB (SUBtra c t binary) Subtract Binary

Operation

Rd – Rs → Rd

Assembly-Language Format

SUB.B Rs, Rd

Operand Size

Byte

Condition Code

↔

———

UIHUNZVC

H: Set to 1 if th er e is a bor row at b it 3;

otherwise cleared to 0.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a borrow at bit 7;

otherwise cleared to 0.

Description

This instruction subtracts the contents of an 8-bit register Rs (source operand) from the contents of

an 8-bit r egister Rd (destination operand) and stores the result in the 8- bit register Rd.

Available Registers

Rd: R0L to R7 L, R0H to R7H

Rs: R0L to R7L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

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SUB (SUBtra c t binary) Subtract Binary

Notes

The SUB.B instruction can operate only on general registers. Immediate data can be subtracted

from general register contents by using the SUBX instruction. Before executing SUBX #xx:8, Rd,

first set the Z flag to 1 and clear the C flag to 0. The following coding examples can also be used

to subtract nonzero immediate data #IMM.

(1) ORC #H'05,CCR

SUBX #(IMM-1),Rd

(2) ADD #(0-IMM),Rd

XORC #H'01,CCR

Section 2 Instruction Descriptions

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2.2.65 (2) SUB (W)

SUB (SUBtra c t binary) Subtract Binary

Operation

Rd – (EAs) → Rd

Assembly-Language Format

SUB.W <EAs>, Rd

Operand Size

Word

Condition Code

↔

———

UIHUNZVC

H: Set to 1 if th er e is a bor row at b it 11;

otherwise cleared to 0.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a borrow at bit 15;

otherwise cleared to 0.

Description

This instruction subtracts a source operand from the contents of a 16-bit register Rd (destination

operand) and stores the re sult in the 16-bit register Rd.

Available Registers

Rd: R0 to R7, E0 to E7

Rs: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Immedi ate S UB .W #x x:16, Rd 7 9 3 rd IMM 2

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 236 of 322

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2.2.65 (3) SUB (L)

SUB (SUBtra c t binary) Subtract Binary

Operation

ERd – (EAs) → ERd

Assembly-Language Format

SUB.L <EAs>, ERd

Operand Size

Longword

Condition Code

↔

———

UIHUNZVC

H: Set to 1 if th er e is a bor row at b it 27;

otherwise cleared to 0.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a borrow at bit 31;

otherwise cleared to 0.

Description

This instruction subtracts a source operand from the contents of a 32-bit register ERd (destination

operand) and stores the result in the 32-bit register ERd.

Available Registers

ERd: ER0 to ER7

ERs: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte

No. of

States

Immediate SUB.L #xx:32, ERd 7 A 3 0 erd IMM 3

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 237 of 322

REJ09B0139-0400

2.2.66 SUBS

SUBS (SUBtract with Sign ext ension) Subtract Binary Address Data

Operation

Rd – 1 → ERd

Rd – 2 → ERd

Rd – 4 → ERd

Assembly-Language Format

SUBS #1, ERd

SUBS #2, ERd

SUBS #4, ERd

Operand Size

Longword

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instruction subtracts the immediate value 1, 2, or 4 from the contents of a 32-bit register ERd

(destination operand). Unlike the SUB instruction, it does not affect the condition-code flags.

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 238 of 322

REJ09B0139-0400

2.2.67 SUBX

SUBX (SUBtract wit h eXt e nd ca rry) Subt ract with Borrow

Operation

Rd – (EAs) – C → Rd

Assembly-Language Format

SUBX <EAs>, Rd

Operand Size

Byte

Condition Code

↔

———

UIHUNZVC

H: Set to 1 if th er e is a bor row at b it 3;

otherwise cleared to 0.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Previous value remains unchang ed when

the result is zero; otherwise cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a borrow at bit 7;

otherwise cleared to 0.

Description

This instruction subtracts the source operand and carry flag from the contents of an 8-bit register

Rd (destination operand) and stores th e result in the 8-bit reg ister Rd.

Available Registers

Rd: R0L to R7 L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Immedi ate SUBX #xx:8, Rd B rd IMM 1

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 239 of 322

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2.2.68 TAS

TAS (Test And Set ) Test and Set

Operation

@ERd – 0 → set/clear CCR

1 → (<bit 7> of @ERd)

Assembly-Language Format

TAS @ERd

Operand Size

Byte

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instructio n tests a memory ope r a nd by co mpar ing it with zero, and sets the co n dition-code

Available Registers

ERd: ER0, ER1, ER4, ER5

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 240 of 322

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2.2.69 TRAPA

TRAPA (TRAP Always) Trap Unconditionally

Operation

• When EXR is inva lid

PC → @–SP

CCR → @–SP

<Vector> → PC

• When EXR is valid

PC → @–SP

CCR → @–SP

EXR → @–SP

<Vector> → PC

Assembly-Language Format

TRAPA #x:2

Operand Size

—

Condition Code

————*1 ——

UIHUNZVC

I: Always set to 1.

UI: See note.

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Note: * T he UI bit is se t to 1 when used as an interrupt

mask bit, but retains its previous value wh en

used as a u ser bit. For de tails, see th e r elevant

micr ocontroller hardware manu al.

Description

This instruction pushes the program counter (PC) and condition-code register (CCR) onto the

stack, then sets the I bit to 1. If the extended control r egister (E XR) is valid, EXR is also save d

onto the stack, but bits I2 to I0 are no t modified. Next execution branches to a new address given

by the contents of the vector address corresponding to the specified vector number. The PC value

pushed onto the stack is the starting address of the next instruction after the TRAPA instruction.

Vector Address

#x Normal Mode Advanced Mode

0 H'0010 to H'0011 H'000020 t o H' 000023

1 H'0012 to H'0013 H'000024 t o H' 000027

2 H'0014 to H'0015 H'000028 t o H' 00002B

3 H'0016 to H'0017 H'00002C to H'00002F

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 241 of 322

REJ09B0139-0400

TRAPA (TRAP Always) Trap Unconditionally

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No. o f

States

Note: *Eight states when EXR is valid.

Notes

The stack and vector structure differ between normal mode and advanced mode, and depending on

whether EXR is va lid or invalid.

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 242 of 322

REJ09B0139-0400

2.2.70 (1) XOR (B)

XOR (eXclusive O R logical) Exclusive Logical OR

Operation

Rd ⊕ (EAs) → Rd

Assembly-Language Format

XOR.B <EAs>, Rd

Operand Size

Byte

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction exclusively ORs the source operand with the contents of an 8-bit register Rd

(destination operand) and stores the result in the 8-bit reg ister Rd.

Available Registers

Rd: R0L to R7 L, R0H to R7H

Rs: R0L to R7L, R0H to R7H

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Immedi ate X OR.B #xx:8, Rd D rd IM M 1

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 243 of 322

REJ09B0139-0400

2.2.70 (2) XOR (W)

XOR (eXclusive O R logical) Exclusive Logical OR

Operation

Rd ⊕ (EAs) → Rd

Assembly-Language Format

XOR.W <EAs>, Rd

Operand Size

Word

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction exclusively ORs the source operand with the contents of a 16-bit register Rd

(destination operand) and stores the result in the 16-bit register Rd.

Available Registers

Rd: R0 to R7, E0 to E7

Rs: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Immedi ate X OR.W #x x:16, Rd 7 9 5 rd IM M 2

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 244 of 322

REJ09B0139-0400

2.2.70 (3) XOR (L)

XOR (eXclusive O R logical) Exclusive Logical OR

Operation

ERd ⊕ (EAs) → ERd

Assembly-Language Format

XOR.L <EAs>, ERd

Operand Size

Longword

Condition Code

↔

———— 0 —

UIHUNZVC

H: Previous value remains unchanged.

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zer o; otherwise

cleared to 0.

V: Always cleared to 0.

C: Previous value remains unchanged.

Description

This instruction exclusively ORs the source operand with the contents of a 32-bit register ERd

(destination operand) and stores the result in the 32-bit register ERd.

Available Registers

ERd: ER0 to ER7

ERs: ER0 to ER7

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte

No. of

States

Immediate XOR.L #xx:32, ERd 7 A 5 0 erd IMM 3

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 245 of 322

REJ09B0139-0400

2.2.71 (1) XORC

XORC (eXclusive OR Control register) Exclusive Logical OR with CCR

Operation

CCR ⊕ #IMM → CCR

Assembly-Language Format

XORC #xx:8, CCR

Operand Size

Byte

Condition Code

↔

UIHUNZVC

I: Stores the corresponding bit of the result.

UI: Stor e s the corresp onding bit of the resu lt.

H: Stores the corresponding bit of the result.

U: Stores the corresponding bit of the result.

N: Stores the corresponding bit of the result.

Z: Stores the corresponding bit of the result.

V: Stores the corresponding bit of the result.

C: Stores the corresponding bit of the result.

Description

This instr uction e xclusivel y ORs the contents of th e c ondition-code register (CCR) with

immediate da ta and stores the result in the condition-code register. No interrupt requests,

including NMI, are accepted immediately after execution of this instruction.

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Immediate XORC #xx:8, CCR 0 5 IMM 1

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 246 of 322

REJ09B0139-0400

2.2.71 (2) XORC

XORC (eXclusive OR Control register) Exclusive Logical OR with EXR

Operation

EXR ⊕ #IMM → EXR

Assembly-Language Format

XORC #xx:8, EXR

Operand Size

Byte

Condition Code

————————

UIHUNZVC

H: Previous value remains unchanged.

N: Previous value remains unchanged.

Z: Previous value remains unchanged.

V: Previous value remains unchanged.

C: Previous value remains unchanged.

Description

This instructio n exclusively ORs th e contents of the extended contr ol register (EXR) with

immediate data and stores the result in the extended control register. No interrupt requests,

including NMI, are accepted for three states after execution of this instruction.

Operand Format and Number of States Required for Execution

Instruction Format

Addressing

Mode Mnemonic Operands 1st byte 2nd byte 3rd byte 4th byte No . of

States

Immediate XORC#xx:8, EXR014105 IMM 2

Notes

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 247 of 322

REJ09B0139-0400

2.3 Instruction Set

Table 2.1 Instruction Set

(1) Data Transfer Instructions

Addressing Mode and Instruction Length (Bytes)

Mnemonic Size Operation Condition Code

IHNZVC

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

MOV MOV.B #xx:8,Rd B 2 #xx:8→Rd8 — — 0 — 1

MOV.B Rs,Rd B 2 Rs8→Rd8 — — 0 — 1

MOV.B @ERs,Rd B 2 @ERs→Rd8 — — 0 — 2

MOV.B @(d:16, ERs), Rd B 4 @(d:16,ERs)→Rd8 — — 0 — 3

MOV.B @(d:32,ERs),Rd B 8 @(d:32,ERs)→Rd8 — — 0 — 5

MOV.B @ERs+,Rd B 2 @ERs→Rd8,ERs32+1→ERs32 — — 0 — 3

MOV.B @aa:8,Rd B 2 @aa:8→Rd8 — — 0 — 2

MOV.B @aa:16,Rd B 4 @aa:16→Rd8 — — 0 — 3

MOV.B @aa:32,Rd B 6 @aa:32→Rd8 — — 0 — 4

MOV.B Rs,@ERd B 2 Rs8→@ERd — — 0 — 2

MOV.B Rs,@(d:16,ERd) B 4 Rd8→@(d:16,ERd) — — 0 — 3

MOV.B Rs,@(d:32,ERd) B 8 Rd8→@(d:32,ERd) — — 0 — 5

MOV.B Rs,@–ERd B 2 ERd32–1→ERd32,Rs8→@ERd — — 0 — 3

MOV.B Rs,@aa:8 B 2 Rs8→@aa:8 — — 0 — 2

MOV.B Rs,@aa:16 B 4 Rs8→@aa:16 — — 0 — 3

MOV.B Rs,@aa:32 B 6 Rs8→@aa:32 — — 0 — 4

MOV.W #xx:16,Rd W 4 #xx:16→Rd16 — — 0 — 2

MOV.W Rs,Rd W 2 Rs16→Rd16 — — 0 — 1

MOV.W @ERs,Rd W 2 @ERs→Rd16 — — 0 — 2

MOV.W @(d:16,ERs),Rd W 4 @(d:16,ERs)→Rd16 — — 0 — 3

MOV.W @(d:32,ERs),Rd W 8 @(d:32,ERs)→Rd16 — — 0 — 5

MOV.W @ERs+,Rd W 2 @ERs→Rd16,ERs32+2→@ERs32 — — 0 — 3

MOV.W @aa:16,Rd W 4 @aa:16→Rd16 — — 0 — 3

MOV.W @aa:32,Rd W 6 @aa:32→Rd16 — — 0 — 4

MOV.W Rs,@ERd W 2 Rs16→@ERd — — 0 — 2

MOV.W Rs,@(d:16,ERd) W 4 Rs16→@(d:16,ERd) — — 0 — 3

MOV.W Rs,@(d:32,ERd) W 8 Rs16→@(d:32,ERd) — — 0 — 5

MOV.W Rs,@–ERd W 2 ERd32–2→ERd32,Rs16→@ERd — — 0 — 3

MOV.W Rs,@aa:16 W 4 Rs16→@aa:16 — — 0 — 3

MOV.W Rs,@aa:32 W 6 Rs16→@aa:32 — — 0 — 4

↔

No. of

States*

Normal

Advanced

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 248 of 322

REJ09B0139-0400

Addressing Mode and Instruction Length (Bytes)

Mnemonic Size Operation Condition Code

IHNZVC

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

MOV MOV.L #xx:32,ERd L 6 #xx:32→ERd32 —— 0 — 3

MOV.L ERs,ERd L 2 ERs32→ERd32 —— 0 — 1

MOV.L @ERs,ERd L 4 @ERs→ERd32 —— 0 — 4

MOV.L @(d:16,ERs),ERd L 6 @(d:16,ERs)→ERd32 —— 0 — 5

MOV.L @(d:32,ERs),ERd L 10 @(d:32,ERs)→ERd32 —— 0 — 7

MOV.L @ERs+,ERd L 4 @ERs→ERd32,ERs32+4→@ERs32 —— 0 — 5

MOV.L @aa:16,ERd L 6 @aa:16→ERd32 —— 0 — 5

MOV.L @aa:32,ERd L 8 @aa:32→ERd32 —— 0 — 6

MOV.L ERs,@ERd L 4 ERs32→@ERd —— 0 — 4

MOV.L ERs,@(d:16,ERd) L 6 ERs32→@(d:16,ERd) —— 0 — 5

MOV.L ERs,@(d:32,ERd) L 10 ERs32→@(d:32,ERd) —— 0 — 7

MOV.L ERs,@–ERd L 4 ERd32–4→ERd32,ERs32→@ERd —— 0 — 5

MOV.L ERs,@aa:16 L 6 ERs32→@aa:16 —— 0 — 5

MOV.L ERs,@aa:32 L 8 ERs32→@aa:32 —— 0 — 6

POP POP.W Rn W 2 @SP→Rn16,SP+2→SP —— 0 — 3

POP.L ERn L 4 @SP→ERn32,SP+4→SP —— 0 — 5

PUSH PUSH.W Rn W 2 SP–2→SP,Rn16→@SP —— 0 — 3

PUSH.L ERn L 4 SP–4→SP,ERn32→@SP —— 0 — 5

LDM LDM.L @SP+,(ERm–ERn) L 4 (@SP→ERn32,SP+4→SP)

Repeated for

—————— 7/9/11*

each register restored

STM STM.L (ERm–ERn),@–SP L 4 (SP–4→SP,ERn32→@SP)

Repeated for

—————— 7/9/11*

each register saved

MOVFPE

MOVFPE@aa:16,Rd B 4 @aa:16→Rd (synchronized with —— 0 — (1)

E clock)

MOVTPE

MOVTPE Rs,@aa:16 B 4 Rs→@aa:16 (synchronized with —— 0 — (1)

E clock)

↔

No. of

States*

Normal

Advanced

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 249 of 322

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(2) Arithmetic Operation Instructions

Addressing Mode and Instruction Length (Bytes)

Mnemonic Size Operation Condition Code

IHNZVC

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

ADD ADD.B #xx:8,Rd B 2 Rd8+#xx:8→Rd8 — 1

ADD.B Rs,Rd B 2 Rd8+Rs8→Rd8 — 1

ADD.W #xx:16,Rd W 4 Rd16+#xx:16→Rd16 —(2) 2

ADD.W Rs,Rd W 2 Rd16+Rs16→Rd16 —(2) 1

ADD.L #xx:32,ERd L 6 ERd32+#xx:32→ERd32 —(3) 3

ADD.L ERs,ERd L 2 ERd32+ERs32→ERd32 —(3) 1

ADDX ADDX #xx:8,Rd B 2 Rd8+#xx:8+C→Rd8 —(4) 1

ADDX Rs,Rd B 2 Rd8+Rs8+C→Rd8 —(4) 1

ADDS ADDS #1,ERd L 2 ERd32+1→ERd32 —————— 1

ADDS #2,ERd L 2 ERd32+2→ERd32 —————— 1

ADDS #4,ERd L 2 ERd32+4→ERd32 —————— 1

INC INC.B Rd B 2 Rd8+1→Rd8 —— — 1

INC.W #1,Rd W 2 Rd16+1→Rd16 —— — 1

INC.W #2,Rd W 2 Rd16+2→Rd16 —— — 1

INC.L #1,ERd L 2 ERd32+1→ERd32 —— — 1

INC.L #2,ERd L 2 ERd32+2→ERd32 —— — 1

DAA DAA Rd B 2 Rd8 decimal adjust →Rd8 —

— 1

SUB SUB.B Rs,Rd B 2 Rd8–Rs8→Rd8 — 1

SUB.W #xx:16,Rd W 4 Rd16–#xx:16→Rd16 —(2) 2

SUB.W Rs,Rd W 2 Rd16–Rs16→Rd16 —(2) 1

SUB.L #xx:32,ERd L 6 ERd32–#xx:32→ERd32 —(3) 3

SUB.L ERs,ERd L 2 ERd32–ERs32→ERd32 —(3) 1

SUBX SUBX #xx:8,Rd B 2 Rd8–#xx:8–C→Rd8 —(4) 1

SUBX Rs,Rd B 2 Rd8–Rs8–C→Rd8 —(4) 1

SUBS SUBS #1,ERd L 2 ERd32–1→ERd32 —————— 1

SUBS #2,ERd L 2 ERd32–2→ERd32 —————— 1

SUBS #4,ERd L 2 ERd32–4→ERd32 —————— 1

DEC DEC.B Rd B 2 Rd8–1→Rd8 —— — 1

DEC.W #1,Rd W 2 Rd16–1→Rd16 —— — 1

DEC.W #2,Rd W 2 Rd16–2→Rd16 ——— 1

DEC.L #1,ERd L 2 ERd32–1→ERd32 —— — 1

DEC.L #2,ERd L 2 ERd32–2→ERd32 —— — 1

↔

↔↔

↔

↔↔↔↔↔↔↔↔

↔

↔↔

No. of

States*

Normal

Advanced

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 250 of 322

REJ09B0139-0400

Addressing Mode and Instruction Length (Bytes)

Mnemonic Size Operation Condition Code

IHNZVC

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

DAS DAS Rd B 2 Rd8 decimal adjust →Rd8 —

— 1

MULXU MULXU.B Rs,Rd B 2 Rd8×Rs8→Rd16 —————— 3 (12*

)

(unsigned multiplication)

MULXU.W Rs,ERd W 2 Rd16×Rs16→ERd32 —————— 4 (20*

)

(unsigned multiplication)

MULXS MULXS.B Rs,Rd B 4 Rd8×Rs8→Rd16 —— —— 4 (13*

)

(signed multiplication)

MULXS.W Rs,ERd W 4 Rd16×Rs16→ERd32 —— —— 5 (21*

)

(signed multiplication)

DIVXU DIVXU.B Rs,Rd B 2 Rd16÷Rs8→Rd16 (RdH: remainder, ——(5) (6) —— 12

RdL: quotient) (unsigned division)

DIVXU.W Rs,ERd W 2 ERd32÷Rs16→ERd32 (Ed: remainder, ——(5) (6) —— 20

Rd: quotient) (unsigned division)

DIVXS DIVXS.B Rs,Rd B 4 Rd16÷Rs8→Rd16 (RdH: remainder, ——(7) (6) —— 13

RdL: quotient) (signed division)

DIVXS.W Rs,ERd W 4 ERd32÷Rs16→ERd32 (Ed: remainder, ——(7) (6) —— 21

Rd: quotient) (signed division)

CMP CMP.B #xx:8,Rd B 2 Rd8–#xx:8 — 1

CMP.B Rs,Rd B 2 Rd8–Rs8 — 1

CMP.W #xx:16,Rd W 4 Rd16–#xx:16 — (2) 2

CMP.W Rs,Rd W 2 Rd16–Rs16 —(2) 1

CMP.L #xx:32,ERd L 6 ERd32–#xx:32 — (3) 3

CMP.L ERs,ERd L 2 ERd32–ERs32 —(3) 1

NEG NEG.B Rd B 2 0–Rd8→Rd8 — 1

NEG.W Rd W 2 0–Rd16→Rd16 — 1

NEG.L ERd L 2 0–ERd32→ERd32 — 1

EXTU EXTU.W Rd W2 0

→(<bits 15 to 8> of Rd16) ——00 — 1

EXTU.L ERd L 2 0→(<bits 31 to 16> of ERd32) ——00— 1

EXTS EXTS.W Rd W 2 (<bit 7> of Rd16)→(<bits 15 to 8> —— 0 — 1

of Rd16)

EXTS.L ERd L 2 (<bit 15> of ERd32)→(<bits 31 to 16> —— 0— 1

of ERd32)

TAS TAS @ERd*

B 4 @ERd–0→set CCR, 1→(<bit 7> of —— 0 — 4

@ERd)

↔

↔↔↔↔

↔

↔↔

↔

No. of

States*

Normal

Advanced

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 251 of 322

REJ09B0139-0400

Addressing Mode and Instruction Length (Bytes)

Mnemonic Size Operation Condition Code

IHNZVC

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

MAC*

MAC @ERn+,@ERm+ —4 @ERn×@ERm+MAC→MAC (signed —————— 4

multiplication) (8) (8) (8)

ERn+2→ERn,ERm+2→ERm

CLRMAC

CLRMAC —20→MACH, MACL —————— 2*

LDMAC*

LDMAC ERs,MACH L 2 ERs→MACH —————— 2*

LDMAC ERs,MACL L 2 ERs→MACL —————— 2*

STMAC*

STMAC MACH,ERd L 2 MACH→ERd ——— 1*

STMAC MACL,ERd L 2 MACL→ERd —— — 1*

↔

No. of

States*

Normal

Advanced

Section 2 Instruction Descriptions

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REJ09B0139-0400

(3) Logic Operation Instructions

Addressing Mode and Instruction Length (Bytes)

Mnemonic Size Operation Condition Code

IHNZVC

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

AND AND.B #xx:8,Rd B 2 Rd8∧#xx:8→Rd8 —— 0 — 1

AND.B Rs,Rd B 2 Rd8∧Rs8→Rd8 —— 0 — 1

AND.W #xx:16,Rd W 4 Rd16∧#xx:16→Rd16 —— 0 — 2

AND.W Rs,Rd W 2 Rd16∧Rs16→Rd16 —— 0 — 1

AND.L #xx:32,ERd L 6 ERd32∧#xx:32→ERd32 —— 0 — 3

AND.L ERs,ERd L 4 ERd32∧ERs32→ERd32 —— 0 — 2

OR OR.B #xx:8,Rd B 2 Rd8∨#xx:8→Rd8 —— 0 — 1

OR.B Rs,Rd B 2 Rd8∨Rs8→Rd8 —— 0 — 1

OR.W #xx:16,Rd W 4 Rd16∨#xx:16→Rd16 —— 0 — 2

OR.W Rs,Rd W 2 Rd16∨Rs16→Rd16 —— 0 — 1

OR.L #xx:32,ERd L 6 ERd32∨#xx:32→ERd32 —— 0 — 3

OR.L ERs,ERd L 4 ERd32∨ERs32→ERd32 —— 0 — 2

XOR XOR.B #xx:8,Rd B 2 Rd8⊕#xx:8→Rd8 —— 0 — 1

XOR.B Rs,Rd B 2 Rd8⊕Rs8→Rd8 —— 0 — 1

XOR.W #xx:16,Rd W 4 Rd16⊕#xx:16→Rd16 —— 0 — 2

XOR.W Rs,Rd W 2 Rd16⊕Rs16→Rd16 —— 0 — 1

XOR.L #xx:32,ERd L 6 ERd32⊕#xx:32→ERd32 —— 0 — 3

XOR.L ERs,ERd L 4 ERd32⊕ERs32→ERd32 —— 0 — 2

NOT NOT.B Rd B 2 ¬Rd8→Rd8 —— 0 — 1

NOT.W Rd W 2 ¬Rd16→Rd16 —— 0 — 1

NOT.L ERd L 2 ¬Rd32→Rd32 —— 0 — 1

↔

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(4) Shift Instructions

Addressing Mode and Instruction Length (Bytes)

Mnemonic Size Operation Condition Code

IHNZVC

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

SHAL SHAL.B Rd B 2 —— 1

SHAL.B #2,Rd B 2 —— 1

SHAL.W Rd W 2 —— 1

SHAL.W #2,Rd W 2 —— 1

SHAL.L ERd L 2 —— 1

SHAL.L #2,ERd L 2 —— 1

SHAR SHAR.B Rd B 2 —— 01

SHAR.B #2,Rd B 2 —— 01

SHAR.W Rd W 2 —— 01

SHAR.W #2,Rd W 2 —— 01

SHAR.L ERd L 2 —— 01

SHAR.L #2,ERd L 2 —— 01

SHLL SHLL.B Rd B 2 —— 01

SHLL.B #2,Rd B 2—— 01

SHLL.W Rd W 2 —— 01

SHLL.W #2,Rd W 2 —— 01

SHLL.L ERd L 2 —— 01

SHLL.L #2,ERd L 2 —— 01

SHLR SHLR.B Rd B 2 ——00 1

SHLR.B #2,Rd B 2——001

SHLR.W Rd W 2 ——00 1

SHLR.W #2,Rd W 2 ——00 1

SHLR.L ERd L 2——001

SHLR.L #2,ERd L 2 ——00 1

ROTXL ROTXL.B Rd B 2 —— 01

ROTXL.B #2,Rd B 2 —— 01

ROTXL.W Rd W 2 —— 01

ROTXL.W #2,Rd W 2 —— 01

ROTXL.L ERd L 2 —— 01

ROTXL.L #2,ERd L 2 —— 01

C MSB LSB

CMSB LSB

MSB LSB

C MSB LSB

↔

↔↔↔↔↔↔

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Addressing Mode and Instruction Length (Bytes)

Mnemonic Size Operation Condition Code

IHNZVC

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

ROTXR ROTXR.B Rd B 2 —— 01

ROTXR.B #2,Rd B 2 —— 01

ROTXR.W Rd W 2 —— 01

ROTXR.W #2,Rd W 2 —— 01

ROTXR.L ERd L 2 —— 01

ROTXR.L #2,ERd L 2 —— 01

ROTL ROTL.B Rd B 2 —— 01

ROTL.B #2,Rd B 2 —— 01

ROTL.W Rd W 2 —— 01

ROTL.W #2,Rd W 2 —— 01

ROTL.L ERd L 2 —— 01

ROTL.L #2,ERd L 2 —— 01

ROTR ROTR.B Rd B 2 —— 01

ROTR.B #2,Rd B 2 —— 01

ROTR.W Rd W 2 —— 01

ROTR.W #2,Rd W 2 —— 01

ROTR.L ERd L 2 —— 01

ROTR.L #2,ERd L 2 —— 01

CMSB LSB

C MSB LSB

↔

↔↔

↔

No. of

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(5) Bit Manipulation Instructions

Addressing Mode and Instruction Length (Bytes)

Mnemonic Size Operation Condition Code

IHNZVC

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

BSET BSET #xx:3,Rd B 2 (#xx:3 of Rd8)←1—————— 1

BSET #xx:3,@ERd B 4 (#xx:3 of @ERd)←1—————— 4

BSET #xx:3,@aa:8 B 4 (#xx:3 of @aa:8)←1—————— 4

BSET #xx:3,@aa:16 B 6 (#xx:3 of @aa:16)←1—————— 5

BSET #xx:3,@aa:32 B 8 (#xx:3 of @aa:32)←1 — ————— 6

BSET Rn,Rd B 2 (Rn8 of Rd8)←1—————— 1

BSET Rn,@ERd B 4 (Rn8 of @ERd)←1—————— 4

BSET Rn,@aa:8 B 4 (Rn8 of @aa:8)←1—————— 4

BSET Rn,@aa:16 B 6 (Rn8 of @aa:16)←1—————— 5

BSET Rn,@aa:32 B 8 (Rn8 of @aa:32)←1—————— 6

BCLR BCLR #xx:3,Rd B 2 (#xx:3 of Rd8)←0—————— 1

BCLR #xx:3,@ERd B 4 (#xx:3 of @ERd)←0—————— 4

BCLR #xx:3,@aa:8 B 4 (#xx:3 of @aa:8)←0—————— 4

BCLR #xx:3,@aa:16 B 6 (#xx:3 of @aa:16)←0 — ————— 5

BCLR #xx:3,@aa:32 B 8 (#xx:3 of @aa:32)←0—————— 6

BCLR Rn,Rd B 2 (Rn8 of Rd8)←0—————— 1

BCLR Rn,@ERd B 4 (Rn8 of @ERd)←0 — ————— 4

BCLR Rn,@aa:8 B 4 (Rn8 of @aa:8)←0—————— 4

BCLR Rn,@aa:16 B 6 (Rn8 of @aa:16)←0—————— 5

BCLR Rn,@aa:32 B 8 (Rn8 of @aa:32)←0—————— 6

BNOT BNOT #xx:3,Rd B 2 (#xx:3 of Rd8)← [¬(#xx:3 of Rd8)] —————— 1

BNOT #xx:3,@ERd B 4 (#xx:3 of @ERd)← [¬(#xx:3 of @ERd)] —————— 4

BNOT #xx:3,@aa:8 B4

(#xx:3 of @aa:8)← [¬(#xx:3 of @aa:8)]

—————— 4

BNOT #xx:3,@aa:16 B 6

(#xx:3 of @aa:16)← [¬(#xx:3 of @aa:16)]

—————— 5

BNOT #xx:3,@aa:32 B 8

(#xx:3 of @aa:32)← [¬(#xx:3 of @aa:32)]

—————— 6

BNOT Rn,Rd B 2 (Rn8 of Rd8)← [¬(Rn8 of Rd8)] —————— 1

BNOT Rn,@ERd B 4 (Rn8 of @ERd)← [¬(Rn8 of @ERd)] —————— 4

BNOT Rn,@aa:8 B 4 (Rn8 of @aa:8)← [¬(Rn8 of @aa:8)] —————— 4

BNOT Rn,@aa:16 B6

(Rn8 of @aa:16)← [¬(Rn8 of @aa:16)]

—————— 5

BNOT Rn,@aa:32 B 8

(Rn8 of @aa:32)← [¬(Rn8 of @aa:32)]

—————— 6

No. of

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Addressing Mode and Instruction Length (Bytes)

Mnemonic Size Operation Condition Code

IHNZVC

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

BTST BTST #xx:3,Rd B 2 (#xx:3 of Rd8)→Z——— —— 1

BTST #xx:3,@ERd B 4 (#xx:3 of @ERd)→Z——— —— 3

BTST #xx:3,@aa:8 B 4 (#xx:3 of @aa:8)→Z——— —— 3

BTST #xx:3,@aa:16 B 6 (#xx:3 of @aa:16)→Z——— —— 4

BTST #xx:3,@aa:32 B 8 (#xx:3 of @aa:32)→Z——— —— 5

BTST Rn,Rd B 2 (Rn8 of Rd8)→Z — —— —— 1

BTST Rn,@ERd B 4 (Rn8 of @ERd)→Z——— —— 3

BTST Rn,@aa:8 B 4 (Rn8 of @aa:8)→Z——— —— 3

BTST Rn,@aa:16 B 6 (Rn8 of @aa:16)→Z——— —— 4

BTST Rn,@aa:32 B 8 (Rn8 of @aa:32)→Z——— —— 5

BLD BLD #xx:3,Rd B 2 (#xx:3 of Rd8)→C————— 1

BLD #xx:3,@ERd B 4 (#xx:3 of @ERd)→C — ———— 3

BLD #xx:3,@aa:8 B 4 (#xx:3 of @aa:8)→C————— 3

BLD #xx:3,@aa:16 B 6 (#xx:3 of @aa:16)→C————— 4

BLD #xx:3,@aa:32 B 8 (#xx:3 of @aa:32)→C — ———— 5

BILD BILD #xx:3,Rd B 2 ¬(#xx:3 of Rd8)→C————— 1

BILD #xx:3,@ERd B 4 ¬(#xx:3 of @ERd)→C————— 3

BILD #xx:3,@aa:8 B 4 ¬ (#xx:3 of @aa:8)→C — ———— 3

BILD #xx:3,@aa:16 B 6 ¬(#xx:3 of @aa:16)→C————— 4

BILD #xx:3,@aa:32 B 8 ¬(#xx:3 of @aa:32)→C————— 5

BST BST #xx:3,Rd B2 C

→(#xx:3 of Rd8) —————— 1

BST #xx:3,@ERd B 4 C→(#xx:3 of @ERd24) —————— 4

BST #xx:3,@aa:8 B 4 C→(#xx:3 of @aa:8) —————— 4

BST #xx:3,@aa:16 B 6C

→(#xx:3 of @aa:16) —————— 5

BST #xx:3,@aa:32 B 8 C→(#xx:3 of @aa:32) —————— 6

BIST BIST #xx:3,Rd B 2 ¬ C→(#xx:3 of Rd8) —————— 1

BIST #xx:3,@ERd B 4 ¬ C→(#xx:3 of @ERd24) —————— 4

BIST #xx:3,@aa:8 B 4 ¬ C→(#xx:3 of @aa:8) —————— 4

BIST #xx:3,@aa:16 B 6 ¬ C→(#xx:3 of @aa:16) —————— 5

BIST #xx:3,@aa:32 B 8 ¬ C→(#xx:3 of @aa:32) —————— 6

↔↔↔↔↔↔↔↔↔↔

No. of

States*1

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Advanced

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 257 of 322

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Addressing Mode and Instruction Length (Bytes)

Mnemonic Size Operation Condition Code

IHNZVC

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

BAND BAND #xx:3,Rd B 2 C∧(#xx:3 of Rd8)→C————— 1

BAND #xx:3,@ERd B 4 C∧(#xx:3 of @ERd24)→C————— 3

BAND #xx:3,@aa:8 B 4 C∧(#xx:3 of @aa:8)→C————— 3

BAND #xx:3,@aa:16 B 6 C∧(#xx:3 of @aa:16)→C————— 4

BAND #xx:3,@aa:32 B 8 C∧(#xx:3 of @aa:32)→C————— 5

BIAND BIAND #xx:3,Rd B 2 C∧ [¬(#xx:3 of Rd8)]→C————— 1

BIAND #xx:3,@ERd B 4 C∧ [¬(#xx:3 of @ERd24)]→C————— 3

BIAND #xx:3,@aa:8 B 4 C∧ [¬(#xx:3 of @aa:8)]→C————— 3

BIAND #xx:3,@aa:16 B 6 C∧ [¬(#xx:3 of @aa:16)]→C————— 4

BIAND #xx:3,@aa:32 B 8 C∧ [¬(#xx:3 of @aa:32)]→C————— 5

BOR BOR #xx:3,Rd B 2 C∨(#xx:3 of Rd8)→C————— 1

BOR #xx:3,@ERd B 4 C∨(#xx:3 of @ERd24)→C————— 3

BOR #xx:3,@aa:8 B 4 C∨(#xx3: of @aa:8)→C————— 3

BOR #xx:3,@aa:16 B 6 C∨(#xx3: of @aa:16)→C————— 4

BOR #xx:3,@aa:32 B 8 C∨(#xx3: of @aa:32)→C————— 5

BIOR BIOR #xx:3,Rd B 2 C∨ [¬(#xx:3 of Rd8)]→C————— 1

BIOR #xx:3,@ERd B 4 C∨ [¬(#xx:3 of @ERd24)]→C————— 3

BIOR #xx:3,@aa:8 B 4 C∨ [¬(#xx:3 of @aa:8)]→C————— 3

BIOR #xx:3,@aa:16 B 6 C∨ [¬(#xx:3 of @aa:16)]→C————— 4

BIOR #xx:3,@aa:32 B 8 C∨ [¬(#xx:3 of @aa:32)]→C————— 5

BXOR BXOR #xx:3,Rd B 2 C⊕(#xx:3 of Rd8)→C————— 1

BXOR #xx:3,@ERd B 4 C⊕(#xx:3 of @ERd24)→C————— 3

BXOR #xx:3,@aa:8 B 4 C⊕(#xx:3 of @aa:8)→C————— 3

BXOR #xx:3,@aa:16 B 6 C⊕(#xx:3 of @aa:16)→C————— 4

BXOR #xx:3,@aa:32 B 8 C⊕(#xx:3 of @aa:32)→C————— 5

BIXOR BIXOR #xx:3,Rd B 2 C⊕[¬(#xx:3 of Rd8)]→C————— 1

BIXOR #xx:3,@ERd B 4 C⊕[¬(#xx:3 of @ERd24)]→C————— 3

BIXOR #xx:3,@aa:8 B 4 C⊕[¬(#xx:3 of @aa:8)]→C————— 3

BIXOR #xx:3,@aa:16 B 6 C⊕[¬(#xx:3 of @aa:16)]→C————— 4

BIXOR #xx:3,@aa:32 B 8 C⊕[¬(#xx:3 of @aa:32)]→C————— 5

↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔

No. of

States*

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Advanced

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 258 of 322

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(6) Branch Instructions

Addressing Mode and Instruction Length (Bytes)

Mnemonic Size Operation Condition Code

IHNZVC

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

Bcc BRA d:8(BT d:8) —2 if condition is true then Always —————— 2

BRA d:16(BT d:16) —4PC←PC+d —————— 3

BRN d:8(BF d:8) —2 else next; Never —————— 2

BRN d:16(BF d:16) — 4 —————— 3

BHI d:8 —2C∨z=0 —————— 2

BHI d:16 — 4 —————— 3

BLS d:8 —2C∨z=1 —————— 2

BLS d:16 — 4 —————— 3

BCC d:8(BHS d:8) —2 C=0 —————— 2

BCC d:16(BHS d:16) — 4 —————— 3

BCS d:8(BLO d:8) —2 C=1 —————— 2

BCS d:16(BLO d:16) — 4 —————— 3

BNE d:8 —2 Z=0 —————— 2

BNE d:16 — 4 —————— 3

BEQ d:8 —2 Z=1 —————— 2

BEQ d:16 — 4 —————— 3

BVC d:8 —2 V=0 —————— 2

BVC d:16 — 4 —————— 3

BVS d:8 —2 V=1 —————— 2

BVS d:16 — 4 —————— 3

BPL d:8 —2 N=0 —————— 2

BPL d:16 — 4 —————— 3

BMI d:8 — 2 N=1 —————— 2

BMI d:16 — 4 —————— 3

BGE d:8 —2N⊕V=0 —————— 2

BGE d:16 — 4 —————— 3

BLT d:8 — 2 N⊕V=1 —————— 2

BLT d:16 — 4 —————— 3

BGT d:8 — 2 Z∨(N⊕V)=0 —————— 2

BGT d:16 — 4 —————— 3

BLE d:8 —2Z∨(N⊕V)=1 —————— 2

BLE d:16 — 4 —————— 3

Branch

Condition

No. of

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Addressing Mode and Instruction Length (Bytes)

Mnemonic Size Operation Condition Code

IHNZVC

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

JMP JMP @ERn —2PC←Ern —————— 2

JMP @aa:24 —4PC←aa:24 —————— 3

JMP @@aa:8 —2PC←@aa:8 —————— 45

BSR BSR d:8 —2PC→@–SP,PC←PC+d:8 —————— 34

BSR d:16 —4PC→@–SP,PC←PC+d:16 —————— 45

JSR JSR @ERn —2PC→@–SP,PC←ERn —————— 34

JSR @aa:24 —4PC→@–SP,PC←aa:24 —————— 45

JSR @@aa:8 —2PC→@–SP,PC←aa:8 —————— 46

RTS RTS —2PC←@SP+ —————— 45

Branch

Condition

No. of

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(7) System Control Instructions

Addressing Mode and Instruction Length (Bytes)

Mnemonic Size Operation Condition Code

No. of

States*

IHNZVC

Normal

Advanced

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

TRAPA TRAPA #x:2 —2PC→@–SP,CCR→@–SP, 1 —————7[9] 8[9]

EXR→@–SP,<vector>→PC

RTE RTE —EXR←@SP+,CCR←@SP+, 5[9]

PC←@SP+

SLEEP SLEEP —Transition to power-down state —————— 2

LDC LDC #xx:8,CCR B 2 #xx:8→CCR 1

LDC #xx:8,EXR B 4 #xx:8→EXR —————— 2

LDC Rs,CCR B 2 Rs8→CCR 1

LDC Rs,EXR B 2 Rs8→EXR —————— 1

LDC @ERs,CCR W 4 @ERs→CCR 3

LDC @ERs,EXR W 4 @ERs→EXR —————— 3

LDC @(d:16,ERs),CCR W 6 @(d:16,ERs)→CCR 4

LDC @(d:16,ERs),EXR W 6 @(d:16,ERs)→EXR —————— 4

LDC @(d:32,ERs),CCR W 10 @(d:32,ERs)→CCR 6

LDC @(d:32,ERs),EXR W 10 @(d:32,ERs)→EXR —————— 6

LDC @ERs+,CCR W 4 @ERs→CCR,ERs32+2→ERs32 4

LDC @ERs+,EXR W 4 @ERs→EXR,ERs32+2→ERs32 —————— 4

LDC @aa:16,CCR W 6 @aa:16→CCR 4

LDC @aa:16,EXR W 6 @aa:16→EXR —————— 4

LDC @aa:32,CCR W 8 @aa:32→CCR 5

LDC @aa:32,EXR W 8 @aa:32→EXR —————— 5

↔

*7*7

Section 2 Instruction Descriptions

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Addressing Mode and Instruction Length (Bytes)

Mnemonic Size Operation Condition Code

IHNZVC

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

STC STC CCR,Rd B 2 CCR→Rd8 —————— 1

STC EXR,Rd B 2 EXR→Rd8 —————— 1

STC CCR,@ERd W 4 CCR→@ERd —————— 3

STC EXR,@ERd W 4 EXR→@ERd —————— 3

STC CCR,@(d:16,ERd) W 6 CCR→@(d:16,ERd) —————— 4

STC EXR,@(d:16,ERd) W 6 EXR→@(d:16,ERd) —————— 4

STC CCR,@(d:32,ERd) W 10 CCR→@(d:32,ERd) —————— 6

STC EXR,@(d:32,ERd) W 10 EXR→@(d:32,ERd) —————— 6

STC CCR,@–ERd W 4 ERd32–2→ERd32,CCR→@ERd —————— 4

STC EXR,@–ERd W 4 ERd32–2→ERd32,EXR→@ERd —————— 4

STC CCR,@aa:16 W 6 CCR→@aa:16 —————— 4

STC EXR,@aa:16 W 6 EXR→@aa:16 —————— 4

STC CCR,@aa:32 W 8 CCR→@aa:32 —————— 5

STC EXR,@aa:32 W 8 EXR→@aa:32 —————— 5

ANDC ANDC #xx:8,CCR B 2 CCR∧#xx:8→CCR 1

ANDC #xx:8,EXR B 4 EXR∧#xx:8→EXR —————— 2

ORC ORC #xx:8,CCR B 2 CCR∨#xx:8→CCR 1

ORC #xx:8,EXR B 4 EXR∨#xx:8→EXR —————— 2

XORC XORC #xx:8,CCR B 2 CCR⊕#xx:8→CCR 1

XORC #xx:8,EXR B 4 EXR⊕#xx:8→EXR —————— 2

NOP NOP —2PC←PC+2 —————— 1

↔

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(8) Block Transfer Instructions

Addressing Mode and Instruction Length (Bytes)

Mnemonic Size Operation Condition Code

IHNZVC

#xx

@ERn

@(d,ERn)

@–ERn/@ERn+

@aa

@(d,PC)

@@aa

—

EEPMOV

EEPMOV.B —4 if R4L ≠0—————— 4+2n*2

Repeat @ER5+→@ER6+

ER5+1→ER5

ER6+1→ER6

R4L–1→R4L

Until R4L=0

else next;

EEPMOV.W — 4 if R4 ≠0—————— 4+2n*2

Repeat @ER5+→@ER6+

ER5+1→ER5

ER6+1→ER6

R4–1→ 4

Until R4=0

else next;

No. of

States*1

Normal

Advanced

Notes: 1. The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory.

2. n is the initial setting of R4L or R4.

3. Seven states for saving or restoring two registers, nine states for three registers, or eleven states for four registers.

4. One additional state is required for execution immediately after a MULXU, MULXS, or STMAC instruction. Also, a maximum of three additional states

are required for execution of a MULXU instruction within three states after execution of a MAC instruction. For example, if there is a one-state instruction

(such as NOP) between a MAC instruction and a MULXU instruction, the MULXU instruction will be two states longer.

5. A maximum of two additional states are required for execution of a MULXS instruction within two states after execution of a MAC instruction.

For example, if there is a one-state instruction (such as NOP) between a MAC instruction and a MULXS instruction, the MULXS instruction will be one

state longer.

6. A maximum of three additional states are required for execution of one of these instructions within three states after execution of a MAC instruction.

For example, if there is a one-state instruction (such as NOP) between a MAC instruction and one of these instructions, that instruction will be two states

longer.

7. Values in parentheses ( ) are for the H8S/2000 CPU. Values in square brackets [ ] apply to interrupt control modes 2 and 3.

8. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

9. These instructions are supported only by the H8S/2600 CPU.

10. The number of states may differ depending on the product. For details, refer to the relevant microcontroller hardware manual of the product in question.

(1) The number of states required for execution of an instruction that transfers data in synchronization with the E clock is variable.

(2) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.

(3) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0.

(4) Retains its previous value when the result is zero; otherwise cleared to 0.

(5) Set to 1 when the divisor is negative; otherwise cleared to 0.

(6) Set to 1 when the divisor is zero; otherwise cleared to 0.

(7) Set to 1 when the quotient is negative; otherwise cleared to 0.

(8) MAC instruction results are indicated in the flags when the STMAC instruction is executed.

(9) One additional state is required for execution when EXR is valid.

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2.4 Instruction Code

Table 2.2 Instruction Codes

Instruction Format

Instruction Mnemonic Size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

ADD ADD.B #xx:8,Rd B 8 rd IMM

ADD.B Rs,Rd B 0 8 rs rd

ADD.W #xx:16,Rd W 7 9 1 rd IMM

ADD.W Rs,Rd W 0 9 rs rd

ADD.L #xx:32,ERd L 7 A 1 0 erd IMM

ADD.L ERs,ERd L 0 A 1 ers 0 erd

ADDS ADDS #1,ERd L 0 B 0 0 erd

ADDS #2,ERd L 0 B 8 0 erd

ADDS #4,ERd L 0 B 9 0 erd

ADDX ADDX #xx:8,Rd B 9 rd IMM

ADDX Rs,Rd B 0 E rs rd

AND AND.B #xx:8,Rd B E rd IMM

AND.B Rs,Rd B 1 6 rs rd

AND.W #xx:16,Rd W 7 9 6 rd IMM

AND.W Rs,Rd W 6 6 rs rd

AND.L #xx:32,ERd L 7 A 6 0 erd IMM

AND.L ERs,ERd L 0 1 F 0 6 6 0 ers 0 erd

ANDC ANDC #xx:8,CCR B 0 6 IMM

ANDC #xx:8,EXR B 0 1 4 1 0 6 IMM

BAND BAND #xx:3,Rd B 7 6 0 IMM rd

BAND #xx:3,@ERd B 7 C 0 erd 0 7 6 0 IMM 0

BAND #xx:3,@aa:8 B 7 E abs 7 6 0 IMM 0

BAND #xx:3,@aa:16 B 6 A 1 0 abs 7 6 0 IMM 0

BAND #xx:3,@aa:32 B 6 A 3 0 abs 7 6 0 IMM 0

Bcc BRA d:8 (BT d:8) — 4 0 disp

BRA d:16 (BT d:16) — 5 8 0 0 disp

BRN d:8 (BF d:8) — 4 1 disp

BRN d:16 (BF d:16) — 5 8 1 0 disp

BHI d:8 — 4 2 disp

BHI d:16 — 5 8 2 0 disp

BLS d:8 — 43 disp

BLS d:16 — 5 8 3 0 disp

BCC d:8 (BHS d:8) — 4 4 disp

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Instruction Format

Instruction Mnemonic Size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

Bcc BCC d:16 (BHS d:16) —5 8 4 0 disp

BCS d:8 (BLO d:8) —4 5 disp

BCS d:16 (BLO d:16) —5 8 5 0 disp

BNE d:8 —4 6 disp

BNE d:16 —5 8 6 0 disp

BEQ d:8 —4 7 disp

BEQ d:16 —5 8 7 0 disp

BVC d:8 —4 8 disp

BVC d:16 —5 8 8 0 disp

BVS d:8 —4 9 disp

BVS d:16 —5 8 9 0 disp

BPL d:8 —4 A disp

BPL d:16 —5 8 A 0 disp

BMI d:8 —4 B disp

BMI d:16 —5 8 B 0 disp

BGE d:8 —4 C disp

BGE d:16 —5 8 C 0 disp

BLT d:8 —4 D disp

BLT d:16 —5 8 D 0 disp

BGT d:8 —4 E disp

BGT d:16 —5 8 E 0 disp

BLE d:8 —4 F disp

BLE d:16 —5 8 F 0 disp

BCLR BCLR #xx:3,Rd B 7 2 0 IMM rd

BCLR #xx:3,@ERd B 7 D 0 erd 0 7 2 0 IMM 0

BCLR #xx:3,@aa:8 B 7 F abs 7 2 0 IMM 0

BCLR #xx:3,@aa:16 B 6 A 1 8 abs 7 2 0 IMM 0

BCLR #xx:3,@aa:32 B 6 A 3 8 abs 7 2 0 IMM 0

BCLR Rn,Rd B 6 2 rn rd

BCLR Rn,@ERd B 7 D 0 erd 0 6 2 rn 0

BCLR Rn,@aa:8 B 7 F abs 6 2 rn 0

BCLR Rn,@aa:16 B 6 A 1 8 abs 6 2 rn 0

BCLR Rn,@aa:32 B 6 A 3 8 abs 6 2 rn 0

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Instruction Format

Instruction Mnemonic Size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

BIAND BIAND #xx:3,Rd B 7 6 1 IMM rd

BIAND #xx:3,@ERd B 7 C 0 erd 0 7 6 1 IMM 0

BIAND #xx:3,@aa:8 B 7 E abs 7 6 1 IMM 0

BIAND #xx:3,@aa:16 B 6 A 1 0 abs 7 6 1 IMM 0

BIAND #xx:3,@aa:32 B 6 A 3 0 abs 7 6 1 IMM 0

BILD BILD #xx:3,Rd B 7 7 1 IMM rd

BILD #xx:3,@ERd B 7 C 0 erd 0 7 7 1 IMM 0

BILD #xx:3,@aa:8 B 7 E abs 7 7 1 IMM 0

BILD #xx:3,@aa:16 B 6 A 1 0 abs 7 7 1 IMM 0

BILD #xx:3,@aa:32 B 6 A 3 0 abs 7 7 1 IMM 0

BIOR BIOR #xx:3,Rd B 7 4 1 IMM rd

BIOR #xx:3,@ERd B 7 C 0 erd 0 7 4 1 IMM 0

BIOR #xx:3,@aa:8 B 7 E abs 7 4 1 IMM 0

BIOR #xx:3,@aa:16 B 6 A 1 0 abs 7 4 1 IMM 0

BIOR #xx:3,@aa:32 B 6 A 3 0 abs 7 4 1 IMM 0

BIST BIST #xx:3,Rd B 6 7 1 IMM rd

BIST #xx:3,@ERd B 7 D 0 erd 0 6 7 1 IMM 0

BIST #xx:3,@aa:8 B 7 F abs 6 7 1 IMM 0

BIST #xx:3,@aa:16 B 6 A 1 8 abs 6 7 1 IMM 0

BIST #xx:3,@aa:32 B 6 A 3 8 abs 6 7 1 IMM 0

BIXOR BIXOR #xx:3,Rd B 7 5 1 IMM rd

BIXOR #xx:3,@ERd B 7 C 0 erd 0 7 5 1 IMM 0

BIXOR #xx:3,@aa:8 B 7 E abs 7 5 1 IMM 0

BIXOR #xx:3,@aa:16 B 6 A 1 0 abs 7 5 1 IMM 0

BIXOR #xx:3,@aa:32 B 6 A 3 0 abs 7 5 1 IMM 0

BLD BLD #xx:3,Rd B 7 7 0 IMM rd

BLD #xx:3,@ERd B 7 C 0 erd 0 7 7 0 IMM 0

BLD #xx:3,@aa:8 B 7 E abs 7 7 0 IMM 0

BLD #xx:3,@aa:16 B 6 A 1 0 abs 7 7 0 IMM 0

BLD #xx:3,@aa:32 B 6 A 3 0 abs 7 7 0 IMM 0

BNOT BNOT #xx:3,Rd B 7 1 0 IMM rd

BNOT #xx:3,@ERd B 7 D 0 erd 0 7 1 0 IMM 0

BNOT #xx:3,@aa:8 B 7 F abs 7 1 0 IMM 0

BNOT #xx:3,@aa:16 B 6 A 1 8 abs 7 1 0 IMM 0

BNOT #xx:3,@aa:32 B 6 A 3 8 abs 7 1 0 IMM 0

BNOT Rn,Rd B 6 1 rn rd

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Instruction Format

Instruction Mnemonic Size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

BNOT BNOT Rn,@ERd B 7 D 0 erd 0 6 1 rn 0

BNOT Rn,@aa:8 B 7 F abs 6 1 rn 0

BNOT Rn,@aa:16 B 6 A 1 8 abs 6 1 rn 0

BNOT Rn,@aa:32 B 6 A 3 8 abs 6 1 rn 0

BOR BOR #xx:3,Rd B 7 4 0 IMM rd

BOR #xx:3,@ERd B 7 C 0 erd 0 7 4 0 IMM 0

BOR #xx:3,@aa:8 B 7 E abs 7 4 0 IMM 0

BOR #xx:3,@aa:16 B 6 A 1 0 abs 7 4 0 IMM 0

BOR #xx:3,@aa:32 B 6 A 3 0 abs 7 4 0 IMM 0

BSET BSET #xx:3,Rd B 7 0 0 IMM rd

BSET #xx:3,@ERd B 7 D 0 erd 0 7 0 0 IMM 0

BSET #xx:3,@aa:8 B 7 F abs 7 0 0 IMM 0

BSET #xx:3,@aa:16 B 6 A 1 8 abs 7 0 0 IMM 0

BSET #xx:3,@aa:32 B 6 A 3 8 abs 7 0 0 IMM 0

BSET Rn,Rd B 6 0 rn rd

BSET Rn,@ERd B 7 D 0 erd 0 6 0 rn 0

BSET Rn,@aa:8 B 7 F abs 6 0 rn 0

BSET Rn,@aa:16 B 6 A 1 8 abs 6 0 rn 0

BSET Rn,@aa:32 B 6 A 3 8 abs 6 0 rn 0

BSR BSR d:8 —5 5 disp

BSR d:16 —5 C 0 0 disp

BST BST #xx:3,Rd B 6 7 0 IMM rd

BST #xx:3,@ERd B 7 D 0 erd 0 6 7 0 IMM 0

BST #xx:3,@aa:8 B 7 F abs 6 7 0 IMM 0

BST #xx:3,@aa:16 B 6 A 1 8 abs 6 7 0 IMM 0

BST #xx:3,@aa:32 B 6 A 3 8 abs 6 7 0 IMM 0

BTST BTST #xx:3,Rd B 7 3 0 IMM rd

BTST #xx:3,@ERd B 7 C 0 erd 0 7 3 0 IMM 0

BTST #xx:3,@aa:8 B 7 E abs 7 3 0 IMM 0

BTST #xx:3,@aa:16 B 6 A 1 0 abs 7 3 0 IMM 0

BTST #xx:3,@aa:32 B 6 A 3 0 abs 7 3 0 IMM 0

BTST Rn,Rd B 6 3 rn rd

BTST Rn,@ERd B 7 C 0 erd 0 6 3 rn 0

BTST Rn,@aa:8 B 7 E abs 6 3 rn 0

BTST Rn,@aa:16 B 6 A 1 0 abs 6 3 rn 0

BTST Rn,@aa:32 B 6 A 3 0 abs 6 3 rn 0

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Instruction Format

Instruction Mnemonic Size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

BXOR BXOR #xx:3,Rd B 7 5 0 IMM rd

BXOR #xx:3,@ERd B 7 C 0 erd 0 7 5 0 IMM 0

BXOR #xx:3,@aa:8 B 7 E abs 7 5 0 IMM 0

BXOR #xx:3,@aa:16 B 6 A 1 0 abs 7 5 0 IMM 0

BXOR #xx:3,@aa:32 B 6 A 3 0 abs 7 5 0 IMM 0

CLRMAC*1CLRMAC —01A0

CMP CMP.B #xx:8,Rd B A rd IMM

CMP.B Rs,Rd B 1 C rs rd

CMP.W #xx:16,Rd W 7 9 2rd IMM

CMP.W Rd,Rd W 1 D rs rd

CMP.L #xx:32,ERd L 7 A 2 0 erd IMM

CMP.L ERs,ERd L 1 F 1 ers 0 erd

DAA DAA Rd B 0 F 0 rd

DAS DAS Rd B 1 F 0 rd

DEC DEC.B Rd B 1 A 0 rd

DEC.W #1,Rd W 1 B 5rd

DEC.W #2,Rd W 1 B D rd

DEC.L #1,ERd L 1 B 7 0 erd

DEC.L #2,ERd L 1 B F 0 erd

DIVXS DIVXS.B Rs,Rd B 0 1 D 0 5 1 rs rd

DIVXS.W Rs,ERd W 0 1 D 0 5 3 rs 0 erd

DIVXU DIVXU.B Rs,Rd B 5 1 rs rd

DIVXU.W Rs,ERd W 5 3 rs 0 erd

EEPMOV EEPMOV.B —7B5C598F

EEPMOV.W —7BD4598F

EXTS EXTS.W Rd W 1 7 D rd

EXTS.L ERd L 1 7 F 0 erd

EXTU EXTU.W Rd W 1 7 5 rd

EXTU.L ERd L 1 7 7 0 erd

INC INC.B Rd B 0 A 0 rd

INC.W #1,Rd W 0 B 5 rd

INC.W #2,Rd W 0 B D rd

INC.L #1,ERd L 0 B 7 0 erd

INC.L #2,ERd L 0 B F 0 erd

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Instruction Format

Instruction Mnemonic Size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

JMP JMP @ERn —590ern0

JMP @aa:24 —5 A abs

JMP @aa:8 —5 B abs

JSR JSR @ERn —5D0ern0

JSR @aa:24 —5 E abs

JSR @@aa:8 —5 F abs

LDC LDC #xx:8,CCR B 0 7 IMM

LDC #xx:8,EXR B 014107 IMM

LDC Rs,CCR B 0 3 0 rs

LDC Rs,EXR B 0 3 1 rs

LDC @ERs,CCR W0140690ers0

LDC @ERs,EXR W 0141690ers0

LDC @(d:16,ERs),CCR W 01406F0ers0 disp

LDC @(d:16,ERs),EXR W 01416F0ers0 disp

LDC @(d:32,ERs),CCR W 0140780ers06B20 disp

LDC @(d:32,ERs),EXR W 0141780ers06B20 disp

LDC @ERs+,CCR W 01406D0ers0

LDC @ERs+,EXR W 01416D0ers0

LDC @aa:16,CCR W 01406B00 abs

LDC @aa:16,EXR W 01416B00 abs

LDC @aa:32,CCR W 01406B20 abs

LDC @aa:32,EXR W 01416B20 abs

LDM LDM.L @SP+,(ERn–ERn+1) L 01106D70

ern+1

LDM.L @SP+,(ERn–ERn+2) L 01206D70

ern+2

LDM.L @SP+,(ERn–ERn+3) L 01306D70

ern+3

LDMAC*

LDMAC ERS,MACH L 0 3 2 0 ers

LDMAC ERs,MACL L 0 3 3 0 ers

MAC*

MAC @ERn+,@ERm+ —01606D0ern0erm

MOV MOV.B #xx:8,Rd B F rd IMM

MOV.B Rs,Rd B 0 C rs rd

MOV.B @ERs,Rd B 6 8 0 ers rd

MOV.B @(d:16,ERs),Rd B 6 E 0 ers rd disp

MOV.B @(d:32,ERs),Rd B 7 8 0 ers 0 6 A 2 rd disp

MOV.B @ERs+,Rd B 6 C 0 ers rd

MOV.B @aa:8,Rd B 2 rd abs

MOV.B @aa:16,Rd B 6 A 0 rd abs

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Instruction Format

Instruction Mnemonic Size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

MOV MOV.B @aa:32,Rd B 6 A 2 rd abs

MOV.B Rs,@ERd B 6 8 1 erd rs

MOV.B Rs,@(d:16,ERd) B 6 E 1 erd rs disp

MOV.B Rs,@(d:32,ERd) B 7 8 0 erd 0 6 A A rs disp

MOV.B Rs,@–ERd B 6 C 1 erd rs

MOV.B Rs,@aa:8 B 3 rs abs

MOV.B Rs,@aa:16 B 6 A 8 rs abs

MOV.B Rs,@aa:32 B 6 A A rs abs

MOV.W #xx:16,Rd W 7 9 0 rd IMM

MOV.W Rs,Rd W 0 D rs rd

MOV.W @ERs,Rd W 6 9 0 ers rd

MOV.W @(d:16,ERs),Rd W 6 F 0 ers rd disp

MOV.W @(d:32,ERs),Rd W 7 8 0 ers 0 6 B 2 rd disp

MOV.W @ERs+,Rd W 6 D 0 ers rd

MOV.W @aa:16,Rd W 6 B 0 rd abs

MOV.W @aa:32,Rd W 6 B 2 rd abs

MOV.W Rs,@ERd W 6 9 1 erd rs

MOV.W Rs,@(d:16,ERd) W 6 F 1 erd rs disp

MOV.W Rs,@(d:32,ERd) W 7 8 0 erd 0 6 B A rs disp

MOV.W Rs,@–ERd W 6 D 1 erd rs

MOV.W Rs,@aa:16 W 6 B 8 rs abs

MOV.W Rs,@aa:32 W 6 B A rs abs

MOV.L #xx:32,Rd L 7 A 0 0 erd IMM

MOV.L ERs,ERd L 0 F 1 ers 0 erd

MOV.L @ERs,ERd L 0100690ers0erd

MOV.L @(d:16,ERs),ERdL01006F0ers0erd disp

MOV.L @(d:32,ERs),ERdL0100780ers06B20erd disp

MOV.L @ERs+,ERd L 01006D0ers0erd

MOV.L @aa:16,ERd L 01006B00erd abs

MOV.L @aa:32,ERd L 01006B20erd abs

MOV.L ERs,@ERd L 01006 9 1 erd 0 ers

MOV.L ERs,@(d:16,ERd) L 01006F1erd0

ers disp

MOV.L ERs,@(d:32,ERd)*

L0100780erd06BA0ers disp

MOV.L ERs,@–ERd L 0 1 0 0 6 D 1 erd 0 ers

MOV.L ERs,@aa:16 L 01006B8

0 ers abs

MOV.L ERs,@aa:32 L 0 1 0 0 6 B A 0 ers abs

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Instruction Format

Instruction Mnemonic Size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

MOVFPE MOVFPE @aa:16,Rd B 6 A 4 rd abs

MOVTPE MOVTPE Rs,@aa:16 B 6 A C rs abs

MULXS MULXS.B Rs,Rd B 0 1 C 0 5 0 rs rd

MULXS.W Rs,ERd W 0 1 C 0 5 2 rs 0 erd

MULXU MULXU.B Rs,Rd B 5 0 rs rd

MULXU.W Rs,ERd W 5 2 rs 0 erd

NEG NEG.B Rd B 1 7 8 rd

NEG.W Rd W 1 7 9 rd

NEG.L ERd L 1 7 B 0 erd

NOP NOP —0000

NOT NOT.B Rd B 1 7 0 rd

NOT.W Rd W 1 7 1 rd

NOT.L ERd L 1 7 3 0 erd

OR OR.B #xx:8,Rd B C rd IMM

OR.B Rs,Rd B 1 4 rs rd

OR.W #xx:16,Rd W 7 9 4 rd IMM

OR.W Rs,Rd W 6 4 rs rd

OR.L #xx:32,ERd L 7 A 4 0 erd IMM

OR.L ERs,ERd L 0 1 F 0 6 4 0 ers 0 erd

ORC ORC #xx:8,CCR B 0 4 IMM

ORC #xx:8,EXR B 0 1 4 1 0 4 IMM

POP POP.W Rn W 6 D 7 rn

POP.L ERn L 0 1 0 0 6 D 7 0 ern

PUSH PUSH.W Rn W 6 D F rn

PUSH.L ERn L 0 1 0 0 6 D F 0 ern

ROTL ROTL.B Rd B 1 2 8 rd

ROTL.B #2,Rd B 1 2 C rd

ROTL.W Rd W 1 2 9 rd

ROTL.W #2,Rd W 1 2 D rd

ROTL.L ERd L 1 2 B 0 erd

ROTL.L #2,ERd L 1 2 F 0 erd

ROTR ROTR.B Rd B 1 3 8 rd

ROTR.B #2,Rd B 1 3 C rd

ROTR.W Rd W 1 3 9 rd

ROTR.W #2,Rd W 1 3 D rd

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Instruction Format

Instruction Mnemonic Size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

ROTR ROTR.L ERd L 1 3 B 0 erd

ROTR.L #2,ERd L 1 3 F 0 erd

ROTXL ROTXL.B Rd B 1 2 0 rd

ROTXL.B #2,Rd B 1 2 4 rd

ROTXL.W Rd W 1 2 1 rd

ROTXL.W #2,Rd W 1 2 5 rd

ROTXL.L ERd L 1 2 3 0 erd

ROTXL.L #2,ERd L 1 2 7 0 erd

ROTXR ROTXR.B Rd B 1 3 0 rd

ROTXR.B #2,Rd B 1 3 4 rd

ROTXR.W Rd W 1 3 1 rd

ROTXR.W #2,Rd W 1 3 5 rd

ROTXR.L ERd L 1 3 3 0 erd

ROTXR.L #2,ERd L 1 3 7 0 erd

RTE RTE —5670

RTS RTS —5470

SHAL SHAL.B Rd B 1 0 8 rd

SHAL.B #2,Rd B 1 0 C rd

SHAL.W Rd W 1 0 9 rd

SHAL.W #2,Rd W 1 0 D rd

SHAL.L ERd L 1 0 B 0 erd

SHAL.L #2,ERd L 1 0 F 0 erd

SHAR SHAR.B Rd B 1 1 8 rd

SHAR.B #2,Rd B 1 1 C rd

SHAR.W Rd W 1 1 9 rd

SHAR.W #2,Rd W 1 1 D rd

SHAR.L ERd L 1 1 B 0 erd

SHAR.L #2,ERd L 1 1 F 0 erd

SHLL SHLL.B Rd B 1 0 0 rd

SHLL.B #2,Rd B 1 0 4 rd

SHLL.W Rd W 1 0 1 rd

SHLL.W #2,Rd W 1 0 5 rd

SHLL.L ERd L 1 0 3 0 erd

SHLL.L #2,ERd L 1 0 7 0 erd

SHLR SHLR.B Rd B 1 1 0 rd

SHLR.B #2,Rd B 1 1 4 rd

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Instruction Format

Instruction Mnemonic Size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

SHLR SHLR.W Rd W 1 1 1 rd

SHLR.W #2,Rd W 1 1 5 rd

SHLR.L ERd L 1 1 3 0 erd

SHLR.L #2,ERd L 1 1 7 0 erd

SLEEP SLEEP —0180

STC STC.B CCR,Rd B 0 2 0 rd

STC.B EXR,Rd B 0 2 1 rd

STC.W CCR,@ERd W 0 1 4 0 6 9 1 erd 0

STC.W EXR,@ERd W 0 1 4 1 6 9 1 erd 0

STC.W CCR,@(d:16,ERd) W 0 1 4 0 6 F 1 erd 0 disp

STC.W EXR,@(d:16,ERd) W 0 1 4 1 6 F 1 erd 0 disp

STC.W CCR,@(d:32,ERd) W 0 1 4 0 7 8 0 erd 0 6 B A 0 disp

STC.W EXR,@(d:32,ERd) W 0 1 4 1 7 8 0 erd 0 6 B A 0 disp

STC.W CCR,@–ERd W 0 1 4 0 6 D 1 erd 0

STC.W EXR,@–ERd W 0 1 4 1 6 D 1 erd 0

STC.W CCR,@aa:16 W 0 1 4 0 6 B 8 0 abs

STC.W EXR,@aa:16 W 0 1 4 1 6 B 8 0 abs

STC.W CCR,@aa:32 W 0 1 4 0 6 B A 0 abs

STC.W EXR,@aa:32 W 0 1 4 1 6 B A 0 abs

STM

STM.L (ERn–ERn+1),@–SP

L01106DF0ern

STM.L (ERn–ERn+2),@–SP

L01206DF0ern

STM.L (ERn–ERn+3),@–SP

L01306DF0ern

STMAC*1STMAC MACH,ERd L 0 2 2 0 ers

STMAC MACL,ERd L 0 2 3 0 ers

SUB SUB.B Rs,Rd B 1 8 rs rd

SUB.W #xx:16,Rd W 7 9 3 rd IMM

SUB.W Rs,Rd W 1 9 rs rd

SUB.L #xx:32,ERd L 7 A 3 0 erd IMM

SUB.L ERs,ERd L 1 A 1 ers 0 erd

SUBS SUBS #1,ERd L 1 B 0 0 erd

SUBS #2,ERd L 1 B 8 0 erd

SUBS #4,ERd L 1 B 9 0 erd

SUBX SUBX #xx:8,Rd B B rd IMM

SUBX Rs,Rd B 1 E rs rd

TAS TAS @ERd*

B0 1 E 0 7 B 0 erd C

TRAPA TRAPA #x:2 —57

00 IMM

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Instruction Format

Instruction Mnemonic Size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte

Legend:

IMM: Immediate data (2, 3, 8, 16, or 32 bits)

abs: Absolute address (8, 16, 24, or 32 bits)

disp: Displacement (8, 16, or 32 bits)

rs, rd, rn: Register field (4 bits specifying an 8-bit or 16-bit register. The symbols rs, rd, and rn correspond to operand symbols Rs, Rd,

and Rn.)

ers, erd, ern, erm: Register field (3 bits specifying an address register or 32-bit register. The symbols ers, erd, ern, and erm correspond to operand

symbols ERs, ERd, ERn, and ERm.)

The register fields specify general registers as follows.

Address Register

32-Bit Register 16-Bit Register 8-Bit Register

Field Register Field Register Field Register

000 ER0 0000 R0 0000 R0H

001 ER1 0001 R1 0001 R1H

·· · · · ·

111 ER7 0111 R7 0111 R7H

1000 E0 1000 R0L

1001 E1 1001 R1L

·· ··

1111 E7 1111 R7L

XOR XOR.B #xx:8,Rd B D rd IMM

XOR.B Rs,Rd B 1 5 rs rd

XOR.W #xx:16,Rd W 7 9 5 rd IMM

XOR.W Rs,Rd W 6 5 rs rd

XOR.L #xx:32,ERd L 7 A 5 0 erd IMM

XOR.L ERs,ERd L 0 1 F 0 6 5 0 ers 0 erd

XORC XORC #xx:8,CCR B 0 5 IMM

XORC #xx:8,EXR B 014105 IMM

Notes: 1. These instructions are supported by the H8S/2600 CPU only.

2. Bit 7 of the 4th byte of the MOV.L ERs, @(d:32,ERd) instruction can be either 1 or 0.

3. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

Section 2 Instruction Descriptions

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2.5 Operation Code Map

Table 2.3 shows an operation code map.

Table 2.3 Operation Code Map (1)

NOP

Table 2.3 (2)

BRA

MULXU

BSET

Note: * These instructions are supported by the H8S/2600 CPU only.

Table 2.3 (2)

BRN

DIVXU

BNOT

Table 2.3 (2)

BHI

MULXU

BCLR

Table 2.3 (2)

BLS

DIVXU

BTST

ORC

BCC

RTS

XORC

XOR

BCS

BSR

XOR

ANDC

AND

BNE

RTE

AND

LDC

Table 2.3 (2)

BEQ

TRAPA

BVC

Table 2.3 (2)

MOV

BVS

Table 2.3 (2)

BPL

JMP

Table 2.3 (2)

BMI

EEPMOV

MOV

CMP

BGE

BSR

MOV

BLT

ADDX

SUBX

BGT

JSR

Table 2.3 (2)

BLE

BOR BIOR

STC

STMAC

*LDC

LDMAC

BXOR

BIXOR BAND

BIAND

BST BIST

BLD BILD

Table 2.3 (3)

ADD

ADDX

CMP

SUBX

XOR

AND

MOV

Operation Code: 1st byte 2nd byte

AH AL BH BL

Instruction when most significant bit of BH is 0.

Instruction when most significant bit of BH is 1.

AH AL

ADD

SUB

MOV.B

MOV

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Table 2.3 Operation Code Map (2)

ADDS

BVS

Operation Code: 1st byte 2nd byte

AH AL BH BL

AH AL BH 0

MOV

INC

ADDS

DAA

DEC

SUBS

DAS

BRA

MOV

BRN

Table 2.3 (4)

ADD

BHI

MOV

CMP

SHLL

SHLR

ROTXL

ROTXR

NOT

BLS

Table 2.3 (4)

SUB

BCC

MOVFPE

INC

EXTU

DEC

BCS

XOR

MAC

BNE

AND

INC

SHLL

SHLR

ROTXL

ROTXR

EXTU

DEC

BEQ

SLEEP

BVC

MOV

CLRMAC

BPL

MOV

BMI

Table 2.3 (3)

BGE

MOVTPE

Table 2.3 (3)

INC

EXTS

DEC

BLT

TAS

BGT

Table 2.3 (3)

INC

SHAL

SHAR

ROTL

ROTR

EXTS

DEC

BLE

ADD

MOV

SUB

CMP

NEG

SHLL

SHLR

ROTXL

ROTXR

NOT

LDC STC

SHAL

SHAR

ROTL

ROTR

NEG

SUBS

LDM STM

SHAL

SHAR

ROTL

ROTR

Note: * These instructions are supported by the H8S/2600 CPU only.

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Table 2.3 Operation Code Map (3)

Operation Code: 1st byte 2nd byte

AH AL BH BL

3rd byte 4th byte

CH CL DH DL

01C05

01D05

01F06

7Cr06

7Cr07

7Dr06

7Dr07

7Eaa6

7Eaa7

7Faa6

7Faa7

AHALBHBLCH

CL 0

MULXS

BSET

DIVXS

BNOT

MULXS

BCLR

DIVXS

BTST

XOR

AND

789ABCDEF

BORBIOR BXOR

BIXOR BAND

BIAND BLD BILD

BST BIST

BORBIOR BXOR

BIXOR BAND

BIAND BLD BILD

BST BIST

The letter “r” indicates a register field.

The letters “aa” indicate an absolute address field.

Instruction when most significant bit of DH is 0.

Instruction when most significant bit of DH is 1.

Notes: 1.

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Table 2.3 Operation Code Map (4)

Operation Code: 1st byte 2nd byte

AH AL BH BL

3rd byte 4th byte

CH CL DH DL

6A10aaaa6

6A10aaaa7

6A18aaaa6

6A18aaaa7

AHALBHBLCHCLDHDLEH

EL 0123456789ABCDEF

BORBIOR BXOR

BIXOR BAND

BIAND BLD BILD

BST BIST

Instruction when most significant bit of FH is 0.

Instruction when most significant bit of FH is 1.

BTST

BSET BNOT BCLR

5th byte 6th byte

EH EL FH FL

Operation Code: 1st byte 2nd byte

AH AL BH BL

3rd byte 4th byte

CH CL DH DL

6A30aaaaaaaa6

6A30aaaaaaaa7

6A38aaaaaaaa6

6A38aaaaaaaa7

AHALBHBL ... FHFLGH

EL 0123456789ABCDEF

BORBIOR BXOR

BIXOR BAND

BIAND BLD BILD

BST BIST

The letters “aa” indicate an absolute address field.

Instruction when most significant bit of HH is 0.

Instruction when most significant bit of HH is 1.

Note: *

BTST

BSET BNOT BCLR

5th byte 6th byte

EH EL FH FL

7th byte 8th byte

GH GL HH HL

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2.6 Number of States Required for Instruction Execution

The tables in this section can be used to calculate the number of states required for instruction

execution by the CPU. Table 2.5 indicates the number of instruction fetch, data read/write, and

other cycles occurring in each instruction. Table 2.4 indicates the number of states required for

each cycle, depending on its size. The number of states required for each cycle depends on the

product. See the hardware manual named for the relevant product for details. The number of states

required for execution of an instruction can b e calculated f rom these two tables as follo ws:

Execution states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN

Examples: Advanced mode, program code and stack located in external memory, on-chip

supporting modules accessed in two states with 8-bit bus width, external devices accessed in three

states with one wait state and 16-bit bus width.

1. BSET #0, @FFFFC7:8

From table 2.5:

I = L = 2, J = K = M = N= 0

From table 2.4:

SI = 4, SL = 2

Number of states required for execution = 2 × 4 + 2 × 2 = 12

2. JSR @@30

From table 2.5:

I = J = K = 2, L = M = N = 0

From table 2.4:

SI = SJ = SK = 4

Number of states required for execution = 2 × 4 + 2 × 4 + 2 × 4 = 24

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Table 2.4 Number of States per Cycle

Access Conditions

External Device

On-Chip Supporting

Module 8-Bit Bus 16-Bit Bus

Cycle On-Chip

Memory 8-Bit

Bus 16-Bit

Bus 2-State

Access 3-State

Access 2-State

Access 3-State

Access

Instruction fetch SI

Branch address read SJ

Stack operati on SK

2n 4 6 + 2m

Byte data access SLn23 + m

Word data access SM

46 + 2m

23 + m*

Internal operat i on SN1111111

Note: *For the MOVFPE and MOVTPE instructions, refer to the relevant microcontroller hardware

manual.

Legend:

m: Number of wait states inserted into external device access

n: Number of states required for access to an on-chip supporting module. For the specific number,

refer to the relevant microcontroller hardware manual.

Section 2 Instruction Descriptions

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Table 2.5 Number of Cycles in Instruction Execution

Instruction

Fetch

Branch

Address

Read Stack

Operation Byte Data

Access Word Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

ADD ADD.B #xx:8,Rd 1

ADD.B Rs,Rd 1

ADD.W #xx:16,Rd 2

ADD.W Rs,Rd 1

ADD.L #xx:32,ERd 3

ADD.L ERs,ERd 1

ADDS ADDS #1/2/4,ERd 1

ADDX ADDX #xx:8,Rd 1

ADDX Rs,Rd 1

AND AND.B #xx:8,Rd 1

AND.B Rs,Rd 1

AND.W #xx:16,Rd 2

AND.L #xx:32,ERd 3

AND.L ERs,ERd 2

ANDC ANDC #xx:8,CCR 1

ANDC #xx:8,EXR 2

BAND BAND #xx:3,Rd 1

BAND #xx:3,@ERd 2 1

BAND #xx:3,@aa:8 2 1

BAND #xx:3,@aa:16 3 1

BAND #xx:3,@aa:32 4 1

Bcc BRA d:8 (BT d:8) 2

BRN d:8 (BF d:8) 2

BHI d:8 2

BLS d:8 2

BCC d:8 (BHS d:8) 2

BCS d:8 (BLO d:8) 2

BNE d:8 2

BEQ d:8 2

BVC d:8 2

BVS d:8 2

BPL d:8 2

BMI d:8 2

BGE d:8 2

BLT d:8 2

BGT d:8 2

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Instruction

Fetch

Branch

Address

Read Stack

Operation Byte Data

Access Word Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

Bcc BLE d:8 2

BRA d:16 (BT d:16) 2 1

BRN d:16 (BF d:16) 2 1

BHI d:16 2 1

BLS d:16 2 1

BCC d:16 (BHS d:16) 2 1

BCS d:16 (BLO d:16) 2 1

BNE d:16 2 1

BEQ d:16 2 1

BVC d:16 2 1

BVS d:16 2 1

BPL d:16 2 1

BMI d:16 2 1

BGE d:16 2 1

BLT d:16 2 1

BGT d:16 2 1

BLE d:16 2 1

BCLR BCLR #xx:3,Rd 1

BCLR #xx:3,@ERd 2 2

BCLR #xx:3,@aa:8 2 2

BCLR #xx:3,@aa:16 3 2

BCLR #xx:3,@aa:32 4 2

BCLR Rn,Rd 1

BCLR Rn,@ERd 2 2

BCLR Rn,@aa:8 2 2

BCLR Rn,@aa:16 3 2

BCLR Rn,@aa:32 4 2

BIAND BIAND #xx:3,Rd 1

BIAND #xx:3,@ERd 2 1

BIAND #xx:3,@aa:8 2 1

BIAND #xx:3,@aa:16 3 1

BIAND #xx:3,@aa:32 4 1

BILD BILD #xx:3,Rd 1

BILD #xx:3,@ERd 2 1

BILD #xx:3,@aa:8 2 1

BILD #xx :3,@aa:16 3 1

BILD #xx :3,@aa:32 4 1

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Instruction

Fetch

Branch

Address

Read Stack

Operation Byte Data

Access Word Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

BIOR BIOR #xx:8,Rd 1

BIOR #xx:8,@ERd 2 1

BIOR #xx:8,@aa:8 2 1

BIOR #xx:8,@aa:16 3 1

BIOR #xx:8,@aa:32 4 1

BIST BIST #xx:3,Rd 1

BIST #xx:3,@ERd 2 2

BIST #xx:3,@aa:8 2 2

BIST #xx:3,@ aa:16 3 2

BIST #xx:3,@ aa:32 4 2

BIXOR BIXOR #xx:3,Rd 1

BIXOR #xx:3,@ERd 2 1

BIXOR #xx:3,@aa:8 2 1

BIXOR #xx:3,@aa:16 3 1

BIXOR #xx:3,@aa:32 4 1

BLD BLD #xx:3,Rd 1

BLD #xx:3,@ERd 2 1

BLD #xx:3,@aa:8 2 1

BLD #xx:3,@aa:16 3 1

BLD #xx:3,@aa:32 4 1

BNOT BNOT #xx:3,Rd 1

BNOT #xx:3,@ER d 2 2

BNOT #xx:3,@aa:8 2 2

BNOT #xx:3,@aa:16 3 2

BNOT #xx:3,@aa:32 4 2

BNOT Rn,Rd 1

BNOT Rn,@ERd 2 2

BNOT Rn,@aa:8 2 2

BNOT Rn,@aa:16 3 2

BNOT Rn,@aa:32 4 2

BOR BOR #xx:3,Rd 1

BOR #xx:3,@ERd 2 1

BOR #xx:3,@aa:8 2 1

BOR #xx:3,@aa:16 3 1

BOR #xx:3,@aa:32 4 1

BSET BSET #xx:3,Rd 1

BSET #xx:3, @ERd 2 2

BSET #xx:3,@aa:8 2 2

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Instruction

Fetch

Branch

Address

Read Stack

Operation Byte Data

Access Word Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

BSET BSET #xx:3,@aa:16 3 2

BSET #xx:3,@aa:32 4 2

BSET Rn,Rd 1

BSET Rn,@ERd 2 2

BSET Rn,@aa:8 2 2

BSET Rn,@aa:16 3 2

BSET Rn,@aa:32 4 2

BSR BSR d:8 Normal 2 1

Advanced 2 2

BSR d:16 Normal 2 1 1

Advanced 2 2 1

BST BST #xx:3,Rd 1

BST #xx:3,@ERd 2 2

BST #xx:3,@aa:8 2 2

BST #xx:3,@aa:16 3 2

BST #xx:3,@aa:32 4 2

BTST BTST #xx:3,Rd 1

BTST #xx:3,@ERd 2 1

BTST #xx:3,@ aa: 8 2 1

BTST #xx:3,@ aa: 16 3 1

BTST #xx:3,@ aa: 32 4 1

BTST Rn,Rd 1

BTST Rn,@ERd 2 1

BTST Rn,@aa:8 2 1

BTST Rn,@aa:16 3 1

BTST Rn,@aa:32 4 1

BXOR BXOR #xx:3,Rd 1

BXOR #xx:3,@ERd 2 1

BXOR #xx:3,@aa:8 2 1

BXOR #xx:3,@aa:16 3 1

BXOR #xx:3,@aa:32 4 1

CLRMAC*5CLRMAC 1 1*3 *6

CMP CMP.B #xx:8,Rd 1

CMP.B Rs,Rd 1

CMP.W #xx:16,Rd 2

CMP.W Rs,Rd 1

CMP.L #xx:32 ,E Rd 3

CMP.L ERs,ERd 1

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Instruction

Fetch

Branch

Address

Read Stack

Operation Byte Data

Access Word Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

DAA DAA Rd 1

DAS DAS Rd 1

DEC DEC.B Rd 1

DEC.W #1/2,Rd 1

DEC.L #1/2,ERd 1

DIVXS DIVXS.B Rs,Rd 2 11

DIVXS.W Rs,ERd 2 19

DIVXU DIVXU.B Rs,Rd 1 11

DIVXU.W Rs,ERd 1 19

EEPMOV EEPMOV.B 2 2n + 2*1

EEPMOV.W 2 2n + 2*1

EXTS EXTS.W Rd 1

EXTS.L ERd 1

EXTU EXTU.W Rd 1

EXTU.L ERd 1

INC INC.B Rd 1

INC.W #1/2,Rd 1

INC.L #1/2,E R d 1

JMP JMP @ERn 2

JMP @aa:24 2 1

JMP @@aa:8 Normal 2 1 1

Advanced 2 2 1

JSR JSR @ERn Normal 2 1

Advanced 2 2

JSR @aa:24 Normal 2 1 1

Advanced 2 2 1

JSR @@aa:8 Normal 2 1 1

Advanced 2 2 2

LDC LDC #xx:8,CCR 1

LDC #xx:8,EXR 2

LDC Rs,CCR 1

LDC Rs,EXR 1

LDC @ERs,CCR 2 1

LDC @ERs,EXR 2 1

LDC @(d:16,ERs),CCR 3 1

LDC @(d:16,ERs),EXR 3 1

LDC @(d:32,ERs),CCR 5 1

LDC @(d:32,ERs),EXR 5 1

Section 2 Instruction Descriptions

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Instruction

Fetch

Branch

Address

Read Stack

Operation Byte Data

Access Word Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

LDC LDC @ERs+,CCR 2 1 1

LDC @ERs+,EXR 2 1 1

LDC @aa:16,CCR 3 1

LDC @aa:16,EXR 3 1

LDC @aa:32,CCR 4 1

LDC @aa:32,EXR 4 1

LDM LDM.L @SP+,(ERn–ERn+1) 2 4 1

LDM.L @SP+,(ERn–ERn+2) 2 6 1

LDM.L @SP+,(ERn–ERn+3) 2 8 1

LDMAC*5LDMAC ERs,MACH 1 1*3 *6

LDMAC ERs,MACL 1 1*3 *6

MAC*5MAC @ERn+,@ERm+ 2 2

MOV MOV.B #xx:8,Rd 1

MOV.B Rs,Rd 1

MOV.B @ERs,Rd 1 1

MOV.B @(d:16,ERs),Rd 2 1

MOV.B @(d:32,ERs),Rd 4 1

MOV.B @ERs+,Rd 1 1 1

MOV.B @aa:8,Rd 1 1

MOV.B @aa:16,Rd 2 1

MOV.B @aa:32,Rd 3 1

MOV.B Rs,@ERd 1 1

MOV.B Rs,@(d:16,ERd) 2 1

MOV.B Rs,@(d:32,ERd) 4 1

MOV.B Rs,@–ERd 1 1 1

MOV.B Rs,@aa: 8 1 1

MOV.B Rs,@aa: 16 2 1

MOV.B Rs,@aa: 32 3 1

MOV.W #xx:16,Rd 2

MOV.W Rs,Rd 1

MOV.W @ERs ,R d 1 1

MOV.W @(d:16,ERs),Rd 2 1

MOV.W @(d:32,ERs),Rd 4 1

MOV.W @ERs+,Rd 1 1 1

MOV.W @aa:16,Rd 2 1

MOV.W @aa:32,Rd 3 1

MOV.W Rs,@ERd 1 1

Section 2 Instruction Descriptions

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Instruction

Fetch

Branch

Address

Read Stack

Operation Byte Data

Access Word Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

MOV MOV.W Rs,@(d: 16,E R d) 2 1

MOV.W Rs,@(d:32,E R d) 4 1

MOV.W Rs,@ –ERd 1 1 1

MOV.W Rs,@aa:16 2 1

MOV.W Rs,@aa:32 3 1

MOV.L #xx:32,ERd 3

MOV.L ERs,ERd 1

MOV.L @ERs,ERd 2 2

MOV.L @(d:16,ERs),ERd 3 2

MOV.L @(d:32,ERs),ERd 5 2

MOV.L @ERs+,ERd 2 2 1

MOV.L @aa:16,ERd 3 2

MOV.L @aa:32,ERd 4 2

MOV.L ERs,@ERd 2 2

MOV.L ERs,@(d:16,ERd) 3 2

MOV.L ERs,@(d:32,ERd) 5 2

MOV.L ERs,@–ERd 2 2 1

MOV.L ERs,@aa:16 3 2

MOV.L ERs,@aa:32 4 2

MOVFPE MOVFPE @:aa:16, Rd 2 1*2

MOVTPE MOVTPE Rs,@:aa:16 2 1*2

MULXS MULXS.B Rs,Rd H8S/2600 2 2*3 *6

H8S/2000 2 11

MULXS.W Rs,ERd H8S/2600 2 3*3 *6

H8S/2000 2 19

MULXU MULXU.B Rs,Rd H8S/2600 1 2*3 *6

H8S/2000 1 11

MULXU.W Rs,ERd H8S/2600 1 3*3 *6

H8S/2000 1 19

NEG NEG.B Rd 1

NEG.W Rd 1

NEG.L ERd 1

NOP NOP 1

NOT NOT.B Rd 1

NOT.W Rd 1

NOT.L ERd 1

Section 2 Instruction Descriptions

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REJ09B0139-0400

Instruction

Fetch

Branch

Address

Read Stack

Operation Byte Data

Access Word Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

OR OR.B #xx:8,Rd 1

OR.B Rs,Rd 1

OR.W #xx:16,Rd 2

OR.W Rs,Rd 1

OR.L #xx:32,ER d 3

OR.L ERs,ERd 2

ORC ORC #xx:8,CCR 1

ORC #xx:8,EXR 2

POP POP.W Rn 1 1 1

POP.L ERn 2 2 1

PUSH PUSH.W Rn 1 1 1

PUSH.L ERn 2 2 1

ROTL ROTL.B Rd 1

ROTL.B #2,Rd 1

ROTL.W Rd 1

ROTL.W #2,R d 1

ROTL.L ERd 1

ROTL.L #2,ERd 1

ROTR ROT R.B Rd 1

ROTR.B #2,Rd 1

ROTR.W Rd 1

ROTR.W #2,Rd 1

ROTR.L ERd 1

ROTR.L #2,ERd 1

ROTXL ROTXL.B Rd 1

ROTXL.B #2,Rd 1

ROTXL.W Rd 1

ROTXL.W #2,Rd 1

ROTXL.L ERd 1

ROTXL .L #2,E R d 1

ROTXR ROTXR.B Rd 1

ROTXR.B #2,Rd 1

ROTXR.W Rd 1

ROTXR.W #2,Rd 1

ROTXR.L ERd 1

ROTXR.L #2,ERd 1

RTE RTE 2 2/3*11

RTS RTS Normal 2 1 1

Advanced 2 2 1

Section 2 Instruction Descriptions

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REJ09B0139-0400

Instruction

Fetch

Branch

Address

Read Stack

Operation Byte Data

Access Word Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

SHAL SHAL.B Rd 1

SHAL.B #2,Rd 1

SHAL.W Rd 1

SHAL.W #2,Rd 1

SHAL.L ERd 1

SHAL.L #2,ERd 1

SHAR SHAR.B Rd 1

SHAR.B #2,Rd 1

SHAR.W Rd 1

SHAR.W #2,Rd 1

SHAR.L ERd 1

SHAR.L #2,ERd 1

SHLL SHLL.B Rd 1

SHLL.B #2,R d 1

SHLL.W Rd 1

SHLL.W #2, Rd 1

SHLL.L ERd 1

SHLL.L #2,ERd 1

SHLR SHLR.B Rd 1

SHLR.B #2,Rd 1

SHLR.W Rd 1

SHLR.W #2,R d 1

SHLR.L ERd 1

SHLR.L #2 ,ER d 1

SLEEP SLEEP 1 1

STC STC.B CCR,Rd 1

STC.B EXR,Rd 1

STC.W CCR,@ERd 2 1

STC.W EXR,@ERd 2 1

STC.W CCR,@(d:16,ERd) 3 1

STC.W EXR,@(d:16,ERd) 3 1

STC.W CCR,@(d:32,ERd) 5 1

STC.W EXR,@(d:32,ERd) 5 1

STC.W CCR,@–ERd 2 1 1

STC.W EXR,@–ERd 2 1 1

STC.W CCR,@aa:16 3 1

STC.W EXR,@aa:16 3 1

STC.W CCR,@aa:32 4 1

STC.W EXR,@aa:32 4 1

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REJ09B0139-0400

Instruction

Fetch

Branch

Address

Read Stack

Operation Byte Data

Access Word Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

STM STM.L (ERn–ERn+1),@–SP 2 4 1

STM.L(ERn–ERn+2),@–SP 2 6 1

STM.L(ERn–ERn+3),@–SP 2 8 1

STMAC*5STMAC MACH,ERd 1 0*3 *6

STMAC MACL,ERd 1 0*3 *6

SUB SUB.B Rs,Rd 1

SUB.W #xx:16,Rd 2

SUB.W Rs,Rd 1

SUB.L #xx:32,ERd 3

SUB.L ERs,ERd 1

SUBS SUBS #1/2/4,ERd 1

SUBX SUBX #xx:8,Rd 1

SUBX Rs,Rd 1

TAS TAS @ERd*422

TRAPA TRAPA #x:2 Normal 2 1 2/3*12

Advanced 2 2 2/3*12

XOR XOR.B #xx:8,Rd 1

XOR.B Rs,Rd 1

XOR.W #xx:16,Rd 2

XOR.W Rs,Rd 1

XOR.L #xx:32,E R d 3

XOR.L ERs,ERd 2

XORC XORC #xx:8,CCR 1

XORC XORC #xx:8,EXR 2

Notes: 1. 2 when EXR is invalid, 3 when EXR is valid.

2. 5 for concatenated execution, 4 otherwise.

3. An internal operation may require between 0 and 3 additional states, depending on the

preceding instruction.

4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

5. These instructions are supported by the H8S/2600 CPU only.

6. The number of states may differ depending on the product. For details, refer to the

relevant microcontroller hardware manual of the product in question.

Section 2 Instruction Descriptions

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2.7 Bus States During Instruction Execution

Table 2.6 indicates the types of cycles that occur during instruction execution by the CPU. See

table 2.4 for the number of states per cycle.

How to Read the Table:

Internal operation,

1 state

Order of execution

End of instruction

Read effective address (word-size read)

No read or write

Instruction12345678

JMP @aa:24 R:W 2nd R:W EA

Read 2nd word of current instruction

(word-size read)

Legend

R:B Byte-size read

R:W Word-size read

W:B Byte-size write

W:W Word-size write

2nd Address of 2nd word (3rd and 4th bytes)

3rd Address of 3rd wo rd (5th and 6th bytes)

4th Address of 4th word (7th and 8th bytes)

5th Address of 5th word (9th and 10th bytes)

NEXT Address of next instruction

EA Effective address

VEC Vector address

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 291 of 322

REJ09B0139-0400

Figure 2.1 shows timing waveforms for the address bus and the RD and WR (HWR or LWR)

signals during execution of the above instruction with an 8-bit bus, using three-state access with

no wait states.

Address bus

WR (HWR or

LWR)High level

Fetching

3rd byte

of instruction

Fetching

4th byte

of instruction

Fetching

1st byte of

instruction at

jump address

Fetching

2nd byte of

instruction at

jump address

R:W EAR:W 2nd Internal

operation

Figure 2.1 Address Bus, RD

RDRD

RD, and WR

WRWR

WR ( HWR

HWRHWR

HWR or LWR

LWRLWR

LWR) Timing

(8-Bit Bus, Three-State Access, No Wait States)

Section 2 Instruction Descriptions

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REJ09B0139-0400

Table 2.6 Instruction Execution Cycles

Instruction 1 2 3 4 5 6 7 8 9

ADD.B #xx:8,Rd R:W NEXT

ADD.B Rs,Rd R:W NEXT

ADD.W #xx:16,Rd R:W 2nd R:W NEXT

ADD.W Rs,Rd R:W NEXT

ADD.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT

ADD.L ERs,ERd R:W NEXT

ADDS #1/2/4,ERd R:W NEXT

ADDX #xx:8,Rd R:W NEXT

ADDX Rs,Rd R:W NEXT

AND.B #xx:8,Rd R:W NEXT

AND.B Rs,Rd R:W NEXT

AND.W #xx:16,Rd R:W 2nd R:W NEXT

AND.W Rs,Rd R:W NEXT

AND.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT

AND.L ERs,ERd R:W 2nd R:W NEXT

ANDC #xx:8,CCR R:W NEXT

ANDC #xx:8,EXR R:W 2nd R:W NEXT

BAND #xx:3,Rd R:W NEXT

BAND #xx:3,@ERd R:W 2nd R:B EA R:W NEXT

BAND #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT

BAND #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W NEXT

BAND #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W NEXT

BRA d:8 (BT d:8) R:W NEXT R:W EA

BRN d:8 (BF d:8) R:W NEXT R:W EA

BHI d:8 R:W NEXT R:W EA

BLS d:8 R:W NEXT R:W EA

BCC d:8 (BHS d:8) R:W NEXT R:W EA

BCS d:8 (BLO d:8) R:W NEXT R:W EA

BNE d:8 R:W NEXT R:W EA

BEQ d:8 R:W NEXT R:W EA

BVC d:8 R:W NEXT R:W EA

BVS d:8 R:W NEXT R:W EA

BPL d:8 R:W NEXT R:W EA

BMI d:8 R:W NEXT R:W EA

BGE d:8 R:W NEXT R:W EA

BLT d:8 R:W NEXT R:W EA

BGT d:8 R:W NEXT R:W EA

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 293 of 322

REJ09B0139-0400

Instruction 123456789

BLE d:8 R:W NEXT R:W EA

BRA d:16 (BT d:16) R:W 2nd Internal operation, R:W EA

1 state

BRN d:16 (BF d:16) R:W 2nd Internal operation, R:W EA

1 state

BHI d:16 R:W 2nd Internal operation, R:W EA

1 state

BLS d:16 R:W 2nd Internal operation, R:W EA

1 state

BCC d:16 (BHS d:16) R:W 2nd Internal operation, R:W EA

1 state

BCS d:16 (BLO d:16) R:W 2nd Internal operation, R:W EA

1 state

BNE d:16 R:W 2nd Internal operation, R:W EA

1 state

BEQ d:16 R:W 2nd Internal operation, R:W EA

1 state

BVC d:16 R:W 2nd Internal operation, R:W EA

1 state

BVS d:16 R:W 2nd Internal operation, R:W EA

1 state

BPL d:16 R:W 2nd Internal operation, R:W EA

1 state

BMI d:16 R:W 2nd Internal operation, R:W EA

1 state

BGE d:16 R:W 2nd Internal operation, R:W EA

1 state

BLT d:16 R:W 2nd Internal operation, R:W EA

1 state

BGT d:16 R:W 2nd Internal operation, R:W EA

1 state

BLE d:16 R:W 2nd Internal operation, R:W EA

1 state

BCLR #xx:3,Rd R:W NEXT

BCLR #xx:3,@ERd R:W 2nd R:B EA R:W NEXT W:B EA

BCLR #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT W:B EA

BCLR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W NEXT W:B EA

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 294 of 322

REJ09B0139-0400

Instruction 123456789

BCLR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W NEXT W:B EA

BCLR Rn,Rd R:W NEXT

BCLR Rn,@ERd R:W 2nd R:B EA R:W NEXT W:B EA

BCLR Rn,@aa:8 R:W 2nd R:B EA R:W NEXT W:B EA

BCLR Rn,@aa:16 R:W 2nd R:W 3rd R:B EA R:W NEXT W:B EA

BCLR Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W NEXT W:B EA

BIAND #xx:3,Rd R:W NEXT

BIAND #xx:3,@ERd R:W 2nd R:B EA R:W NEXT

BIAND #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT

BIAND #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W NEXT

BIAND #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W NEXT

BILD #xx:3,Rd R:W NEXT

BILD #xx:3,@ERd R:W 2nd R:B EA R:W NEXT

BILD #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT

BILD #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W NEXT

BILD #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W NEXT

BIOR #xx:3,Rd R:W NEXT

BIOR #xx:3,@ERd R:W 2nd R:B EA R:W NEXT

BIOR #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT

BIOR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W NEXT

BIOR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W NEXT

BIST #xx:3,Rd R:W NEXT

BIST #xx:3,@ERd R:W 2nd R:B EA R:W NEXT W:B EA

BIST #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT W:B EA

BIST #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W NEXT W:B EA

BIST #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W NEXT W:B EA

BIXOR #xx:3,Rd R:W NEXT

BIXOR #xx:3,@ERd R:W 2nd R:B EA R:W NEXT

BIXOR #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT

BIXOR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W NEXT

BIXOR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W NEXT

BLD #xx:3,Rd R:W NEXT

BLD #xx:3,@ERd R:W 2nd R:B EA R:W NEXT

BLD #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT

BLD #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W NEXT

BLD #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W NEXT

BNOT #xx:3,Rd R:W NEXT

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 295 of 322

REJ09B0139-0400

Instruction 123456789

BNOT #xx:3,@ERd R:W 2nd R:B EA R:W NEXT W:B EA

BNOT #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT W:B EA

BNOT #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W NEXT W:B EA

BNOT #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W NEXT W:B EA

BNOT Rn,Rd R:W NEXT

BNOT Rn,@ERd R:W 2nd R:B EA R:W NEXT W:B EA

BNOT Rn,@aa:8 R:W 2nd R:B EA R:W NEXT W:B EA

BNOT Rn,@aa:16 R:W 2nd R:W 3rd R:B EA R:W NEXT W:B EA

BNOT Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W NEXT W:B EA

BOR #xx:3,Rd R:W NEXT

BOR #xx:3,@ERd R:W 2nd R:B EA R:W NEXT

BOR #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT

BOR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W NEXT

BOR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W NEXT

BSET #xx:3,Rd R:W NEXT

BSET #xx:3,@ERd R:W 2nd R:B EA R:W NEXT W:B EA

BSET #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT W:B EA

BSET #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W NEXT W:B EA

BSET #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W NEXT W:B EA

BSET Rn,Rd R:W NEXT

BSET Rn,@ERd R:W 2nd R:B EA R:W NEXT W:B EA

BSET Rn,@aa:8 R:W 2nd R:B EA R:W NEXT W:B EA

BSET Rn,@aa:16 R:W 2nd R:W 3rd R:B EA R:W NEXT W:B EA

BSET Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W NEXT W:B EA

BSR d:8 Normal R:W NEXT R:W EA W:W stack

Advanced R:W NEXT R:W EA W:W stack (H) W:W stack (L)

BSR d:16 Normal R:W 2nd Internal operation, R:W EA W:W stack

1 state

Advanced R:W 2nd Internal operation, R:W EA W:W stack (H) W:W stack (L)

1 state

BST #xx:3,Rd R:W NEXT

BST #xx:3,@ERd R:W 2nd R:B EA R:W NEXT W:B EA

BST #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT W:B EA

BST #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W NEXT W:B EA

BST #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W NEXT W:B EA

BTST #xx:3,Rd R:W NEXT

BTST #xx:3,@ERd R:W 2nd R:B EA R:W NEXT

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 296 of 322

REJ09B0139-0400

Instruction 123456789

BTST #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT

BTST #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W NEXT

BTST #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W NEXT

BTST Rn,Rd R:W NEXT

BTST Rn,@ERd R:W 2nd R:B EA R:W NEXT

BTST Rn,@aa:8 R:W 2nd R:B EA R:W NEXT

BTST Rn,@aa:16 R:W 2nd R:W 3rd R:B EA R:W NEXT

BTST Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W NEXT

BXOR #xx:3,Rd R:W NEXT

BXOR #xx:3,@ERd R:W 2nd R:B EA R:W NEXT

BXOR #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT

BXOR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W NEXT

BXOR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W NEXT

CLRMAC*R:W NEXT Internal operation,

1 state*

CMP.B #xx:8,Rd R:W NEXT

CMP.B Rs,Rd R:W NEXT

CMP.W #xx:16,Rd R:W 2nd R:W NEXT

CMP.W Rs,Rd R:W NEXT

CMP.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT

CMP.L ERs,ERd R:W NEXT

DAA Rd R:W NEXT

DAS Rd R:W NEXT

DEC.B Rd R:W NEXT

DEC.W #1/2,Rd R:W NEXT

DEC.L #1/2,ERd R:W NEXT

DIVXS.B Rs,Rd R:W 2nd R:W NEXT Internal operation, 11 states

DIVXS.W Rs,ERd R:W 2nd R:W NEXT Internal operation, 19 states

DIVXU.B Rs,Rd R:W NEXT Internal operation, 11 states

DIVXU.W Rs,ERd R:W NEXT Internal operation, 19 states

EEPMOV.B R:W 2nd R:B EAs

R:B EAd

R:B EAs

W:B EAd

R:W NEXT

EEPMOV.W R:W 2nd R:B EAs

R:B EAd

R:B EAs

W:B EAd

R:W NEXT

EXTS.W Rd R:W NEXT ← Repeated n times

→

EXTS.L ERd R:W NEXT

EXTU.W Rd R:W NEXT

EXTU.L ERd R:W NEXT

INC.B Rd R:W NEXT

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 297 of 322

REJ09B0139-0400

Instruction 123456789

INC.W #1/2,Rd R:W NEXT

INC.L #1/2,ERd R:W NEXT

JMP @ERn R:W NEXT R:W EA

JMP @aa:24 R:W 2nd Internal operation, R:W EA

1 state

JMP @@aa:8 Normal R:W NEXT R:W aa:8 Internal operation, R:W EA

1 state

Advanced R:W NEXT R:W aa:8 (H) R:W aa:8 (L) Internal operation, R:W EA

1 state

JSR @ERn Normal R:W NEXT R:W EA W:W stack

Advanced R:W NEXT R:W EA W:W stack (H) W:W stack (L)

JSR @aa:24 Normal R:W 2nd Internal operation, R:W EA W:W stack

1 state

Advanced R:W 2nd Internal operation, R:W EA W:W stack (H) W:W stack (L)

1 state

JSR @@aa:8 Normal R:W NEXT R:W aa:8 W:W stack R:W EA

Advanced R:W NEXT R:W aa:8 (H) R:W aa:8 (L) W:W stack (H) W:W stack (L) R:W EA

LDC #xx:8,CCR R:W NEXT

LDC #xx:8,EXR R:W 2nd R:W NEXT

LDC Rs,CCR R:W NEXT

LDC Rs,EXR R:W NEXT

LDC @ERs,CCR R:W 2nd R:W NEXT R:W EA

LDC @ERs,EXR R:W 2nd R:W NEXT R:W EA

LDC @(d:16,ERs),CCR R:W 2nd R:W 3rd R:W NEXT R:W EA

LDC @(d:16,ERs),EXR R:W 2nd R:W 3rd R:W NEXT R:W EA

LDC @(d:32,ERs),CCR R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT R:W EA

LDC @(d:32,ERs),EXR R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT R:W EA

LDC @ERs+,CCR R:W 2nd R:W NEXT Internal operation, R:W EA

1 state

LDC @ERs+,EXR R:W 2nd R:W NEXT Internal operation, R:W EA

1 state

LDC @aa:16,CCR R:W 2nd R:W 3rd R:W NEXT R:W EA

LDC @aa:16,EXR R:W 2nd R:W 3rd R:W NEXT R:W EA

LDC @aa:32,CCR R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA

LDC @aa:32,EXR R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA

LDM.L @SP+,(ERn–ERn+1) R:W 2nd R:W NEXT Internal operation,

R:W stack (H)

R:W stack (L)

1 state

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 298 of 322

REJ09B0139-0400

Instruction 123456789

LDM.L @SP+,(ERn–ERn+2) R:W 2nd R:W NEXT Internal operation,

R:W stack (H)

R:W stack (L)

1 state

LDM.L @SP+,(ERn–ERn+3) R:W 2nd R:W NEXT Internal operation,

R:W stack (H)

R:W stack (L)

1 state

LDMAC ERs,MACH

*11

R:W NEXT Internal operation, ← Repeated n times

→

1 state*

LDMAC ERs,MACL

*11

R:W NEXT Internal operation,

1 state*

MAC @ERn+,@ERm+

*11

R:W 2nd R:W NEXT R:W EAn R:W EAm

MOV.B #xx:8,Rd R:W NEXT

MOV.B Rs,Rd R:W NEXT

MOV.B @ERs,Rd R:W NEXT R:B EA

MOV.B @(d:16,ERs),Rd R:W 2nd R:W NEXT R:B EA

MOV.B @(d:32,ERs),Rd R:W 2nd R:W 3rd R:W 4th R:W NEXT R:B EA

MOV.B @ERs+,Rd R:W NEXT Internal operation, R:B EA

1 state

MOV.B @aa:8,Rd R:W NEXT R:B EA

MOV.B @aa:16,Rd R:W 2nd R:W NEXT R:B EA

MOV.B @aa:32,Rd R:W 2nd R:W 3rd R:W NEXT R:B EA

MOV.B Rs,@ERd R:W NEXT W:B EA

MOV.B Rs,@(d:16,ERd) R:W 2nd R:W NEXT W:B EA

MOV.B Rs,@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W NEXT W:B EA

MOV.B Rs,@–ERd R:W NEXT Internal operation, W:B EA

1 state

MOV.B Rs,@aa:8 R:W NEXT W:B EA

MOV.B Rs,@aa:16 R:W 2nd R:W NEXT W:B EA

MOV.B Rs,@aa:32 R:W 2nd R:W 3rd R:W NEXT W:B EA

MOV.W #xx:16,Rd R:W 2nd R:W NEXT

MOV.W Rs,Rd R:W NEXT

MOV.W @ERs,Rd R:W NEXT R:W EA

MOV.W @(d:16,ERs),Rd R:W 2nd R:W NEXT R:W EA

MOV.W @(d:32,ERs),Rd R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA

MOV.W @ERs+, Rd R:W NEXT Internal operation, R:W EA

1 state

MOV.W @aa:16,Rd R:W 2nd R:W NEXT R:W EA

MOV.W @aa:32,Rd R:W 2nd R:W 3rd R:W NEXT R:B EA

MOV.W Rs,@ERd R:W NEXT W:W EA

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 299 of 322

REJ09B0139-0400

MOV.W Rs,@(d:16,ERd) R:W 2nd R:W NEXT W:W EA

MOV.W Rs,@(d:32,ERd) R:W 2nd R:W 3rd R:E 4th R:W NEXT W:W EA

MOV.W Rs,@aa:16 R:W 2nd R:W NEXT W:W EA

MOV.W Rs,@aa:32 R:W 2nd R:W 3rd R:W NEXT W:W EA

MOV.W Rs,@–ERd R:W NEXT Internal operation, W:W EA

1 state

MOV.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT

MOV.L ERs,ERd R:W NEXT

MOV.L @ERs,ERd R:W 2nd R:W NEXT R:W EA R:W EA+2

MOV.L @(d:16,ERs),ERd R:W 2nd R:W 3rd R:W NEXT R:W EA R:W EA+2

MOV.L @(d:32,ERs),ERd R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT R:W EA R:W EA+2

MOV.L @ERs+,ERd R:W 2nd R:W NEXT Internal operation, R:W EA R:W EA+2

1 state

MOV.L @aa:16,ERd R:W 2nd R:W 3rd R:W NEXT R:W EA R:W EA+2

MOV.L @aa:32,ERd R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA R:W EA+2

MOV.L ERs,@ERd R:W 2nd R:W NEXT W:W EA W:W EA+2

MOV.L ERs,@(d:16,ERd) R:W 2nd R:W 3rd R:W NEXT W:W EA W:W EA+2

MOV.L ERs,@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA W:W EA+2

MOV.L ERs,@–ERd R:W 2nd R:W NEXT Internal operation, W:W EA W:W EA+2

1 state

MOV.L ERs,@aa:16 R:W 2nd R:W 3rd R:W NEXT W:W EA W:W EA+2

MOV.L ERs,@aa:32 R:W 2nd R:W 3rd R:W 4th R:W NEXT W:W EA W:W EA+2

MOVFPE @aa:16,Rd R:W 2nd R:W NEXT R:W

MOVTPE Rs,@aa:16 R:W 2nd R:W NEXT W:B

MULXS.B Rs,Rd H8S/2600 R:W 2nd R:W NEXT Internal operation, 2 states

H8S/2000 R:W 2nd R:W NEXT Internal operation, 11 states

MULXS.W Rs,ERd H8S/2600 R:W 2nd R:W NEXT Internal operation, 3 states

H8S/2000 R:W 2nd R:W NEXT Internal operation, 19 states

MULXU.B Rs,Rd H8S/2600 R:W NEXT Internal operation, 2 states

H8S/2000 R:W NEXT Internal operation, 11 states

MULXU.W Rs,ERd H8S/2600 R:W NEXT Internal operation, 3 states

H8S/2000 R:W NEXT Internal operation, 19 states

NEG.B Rd R:W NEXT

NEG.W Rd R:W NEXT

NEG.L ERd R:W NEXT

NOP R:W NEXT

NOT.B Rd R:W NEXT

Instruction 123456789

Section 2 Instruction Descriptions

Rev. 4.00 Feb 24, 2006 page 300 of 322

REJ09B0139-0400

NOT.W Rd R:W NEXT

NOT.L ERd R:W NEXT

OR.B #xx:8,Rd R:W NEXT

OR.B Rs,Rd R:W NEXT

OR.W #xx:16,Rd R:W 2nd R:W NEXT

OR.W Rs,Rd R:W NEXT

OR.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT

OR.L ERs,ERd R:W 2nd R:W NEXT

ORC #xx:8,CCR R:W NEXT

ORC #xx:8,EXR R:W 2nd R:W NEXT

POP.W Rn R:W NEXT Internal operation, R:W EA

1 state

POP.L ERn R:W 2nd R:W NEXT Internal operation, R:W EA R:W EA+2

1 state

PUSH.W Rn R:W NEXT Internal operation, W:W EA

1 state

PUSH.L ERn R:W 2nd R:W NEXT Internal operation W:W EA W:W EA+2

ROTL.B Rd R:W NEXT

ROTL.B #2,Rd R:W NEXT

ROTL.W Rd R:W NEXT

ROTL.W #2,Rd R:W NEXT

ROTL.L ERd R:W NEXT

ROTL.L #2,ERd R:W NEXT

ROTR.B Rd R:W NEXT

ROTR.B #2,Rd R:W NEXT

ROTR.W Rd R:W NEXT

ROTR.W #2,Rd R:W NEXT

ROTR.L ERd R:W NEXT

ROTR.L #2,ERd R:W NEXT

ROTXL.B Rd R:W NEXT

ROTXL.B #2,Rd R:W NEXT

ROTXL.W Rd R:W NEXT

ROTXL.W #2,Rd R:W NEXT

ROTXL.L ERd R:W NEXT

ROTXL.L #2,ERd R:W NEXT

ROTXR.B Rd R:W NEXT

Instruction 1 23456789

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Instruction 123456789

ROTXR.B #2,Rd R:W NEXT

ROTXR.W Rd R:W NEXT

ROTXR.W #2,Rd R:W NEXT

ROTXR.L ERd R:W NEXT

ROTXR.L #2,ERd R:W NEXT

RTE R:W NEXT R:W stack (EXR) R:W stack (H) R:W stack (L) Internal operation, R:W *5

1 state

RTS Normal R:W NEXT R:W stack Internal operation, R:W *5

1 state

Advanced R:W NEXT R:W stack (H) R:W stack (L) Internal operation, R:W *5

1 state

SHAL.B Rd R:W NEXT

SHAL.B #2,Rd R:W NEXT

SHAL.W Rd R:W NEXT

SHAL.W #2,Rd R:W NEXT

SHAL.L ERd R:W NEXT

SHAL.L #2,ERd R:W NEXT

SHAR.B Rd R:W NEXT

SHAR.B #2,Rd R:W NEXT

SHAR.W Rd R:W NEXT

SHAR.W #2,Rd R:W NEXT

SHAR.L ERd R:W NEXT

SHAR.L #2,ERd R:W NEXT

SHLL.B Rd R:W NEXT

SHLL.B #2,Rd R:W NEXT

SHLL.W Rd R:W NEXT

SHLL.W #2,Rd R:W NEXT

SHLL.L ERd R:W NEXT

SHLL.L #2,ERd R:W NEXT

SHLR.B Rd R:W NEXT

SHLR.B #2,Rd R:W NEXT

SHLR.W Rd R:W NEXT

SHLR.W #2,Rd R:W NEXT

SHLR.L ERd R:W NEXT

SHLR.L #2,ERd R:W NEXT

SLEEP R:W NEXT

Internal operation,

1 state

STC CCR,Rd R:W NEXT

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STC EXR,Rd R:W NEXT

STC CCR,@ERd R:W 2nd R:W NEXT W:W EA

STC EXR,@ERd R:W 2nd R:W NEXT W:W EA

STC CCR,@(d:16,ERd) R:W 2nd R:W 3rd R:W NEXT W:W EA

STC EXR,@(d:16,ERd) R:W 2nd R:W 3rd R:W NEXT W:W EA

STC CCR,@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA

STC EXR,@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA

STC CCR,@–ERd R:W 2nd R:W NEXT Internal operation, W:W EA

1 state

STC EXR,@–ERd R:W 2nd R:W NEXT Internal operation, W:W EA

1 state

STC CCR,@aa:16 R:W 2nd R:W 3rd R:W NEXT W:W EA

STC EXR,@aa:16 R:W 2nd R:W 3rd R:W NEXT W:W EA

STC CCR,@aa:32 R:W 2nd R:W 3rd R:W 4th R:W NEXT W:W EA

STC EXR,@aa:32 R:W 2nd R:W 3rd R:W 4th R:W NEXT W:W EA

STM.L(ERn–ERn+1),@–SP R:W 2nd R:W NEXT Internal operation,

W:W stack (H)

W:W stack (L)

1 state

STM.L(ERn–ERn+2),@–SP R:W 2nd R:W NEXT Internal operation,

W:W stack (H)

W:W stack (L)

1 state

STM.L(ERn–ERn+3),@–SP R:W 2nd R:W NEXT Internal operation,

W:W stack (H)

W:W stack (L)

1 state

STMAC MACH,ERd

*11

R:W NEXT *9← Repeated n times

→

STMAC MACL,ERd

*11

R:W NEXT *9

SUB.B Rs,Rd R:W NEXT

SUB.W #xx:16,Rd R:W 2nd R:W NEXT

SUB.W Rs,Rd R:W NEXT

SUB.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT

SUB.L ERs,ERd R:W NEXT

SUBS #1/2/4,ERd R:W NEXT

SUBX #xx:8,Rd R:W NEXT

SUBX Rs,Rd R:W NEXT

TAS @ERd

*10

R:W 2nd R:W NEXT R:B EA W:B EA

TRAPA #x:2 Normal R:W NEXT Internal operation, W:W stack (L) W:W stack (H) W:W stack (EXR) R:W VEC Internal operation, R:W

1 state 1 state

Advanced R:W NEXT Internal operation, W:W stack (L) W:W stack (H) W:W stack (EXR) R:W VEC R:W VEC+2 Internal operation, R:W

1 state 1 state

XOR.B #xx8,Rd R:W NEXT

Instruction 123456789

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Instruction 123456789

XOR.B Rs,Rd R:W NEXT

XOR.W #xx:16,Rd R:W 2nd R:W NEXT

XOR.W Rs,Rd R:W NEXT

XOR.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT

XOR.L ERs,ERd R:W 2nd R:W NEXT

XORC #xx:8,CCR R:W NEXT

XORC #xx:8,EXR R:W 2nd R:W NEXT

Reset exception Normal R:W VEC Internal operation, R:W

handling 1 state

Advanced R:W VEC R:W VEC+2 Internal operation, R:W

1 state

Interrupt exception Normal R:W

Internal operation, W:W stack (L) W:W stack (H) W:W stack (EXR) R:W VEC Internal operation, R:W

handling 1 state 1 state

Advanced R:W

Internal operation, W:W stack (L) W:W stack (H) W:W stack (EXR) R:W:M VEC R:W VEC+2 Internal operation, R:W

1 state 1 state

Notes: 1. EAs is the contents of ER5. EAd is the contents of ER6.

2. EAs is the contents of ER5. EAd is the contents of ER6. Both registers are incremented by 1 after execution of the instruction. n is the initial

value of R4L or R4. If n = 0, these bus cycles are not executed.

3. Repeated two times to save or restore two registers, three times for three registers, or four times for four registers.

4. For the number of states required for byte-size read or write, refer to the relevant microcontroller hardware manual.

5. Start address after return.

6. Start address of the program.

7. Prefetch address, equal to two plus the PC value pushed onto the stack. In recovery from sleep mode or software standby mode the read

operation is replaced by an internal operation.

8. Start address of the interrupt-handling routine.

9. An internal operation may require between 0 and 3 additional states, depending on the preceding instruction.

10. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

11. These instructions are supported by the H8S/2600 CPU only.

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2.8 Condition Code Modification

This section ind icates th e effect of each CPU instruction on the condition code. The notation used

in the table is def ined below.

31 for longword operands

15 for word operands

m =

7 for byte operands

Si The i-th bit of the source operand

Di The i- th bit of the destination operand

Ri The i- th bit of the result

Dn The specified bit in the destination operand

— Not affected

↔

Modified according to the resu lt of th e in struction (see definition)

0 Always cleared to 0

1 A lways set to 1

* Undetermined (no guaranteed value)

Z' Z flag before instruction execution

C' C flag before instruction execution

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Table 2.7 Condition Code Modification

Instruction H N Z V C Definition

ADD H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4

N = Rm

Z = Rm · Rm–1 · ...... · R0

V = Sm · Dm · Rm + Sm · Dm · Rm

C = Sm · Dm + Dm · Rm + Sm · Rm

ADDS —————

ADDX H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4

N = Rm

Z = Z' · Rm · ...... · R0

V = Sm · Dm · Rm + Sm · Dm · Rm

C = Sm · Dm + Dm · Rm + Sm · Rm

AND — 0 — N = Rm

Z = Rm · Rm–1 · ...... · R0

ANDC Stores the corresponding bits of the result.

No flags change when the operand is EXR.

BAND ———— C = C' · Dn

Bcc —————

BCLR —————

BIAND ———— C = C' · Dn

BILD ———— C = Dn

BIOR ———— C = C' + Dn

BIST —————

BIXOR ———— C = C' · Dn + C' · Dn

BLD ———— C = Dn

BNOT—————

BOR ———— C = C' + Dn

BSET —————

BSR —————

BST —————

BTST —— —— Z = Dn

BXOR ———— C = C' · Dn + C' · Dn

CLRMAC*—————

CMP H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4

N = Rm

Z = Rm · Rm–1 · ... · R0

V = Sm · Dm · Rm + Sm · Dm · Rm

C = Sm · Dm + Dm · Rm + Sm · Rm

↔

↔↔

↔

↔↔↔↔↔↔↔↔↔

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Instruction H N Z V C Definition

DAA **N = Rm

Z = Rm · Rm–1· ...... · R0

C: decimal arithmetic carry

DAS **N = Rm

Z = Rm · Rm–1· ...... · R0

C: decimal arithmetic borrow

DEC ——N = Rm

Z = Rm · Rm–1· ...... · R0

V = Dm · Rm

DIVXS ———N = Sm · Dm + Sm · Dm

Z = Sm · Sm–1· ...... · S0

DIVXU ———N = Sm

Z = Sm · Sm–1· ...... · S0

EEPMOV —————

EXTS — 0 — N = Rm

Z = Rm · Rm–1· ...... · R0

EXTU — 00— Z = Rm · Rm–1· ...... · R0

INC ——N = Rm

Z = Rm · Rm–1· ...... · R0

V = Dm · Rm

JMP —————

JSR —————

LDC Stores the corresponding bits of the result.

No flags change when the operand is EXR.

LDM —————

LDMAC

—————

MAC

—————

MOV — 0 — N = Rm

Z = Rm · Rm–1· ...... · R0

MOVFPE — 0— N = Rm

Z = Rm · Rm–1· ...... · R0

MOVTPE — 0— N = Rm

Z = Rm · Rm–1· ...... · R0

MULXS ———N = R2m

Z = R2m · R2m–1· ...... · R0

↔

↔↔

↔

↔ ↔

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Instruction H N Z V C Definition

MULXU —————

NEG H = Dm–4 + Rm–4

N = Rm

Z = Rm · Rm–1· ...... · R0

V = Dm · Rm

C = Dm + Rm

NOP —————

NOT — 0 — N = Rm

Z = Rm · Rm–1· ...... · R0

OR — 0 — N = Rm

Z = Rm · Rm–1· ...... · R0

ORC Stores the corresponding bits of the result.

No flags change when the operand is EXR.

POP — 0 — N = Rm

Z = Rm · Rm–1· ...... · R0

PUSH — 0 — N = Rm

Z = Rm · Rm–1· ...... · R0

ROTL — 0 N = Rm

Z = Rm · Rm–1· ...... · R0

C = Dm (1-bit shift) or C = Dm–1 (2-bit shift)

ROTR —0 N = Rm

Z = Rm · Rm–1· ...... · R0

C = D0 (1-bit shift) or C = D1 (2-bit shift)

ROTXL — 0 N = Rm

Z = Rm · Rm–1· ...... · R0

C = Dm (1-bit shift) or C = Dm–1 (2-bit shift)

ROTXR — 0 N = Rm

Z = Rm · Rm–1· ...... · R0

C = D0 (1-bit shift) or C = D1 (2-bit shift)

RTE Stores the corresponding bits of the result.

RTS —————

SHAL —N = Rm

Z = Rm · Rm–1· ...... · R0

V = Dm · Dm–1+ Dm · Dm–1(1-bit shift)

V = Dm · Dm–1· Dm–2+ Dm · Dm–1· Dm–2(2-bit shift)

C = Dm (1-bit shift) or C = Dm–1 (2-bit shift)

↔

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Instruction H N Z V C Definition

SHAR — 0 N = Rm

Z = Rm · Rm–1· ...... · R0

C = D0 (1-bit shift) or C = D1 (2-bit shift)

SHLL — 0 N = Rm

Z = Rm · Rm–1· ...... · R0

C = Dm (1-bit shift) or C = Dm–1 (2-bit shift)

SHLR — 0 0 N = Rm

Z = Rm · Rm–1· ...... · R0

C = D0 (1-bit shift) or C = D1 (2-bit shift)

SLEEP —————

STC —————

STM —————

STMAC

——N = 1 if MAC instruction resulted in negative value in MAC register

Z = 1 if MAC instruction resulted in zero value in MAC register

V = 1 if MAC instruction resulted in overflow

SUB H = Sm–4 · Dm–4+ Dm–4· Rm–4 + Sm–4 · Rm–4

N = Rm

Z = Rm · Rm–1· ...... · R0

V = Sm · Dm · Rm + Sm · Dm · Rm

C = Sm · Dm + Dm · Rm + Sm · Rm

SUBS —————

SUBX H = Sm–4 · Dm–4+ Dm–4· Rm–4 + Sm–4 · Rm–4

N = Rm

Z = Z' · Rm · ...... · R0

V = Sm · Dm · Rm + Sm · Dm · Rm

C = Sm · Dm + Dm · Rm + Sm · Rm

TAS — 0— N = Dm

Z = Dm · Dm–1· ...... · D0

TRAPA —————

XOR —0— N = Rm

Z = Rm · Rm–1· ...... · R0

XORC Stores the corresponding bits of the result.

No flags change when the operand is EXR.

Note: *These instructions are supported by the H8S/2600 CPU only.

↔

↔↔

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Section 3 Processing States

3.1 Overview

The CPU has five main processing states: the reset state, exception handling state, program

execution state, bus-released state, and power-down state. Figure 3.1 shows a diagram of the

processing states. Figure 3.2 indicates the state transitions.

Reset state

The CPU and all on-chip supporting modules have been

initialized and are stopped.

Exception-handling

state

A transient state in which the CPU changes the normal

processing flow in response to a reset, interrupt, or trap

instruction.

Program execution

state

The CPU executes program instructions in sequence.

Bus-released state

The external bus has been released in response to a bus

request signal from a bus master other than the CPU.

Power-down state

CPU operation is stopped

to conserve power.*

Sleep mode

Software standby

mode

Hardware standby

mode

Processing

states

Note: The power-down state also includes a medium-speed mode, module stop mode, etc.

Figure 3.1 Processing States

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End of bus request

Bus request

Program execution

state

Bus-released state

Sleep mode

Exception-handling state

External interrupt Software standby mode

RES = high

Reset state STBY = high, RES = low Hardware standby mode

Power-down state

Notes: 1.

From any state except hardware standby mode, a transition to the reset state occurs whenever RES

goes low.

From any state, a transition to hardware standby mode occurs when STBY goes low.

SLEEP

instruction

with

SSBY = 0

SLEEP

instruction

with

SSBY = 1

Interrupt

request

End of bus

request Bus

request

Request for

exception

handling

End of

exception

handling

Figure 3.2 State Transitions

3.2 Reset State

When the RES input goes low all current processing stops and the CPU enters the reset state.

Reset exception handling starts when the RES signal changes from low to high.

The reset state can also b e entered by a watchdog timer overflo w. For d e tails, r ef e r to th e r elevan t

microcontroller hardware manual.

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3.3 Exception-Handling State

The exception-handling state is a transient state that occurs when the CPU alters the normal

processing f low due to a reset, interrupt, or trap instr uction. The CPU fetches a start address

(vector) from the exception vector table and branches to that address.

3.3.1 Types of Ex ception Handling and Their Priority

Exception handling is performed for traces, resets, interrupts, and trap instructions. Table 3.1

indicates the types of exception handling and their priority. Trap instruction exception handling is

always accepted, in the program execution state.

Exception handling and the stack structure differ according to the interrupt control mode set in

SYSCR.

Table 3.1 Exception Handling Types and Prio rity

Priority Type of Exception Detection Timing Start of Exception Handling

High Reset Synchronized with clock Exception handling starts

immediately when RES changes

from low to high

Trace End of instruction

execution or end of

exception-handling

sequence*1

When the trace (T) bit is set to 1, the

trace starts at the end of the current

instruction or current exception-

handling sequence

Interrupt End of instruction

execution or end of

exception-handling

sequence*2

When an interrupt is requested,

exception handling starts at the end

of the current instruct ion or current

exception-handling sequence

Low

Trap instruction When TRAPA instruction

is executed Exception handling starts when a

trap (TRAPA) instruction is

executed*3

Notes: 1. Traces are enabled only in interrupt control modes 2 and 3. Trace exception-handling is

not executed at the end of the RTE instruction.

2. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions,

or immediately after reset exception handling.

3. Trap instruction exception handling is always accepted, in the program execution state.

For details on interrupt control modes, exception sources, and exception handling, refer to the

relevant microcontroller hardware manual.

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3.3.2 Reset Exception Handling

After the RES pin has gone low and the reset state has been entered, reset exception handling

starts when RES goes high again. When reset exception handling starts the CPU fetches a start

address (vector) from the exception vector table and starts program execution from that address.

All interrupts, in cluding NMI, are disabled during reset ex ception handling and after it ends.

3.3.3 Trace

Traces are enabled only in interrupt control modes 2 and 3. Trace mode is entered when the T bit

of EXR is set to 1. When trace mode is established, trace exception handling starts at the end of

each instruction.

At the end of a trace exception-handling sequence, the T bit of EXR is cleared to 0 and trace mode

is cleared. Interrupt masks are no t affected.

The T bit saved on th e stack retains its value of 1, and when the RTE instruction is executed to

return from the trace exception-handling routine, trace mode is entered again. Trace exception-

handling is not executed at the end of the RTE instruction.

Trace mode is not entered in interrupt control modes 0 and 1, regardless of the state of the T bit.

3.3.4 Interrupt Exception Handling a nd Trap Instructio n Exception Handling

When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer

(ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU

alters the settings of the interrupt mask bits in the contro l register s. Then the CPU fetches a start

address (vector) from the exception vector table and execution branches to that address.

Figure 3.3 shows the stack after exception handling ends, for the case of interrupt mode 1 in

advanced mode.

3.3.5 Usage Notes

(1) Conf lict between Interrupt Generation and Disabling

When an inter r upt enable bit is cleared to 0 to disab le in ter rupts, the disabling becomes eff ective

after execution of the instruction.

When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an

interrupt is generated during execution o f the instr uction, the interrupt concerned will still be

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enabled on completio n of the instruction, an d so interrupt exception handling for that interrupt will

be executed on completion of the instruction. However, if there is an interrupt request of higher

priority than that interrupt, interrup t exception handling will be executed for the higher-priority

interrupt, and the lower-priority interrupt will b e igno red. The same also applies when an interrupt

source flag is cleared to 0. The above conflict will not occur if an enable bit or interrupt source

flag is cleared to 0 while th e interrupt is masked by th e CPU.

(2) Instructions that Disable Interrupts

The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these

instructions are executed, all interrup ts including NMI are disabled and the next instruction is

always executed. When the I bit is set by one of these instructions, the new value becomes valid

two states after execution of the instruction ends.

(3) Interrupts during Execution of EEPMOV Instructions

Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.

With the EEPMOV.B instruction, an in ter rupt request (including NMI) issued d urin g the transfer

is not accepted until the tran sfer is completed.

With the EEPMOV.W ins tr uction, if an interr upt r e quest is issued d u ring the transfer, interrup t

exception handling starts at the next break in the transfer cycle. The PC value saved on th e stack in

this case is the address of the next instruction.

Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the

following coding should be used.

L1: EEPMOV.W

MOV.W R4,R4

BNE L1

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CCR

(24 bits)

Note: * Ignored when returning.

CCR

(24 bits)

EXR

Reserved*

(a) Interrupt control modes 0 & 1 (b) Interrupt control modes 2 & 3

CCR

CCR*

(16 bits)

CCR

CCR*

(16 bits)

EXR

Reserved*

Normal mode

Advanced mode

Figure 3.3 Stack Structure after Exception Handling (Example)

3.4 Program Execution State

In this state the CPU executes program instructions in sequence.

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3.5 Bus-Released State

This is a state in which the bus has been released in response to a bus request from a bus master

other than the CPU. Wh ile the bus is released, the CPU halts except for internal operations.

Bus masters other than the CPU may include the direct memory access controller (DMAC) and

data transfer contr oller (DTC).

For further details, refer to the relevant microcontroller hardware manual.

3.6 Power-Down State

The power-down state includes both modes in which the CPU stops operating and modes in which

the CPU does not stop. There are three modes in which the CPU stops operating: sleep mode,

software standby mode, and hardware standby mode. There are also two other power-down

modes: medium-speed mode and module stop mode. In medium-speed mode the CPU and other

bus masters operate on a medium-speed clock. Module stop mode permits halting of the operation

of individual modules, other than the CPU. For details, refer to the relevant microcontroller

hardware manual.

3.6.1 Sleep Mode

A transition to sleep mode is made if the SLEEP instruction is executed while the software

standby bit (SSBY) in the system control register (SYSCR) is cleared to 0. In sleep mode, CPU

operations stop immediately after execution of the SLEEP instruction. The contents of CPU

registers are retained.

3.6.2 Software Standby Mode

A transition to software standby mode is made if the SLEEP instruction is executed while the

SSBY bit in SYSCR is set to 1. In software standby mode, the CPU and clock halt and all on-chip

operations stop. The on-chip supporting modules are reset, but as long as a specified voltage is

supplied, the contents of CPU registers and on-chip RAM are retained. The I/O ports also remain

in their existing states.

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3.6.3 Hardware Standby Mode

A transition to hardware standby mode is made when the STBY pin goes low. In hardware

standby mode, the CPU and clock halt and all on-chip operations stop. The on-chip supporting

modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are

retained.

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Section 4 Basic Timing

4.1 Overview

The CPU is driven by a system clock, denoted by the symbol φ. The period from one rising edge

of φ to the next is referred to as a “state.” The memory cycle or bus cycle consists of one, two, or

three states. Different methods are used to access on-chip memory, on-chip supporting modules,

and the external address space. Refer to the relevant microcontroller hardware manual for details.

4.2 On-Chip Memory (ROM, RAM)

On-chip memory is accessed in one state. Th e data bus is 16 bits wide, permitting both byte and

word access. Figure 4.1 shows the on-chip memory access cycle. Figure 4.2 shows the pin states.

Internal address bus

Internal read signal

Internal data bus

Internal write signal

Internal data bus

Bus cycle

Address

Read data

Write data

Read

access

Write

access

Figure 4.1 On-Chip Memory Access Cycle

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Bus cycle

UnchangedAddress bus

HWR, LWR

Data bus

High

High-impedance state

Figure 4.2 Pin States during On-Chip Memory Access

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4.3 On-Chip Supporting Module Access Timing

The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits

wide, depending on the particular on-chip register being accessed. Figure 4.3 shows the access

timing for the on-chip supporting modules. Figure 4.4 shows the pin states.

Bus cycle

T1 T2

Address

Read data

Write data

Internal read signal

Internal data bus

Internal write signal

Internal data bus

Read

access

Write

access

Internal address bus

Figure 4.3 On-C hip Supporting Module Access Timing

Section 4 Basic Timing

Rev. 4.00 Feb 24, 2006 page 320 of 322

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Bus cycle

T1 T2

Unchanged

Address bus

HWR, LWR

Data bus

High

High-impedance state

Figure 4.4 Pin States during O n-Chip Supporting Module Access

4.4 External Address Space Access Timing

The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or

three-state bus cycle. Figure 4.5 shows the read timing for two-state and three-state access. Figure

4.6 shows the write timing for two-state and three-state access. In three-state access, wait states

can be inserted . For furth er details, refer to the relevant m icrocontroller hardware manual.

Section 4 Basic Timing

Rev. 4.00 Feb 24, 2006 page 321 of 322

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Read cycle

T1 T2

Address

Read data

(a) Two-State Access

Address bus

Data bus

Read cycle

T1 T2

Address

Read data

(b) Three-State Access

Address bus

Data bus

Figure 4.5 External Device Access Timing (Read Timing)

Section 4 Basic Timing

Rev. 4.00 Feb 24, 2006 page 322 of 322

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Write cycle

T1 T2

Address

(a) Two-State Access

Address bus

HWR, LWR

Data bus

Write data

Write cycle

T1 T2

Address

Write data

(b) Three-State Access

Address bus

Data bus

HWR, LWR

Figure 4.6 External Device Access Timing (Write Timing)

Renesas 16-Bit Single-Chip Microcomputer

Software Manual

H8S/2600 Series, H8S/2000 Series

Publication Date: 1st Edition, March 1995

Rev.4.00, February 24, 2006

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REJ09B0139-0400

Software Manual