ADVANCE INFORMATION PE4462 High Isolation, Non-Blocking 4x6 RF Matrix Switch Product Description The PE4462 is a high-performance monolithic CMOS switch matrix with integrated power splitters for nonblocking operation. Any of the four RF inputs can be connected to one or more of the six RF outputs simultaneously. With its excellent isolation, small package, and simple interface, the PE4462 is ideal for receiver switching in dual-mode, dual-band base stations. Features The PE4462 is manufactured in Peregrine's patented Ultra-Thin Silicon (UTSi) CMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Schematic Diagram * Three inputs at 1710 - 2025 MHz * One input at 824 - 924 MHz * High isolation: 43 dB @ 2 GHz * High input 1 dB compression point of +31 dBm * High input IP3 of +50 dBm * Single 3-volt nominal power supply * Less than 10 uA current drain * Simple SPI control bus * Small 7x7 mm MLPQ package Figure 2. Package Type OUT1 OUT2 OUT3 37 36 48 1 IN1 48-lead MLPQ 7x7 mm IN2 IN3 IN4 12 13 25 24 OUT4 OUT5 OUT6 Table 1. Electrical Specifications @ +25 C (ZS = ZL = 50 ) Parameter Conditions Minimum Typical Maximum Units 2.7 3.0 3.3 V 1 10 uA Supply Voltage Supply Current Insertion Loss 824 - 924 MHz 1710 - 2025 MHz 11.7 13.5 dB Insertion Loss Flatness 824 - 924 MHz 1710 - 2025 MHz +0.4 +0.4 dB Insertion Loss Variation Any input to any output +0.4 dB Isolation Output to output port with uncommon input port 43 dB Splitter Isolation Output to output port with common input port 25 dB PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2002 Page 1 of 12 PE4462 Advance Information Table 2. Electrical Specifications @ +25 C -- Continued (ZS = ZL = 50 ) Parameter Conditions Minimum Typical Maximum Units Input 1 dB Compression Pt. 31 dBm Input IP3 50 dBm Input Return Loss 824 - 924 MHz 1710 - 2025 MHz 9 6 dB dB Output Return Loss 824 - 924 MHz 1710 - 2025 MHz 11 7 dB dB Switching Time 50% CTL to 90/10% RF 180 ns Video Feedthrough 15 mVpp SPI Clock 5 10 MHz Figure 3. Detailed Functional Schematic Diagram OUT1 OUT2 OUT3 VDD DATA GND CLK EN IN1 824 - 924 MHz 6-way power splitter 1710 - 2025 MHz 6-way power splitter IN2 IN3 1710 - 2025 MHz 6-way power splitter 1710 - 2025 MHz 6-way power splitter IN4 OUT4 OUT5 OUT6 Copyright Peregrine Semiconductor Corp. 2002 Page 2 of 12 File No. 70/0081~00A | UTSi CMOS RFIC SOLUTIONS PE4462 Advance Information Figure 4. Pin Configuration Table 4. Absolute Maximum Ratings GND GND OUT4 GND GND GND OUT5 GND GND GND OUT6 GND Symbol 37 36 48 48-lead MLPQ 7x7 mm 12 13 25 24 GND GND GND IN4 GND GND GND GND IN3 GND GND GND Table 3. Pin Descriptions Pin No. Pin Name 3 EN (ENABLE) 4 Min Max Units Supply voltage -0.3 4.0 V TST Storage temperature range -65 150 C TOP Operating temperature range -40 85 C Vi Maximum input voltage -0.3 VDD+0.3 V 250 V VDD GND GND OUT1 GND GND GND OUT2 GND GND GND OUT3 GND GND GND EN IN2 GND DATA GND CLK GND IN1 VDD GND 1 Parameter/Conditions Description VESD ESD voltage (Human Body Model) Electrostatic Discharge (ESD) Precautions When handling this UTSi device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in table. Latch-Up Avoidance Serial register is loaded into parallel register on rising edge of ENABLE control input. RF switches are now reconfigured. Unlike conventional CMOS devices, UTSi CMOS devices are immune to latch-up. IN2 RF input number 2 (1710 - 2025 MHz). Device Functional Considerations 6 DATA DATA is loaded LSB first into the 32-bit serial shift register on the falling edge of CLK (CLOCK). 8 CLK (CLOCK) Falling edge of CLK loads one bit of DATA into the 32-bit serial shift register. Nominal CLK frequency is 5 MHz. 10 IN1 RF input number 1 (824 - 924 MHz). 11 VDD Supply voltage input for the matrix switch. This supply pin must be AC shunted to GND as close as possible to the pin. 15 OUT1 RF output number 1. 19 OUT2 RF output number 2. 23 OUT3 RF output number 3. 28 IN3 RF input number 3 (1710 - 2025 MHz). 33 IN4 RF input number 4 (1710 - 2025 MHz). 38 OUT6 RF output number 6. 42 OUT5 RF output number 5. 46 OUT4 RF output number 4. The PE4462 offers very high isolation only when care is taken in the PCB layout. Ground fill should isolate all of the RF traces from one another, and the exposed paddle should be soldered to the ground plane. All of the RF pins must be DC blocked for proper operation. All other pins and the ground paddle must be grounded. (PINS 1, 2, 5, 7, 9, 12-14, 16-18, 20-22, 24-27, 29-32, 34-37, 39-41, 43-45, 47-48 are GND pins) PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2002 Page 3 of 12 PE4462 Advance Information SPI Programming Each bit (except the unused bits marked by X) controls one RF switch and can connect an input to a selected output by programming that bit high (B(0-31) = 1) as shown in Table 5. The serial bus timing is shown in Figure 5, Serial Programming Interface Timing Diagram, and Table 6, Serial Interface AC Characteristics. The serial programming interface consists of three CMOS compatible signals; input programming data (DATA), the serial bus clock (CLK) and a Latch Enable (EN) control line. A 32-bit data word is serially clocked LSB (B0) first into a control register on the leading edge of the serial bus clock and then captured in the control latch by taking the EN line high (EN=1) and then subsequently low (EN=0). For example if bit B3 is programmed high (B3 = 1), then RF Input 1 is connected to RF Output 4. Table 5. Programming Data Words DATA Bit B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 RF Input 4 To: RF Output Port: DATA Bit Port: B19 B18 B17 B16 RF Input 3 To: X X 6 5 4 3 2 1 X X 6 5 4 3 2 1 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 3 2 1 RF Input 2 To: RF Output B20 X X 6 5 4 RF Input 1 To: 3 2 1 X X 6 5 4 Figure 5. Serial Programming Interface Timing Diagram DATA CLK EN tDSU Copyright Peregrine Semiconductor Corp. 2002 Page 4 of 12 tDHLD tClkH tClkL tCOLE File No. 70/0081~00A tPW tOLEC | UTSi CMOS RFIC SOLUTIONS PE4462 Advance Information Table 6. Serial Interface AC Characteristics VDD = 3.0 V, -40 C < TA < 85 C, unless otherwise specified Symbol Parameter Min Max Unit 10 MHz fClk Serial data clock frequency (Note 1) tClkH Serial clock HIGH time 60 ns tClkL Serial clock LOW time 60 ns tDSU Sdata set-up time to Sclk rising edge 20 ns tDHLD Sdata hold time after Sclk rising edge 20 ns tPW OLE pulse width 60 ns tCWR Sclk rising edge to S_WR rising edge 60 ns tOLEC OLE falling edge to Sclk rising edge 60 ns Note 1: fClk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 5 MHz to verify fclk specification. Figure 6. High Frequency System Application OUT1 OUT2 OUT3 IN1 IN2 Base Station Receivers IN3 IN4 OUT4 OUT5 OUT6 PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2002 Page 5 of 12 PE4462 Advance Information Typical Performance Data @ +25 C Figure 8. Input 1 dB Compression Point & IIP3 Figure 7. Insertion Loss - Low Band 60 60 0 IIP3 -2 IIP3 (dBM) Insertion Loss (dB) -6 -8 50 50 40 40 30 30 -10 1dB Compression Point (dBm) -4 -12 Input 1dB Compression -14 0.6 0.7 0.8 0.9 1 1.1 20 20 1.2 0.4 0.6 0.8 Frequency (GHz) 1 1.2 1.4 1.6 Frequency (GHz) Figure 9. Insertion Loss - High Band Figure 10. Output to Output Isolation - Uncommon Input 0 0 -2 -10 -20 -6 Isolation (dB) Insertion Loss (dB) -4 -8 -10 -30 -40 -12 -50 -14 -16 -60 1.5 1.6 1.7 1.8 1.9 2 Frequency (GHz) Copyright Peregrine Semiconductor Corp. 2002 Page 6 of 12 2.1 2.2 2.3 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 Frequency (GHz) File No. 70/0081~00A | UTSi CMOS RFIC SOLUTIONS PE4462 Advance Information Typical Performance Data @ +25 C Figure 12. Output to Output Isolation - High Band Common Input 0 0 -10 -10 Isolation (dB) Isolation (dB) Figure 11. Output to Output Isolation - Low Band Common Input -20 -20 -30 -30 -40 -40 0.6 0.7 0.8 0.9 1 1.1 1.5 1.2 1.6 1.7 1.9 2 2.1 2.2 2.3 2.2 2.3 Frequency (GHz) Frequency (GHz) Figure 13. Input to Input Isolation - Low Band to High Band Figure 14. Input to Input Isolation - High Band to High Band 0 0 -10 -10 -20 -20 Isolation (dB) Isolation (dB) 1.8 -30 -30 -40 -40 -50 -50 -60 -60 0.6 0.7 0.8 0.9 1 1.1 1.2 Frequency (GHz) PEREGRINE SEMICONDUCTOR CORP. | 1.5 1.6 1.7 1.8 1.9 2 2.1 Frequency (GHz) http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2002 Page 7 of 12 PE4462 Advance Information Typical Performance Data @ +25 C Figure 16. On-Off Isolation - High Band 0 0 -10 -10 -20 -20 Isolation (dB) Isolation (dB) Figure 15. On-Off Isolation - Low Band -30 -30 -40 -40 -50 -50 -60 -60 0.6 0.7 0.8 0.9 1 1.1 1.2 1.5 1.6 1.7 Frequency (GHz) 1.9 2 2.1 2.2 2.3 Frequency (GHz) Figure 17. Input Return Loss - Low Band Figure 18. Input Return Loss - High Band 0 0 -5 -5 Return Loss (dB) Return Loss (dB) 1.8 -10 -15 -10 -15 -20 -20 -25 -25 0.6 0.7 0.8 0.9 1 Frequency (GHz) Copyright Peregrine Semiconductor Corp. 2002 Page 8 of 12 1.1 1.2 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 Frequency (GHz) File No. 70/0081~00A | UTSi CMOS RFIC SOLUTIONS PE4462 Advance Information Typical Performance Data @ +25 C Figure 20. Output Return Loss - High Band 0 0 -5 -5 Return Loss (dB) Return Loss (dB) Figure 19. Output Return Loss - Low Band -10 -15 -20 -10 -15 -20 -25 -25 0.6 0.7 0.8 0.9 1 1.1 1.2 Frequency (GHz) PEREGRINE SEMICONDUCTOR CORP. | 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 Frequency (GHz) http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2002 Page 9 of 12 PE4462 Advance Information Figure 21. Package Drawing 48 Lead 7x7 mm MLPQ 7.00 -B- 3.50 7.00 3.50 INDEX AREA 3.50 X 3.50 0.25 C 0.80 -A- 0.10 C 2 0.08 C SEATING -CPLANE 0.30 0.50 5.00 5.25 2.50 2.63 13 24 25 5.00 5.25 0.23 7.00 5.50 TYP 0.23 2.50 2.63 2.75 TYP 12 0.18 0.20 REF 0.020 EXPOSED PAD & TERMINAL PADS 0.18 1 48 36 37 EXPOSED PAD DETAIL A 2 0.50 TYP 0.23 0.10 C A B 1 1. DIMENSION APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 FROM TERMINAL TIP. 2. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. Copyright Peregrine Semiconductor Corp. 2002 Page 10 of 12 File No. 70/0081~00A | UTSi CMOS RFIC SOLUTIONS PE4462 Advance Information Table 7. Ordering Information Order Code Part Marking Description Package Shipping Method 4462-01 PE4462 PE4462-48MLP7X7-4000C 48-lead 7x7 mm MLPQ 4000 pcs. / T&R 4462-02 PE4462 PE4462-48MLP7X7-52A 48-lead 7x7 mm MLPQ 52 pcs. / Tube 4462-00 PE4462-EK PE4462-48MLP7X7-EK Evaluation Board 1 / Box PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2002 Page 11 of 12 PE4462 Advance Information Sales Offices United States Japan Peregrine Semiconductor Corp. Peregrine Semiconductor K.K. 6175 Nancy Ridge Drive San Diego, CA 92121 Tel 1-858-455-0660 Fax 1-858-455-0770 The Imperial Tower, 15th floor 1-1-1 Uchisaiawaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: 03-3507-5755 Fax: 03-3507-5601 Europe Australia Peregrine Semiconductor Europe Peregrine Semiconductor Australia Aix-En-Provence Office Parc Club du Golf, bat 9 13856 Aix-En-Provence Cedex 3 France Tel 33-0-4-4239-3360 Fax 33-0-4-4239-7227 8 Herb Elliot Ave. Homebush, NSW 2140 Australia Tel: 011-61-2-9763-4111 Fax: 011-61-2-9746-1501 For a list of representatives in your area, please refer to our Web site at: http://www.peregrine-semi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out Product Specification of the use of its products in such applications. The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a PCN (Product Change Notice). Peregrine products are protected under one or more of the following U.S. patents: 6,090,648; 6,057,555; 5,973,382; 5,973,363; 5,930,638; 5,920,233; 5,895,957; 5,883,396; 5,864,162; 5,863,823; 5,861,336; 5,663,570; 5,610,790; 5,600,169; 5,596,205; 5,572,040; 5,492,857; 5,416,043. Other patents may be pending or applied for. UTSi, the Peregrine logotype, SEL Safe, and Peregrine Semiconductor Corp. are registered trademarks of Peregrine Semiconductor Corp. All PE product names and prefixes are trademarks of Peregrine Semiconductor Corp. Copyright (c) 2002 Peregrine Semiconductor Corp. All rights reserved. Copyright Peregrine Semiconductor Corp. 2002 Page 12 of 12 File No. 70/0081~00A | UTSi CMOS RFIC SOLUTIONS