SST49LF008A-33-4C-EIE-T - Microchip Technology

Microchip Technology Company

Data Sheet

www.microchip.com

Features

• Firmware Hub for Intel 8xx Chipsets

• 8 Mbit SuperFlash memory array for code/data

storage

– 1024K x8

• Flexible Erase Capability

– Uniform 4 KByte Sectors

– Uniform 64 KByte overlay blocks

– 64 KByte Top Boot Block protection

– Chip-Erase for PP Mode Only

• Single 3.0-3.6V Read and Write Operations

• Superior Reliability

– Endurance:100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption

– Active Read Current: 6 mA (typical)

– Standby Current: 10 µA (typical)

• Fast Sector-Erase/Byte-Program Operation

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 70 ms (typical)

– Byte-Program Time: 14 µs (typical)

– Chip Rewrite Time: 15 seconds (typical)

– Single-pulse Program or Erase

– Internal timing generation

• Two Operational Modes

– Firmware Hub Interface (FWH) Mode for

In-System operation

– Parallel Programming (PP) Mode for fast

production programming

• Firmware Hub Hardware Interface Mode

– 5-signal communication interface supporting byte Read

and Write

– 33 MHz clock frequency operation

– WP# and TBL# pins provide hardware write

protect for entire chip and/or top Boot Block

– Block Locking Register for all blocks

– Standard SDP Command Set

– Data# Polling and Toggle Bit for End-of-Writedetection

– 5 GPI pins for system design flexibility

– 4 ID pins for multi-chip selection

• Parallel Programming (PP) Mode

– 11-pin multiplexed address and

8-pin data I/O interface

– Supports fast In-System or PROM programming for

manufacturing

• CMOS and PCI I/O Compatibility

• Packages Available

– 32-lead PLCC

– 32-lead TSOP (8mm x 14mm)

– 40-lead TSOP (10mm x 20mm)

– Non-Pb (lead-free) packages available

• All non-Pb (lead-free) devices are RoHS compliant

8 Mbit Firmware Hub

SST49LF008A

The SST49LF008A flash memory devices are designed to be read-compatible

with the Intel® 82802 Firmware Hub (FWH) device for PC-BIOS application.

These devices provide protection for the storage and update of code and data in

addition to adding system design flexibility through five general purpose inputs.

Two interface modes are supported by the SST49LF008A: Firmware Hub (FWH)

Interface mode for in-system programming and Parallel Programming (PP) mode

for fast factory programming of PC-BIOS applications.

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Product Description

The SST49LF008A flash memory devices are designed to be read-compatible with the Intel® 82802

Firmware Hub (FWH) device for PC-BIOS application. These devices provide protection for the storage

and update of code and data in addition to adding system design flexibility through five general pur-

pose inputs. Two interface modes are supported by the SST49LF008A: Firmware Hub (FWH) Interface

mode for in-system programming and Parallel Programming (PP) mode for fast factory programming of

PC-BIOS applications.

The SST49LF008A flash memory devices are manufactured with SST’s proprietary, high performance

SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reli-

ability and manufacturability compared with alternate approaches. The SST49LF008A devices signifi-

cantly improve performance and reliability, while lowering power consumption.

The SST49LF008A devices write (Program or Erase) with a single 3.0-3.6V power supply. They use

less energy during Erase and Program than alternative flash memory technologies. The total energy

consumed is a function of the applied voltage, current and time of application. Since for any given volt-

age range, the SuperFlash technology uses less current to program and has a shorter Erase time, the

total energy consumed during any Erase or Program operation is less than alternative flash memory

technologies. The SST49LF008A products provide a maximum Byte-Program time of 20 µsec. The

entire memory can be erased and programmed byte-by-byte typically in 15 seconds when using status

detection features such as Toggle Bit or Data# Polling to indicate the completion of Program operation.

The SuperFlash technology provides fixed Erase and Program times independent of the number of

Erase/Program cycles performed. Therefore the system software or hardware does not have to be cal-

ibrated or correlated to the cumulated number of Erase/Program cycles as is necessary with alterna-

tive flash memory technologies, whose Erase and Program time increase with accumulated Erase/

Program cycles.

To protect against inadvertent write, the SST49LF008A devices employ hardware and software data

(SDP) protection schemes. It is offered with typical endurance of 100,000 cycles. Data retention is

rated at greater than 100 years.

To meet high density, surface mount requirements, the SST49LF008A devices are offered in a 32-lead

TSOP package. In addition, the SST49LF008A is offered in 32-lead PLCC and 40-lead TSOP pack-

ages. See Figures 2, 3, and 4 for pin assignments and Table 1 for pin descriptions.

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Functional Block Diagram

Figure 1: Functional Block Diagram

1161 B1.2

Y-Decoder

I/O Buffers and Data Latches

Address Buffers Latches

X-Decoder SuperFlash

Memory

Control Logic

CLK

RST#

FGPI[4:0]

Programmer

Interface

WP#

TBL#

INIT#

ID[3:0]

FWH4

R/C#

OE#

WE#

A[10:0]

DQ[7:0]

FWH[3:0]

FWH

Interface

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Pin Assignments

Figure 2: Pin Assignments for 32-lead TSOP (8mm x 14mm)

Figure 3: Pin Assignments for 32-lead PLCC

VSS (VSS)

IC (IC)

A10 (FGPI4)

R/C# (CLK)

VDD (VDD)

RST# (RST#)

A9 (FGPI3)

A8 (FGPI2)

A7 (FGPI1)

A6 (FGPI0)

A5 (WP#)

A4 (TBL#)

OE# (INIT#)

WE# (FWH4)

VDD (VDD)

DQ7 (RES)

DQ6 (RES)

DQ5 (RES)

DQ4 (RES)

DQ3 (FWH3)

VSS (VSS)

DQ2 (FWH2)

DQ1 (FWH1)

DQ0 (FWH0)

A0 (ID0)

A1 (ID1)

A2 (ID2)

A3 (ID3)

1161 32-tsop P1.0

Standard Pinout

Top View

Die Up

( ) Designates FWH Mode

A7(FGPI1)

A6 (FGPI0)

A5 (WP#)

A4 (TBL#)

A3 (ID3)

A2 (ID2)

A1 (ID1)

A0 (ID0)

DQ0 (FWH0)

IC (IC)

VSS (VSS)

VDD (VDD)

OE# (INIT#)

WE# (FWH4)

DQ7 (RES)

4 3 21323130

A8 (FGPI2)

A9 (FGPI3)

RST# (RST#)

VDD (VDD)

R/C# (CLK)

A10 (FGPI4)

32-lead PLCC

Top View

1161 32-plcc P2.3

14 15 16 17 18 19 20

DQ1 (FWH1)

DQ2 (FWH2)

VSS (VSS)

DQ3 (FWH3)

DQ4 (RES)

DQ5 (RES)

DQ6 (RES)

( ) Designates FWH Mode

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Figure 4: Pin Assignments for 40-lead TSOP

1232 40-tsop P1.0

Standard Pinout

Top View

Die Up

NC (NC)

IC (IC)

NC (NC)

A10 (FGPI4)

NC (NC)

R/C# (CLK)

VDD

NC (NC)

RST# (RST#)

NC (NC)

A9 (FGPI3)

A8 (FGPI2)

A7 (FGPI1)

A6 (FGPI0)

A5 (WP#)

A4 (TBL#)

VSS

VDD

(FWH4) WE#

(INIT#) OE#

(NC) NC

(RES) DQ7

(RES) DQ6

(RES) DQ5

(RES) DQ4

(NC) NC

VSS

(FWH3) DQ3

(FWH2) DQ2

(FWH1) DQ1

(FWH0) DQ0

(ID0) A0

(ID1) A1

(ID2) A2

(ID3) A3

( ) Designates FWH Mode

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Table 1: Pin Description

Symbol Pin Name Type1

Interface

FunctionsPP FWH

A10-A0Address I X Inputs for low-order addresses during Read and Write opera-

tions. Addresses are internally latched during a Write cycle. For

the programming interface, these addresses are latched by R/

C# and share the same pins as the high-order address inputs.

DQ7-DQ0Data I/O X To output data during Read cycles and receive input data during

Write cycles. Data is internally latched during a Write cycle. The

outputs are in tri-state when OE# is high.

OE# Output Enable I X To gate the data output buffers

WE# Write Enable I X To control the Write operations

IC Interface

Configuration

I X X This pin determines which interface is operational. When held

high, programmer mode is enabled and when held low, FWH

mode is enabled. This pin must be setup at power-up or before

return from reset and not change during device operation. This pin

is internally pulled- down with a resistor between 20-100 K

INIT# Initialize I X This is the second reset pin for in-system use. This pin is inter-

nally combined with the RST# pin; If this pin or RST# pin is

driven low, identical operation is exhibited.

ID[3:0] Identification

Inputs

I X These four pins are part of the mechanism that allows multiple

parts to be attached to the same bus. The strapping of these

pins is used to identify the component.The boot device must

have ID[3:0]=0000 and it is recommended that all subsequent

devices should use sequential up-count strapping. These pins

are internally pulled-down with a resistor between 20-100 K

FGPI[4:0] General Pur-

pose Inputs

I X These individual inputs can be used for additional board flexibil-

ity. The state of these pins can be read through GPI_REG regis-

ter. These inputs should be at their desired state before the start

of the PCI clock cycle during which the read is attempted, and

should remain in place until the end of the Read cycle. Unused

GPI pins must not be floated.

TBL# Top Block Lock I X When low, prevents programming to the Boot Block sectors at top of

memory. When TBL# is high it disables hardware write protection for

the top block sectors. This pin cannot be left unconnected.

FWH[3:0] FWH I/Os I/O X I/O Communications

CLK Clock I X To provide a clock input to the control unit

FWH4 FWH Input I X Input Communications

RST# Reset I X X To reset the operation of the device

WP# Write Protect I X When low, prevents programming to all but the highest address-

able blocks. When WP# is high it disables hardware write protec-

tion for these blocks. This pin cannot be left unconnected.

R/C# Row/Column

Select

I X Select For the Programming interface, this pin determines whether

the address pins are pointing to the row addresses, or to the column

addresses.

RES Reserved X These pins must be left unconnected.

VDD Power Supply PWR X X To provide power supply (3.0-3.6V)

VSS Ground PWR X X Circuit ground (OV reference) All VSS pins must be grounded.

NC No Connection I X X Unconnected pins

T1.4 25085

1. I = Input, O = Output

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Device Memory Map

Figure 5: Device Memory Map for SST49LF008A

0FFFFFH

0F0000H

0EFFFFH

0E0000H

0DFFFFH

0D0000H

0CFFFFH

0C0000H

0BFFFFH

0B0000H

0AFFFFH

0A0000H

09FFFFH

090000H

08FFFFH

080000H

07FFFFH

070000H

06FFFFH

060000H

05FFFFH

050000H

04FFFFH

040000H

03FFFFH

030000H

02FFFFH

020000H

01FFFFH

010000H

00FFFFH

Block 7

Block 8

Block 6

Block 5

Block 4

Block 3

Block 2

Block 1

Block 15

Block 14

Block 13

Block 12

Block 11

Block 10

Block 9

Block 0

(64 KByte)

1161 F08.0

WP# for

Block 0 14

TBL#

4 KByte Sector 1

4 KByte Sector 2

4 KByte Sector 15

4 KByte Sector 0

Boot Block

002000H

001000H

000000H

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Design Considerations

SST recommends a high frequency 0.1 µF ceramic capacitor to be placed as close as possible

between VDD and VSS less than 1 cm away from the VDD pin of the device. Additionally, a low fre-

quency 4.7 µF electrolytic capacitor from VDD to VSS should be placed within 1 cm of the VDD pin. If you

use a socket for programming purposes add an additional 1-10 µF next to each socket.

The RST# pin must remain stable at VIH for the entire duration of an Erase operation. WP# must

remain stable at VIH for the entire duration of the Erase and Program operations for non-Boot Block

sectors. To write data to the top Boot Block sectors, the TBL# pin must also remain stable at VIH for the

entire duration of the Erase and Program operations.

Product Identification

The product identification mode identifies the device as the SST49LF008A and manufacturer as SST.

Mode Selection

The SST49LF008A flash memory devices can operate in two distinct interface modes: the Firmware

Hub Interface (FWH) mode and the Parallel Programming (PP) mode. The IC (Interface Configuration

pin) is used to set the interface mode selection. If the IC pin is set to logic High, the device is in PP

mode; while if the IC pin is set Low, the device is in the FWH mode. The IC selection pin must be con-

figured prior to device operation. The IC pin is internally pulled down if the pin is not connected. In

FWH mode, the device is configured to interface with its host using Intel’s Firmware Hub proprietary

protocol. Communication between Host and the SST49LF008A occurs via the 4-bit I/O communication

signals, FWH [3:0] and the FWH4. In PP mode, the device is programmed via an 11-bit address and

an 8-bit data I/O parallel signals. The address inputs are multiplexed in row and column selected by

control signal R/C# pin. The column addresses are mapped to the higher internal addresses, and the

row addresses are mapped to the lower internal addresses. See the Device Memory Map in Figure 5

for address assignments.

Table 2: Product Identification

Byte Data

JEDEC ID

Address

Location

Manufacturer’s ID 0000H BFH FFBC0000H

Device ID

SST49LF008A 0001H 5AH FFBC0001H

T2.7 25085

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Firmware Hub (FWH) Mode

Device Operation

The FWH mode uses a 5-signal communication interface, FWH[3:0] and FWH4, to control operations

of the SST49LF008A. Operations such as Memory Read and Memory Write uses Intel FWH propriety

protocol. JEDEC Standard SDP (Software Data Protection) Byte-Program, Sector-Erase and Block-

Erase command sequences are incorporated into the FWH memory cycles. Chip-Erase is only avail-

able in PP Mode.

The device enters standby mode when FWH4 is high and no internal operation is in progress. The

device is in ready mode when FWH4 is low and no activity is on the FWH bus.

Firmware Hub Interface Cycles

Addresses and data are transferred to and from the SST49LF008A by a series of “fields,” where each

field contains 4 bits of data. SST49LF008A supports only single-byte Read and Write, and all fields are

one clock cycle in length. Field sequences and contents are strictly defined for Read and Write opera-

tions. Addresses in this section refer to addresses as seen from the SST49LF008A’s “point of view,”

some calculation will be required to translate these to the actual locations in the memory map (and

vice versa) if multiple memory devices are used on the bus. Tables 3 and 4 list the field sequences for

Read and Write cycles.

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Figure 6: Single-Byte Read Waveforms

Table 3: FWH Read Cycle

Clock

Cycle

Field

Name

Field Contents

FWH[3:0]1

FWH[3:0]

Direction Comments

1 START 1101 IN FWH4 must be active (low) for the part to respond. Only the

last start field (before FWH4 transitions high) should be recog-

nized. The START field contents indicate a FWH memory

Read cycle.

2 IDSEL 0000 to 1111 IN Indicates which FWH device should respond. If the to IDSEL (ID

select) field matches the value ID[3:0], then that particular device will

respond to the whole bus cycle.

3-9 IMADDR YYYY IN These seven clock cycles make up the 28-bit memory address.

YYYY is one nibble of the entire address. Addresses are trans-

ferred most-significant nibble first.

10 IMSIZE 0000 (1 byte) IN A field of this size indicates how many bytes will be or trans-

ferred during multi-byte operations. The SST49LF008A will only

support single-byte operation. IMSIZE=0000b

11 TAR0 1111 IN

then Float

In this clock cycle, the master (Intel ICH) has driven the bus

then float to all ‘1’s and then floats the bus, prior to the next

clock cycle. This is the first part of the bus “turnaround cycle.”

12 TAR1 1111 (float) Float

then OUT

The SST49LF008A takes control of the bus during this cycle.

During the next clock cycle, it will be driving “sync data.”

13 RSYNC 0000 (READY) OUT During this clock cycle, the FWH will generate a “ready-sync”

(RSYNC) indicating that the least-significant nibble of the least-

significant byte will be available during the next clock cycle.

14 DATA YYYY OUT YYYY is the least-significant nibble of the least-significant data byte.

15 DATA YYYY OUT YYYY is the most-significant nibble of the least-significant data byte.

16 TAR0 1111 OUT

then Float

In this clock cycle, the SST49LF008A has driven the bus to all

ones and then floats the bus prior to the next clock cycle. This

is the first part of the bus “turnaround cycle.”

17 TAR1 1111 (float) Float then

The master (Intel ICH) resumes control of the bus during this

cycle.

T3.3 25085

1. Field contents are valid on the rising edge of the present clock cycle.

CLK

FWH4

FWH[3:0]

1161 F09.0

STR TAR RSYNCIMSIMADDRIDS DATA TAR

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Figure 7: Write Waveforms

Table 4: FWH Write Cycle

Clock

Cycle

Field

Name

Field Contents

FWH[3:0]1

FWH[3:0]

Direction Comments

1 START 1110 IN FWH4 must be active (low) for the part to respond. Only

the last start field (before FWH4 transitions high) should

be recognized. The START field contents indicate a FWH

memory Read cycle.

2 IDSEL 0000 to 1111 IN Indicates which SST49LF008A device should respond.

If the IDSEL (ID select) field matches the value

ID[3:0], then that particular device will respond to the

whole bus cycle.

3-9 IMADDR YYYY IN These seven clock cycles make up the 28-bit memory

address. YYYY is one nibble of the entire address.

Addresses are transferred most-significant nibble first.

10 IMSIZE 0000 (1 byte) IN This size field indicates how many bytes will be trans-

ferred during multi-byte operations. The FWH only

supports single-byte writes. IMSIZE=0000b

11 DATA YYYY IN This field is the least-significant nibble of the data byte.

This data is either the data to be programmed into the

flash memory or any valid flash command.

12 DATA YYYY IN This field is the most-significant nibble of the data byte.

13 TAR0 1111 IN then Float In this clock cycle, the master (Intel ICH) has driven the

then float bus to all ‘1’s and then floats the bus prior to

the next clock cycle. This is the first part of the bus “turn-

around cycle.”

14 TAR1 1111 (float) Float then OUT The SST49LF008A takes control of the bus during this

cycle. During the next clock cycle it will be driving the

“sync” data.

15 RSYNC 0000 OUT The SST49LF008A outputs the values 0000, indicating

that it has received data or a flash command.

16 TAR0 1111 OUT then Float In this clock cycle, the SST49LF008A has driven the bus

to all then float ‘1’s and then floats the bus prior to the

next clock cycle. This is the first part of the bus “turn-

around cycle.”

17 TAR1 1111 (float) Float then IN The master (Intel ICH) resumes control of the bus during this

cycle.

T4.4 25085

1. Field contents are valid on the rising edge of the present clock cycle.

CLK

FWH4

FWH[3:0]

1161 F10.0

STR DATA TARTA R

RSYNC

IMSIMADDRIDS

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Abort Mechanism

If FWH4 is driven low for one or more clock cycles during a FWH cycle, the cycle will be terminated

and the device will wait for the ABORT command. The host may drive the FWH[3:0] with ‘1111b’

(ABORT command) to return the device to Ready mode. If abort occurs during a Write operation, the

data may be incorrectly altered.

Response To Invalid Fields

During FWH operations, the FWH will not explicitly indicate that it has received invalid field sequences.

The response to specific invalid fields or sequences is as follows:

Address out of range:

The FWH address sequence is 7 fields long (28 bits), but only the last five address fields (20 bits) will

be decoded by SST49LF008A.

Address A22 has the special function of directing reads and writes to the flash core (A22=1) or to the

Invalid IMSIZE field:

If the FWH receives an invalid size field during a Read or Write operation, the device will reset and no

operation will be attempted. The SST49LF008A will not generate any kind of response in this situation.

Invalid-size fields for a Read/Write cycle are anything but 0000b.

Device Memory Hardware Write Protection

The Top Boot Lock (TBL#) and Write Protect (WP#) pins are provided for hardware write protection of

device memory in the SST49LF008A. The TBL# pin is used to write protect 16 boot sectors (64 KByte)

at the highest flash memory address range for the SST49LF008A. WP# pin write protects the remain-

ing sectors in the flash memory.

An active low signal at the TBL# pin prevents Program and Erase operations of the top boot sectors.

When TBL# pin is held high, write protection of the top boot sectors is then determined by the Boot

Block Locking register. The WP# pin serves the same function for the remaining sectors of the device

memory. The TBL# and WP# pins write protection functions operate independently of one another.

Both TBL# and WP# pins must be set to their required protection states prior to starting a Program or

Erase operation. A logic level change occurring at the TBL# or WP# pin during a Program or Erase

operation could cause unpredictable results. TBL# and WP# pins cannot be left unconnected.

TBL# is internally OR’ed with the top Boot Block Locking register. When TBL# is low, the top Boot

Block is hardware write protected regardless of the state of the Write-Lock bit for the Boot Block Lock-

ing register. Clearing the Write-Protect bit in the register when TBL# is low will have no functional

effect, even though the register may indicate that the block is no longer locked.

WP# is internally OR’ed with the Block Locking register. When WP# is low, the blocks are hardware

write protected regardless of the state of the Write-Lock bit for the corresponding Block Locking regis-

ters. Clearing the Write-Protect bit in any register when WP# is low will have no functional effect, even

though the register may indicate that the block is no longer locked.

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Reset

IL on INIT# or RST# pin initiates a device reset. INIT# and RST# pins have the same function inter-

nally. It is required to drive INIT# or RST# pins low during a system reset to ensure proper CPU initial-

ization.

During a Read operation, driving INIT# or RST# pins low deselects the device and places the output

drivers, FWH[3:0], in a high-impedance state. The reset signal must be held low for a minimal duration

of time TRSTP. A reset latency will occur if a reset procedure is performed during a Program or Erase

operation. See Table 19, Reset Timing Parameters for more information. A device reset during an

active Program or Erase will abort the operation and memory contents may become invalid due to data

being altered or corrupted from an incomplete Erase or Program operation.

Write Operation Status Detection

The SST49LF008A device provides two software means to detect the completion of a Write (Program

or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two

status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is incorpo-

rated into the FWH Read cycle. The actual completion of the nonvolatile write is asynchronous with the

system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion

of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may

appear to conflict with either DQ7or DQ6. In order to prevent spurious rejection, if an erroneous result

occurs, the software routine should include a loop to read the accessed location an additional two (2)

times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is

valid.

Data# Polling (DQ7)

When the SST49LF008A device is in the internal Program operation, any attempt to read DQ7will pro-

duce the complement of the true data. Once the Program operation is completed, DQ7will produce

true data. Note that even though DQ7may have valid data immediately following the completion of an

internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data

bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase

operation, any attempt to read DQ7will produce a ‘0’. Once the internal Erase operation is completed,

DQ7will produce a ‘1’. Proper status will not be given using Data# Polling if the address is in the invalid

range.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any consecutive attempts to read DQ6will produce

alternating ‘0’s and ‘1’s, i.e., toggling between 0 and 1. When the internal Program or Erase operation

is completed, the toggling will stop.

Multiple Device Selection

The four ID pins, ID[3:0], allow multiple devices to be attached to the same bus by using different ID

strapping in a system. When the SST49LF008A is used as a boot device, ID[3:0] must be strapped as

0000, all subsequent devices should use a sequential up-count strapping (i.e. 0001, 0010, 0011, etc.).

The SST49LF008A will compare the strapping values, if there is a mismatch, the device will ignore the

remainder of the cycle and go into standby mode. For further information regarding FWH device map-

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

ping and paging, please refer to the Intel 82801(ICH) I/O Controller Hub documentation. Since there is

no ID support in PP Mode, to program multiple devices a stand-alone PROM programmer is recom-

mended.

Registers

There are three types of registers available on the SST49LF008A, the General Purpose Inputs regis-

ter, Block Locking registers and the JEDEC ID registers. These registers appear at their respective

address location in the 4 GByte system memory map. Unused register locations will read as 00H.

Attempts to read or write to any registers during internal Write operations will be ignored.

General Purpose Inputs Register

The GPI_REG (General Purpose Inputs Register) passes the state of FGPI[4:0] pins at power-up on

the SST49LF008A. It is recommended that the FGPI[4:0] pins are in the desired state before FWH4 is

brought low for the beginning of the bus cycle, and remain in that state until the end of the cycle. There

is no default value since this is a pass-through register. The GPI register for the boot device appears at

FFBC0100H in the 4 GByte system memory map, and will appear elsewhere if the device is not the

boot device. Register is not available for read when the device is in Erase/Program operation. See

Table 5 for the GPI_REG bits and function.

Table 5: General Purpose Inputs Register

Bit Function

Pin #

32-PLCC 32-TSOP 40-TSOP

7:5 Reserved - - -

4 FGPI[4]

Reads status of general

purpose input pin

30 6 7

3 FGPI[3]

Reads status of general

purpose input pin

31115

2 FGPI[2]

Reads status of general

purpose input pin

41216

1 FGPI[1]

Reads status of general

purpose input pin

51317

0 FGPI[0]

Reads status of general

purpose input pin

61418

T5.3 25085

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Block Locking Registers

SST49LF008A provides software controlled lock protection through a set of Block Locking registers.

The Block Locking Registers are read/write registers and it is accessible through standard addressable

memory locations specified in Table 6. Unused register locations will read as 00H.

Table 6: Block Locking Registers for SST49LF008A1

1. Default value at power up is 01H

T_BLOCK_LK 64K 0FFFFFH - 0F0000H FFBF0002H

T_MINUS01_LK 64K 0EFFFFH - 0E0000H FFBE0002H

T_MINUS02_LK 64K 0DFFFFH - 0D0000H FFBD0002H

T_MINUS03_LK 64K 0CFFFFH - 0C0000H FFBC0002H

T_MINUS04_LK 64K 0BFFFFH - 0B0000H FFBB0002H

T_MINUS05_LK 64K 0AFFFFH - 0A0000H FFBA0002H

T_MINUS06_LK 64K 09FFFFH - 090000H FFB90002H

T_MINUS07_LK 64K 08FFFFH - 080000H FFB80002H

T_MINUS08_LK 64K 07FFFFH - 070000H FFB70002H

T_MINUS09_LK 64K 06FFFFH - 060000H FFB60002H

T_MINUS10_LK 64K 05FFFFH - 050000H FFB50002H

T_MINUS11_LK 64K 04FFFFH - 040000H FFB40002H

T_MINUS12_LK 64K 03FFFFH - 030000H FFB30002H

T_MINUS13_LK 64K 02FFFFH - 020000H FFB20002H

T_MINUS14_LK 64K 01FFFFH -010000H FFB10002H

T_MINUS15_LK 64K 00FFFFH - 000000H FFB00002H

T6.4 25085

Table 7: Block Locking Register Bits

Reserved Bit [7..2] Lock-Down Bit [1] Write-Lock Bit [0] Lock Status

000000 0 0 Full Access

000000 0 1 Write Locked (Default State at Power-Up)

000000 1 0 Locked Open (Full Access Locked Down)

000000 1 1 Write Locked Down

T7.3 25085

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Write Lock

The Write-Lock bit, bit 0, controls the lock state described in Table 7. The default Write status of all

blocks after power-up is write locked. When bit 0 of the Block Locking register is set, Program and

Erase operations for the corresponding block are prevented. Clearing the Write-Lock bit will unprotect

the block. The Write-Lock bit must be cleared prior to starting a Program or Erase operation since it is

sampled at the beginning of the operation.

The Write-Lock bit functions in conjunction with the hardware Write Lock pin TBL# for the top Boot

Block. When TBL# is low, it overrides the software locking scheme. The top Boot Block Locking regis-

ter does not indicate the state of the TBL# pin.

The Write-Lock bit functions in conjunction with the hardware WP# pin for blocks 0 to 6. When WP# is

low, it overrides the software locking scheme. The Block Locking register does not indicate the state of

the WP# pin.

Lock Down

The Lock-Down bit, bit 1, controls the Block Locking register as described in Table 7. When in the FWH

interface mode, the default Lock Down status of all blocks upon power-up is not locked down. Once the

Lock-Down bit is set, any future attempted changes to that Block Locking register will be ignored. The

Lock-Down bit is only cleared upon a device reset with RST# or INIT# or power down. Current Lock

Down status of a particular block can be determined by reading the corresponding Lock-Down bit.

Once a block’s Lock-Down bit is set, the Write-Lock bits for that block can no longer be modified, and

the block is locked down in its current state of write accessibility.

JEDEC ID Registers

The JEDEC ID registers for the boot device appear at FFBC0000H and FFBC0001H in the 4 GByte

system memory map, and will appear elsewhere if the device is not the boot device. Register is not

available for read when the device is in Erase/Program operation. Unused register location will read as

00H. Refer to the relevant application note for details. See Table 2 for the device ID code.

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Parallel Programming Mode

Device Operation

Commands are used to initiate the memory operation functions of the device. The data portion of the

software command sequence is latched on the rising edge of WE#. During the software command

sequence the row address is latched on the falling edge of R/C# and the column address is latched on

the rising edge of R/C#.

Reset

IL on RST# pin initiates a device reset.

Read

The Read operation of the SST49LF008A device is controlled by OE#. OE# is the output control and is

used to gate data from the output pins. Refer to the Read cycle timing diagram, Figure 13, for further

details.

Byte-Program Operation

The SST49LF008A device is programmed on a byte-by-byte basis. Before programming, one must

ensure that the sector, in which the byte which is being programmed exists, is fully erased. The Byte-

Program operation is initiated by executing a four-byte command load sequence for Software Data

Protection with address (BA) and data in the last byte sequence. During the Byte-Program operation,

the row address (A10-A0) is latched on the falling edge of R/C# and the column Address (A21-A11)is

latched on the rising edge of R/C#. The data bus is latched in the rising edge of WE#. The Program

operation, once initiated, will be completed, within 20 µs. See Figure 14 for Program operation timing

diagram, Figure 17 for timing waveforms, and Figure 25 for its flowchart. During the Program opera-

tion, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the

host is free to perform additional tasks. Any commands written during the internal Program operation

will be ignored.

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Sector-Erase Operation

The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The

sector architecture is based on uniform sector size of 4 KByte. The Sector-Erase operation is initiated

by executing a six-byte command load sequence for Software Data Protection with Sector-Erase com-

mand (30H) and sector address (SA) in the last bus cycle. The internal Erase operation begins after

the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit

methods. See Figure 18 for Sector-Erase timing waveforms. Any commands written during the Sector-

Erase operation will be ignored.

Block-Erase Operation

The Block-Erase Operation allows the system to erase the device in 64 KByte uniform block size for

the SST49LF008A. The Block-Erase operation is initiated by executing a six-byte command load

sequence for Software Data Protection with Block-Erase command (50H) and block address. The

internal Block-Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined

using either Data# Polling or Toggle Bit methods. See Figure 19 for timing waveforms. Any commands

written during the Block-Erase operation will be ignored.

Chip-Erase

The SST49LF008A device provides a Chip-Erase operation only in PP Mode, which allows the user to

erase the entire memory array to the ‘1’s state. This is useful when the entire device must be quickly

erased.

The Chip-Erase operation is initiated by executing a six- byte Software Data Protection command

sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The internal

Erase operation begins with the rising edge of the sixth WE#. During the internal Erase operation, the

only valid read is Toggle Bit or Data# Polling. See Table 9 for the command sequence, Figure 20 for

timing diagram, and Figure 28 for the flowchart. Any commands written during the Chip-Erase opera-

tion will be ignored.

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Write Operation Status Detection

The SST49LF008A device provides two software means to detect the completion of a Write (Program

or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two

status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled

after the rising edge of WE# which initiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a

Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this

occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with

either DQ7or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software

routine should include a loop to read the accessed location an additional two (2) times. If both reads

are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

Data# Polling (DQ7)

When the SST49LF008A device is in the internal Program operation, any attempt to read DQ7will pro-

duce the complement of the true data. Once the Program operation is completed, DQ7will produce

true data. Note that even though DQ7may have valid data immediately following the completion of an

internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data

bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase

operation, any attempt to read DQ7will produce a ‘0’. Once the internal Erase operation is completed,

DQ7will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# pulse for Program

operation. For Sector- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# pulse.

See Figure 15 for Data# Polling timing diagram and Figure 26 for a flowchart. Proper status will not be

given using Data# Polling if the address is in the invalid range.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any consecutive attempts to read DQ6will produce

alternating ‘0’s and ‘1’s, i.e., toggling between 0 and 1. When the internal Program or Erase operation

is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is

valid after the rising edge of fourth WE# pulse for Program operation. For Sector-, Block- or Chip-

Erase, the Toggle Bit is valid after the rising edge of sixth WE# pulse. See Figure 16 for Toggle Bit tim-

ing diagram and Figure 26 for a flowchart.

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Data Protection

The SST49LF008A device provides both hardware and software features to protect nonvolatile data

from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# pulse of less than 5 ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, WE# high will inhibit the Write operation. This prevents inadver-

tent writes during power-up or power-down.

Software Data Protection (SDP)

SST49LF008A provides the JEDEC approved Software Data Protection scheme for all data alteration

operation, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-

byte sequences. The three-byte load sequence is used to initiate the Program operation, providing

optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down.

Any Erase operation requires the inclusion of a six-byte load sequence. The SST49LF008A device is

shipped with the Software Data Protection permanently enabled. See Table 9 for the specific software

command codes. During SDP command sequence, invalid commands will abort the device to Read

mode, within TRC.

Table 8: Operation Modes Selection (PP Mode)

Mode RST# OE# WE# DQ Address

Read VIH VIL VIH DOUT AIN

Program VIH VIH VIL DIN AIN

Erase VIH VIH VIL X1Sector or Block address, XXH for Chip-

Erase

Reset VIL X X High Z X

Write Inhibit VIH VIL X High Z/DOUT X

XXV

IH High Z/DOUT X

Product Identification VIH VIL VIH Manufacturer’s ID (BFH)

Device ID2

A18-A1=VIL,A

0=VIL

A18-A1=VIL,A

0=VIH

T8.6 25085

1. X can be VIL or VIH, but no other value.

2. Device ID = 5AH for SST49LF008A

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Software Command Sequence

Table 9: Software Command Sequence

Command

Sequence

1st1

Write Cycle

1. FWH Mode uses consecutive Write cycles to complete a command sequence; PP Mode uses consecutive bus cycles to

complete a command sequence.

2nd1

Write Cycle

3rd1

Write Cycle

4th1

Write Cycle

5th1

Write Cycle

6th1

Write Cycle

Addr2

2. Address format A14-A0(Hex), Addresses A21-A15 can be VIL or VIH, but no other value, for the Command sequence in

PP Mode.

Data Addr2Data Addr2Data Addr2Data Addr2Data Addr2Data

Byte-Program 5555H AAH 2AAAH 55H 5555H A0H BA3

3. BA = Program Byte address

Data

Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX4

4. SAXfor Sector-Erase Address

30H

Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BAX5

5. BAXfor Block-Erase Address

50H

Chip-Erase6

6. Chip-Erase is supported in PP Mode only

5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Software ID Entry7,8

7. SST Manufacturer’s ID = BFH, is read with A0=0,

With A19-A1= 0; 49LF008A Device ID = 5AH, is read with A0=1.

8. The device does not remain in Software Product ID mode if powered down.

5555H AAH 2AAAH 55H 5555H 90H

Software ID Exit9

9. Both Software ID Exit operations are equivalent.

XXH F0H

Software ID Exit95555H AAH 2AAAH 55H 5555H F0H

T9.6 25085

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Electrical Specifications

The AC and DC specifications for the FWH Interface signals (FWH[3:0], CLK, FWH4, and RST#) as

defined in Section 4.2.2 of the PCI Local Bus Specification, Rev. 2.1. Refer to Table 12 for the DC voltage

and current specifications. Refer to the tables on pages 24 through 29 for the AC timing specifications for

Clock, Read/Write, and Reset operations.

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute

Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these conditions or conditions greater than those defined in the

operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating con-

ditions may affect device reliability.)

Temperature Under Bias .............................................. -55°C to +125°C

Storage Temperature................................................. -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential .............................-0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential1.................-2.0V to VDD+2.0V

1. Do not violate processor or chipset limitations on the INIT# pin.

Package Power Dissipation Capability (TA=25°C).................................... 1.0W

Surface Mount Solder Reflow Temperature2...........................260°C for 10 seconds

2. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.

Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest

information.

Output Short Circuit Current3................................................... 50mA

3. Outputs shorted for no more than one second. No more than one output shorted at a time. This note applies to non-PCI

outputs.

Table 10:Operating Range

Range Ambient Temp VDD

Commercial 0°C to +85°C 3.0-3.6V

T10.1 25085

Table 11:AC Conditions of Test1,2

1. See Figures 23 and 24

2. FWH interface signals use PCI load test conditions

Input Rise/Fall Time Output Load

3ns CL=30pF

T11.1 25085

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

DC Characteristics

Table 12:DC Operating Characteristics (All Interfaces)

Symbol Parameter

Limits

Test Conditions1

1. Test conditions apply to PP mode.

Min Max

Unit

IDD Active VDD Current LCLK (FWH mode) and Address Input (PP

mode)=VILT/VIHT at f=33 MHz (FWH mode)or1/

TRC

min (PP Mode)

All other inputs=VIL or VIH

Read 12 mA All outputs = open, VDD=VDD Max

Write2

2. IDD active while Erase or Program is in progress.

24 mA See Note3

3. For PP Mode: OE# = WE# = VIH; For FWH mode:f=1/T

RC min, LFRAME# = VIH, CE# = VIL.

ISB Standby VDD Current

(FWH Interface)

100 µA LCLK (FWH mode) and Address Input (PP

mode)=VILT/VIHT

at f=33 MHz (FWH mode)or1/

TRC min (PP Mode)

LFRAME#=0.9 VDD, f=33 MHz, CE#=0.9 VDD,

VDD=VDD Max, All other inputs 0.9 VDD or 0.1

VDD

IRY4

4. The device is in Ready Mode when no activity is on the FWH bus.

Ready Mode VDD Cur-

rent

(FWH Interface)

10 mA LCLK (FWH mode) and Address Input (PP

mode)=VILT/VIHT

at f=33 MHz (FWH mode)or1/

TRC min (PP Mode)

LFRAME#=VIL, f=33 MHz, VDD=VDD Max

All other inputs 0.9 VDD or 0.1 VDD

IIInput Current for IC,

ID [3:0] pins

200 µA VIN=GND to VDD,V

DD=VDD Max

ILI Input Leakage Current 1 µA VIN=GND to VDD,V

DD=VDD Max

ILO Output Leakage Cur-

rent

1µAV

OUT=GND to VDD,V

DD=VDD Max

VIHI5

5. Do not violate processor or chipset specification regarding INIT# voltage.

INIT# Input High Volt-

age

1.0 VDD+0.

DD=VDD Max

VILI5INIT# Input Low Volt-

age

-0.5 0.4 V VDD=VDD Min

VIL Input Low Voltage -0.5 0.3

VDD

DD=VDD Min

VIH Input High Voltage 0.5

VDD

VDD+0.

DD=VDD Max

VOL Output Low Voltage 0.1

VDD

OL=1500µA, VDD=VDD Min

VOH Output High Voltage 0.9

VDD

OH=-500 µA, VDD=VDD Min

T12.10 25085

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Table 13:Recommended System Power-up Timings

Symbol Parameter Minimum Units

TPU-READ1Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Write Operation 100 µs

T13.2 25085

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter

Table 14:Pin Impedance (VDD=3.3V, TA=25 °C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

I/O Pin Capacitance VI/O =0V 12pF

CIN1Input Capacitance VIN =0V 12pF

LPIN2

2. Refer to PCI spec.

Pin Inductance 20 nH

T14.4 25085

Table 15:Reliability Characteristics

Symbol Parameter Minimum Specification Units Test Method

NEND1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T15.3 25085

Table 16:Clock Timing Parameters

Symbol Parameter Min Max Units

TCYC CLK Cycle Time 30 ns

THIGH CLK High Time 11 ns

TLOW CLK Low Time 11 ns

- CLK Slew Rate (peak-to-peak) 1 4 V/ns

- RST# or INIT# Slew Rate 50 mV/ns

T16.1 25085

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Figure 8: CLK Waveform

AC Characteristics (FWH Mode)

Table 17:Read/Write Cycle Timing Parameters, VDD =3.0-3.6V (FWH Mode)

Symbol Parameter Min Max Units

TCYC Clock Cycle Time 30 ns

TSU Data Set Up Time to Clock Rising 7 ns

TDH Clock Rising to Data Hold Time 0 ns

TVAL1

1. Minimum and maximum times have different loads. See PCI spec.

Clock Rising to Data Valid 2 11 ns

TBP Byte Programming Time 20 µs

TSE Sector-Erase Time 25 ms

TBE Block-Erase Time 25 ms

TSCE Chip-Erase Time 100 ms

TON Clock Rising to Active (Float to Active Delay) 2 ns

TOFF Clock Rising to Inactive (Active to Float Delay) 28 ns

T17.3 25085

1161 F11.0

0.4 VDD p-to-p

(minimum)

Tcyc

Thigh

Tlow

0.4 VDD

0.3 VDD

0.6 VDD

0.2 VDD

0.5 VDD

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Table 18:AC Input/Output Specifications, VDD =3.0-3.6V (FWH Mode)

Symbol Parameter

Limits

Test ConditionsMin Max Units

IOH(AC) Switching Current High -12 VDD

-17.1(VDD-VOUT)

Equation C1

0<V

OUT 0.3VDD

0.3VDD <V

OUT < 0.9VDD

0.7VDD <V

OUT <VDD

(Test Point) -32 VDD mA VOUT=0.7VDD

IOL(AC) Switching Current Low 16 VDD

26.7 VOUT

Equation D1mA

VDD >VOUT 0.6VDD

0.6VDD >V

OUT > 0.1VDD

0.18VDD >V

OUT >0

(Test Point) 38 VDD mA VOUT=0.18VDD

ICL Low Clamp Current -25+(VIN+1)/0.015 mA -3 < VIN -1

ICH High Clamp Current 25+(VIN-VDD-1)/0.015 mA VDD+4 > VIN VDD+1

slewr2Output Rise Slew Rate 1 4 V/ns 0.2VDD-0.6VDD load

slewf2Output Fall Slew Rate 1 4 V/ns 0.6VDD-0.2VDD load

T18.3 25085

1. See PCI spec.

2. PCI specification output load is used.

Table 19:Reset Timing Parameters, VDD =3.0-3.6V (FWH Mode)

Symbol Parameter Min Max Units

TPRST VDD stable to Reset Low 1 ms

TKRST Clock Stable to Reset Low 100 µs

TRSTP RST# Pulse Width 100 ns

TRSTF RST# Low to Output Float 48 ns

TRST1

1. There will be a latency of TRSTE if a reset procedure is performed during a Program or Erase operation.

RST# High to FWH4 Low 1 µs

TRSTE RST# Low to reset during Sector-/Block-Erase or Program 10 µs

T19.5 25085

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Figure 9: Reset Timing Diagram

Figure 10:Output Timing Parameters

CLK

VDD

RST#/INIT#

FWH4

FWH[3:0]

1161 F12.0

TPRST

TKRST TRSTP

TRSTF

TRSTE Sector-/Block-Erase

or Program operation

aborted

TRST

VAL

TEST

OFF

1161 F13.0

CLK

FWH [3:0]

(Valid Output Data)

FWH [3:0]

(Float Output Data)

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Figure 11:Input Timing Parameters

Table 20:Interface Measurement Condition Parameters

Symbol Value Units

VTH1

1. The input test environment is done with 0.1 VDD of overdrive over VIH and VIL. Timing parameters must be met

with no more overdrive than this.

VMAX specified the maximum peak-to-peak waveform allowed for measuring input timing. Production testing may

use different voltage values, but must correlate results back to these parameters.

0.6 VDD V

VTL10.2 VDD V

VTEST 0.4 VDD V

VMAX10.4 VDD V

Input Signal Edge Rate 1 V/ns

T20.3 25085

TSU

TDH

Inputs

Valid

1161 F14.0

CLK

FWH [3:0]

(Valid Input Data)

VTEST

VTL

VMAX

VTH

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

AC Characteristics (PP Mode)

Table 21:Read Cycle Timing Parameters, VDD =3.0-3.6V (PP Mode)

Symbol Parameter Min Max Units

TRC Read Cycle Time 270 ns

TRST RST# High to Row Address Setup 1 µs

TAS R/C# Address Set-up Time 45 ns

TAH R/C# Address Hold Time 45 ns

TAA Address Access Time 120 ns

TOE Output Enable Access Time 60 ns

TOLZ OE# Low to Active Output 0 ns

TOHZ OE# High to High-Z Output 35 ns

TOH Output Hold from Address Change 0 ns

T21.2 25085

Table 22:Program/Erase Cycle Timing Parameters, VDD =3.0-3.6V (PP Mode)

Symbol Parameter Min Max Units

TRST RST# High to Row Address Setup 1 µs

TAS R/C# Address Setup Time 50 ns

TAH R/C# Address Hold Time 50 ns

TCWH R/C# to Write Enable High Time 50 ns

TOES OE# High Setup Time 20 ns

TOEH OE# High Hold Time 20 ns

TOEP OE# to Data# Polling Delay 40 ns

TOET OE# to Toggle Bit Delay 40 ns

TWP WE# Pulse Width 100 ns

TWPH WE# Pulse Width High 100 ns

TDS Data Setup Time 50 ns

TDH Data Hold Time 5 ns

TIDA Software ID Access and Exit Time 150 ns

TBP Byte Programming Time 20 µs

TSE Sector-Erase Time 25 ms

TBE Block-Erase Time 25 ms

TSCE Chip-Erase Time 100 ms

T22.2 25085

Table 23:Reset Timing Parameters, VDD =3.0-3.6V (PP Mode)

Symbol Parameter Min Max Units

TPRST VDD stable to Reset Low 1 ms

TRSTP RST# Pulse Width 100 ns

TRSTF RST# Low to Output Float 48 ns

TRST1

1. There will be a reset latency of TRSTE or TRSTC if a reset procedure is performed during a Program or Erase operation.

RST# High to Row Address Setup 1 µs

TRSTE RST# Low to reset during Sector-/Block-Erase or Program 10 µs

TRSTC RST# Low to reset during Chip-Erase 50 µs

T23.1 25085

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Figure 12:Reset Timing Diagram (PP Mode)

Figure 13:Read Cycle Timing Diagram (PP Mode)

VDD

RST#

Addresses

R/C#

DQ7-0

1161 F15.0

TPRST

TRSTP

TRSTF

TRSTE

Row Address

Sector-/Block-Erase

or Program operation

aborted

TRST

TRSTC Chip-Erase

aborted

1161 F16.0

Column Address

Data Valid High-Z

Row AddressColumn AddressRow Address

RST#

Addresses

R/C#

VIH

High-Z

TRST TRC

TAS TAH TAH

TAA

TOE

TOLZ TOHZ

TOH

TAS

WE#

OE#

DQ7-0

TRSTP

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Figure 14:Write Cycle Timing Diagram (PP Mode)

Figure 15:Data# Polling Timing Diagram (PP Mode)

1161 F17.0

Column AddressRow Address

Data Valid

RST#

Addresses

R/C#

TRST

TAS TAH

TCWH

TWP TWPH

TOEH

TDH

TDS

TAH

TAS

WE#

OE#

DQ7-0

TOES

TRSTP

1161 F18.0

Addresses

R/C#

TOEP

Row Column

WE#

OE#

DQ7D#D D# D

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Figure 16:Toggle Bit Timing Diagram (PP Mode)

Figure 17:Byte-Program Timing Diagram (PP Mode)

1161 F19.0

Addresses

R/C#

TOET

Row Column

WE#

OE#

DQ6D D

1161 F20.0

TWP TWPH TBP

Four-Byte Code for Byte-Program

5555 2AAA 5555 BA

SB0

BA = Byte-Program Address

SB1 SB2 SB3 Internal Program Starts

WE#

Addresses

R/C#

OE#

Data55AA A0

DQ7-0

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Figure 18:Sector-Erase Timing Diagram (PP Mode)

Figure 19:Block-Erase Timing Diagram (PP Mode)

1161 F21.0

TWP TWPH

TSE

Six-Byte code for

Sector-Erase Operation

5555 2AAA 5555 5555 2AAA SAX

SB0

SAX= Sector Address

SB1 SB2 SB3 SB4 SB5 Internal Erasure Starts

WE#

Addresses

R/C#

OE#

55AA55AA 80 30

DQ7-0

1161 F22.0

TWP

TWPH TBE

Six-Byte code for

Block-Erase Operation

5555 2AAA 5555 5555 2AAA BAX

SB0 SB1 SB2 SB3 SB4 SB5 Internal Erasure Starts

WE#

Addresses

R/C#

OE#

55AA55AA 80 50

DQ7-0

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Figure 20:Chip-Erase Timing Diagram (PP Mode)

Figure 21:Software ID Entry and Read (PP Mode)

1161 F23.0

TWP

TWPH

TSCE

Six-Byte code for Chip-Erase Operation

5555 2AAA 5555 5555 2AAA 5555

SB0 SB1 SB2 SB3 SB4 SB5 Internal Erasure Starts

WE#

Addresses

R/C#

OE#

55AA55AA 80 10

DQ7-0

1161 F24.2

Addresses

TIDA

DQ7-0

WE#

SW0

Device ID = 5AH for SST49LF008A

SW1 SW2

5555 2AAA 5555 0000 0001

OE#

R/C#

Three-byte sequence for

Software ID Entry

TWP

TWPH TAA

Device ID

55AA 90

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Figure 22:Software ID Exit and Reset (PP Mode)

Figure 23:AC Input/Output Reference Waveforms (PP Mode)

Figure 24:A Test Load Example (PP Mode)

1161 F25.0

Addresses

DQ7-0

TIDA

TWP

TWPH

WE#

SW0 SW1 SW2

5555 2AAA 5555

Three-Byte Sequence for

Software ID Exit and Reset

OE#

R/C#

AA 55 F0

1161 F26.0

REFERENCE POINTS OUTPUTINPUT VIT

VIHT

VILT

VOT

AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Mea-

surement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise

and fall times (10% 90%) are <5 ns.

Note: VIT -V

INPUT Test

VOT -V

OUTPUT Test

VIHT -V

INPUT HIGH Test

VILT -V

INPUT LOW Test

1161 F27.0

TO TESTER

TO DUT

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Figure 25:Byte-Program Algorithm

1161 F28.0

Start

Write data: AAH

Address: 5555H

Write data: 55H

Address: 2AAAH

Write data: A0H

Address: 5555H

Load Byte

Address/Byte

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Figure 26:Wait Options

1161 F29.0

Wait TBP,

TSCE, TBE

or TSE

Byte-

Program/Erase

Initiated

Internal Timer Toggle Bit

Ye s

Program/Erase

Completed

Does DQ6

match

Read same

byte

Data# Polling

Program/Erase

Completed

Program/Erase

Completed

Read byte

Is DQ7=

true data

Read DQ7

Byte-

Program/Erase

Initiated

Byte-

Program/Erase

Initiated

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Figure 27:Software Product Command Flowcharts

1161 F30.0

Write data: AAH

Address: 5555H

Software Product ID Entry

Command Sequence

Write data: 55H

Address: 2AAAH

Write data: 90H

Address: 5555H

Wait TIDA

Read Software ID

Write data: AAH

Address: 5555H

Software Product ID Exit

Reset Command Sequence

Write data: 55H

Address: 2AAAH

Write data: F0H

Address: 5555H

Write data: F0H

Address: XXH

Return to normal

operation

Wait TIDA

Return to normal

operation

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Figure 28:Erase Command Sequence

1161 F31.0

Write data: AAH

Address: 5555H

Chip-Erase

Command Sequence

Write data: 55H

Address: 2AAAH

Write data: 80H

Address: 5555H

Write data: 55H

Address: 2AAAH

Write data: 10H

Address: 5555H

Write data: AAH

Address: 5555H

Wait Options

Chip erased

to FFH

Write data: AAH

Address: 5555H

Sector-Erase

Command Sequence

Write data: 55H

Address: 2AAAH

Write data: 80H

Address: 5555H

Write data: 55H

Address: 2AAAH

Write data: 30H

Address: SAX

Write data: AAH

Address: 5555H

Wait Options

Sector erased

to FFH

Write data: AAH

Address: 5555H

Block-Erase

Command Sequence

Write data: 55H

Address: 2AAAH

Write data: 80H

Address: 5555H

Write data: 55H

Address: 2AAAH

Write data: 50H

Address: BAX

Write data: AAH

Address: 5555H

Wait Options

Block erased

to FFH

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Product Ordering Information

Valid combinations for SST49LF008A

SST49LF008A-33-4C-WHE SST49LF008A-33-4C-NHE SST49LF008A-33-4C-EIE

Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST

sales representative to confirm availability of valid combinations and to determine availability of new combi-

nations.

SST 49 LF 008A - 33 - 4C - EIE

XX XX XXXX - XX - XX -XXX

Environmental Attribute

E1= non-Pb

Package Modifier

H = 32 leads

I = 40 leads

Package Type

N = PLCC

W = TSOP (type 1, die up, 8mm x

14mm)

E = TSOP (type 1, die up, 10mm x

20mm)

Operating Temperature

C = Commercial = 0°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Serial Access Clock Frequency

33 = 33 MHz

Version

A = Second Version

Device Density

008 = 8 Mbit

Voltage Range

L = 3.0-3.6V

Product Series

49 = Firmware Hub for Intel 8xx Chip-

sets

1. Environmental suffix “E” denotes non-Pb solder.

SST non-Pb solder devices are “RoHS Compliant”.

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Packaging Diagrams

Figure 29:32-lead Plastic Lead Chip Carrier (PLCC)

SST Package Code: NH

.040

.030

.021

.013

.530

.490

.095

.075

.140

.125

.032

.026

.032

.026

.029

.023

.453

.447

.553

.547

.595

.585

.495

.485 .112

.106

.042

.048

.042

.015 Min.

TOP VIEW SIDE VIEW BOTTOM VIEW

1232

.400

BSC

32-plcc-NH-3

Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (max/min).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.

4. Coplanarity: 4 mils.

.050

BSC

.050

BSC

Optional

Pin #1

Identifier .020 R.

MAX. R.

x30°

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Figure 30:32-lead Thin Small Outline Package (TSOP) 8mm x 14mm

SST Package Code: WH

32-tsop-WH-7

Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

1.20

max.

1mm

Pin # 1 Identifier

12.50

12.30

14.20

13.80

0.70

0.50

8.10

7.90 0.27

0.17

0.50

BSC

1.05

0.95

0.15

0.05

0.70

0.50

0°- 5°

DETAIL

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Figure 31:40-lead Thin Small Outline Package (TSOP) 10mm x 20mm

SST Package Code: EI

18.50

18.30

20.20

19.80

0.70

0.50

10.10

9.90

0.27

0.17

1.05

0.95

0.15

0.05

0.70

0.50

40-tsop-EI-7

Note: 1. Complies with JEDEC publication 95 MO-142 CD dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

Pin # 1 Identifier

0.50

BSC

1.20

max.

0°- 5°

DETAIL

1mm

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Table 24:Revision History

Revision Draft Changes Date

06 •2002 Data Book

•Changed Transient Voltage from -1.0V to VDD +1.0V to -2.0V to VDD

+2.0V to match Intel FWH spec per IBM requirement.

•Added footnote for Transient Voltage.

•Updated footnote for Output Short Circuit Current.

•Updated Data# Polling description

•Corrected the values in Table 5 on page 14: General Purpose Inputs

•Added note to Table 12 on page 23: DC Operating Characteristics

July 2001

07 •Added 40-lead TSOP for SST49LF008A only

•Corrected the IDD Test Conditions in Table 12 on page 23

June 2003

08 •2004 Data Book

•Updated document status to Data Sheet

Dec 2003

09 •Removed 2 Mbit and 3 Mbit devices - refer to EOL Product Data Sheet

S71161(01)

Oct 2004

10 •Removed 32-PLCC (NH/NHE) Package and associated MPNs for the 4

Mbit device

refer to EOL Product Data Sheet S71161(03).

•Clarified the Solder Temperature Profile under “Absolute Maximum

Stress Ratings” on page 22

Nov 2004

11 •Removed 4 Mbit WH/WHE device - refer to EOL Product Data Sheet

S71161(03)

•Added statement that non-Pb devices are RoHS compliant to Features

section

•Updated Surface Mount Solder Reflow Temperature information

•Removed leaded part numbers

•Applied new formatting

Mar 2006

A•Applied new document format

•Released document under letter revision system

•Updated Spec number from S71161 to DS25085

Oct 2011

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Tech-

nology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc. All other trademarks and

registered trademarks mentioned herein are the property of their respective owners.

Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation. For the most current

package drawings, please see the Packaging Specification located at http://www.microchip.com/packaging.

Memory sizes denote raw storage capacity; actual usable capacity may be less.

SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of

Sale.

For sales office locations and information, please see www.microchip.com.

Silicon Storage Technology, Inc.

A Microchip Technology Company

www.microchip.com

ISBN:978-1-61341-713-3