711017462 - LSI CORPORATION

EXHIBIT 69

EXHIBIT

Data Sheet

September 2007

TruePHYTMET1011C

Gigabit Ethernet Transceiver

t_s| 232"“

Features

n lOBa.se-T, l()OBase-'l‘X, and lO00Base-T

gigabit Ethemet transceiver:

A 0.13 pm process

- 128-pinTQFP and 84-pinMLCC:

ORGMII, GMII, Mll, RTBI, and TBI interfaces to

MAC or switch

— 68-pin MLCC:

0 RGMII and RTBI interfaces to MAC or switch

ll Low power consumption:

— Typical power less than 750 mW in 1000Basc-T

mode

——Advanced power management

- ACPIcompliantwake-on-LANsupport

II Ovcrsarnpling architecture to improve signal integrity

and SNR

.. Optimized, extended performance echo and NEXT ﬁl

ters

11All-digital baseline wander correction

ll Digital PGA control

n On-chip diagnostic support

I1 Automatic speed negotiation

n Automatic speed downshilt

n Single supply 3.3 V or 2.5 V operation:

— On-chip regulator controllers

# 3.3 V or 2.5 V digital I/O

——3.3 V tolerant l/O pins (MDC, MDIO, COMA,

RESET_N, and JTAG pins)

— l .0 V or 1.1 V core power supplies

4 1.8V or 2.5 V for transformer center tap

It JTAG

n ETIO IlC is a pin-compatible replacement for the

ETl0l1 device

n Commercial- and industrial—temperatureversions avail

able

Introduction

The LS1ETl0l 1C is a Gigabit Ethemet transceiver fabri

cated on a single CMOS chip. Packaged in either an 128

pin TQFP, an 84-pin MLCC, or a

68-pin MLCC, the ETl()l 1C is built on 0.13 um technol

ogy for low power consumption and application in sen/er

and desktop NIC cards. it features single power supply

operation using on-chip regulator controllers. The 10/100/

l00()Base-T device is fully compliant with lEEE® 802.3,

8()2.3u, and 802.3ab standards.

The F.Tl()11C uses an oversampling architecture to gather

more signal energy from the communication channel than

possible with traditional architectures. The additional sig

nal energy or analog complexity transfers into the digital

domain. The result is an analog front end that delivers

robust operation, reduced cost, and lower power consump

tion than traditional architectures.

Using oversampling has allowed for the implementation ot

a fractionally spaced equalizer. which provides better

equalization and has greater immunity to timing jitter.

resulting in better signal-to-noise ratio (SNR) and thus

improved BER. In addition. advanced timing algorithms

are used to enable operation over a wider range of cabling

plants.

Tr:ueP{-IYETl01lC I Data sheet

Gigabit Ethernet Transceiver September 2007

Contents Page

Features.........i...........,.

Introduction

Functional Description

Oversampling Architecttue..........

Automatic Speed Downsbift........

Transmit Functions

Receive Functions...........................

u|uru\>--

Autonegotiation ............7

Carrier Sense (128-Pin TQFP and

84-PinMLCCOnly)

Link Monitor.....................

RegulatorControl

Resetting the 1~1'l‘1011C.........

LoopbaekMode

Digital Loopback

Analog L0opback........

Low-Power Modes................

Pinlnfonnation ....

Pin Diagram, 128-Pin TQFP

Pin Diagram. 84-Pin MLCC

Pin Diagram. 68'Pin MLCC

Pin Descriptions, 128-Pin TQF1’.84-Pin MLCC,

and 68-Pin MLCC ..................................................... ..

MAC lnterface .......

Management Interface

Conﬁguration interface

l,EDs Interface ..........

Media-Dependent Interface:

Transformer lnterface

Clocking and Reset

RegulatorControl

Power,Ground,andNoConnect

Cable Diagnostics...............................

RegisterDescription

Electrical Speciﬁcations ......

Absolute Maximum Ratings ..........

RecommendedOperatingConditions

DeviceElectricalCharacteristics

Timing Speciﬁcation .................. .......................... ..

GM111000Base-T Transmit Timing

(128-Pin TQ1-"Pand 84-1-‘inMLCC Only) ................. ..

GMll l()()0Base-TReceive Timing

(128-Pin TQFP and 84-Pin MLCC Only)...................

RG3/lll 1()O0Basc-TTransmit 'l‘iming..........

RGMH1000Basc-TReceiveTiming

M111()0Base-TX Transmit Timing........

Mll l0OBase-TX Receive Timing

M11l0Base-T Transmit Timing

__r>-~,--»-¢»--»

-|>L’~3{\IK\)l--*@\Q\DOODOO€'OC\l

Table of Contents

Contents Page

M111OBase-T Receive Timing ......

Serial Management Interface Timing.........

ResetTiming

Clock

JTAG

Package

Timing

Diagram, 128-Pin TQFP

Diagram, 84—PinMLCC

Diagram, 68-Pin MLCC

()rdering1nfo1-mation ...............

Table

Table 1. ETIOI 1C Device Signals

Table 2.

Table 3.

‘Table 4.

Table 5.

by Interface, 128-Pin TQFP, 84-Pin

and 68-Pin MLCC.......................

Multiplexed Signals on the ETl011C

GMII Signal Description (10l)()Base-T

Mode) (128-pin TQFP and

84-pin MLCC only) ................................. ..

RGM11Signal Description

(l0l)()Base-T Mode) ................................. ..

Mll Interface (1OOBase-TX and

1()Base-'1‘)(l28~Pin TQFP and

84-Pin MLCC Only).............. ....................

Table 6. Ten-Bit Interface (1000Base-T)

Table 7.

Table 8.

Table 9.

Table 10

Table 11

Table 12

Table 13

Table 14

Table 15

Table 16

Table 17

Table 18

Table 19

Table 20

Table 21

Table 22

Table 23

Table 24

Table 25

Table 26

Table 27

(128-Pin TQFP and 84-Pin MLCC Only)..

RTBI Signal Description

(1000Base—TMode) ........

ManagementFrameStructure

Management 1nterfaee...............

. Conﬁguration Signals.............,

.TransformerlnterfaceSignals

. Clocking and Reset .............

..1'1‘AGTest Interface .........

. Regulator Control 1nterfaee..t......

. Supply Voltage Combinations........

. Power. Ground, and No Connect........

.CableDiagnosticFunctions

. Register Address Map.............. .

. Register Type Deﬁnition

. Control Register—Address (1 .

. Status Register‘/Xddress 1...........

. PHY identiﬁer Register 1—Address 2

. PHY Identiﬁer Register 2-—Address 3

. Autonegotiation Advertisement Rcgister—

Address4 ...................................

.Autonegotiatlon Link Partner Ability

. Autonegotiation Expansion Register

--Address 6 ..............................................,

.......76

.......77

.......78

.......79

.......8O

.......8l

.......82

.......83

.......84

Page

.....2O

.....22

4<4'I24

.....25

.....26

.....28

.....29

I{.—'34

.....35

.....36

.....37

¢I4QI37

......4(1

......4O

......4l

.....43

LS1Corporation

Data Sheet TruePHYET10l1C

September 2007 Gigabit Ethernet Transceiver

Table of Contents (continued)

Table Page Table Page

Table 28

Table 29.

Table 30

Table 31

Table 32

Table 33

Table 34

Table 35

Table 36.

Table 37.

Table 38

Table 39.

Table 40.

Table 41

Table 42.

Table 43

Table 44.

Table 45

Table 46.

Table 47.

Table 48.

Table 49.

Table 50

Table 51

Table 52

Table 53

Table 54.

Table 55

Table 56

. Autonegotiation Next Page Transmit

LinkPartnerNextPageRegister

Acldress 8....................................................... ..

1000 Base-T Control Register——»

Address 9.................... .......................... ..

lOO()Base-T Status Register -----

Address l0 .......................................

ReservedRegisters—Addresses ll—l4

Extended Status Rcgister—-Address l5

Reserved Registers—Acldresses 16»-17

Pl lY Control Register 2——Addrcss

MDI/MDl-X Conﬁguration

MDI/MDI-X Pin

Loopback Control Register—Address

Loopback Bit (0.14) and Cable Diagnostic

Mode Bit (23.13) Settings for

Loopback Mode...... ...................

RX Error Counter Register»-Address 20

Management Interface (MI) Control

PIIY Conﬁguration Rcgister—-Address

PHY Control Register—/Xddress

4‘)

lnterrupt Mask Register—Address 24

Interrupt Status Register—~Address25

PllYStatusRegister-—Address26

LED Control Register l-—Address

LEDControlRegister2*/\ddress28

LEDControlRegister3—Address29

. Diagnostics Control Register

(TDR Mode}—Address 30 ............................ ..

Diagnostics Status Register

(TDR Mode)—Address 31..............................

Diagnostics Control Register

(Link Analysis M0de)—Addrcss 30

. MD]/MDT-XConﬁguration for l00OBase-T

with C and D Swappcd/Not Swapped .............

Absolute Maximum Ratings ...............................

. ETIOI lC Recommended

Operating Conditions.................

. Device Charactei'lstios—3.3 V

Digital l/(J Supply (DVDDIO) ........................

l,Sl Corporation

Table 57

Table 58

Table 59

Table 60

Table 6l

Table (>2

Table 63

Table 64

Table 65

Table 66.

Table 67

Table 68

Table 69.

Table 70.

Table 71

Table 72

Table 73

Table 74

Table 75

Table 76

Table 77

Table 78

Table 79

Table 80

Device Characteristies——-2.5V

Digital l/O Supply (DVDDIO)

ET] 01lC Current Consumption

l000Base-T .....................................

ETl0l lC Current Consumption

l0OBase~TX.................................. ..

ET] Ol1C Current Consumption

l0Base-T .........

ETlOl 1C Current Consumption

l0Base-T idle ..................................

ET1OllC Current Consumption

Hardware Powerdown .....................

ETl0l 1CCurrent Consumption

Low Power Energy Detect (LPIIZD)

ET1011C Current Consumption

Standby Powerdown .......................

lETlO11C Current Consumption

Software Powerdown

GMll l0tl(lBase-T Transmit Timing ..

GMll l000Base-T Receive Tirning....

RGMll l0O0l3ase-TTransmit Timing

RGMII l0()0Base-T Transmit Timing

RGMII lO00Base-T Receive Timing.

RGMII lO0()Base-TReceive Timing.

l\/ill l00Base-TX Transmit Timing

Mll l0()Base-TX Receive Timing......

Mll l0Base-T Transmit Timing

Mll l0Base-T Receive Timing...........

Serial Management Interface Timing.

Reset Timing .................................... ..

Clock Timing.............

JTAG Timing................

Ordering Information

TruePHYET101lC Data Sheet

September 2007

Gigabit Ethernet Transceiver

Table ofContents

Figure Page

Figure l. E'l‘1011CBlock Diagram........

Figure 2. Leopbaek Functionality

Figure 5. External Cable Loopbaek ...........

Figure 6. Pin Diagram for E'l‘l0l TCin

128-Pin TQFP Package (Top View) ..............

Figure 7. Pin Diagram for ETIOI lC in

84-PinMLCCPackage(TopView)

Figure 8. Pin Diagram for ETlOl1C in

68—PinMLCC Package (TopView)

Figure 9. ET1()l lC Gigabit Ethernet Card

BlockDiagram.......... .

Figure10.GMIIMAC-PHYSignals

Figure ll. RGMll MAC-PHY Signals.........

Figure I2. Mll Signals .......

Figure 13.Ten-Bit Interface

Figure 14. Reduced Ten-Bit Interface

Figure 15. GMT]l()0()Base-T Transmit Timing.................

Figure 16. GMII l00OBase-T Receive Timing ..................

Figure 3. Digital Loophack.........................................

Figure 4. Replica and Line Driver Analog Loopback

@<D\‘D\DU1

Figure

Figure l7

Figure 18

Figure l9.

Figure 20.

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

(continued)

Page

RGMII l00OBase-T Transmit Timing—

Trace Delay ......................... ......

RGMII lOO0Base-T Transmit 'l"iming~-

Internal Delay .............................................. ..7O

RGMTI l()0OBase-T Receive Timing—

TraceDelay .................................................7l

RGMII l00OBase-T Receive Timing—

Internal Delay ....................... ..

MII lO0Base-TX Transmit Timing....................73

.Mll l00Base-TX ReceiveTiming........

MII 1OBase-TTransmit Timing

MII 10Base-T Receive Timing.

SerialManagementinterfaceTiming

ResetTiming.............................

Clock

JTAG Timing......... .........80

LS1Corporation

Data Sheet TruePHYETl011C

September 2007 Gigabit Ethernet Transceiver

Functional Description

The LS1ETl01lC is a Gigabit Ethernet transceiver that simultaneously transmits and receives on each of the four UTP pairs of

category 5 cable (signal dimensions or channels A, B, C, and D) at 125 Msymbols/s using ﬁve-level pulse-amplitude modulation

(PAM). Figurc l is a block diagram of its basic conﬁguration.

it ,,,/‘ ,°

if u / ma

GTX_CLK

III

TX_CLK

TXD[7:0]

TX_ER

NEXT Echo Transmit

GM" Cancellers Canceller Shaping DAG

TX_EN

IIII-I

at 71 g G)

RX_C LK

RXD|_7:0]

RX ER

M Hybrld

PCS ADC PGA

TRD[0—3]t

RSET

PHYAD[4:0]

MDC

MDlNT_N

.. PMAA

H 6 I I 

_ BLW Gain @ I

RX_DV Correction Control

COL

CRS :

Trellis Timing Clock

Decoder Control Generator JTAGI

LEDS LEDSI Test

Conﬁg Confls Negaﬁaﬂon 1OBA$E-T

: Management 

MDIO I lmemlce MlRegisters

TCK

TRST_N

TMS

TDO

SYS_CLK

XTAL_1

XTAL__2

RESET_N

Figure 1.ETl011C Block Diagram

Oversampling Architecture

The ETl0l 1C architecture uses oversampling techniques to

sample at two times the symbol rate. A fractionally spaced

feed forward equalizer (FFE) adapts to remove intersymbol

interference (lSl) and to shape the spectrum of the received

signal to maximize the (SNR) at the trellis decoder input.

The l~‘Fliequalizes the channel to a ﬁxed target response.

Oversampling enables the use ofa fractionally spaced equal

izer (FSE) structure for the FFE, resulting in symbol rate

clocking for both the FFE and the rcst of the receiver. This

provides robust operation and substantial power savings.

LSI Corporation

Automatic Speed Downshift

Automatic speed downshift is an enhanced feature ol‘autone

gotiation that allows the BT10] 1C to:

n Fallback in speed, based on cabling conditions or link

partner abilities.

l'\ Operate over CAT-3 cabling (in lOBase-T mode).

n Operate over two—pairCAT-5 cabling (in l00Base-TX

mode).

For speed fallback, the ETl0l1C ﬁrst tries to autonegotiate

by advertising l()()0Base—Tcapability. After a number of

failed attempts to bring up the link, the ETl0l1C falls back

to advertising l00Base—TXand restarts the autonegotiation

process. This process continues through all speeds down to

l0Base—T.At this point, there are no lower speeds to try and

so the host enables all technologies and starts again.

PHY conﬁguration register. address 22, bits ll and |()

enable automatic speed downshift and speciﬁes if fallback to

lOBase-T is allowed. PHY control register. address 23. bits

ll and l2 specify the number of failed attempts before

downshift (programmable to 1,2, 3, or 4 attempts).

TruePHYETl0l1C

Gigabit Ethernet Transceiver Data Sheet

September 2007

Functional Description (continued)

Transmit Functions

l000Base-T Encoder

ln l000Base-T mode, the E'[‘l0llC translates 8-bit data

from the MAC interfaces into 21code group offour quinary

symbols that are then transmitted by the PMA as 4D ﬁve

levcl PAM signals over the four pairs ol‘CAT-5 cable.

l00Base-TX Encoder

ln lO0Base-TX mode, 4-bit data from the media independent

interface (Mil) is 4B/SB encoded to output

5-bit serial data at 125 MHZ. The bit stream is sent to a

scrambler, and then encoded to a three-level MLT3sequence

that is then transmitted by the PMA.

10Base-T Encoder

in l0Base-T mode, the ETl0l 1Ctransmits and receives

Manchester-encoded data.

Receive Functions

Decoder 100llBase-T

In l0O(lBase-Tmode, the PMA recovers the 4D PAM signals

alter compensating for the cabling conditions. The resulting

code group is decoded to 8-bit data. Data stream delimiters

arc translated appropriately, and the data is output to the

receive data pins of the MAC

interfaces. The GMll receive error signal is asserted when

invalid code groups are detected in the data stream.

Decoder l00Base-TX

In lOOBase—TXmode, the PMA recovers the three-level

MLT3 sequence that is descrarnhled and 5B/4B decoded to

4-bit data. This is output to the Mll receive data pins after

data stream delimiters have been translated appropriately.

The Mil receive error signal is asserted when invalid code

groups are detected in the data stream.

Decoder 10Base-T

ln 1OBase-'l‘mode. the ET10 l IC decodes the Manchester

encoded received signal.

Hybrid

The hybrid subtracts the transmitted signal from the input

signal allowing full-duplex operation on each of the twisted

pair cables.

Programmable Gain Ampliﬁer (PGA)

The PGA operates on the received signal in the analog

domain prior to the analog-to-digital converter (ADC). The

gain control module monitors the signal at the output ofthc

ADC in the digital domain to control the PGA. lt implements

a gain that maximizes the signal at the ADC while ensuring

that no hard clipping occurs.

ClockGenerator

A clock generator circuit uses the 25 Mllz input clock signal

and a phase-locked loop (Pl,l.) circuit to generate all the

required internal analog and digital clocks. A 125 Ml-lz sys

tem clock is also generated and is available as an output

clock.

Analog-to-DigitalConverter

The ADC operates at 250 MHz oversampling at twice the

symbol rate in l0OOBase—Tand lO0Basc-TX. This enables

innovative timing recovery and fractional skew correction

and has allowed transfer of analog complexity to the digital

domain.

Timing Recovery/Generation

The liming recovery and generator block creates transmit

and receive clocks for all modes of operation. In transmit

mode, the 1OBase-Tand lO0Base-TX modes use the 25

Ml-lzclock input. While in receive mode, the input clock is

locked to the rcccivc data stream. l000Base—Tis imple

mented using a master-slave timing scheme, where the mas

ter transmit and receive are locked to the 25 MHZ clock

input, and the slave acquires timing information from the

receive data stream. Timing recovery is accomplished by

ﬁrst acquiring lock on one channel and then making use of

the constant phase relationship between channels to lock on

the other pairs, resulting in a simpliﬁed PLL architecture.

Timing shifts due to changing environmental conditions are

trackedby the ETl0l lC.

LSI Corporation

Data Sheet

September 2007 TruePHYET1011C

Gigabit Ethernet Transceiver

Functional Description (continued)

Adaptive Fractionally Spaced Equalizer

The ET101lC’s unique oversampling architecture employs

an FSE in place of the traditional FFE structure. This results

in robust equalization ofthc communications channel, which

translates to superior bit error rate (BER) performance over

the widest variety of worst-case cabling scenarios. The all

digital equalizer automatically adapts to changing condi

Lions.

Echo and Crosstalk Cancellers

Since the four twisted pairs arc bundled together and not

insulated from each other in Gigabit Ethernet, each of the

transmitted signals is coupled onto the three other cables and

is seen at the receiver as near-cnd crosstalk (NEXT). A

hybrid circuit is used to transmit and receive simultaneously

on each pair. if the transmitter is not perfectly matched to the

line. a signal component will be reﬂected back as an ccho.

Reﬂections can also occur at other connectors or cable

imperfections. The ETIOI 1Ccancels echo and NEXT by

subtracting an estimate ofthese signals from the equalizer

output.

Baseline Wander Correction

A known issue for 10()0Base-T and l00Base~TX is that the

transformer attenuates at low ﬂequencies. As a result, when

a large number of symbols of the same sign are transmitted

consecutively, the signal at the receiver gradually dies away.

This effect is called baseline wander. By employing a circuit

that continuously monitors and compensates for this effect,

the probability of encountering a receive symbol cn'or is

reduced.

LS1Corporation

Autonegotiation

Autonegotiation is implemented in accordance with IEEE

802.3. Thc device supports 10Base-T, l00Base-'1'X, and

l00OBase-T and can autonegotiate between them in either

halil or full-duplex mode. it can also parallel detect l0Base

T or l00Base-TX. lfautonegotiation is disabled, a l0Base-T

or lO0Base-TX link can be manually selected via the IEEE

M11registers.

Pair SkewCorrection

ln Gigabit Ethernet, pair skew (timing differences between

pairs ofcable) can result from differences in length or manu

facturing variations between the four individual twisted-pair

cables. The ETIOI 1C automatically corrects forboth integer

and fractional symbol timing differences between pairs.

Automatic MDI Crossover

During autonegotiation, the lZTl0l IC automatically detects

and sets the required MD1conﬁguration so that the remote

transmitter is connected to the local receiver and vice vcrsa.

This eliminates the need for crossover cables or crosswircd

(M1)IX)poi1s. Ifthe remote device also implements auto

matic MDI crossover, and/or the crossover is implemented in

the cable. the crossover algorithm ensures that only one ele

ment implements the required crossover.

Polarity Inversion Correction

In addition to automatic M1)! crossover that is necessary for

autonegotiation, 10Base-T,and 100Base-TX operation, the

ET1011C automatically corrects crossover of the additional

two pairs used in 1000Basc-T. Polarity inversion on all pairs

is also corrected. Both of these effects may arise if the

cabling has been incorrectly wired.

Carrier Sense (128-PinTQFP and 84-PinMLCC

Only)

The carrier sense signal (CRS) of the MAC interface is

asserted by the 1~lT101lCwhenever the receive medium is

nonidle. In hall‘-duplexmode, CRS may also be asserted

when the transmit medium is nonidle. The CRS may be

enabled on transmit in half-duplex mode by writing to the

Pl1Y conﬁguration register, address 22, hit 15.

TruePHYET10l1C

Gigabit Ethernet Transceiver Data Sheet

September 2007

Functional Description (continued)

Link Monitor

l000Base-T 

Once l()00Base-T is autonegotiated and the link is estab

lished. both link partners continuously monitor their local

receiver status. If the master device determines a problem

with its receiver, it signals the slave and both devices cease

transmitting data but transmit IDLE. If the master retrains its

receiver within 750 ms, then normal operation recom

mences. Otherwise, both devices restart autonegotiation.

If the slave device determines a problem with its receiver, it

ceases transmitting and expects the master to transmit the

IDLE sequence. ll’the slave retrains its receiver within 350

ms, normal operation recommcnces when the master signals

that its receiver is ready. Il‘either receiver fails to reacquire,

then autonegotiation is restarted.

100Base-TX

In l0OBase-TX mode, the ETl0l 1C monitors the link and

determines the link quality based on signal energy. mean

square error and scrambler lock. ll’the link quality is deemed

insufﬁcient, transmit and receive data are disabled. lf the

link had been autonegotiated, then control is handed back to

autonegotiation. If the link had been manually set, the

l()()Base~'l‘Xreceiver is retrained, and the transmitter is set

to transmit idle. Once the link quality has been recovered,

data transmit and receive are enabled.

l0Base—T

In lOBase-'l‘mode, the l;‘T|(ll lC monitors the link and

determines the link quality based either on the presence of

valid link pulses or valid l(lBase-T packets. If the link is

deemed to have failed and the link had been autonegotiated,

then control is handed back to autoncgotiation. If the link

had been manually set, the ETI 011C continues to try to rees

tablish the link.

LEDS

Four status LEDs are provided. These can be used to indicate

speed ofopcration, duplex mode, link status, etc. There is a

very high degree of programrnability allowed. Hence. the

LEDs can be programmed to diﬁ"erentstatus functions from

their default value, or they can be controlled directly from

the r\/lllregister interface. The LED signal pins can also be

used for general-purpose I/() if not needed for LED indica

tion.

Regulator Control

The ETl0llC has two on-chip regulator controllers. This

allows the device to be powered from a single supply, either

3.3 V or 2.5 V.The on-chip regulator control circuits provide

output control voltages that can be used to control two exter

nal transistors and thus provide regulated 1.0 V and 2.5 V

supplies.

Resetting the ET1011C

The ETl0l1C provides the ability to reset the device by

hardware (pin RESET_N) or via sollware through the man

agcment interface. A hardware reset is accomplished by

driving the active-low pin RESET_N to Ovolts for a mini

mum of20 ps. The conﬁguration pins and the physical

address conﬁguration are read during a hardware reset. A

hardware reset is required alter powerup in order to ensure

proper operation.

A software reset is accomplished by setting bit l5 of the con

trol register (Mll register address 0. bit 15). The conﬁgura

tion pins and the physical address conﬁguration are not read

during software reset.

LS1 Corporation

Data Sheet TruePHYET10l1C

September 2007 Gigabit Ethernet Transceiver

Functional Description (continued)

Loopback Mode

Enabling loopback mode allows in-circuit testing of the ETlOl lC's digital and analog data path.

The ETIOI IC provides several options for loopbaek that test and verify various functional blocks within the PHY.These are

digital loopbaek and analog loopbaek. Figure 2 is a block diagram that shows the PHY loopbaek functionality.

AllDigital Loopback Replica Loopback

MACI PHY PHY Remote

Switch Digital AFE PHY

T Y

RMllLoopback kl LineDriverLoopback

Figure 2. Loopback Functionality

—~§o

The loopback mode is selected by setting the respective bit in the PHY loopback control register, Mll register address l9. The

default loopbaek mode is digital Mll loopback. Loopback is enabled by writing to the PHY control register, address O,bit l4.

Digital Loopback

Digital loopback provides the ability to loop the transmitted data back to the receiver via the digital circuitry. The point at

which the signal is looped back is selected using the loopback control register with the following options being provided: Mll

and all digital. Selecting the Mil option gives a simple loopbaek with minimal latency where the data is looped back directly

at the media-independent interface. This loopback is currently set as the default, but it should be noted that it only exercises a

small percentage ofthe Pl-lY circuitry. When the all-digital option is selected, the transmitted data is looped back at the inter

face between the digital and the analog circuitry, thereby exercising a high percentage of the digital logic. Figure 3 shows a

block diagram of digital loopback.

MAC! l PHY PHY

Switch Digital AFE

Figure 3. Digital Loopbaek

~—zo

LS1 Corporation 9

TruePHYET1011C Data sheet

Gigabit Ethernet Transceiver September 2007

Functional Description (continued)

Analog Loopback

Analog loopback provides the ability to loop the transmitted signal back to the receiver within the AFE. The point at which the

signal is looped back is selected using the loopback control register with the following options being provided: replica and line

driver.

Selecting the replica option causes the transmitted signal to be looped back through the replica generation circuitry of the on

chip hybrid, thereby allowing most ofthc digital and analog circuitry to be exercised. This loopback mode may be used even

when the device is connected to a network because nothing is transmitted to or received from the l\/[Diin this case.

Line driver loopback transmits data to and receives data from the MDI. llowever, in general, this loopback may not be used

when the device is connected to a network because it could cause an unanticipated response from the link partner. Line driver

loopbaek requires 100Q terminations to be present on the line side of the transformer for each wire pair. For example, for wire

pair A, connect a 100 Q resistor between the leads (pins l and 2) ofa short cable plugged into the RJ45. This should also be

done for wire pairs B, C, and D. Another way to accomplish this is to connect to a link partner with a short cable and power

down the link partner. Figure 4 shows a block diagram of both replica and line driver loopbacks.

REPLICA LOOPBAC K

MACI PHY PHY

Switch Digital AFE R145

Figure 4. Replica and Line Driver Analog Loopback

—-—§CD

External Cable Loopback

External cable loopback loops GMIITx to GM|l Rx via complete digital and analog path and via an external cable.

The external cable should have pair A (pins 1 and 2) looped to pair B (pins 3 and 6), and pair C (pins 4 and 5)

looped to pair D (pins 7 and 8). This willtest all the digital data paths and all the analog circuits. Figure 5 shows a

block diagram of external cable loopback

MAC/ PHY PHY 2

Figure 5. External Cable Loopback

— —- § CD

Q QQQQ

pond

DOOCG

I0 LS1Corporation

Data Sheet

September 2007 TruePHYET1011C

Gigabit Ethernet Transceiver

Functional Description (continued)

Low-Power Modes

Hardware Powerdown Mode

In Hardware Powerdown, all Pl-IY functions (analog and

digital) are disabled. During Hardware Powerdown,

SYSgCLK is not available and the Mll registers are not

accessible. This is the lowest power mode for the ETl011C.

llardware Powerdown is entered when the LPED_EN_N and

SYS__CLK__EN__Npins are high (dcassertcd). and either the

COMA signal is high (asserted) or the RESET_N signal is

driven low (asserted).

Low-Power Energy-Detect (LPED) Mode

In LPED mode, the PHY is in a low power state but still

monitors the cable (MDI interface) for energy. If energy is

detected. the MDINT_N pin is asserted. During LPED

mode, SYS_CLK is not available and the Mll registers are

not accessible. The host system monitors the MDINT_N pin

and then places the PHY into a regular operating mode in

response to the interrupt. LPED mode is entered when the

I.PED_EN_N pin is low (asserted). SYS__CLK_I5N_Npin is

high (deasserted). and either the COMA signal is high

(asserted) or the RESET__Nsignal is driven low (asserted).

At exit from Hardware Powerdown or LPED modes, the

ETl 0l IC does the following:

n Initializes all analog circuits including the PLL.

n Initializes all digital logic and state machines.

n Reads and latches the PHY address pins.

n Initializes all Mil registers to their default values (H/W

conﬁguration pins are reread).

Standby Powerdown Mode

In Standby Powerdown, most PIIY functions (analog and

digital) are disabled but the PLL is still running. During

Standby Powerdown, SYS_CLK is available and the Mil

registers are not accessible. Standby Powerdown mode is

entered when the LPED_l£l\I_Npin is high (deasscrted).

SYS_Cl.K_F.N_N pin is low (asserted), and either the

COMA signal is high (asserted) or the RESET_N signal is

driven low (asserted).

Standby Powerdown with Low-Power Energy—Detect

(LPED) Mode

LSI Corporation

This powerdown mode is a combination of Standby Power

down mode and LPEI) mode. The PLL is running and the

PIIY monitors the cable (MDI interface) for energy. If

energy is detected. the Ml)lN'l‘_N pin is asserted. During

this mode, SYS_CLK is available and the Mll registers are

not accessible. The host system monitors the MI)INT_N pin

and then places the PHY into a regular operating mode in

response to the interrupt. This mode is entered when the

LPED“EN_N pin is low (asserted), SYS___CLK_EN_Npin is

low (asserted), and either the COMA signal is high

(asserted) or the RESET_N signal is driven low (asserted).

At exit from Standby Powerdown or Standby Powerdown

with LPED, the ETIOI lC docs the following:

.1 Initializes all analog circuits excluding the PLL.

.. Initializes all digital logic and state machines.

n Reads and latches the PHY address pins.

l1 Initializes all Mil registers to their default values (l-l/W

conﬁguration pins are reread).

Software Powerdown Mode

Soﬂware powerdown is entered when bit I1of the control

powerdown, all PHY functions except the serial manage

ment interface and clock circuitry are disabled. The Mil reg

isters can be read or written. If the system clock output is

enabled (MII register address 22. bit 4), the 125 Ml-lzsystem

clock will still be available tor use by the MAC on pin

SYS_CLK.

At exit from software powerdown, the BT10] lC initializes

all digital logic and state machines only. NOTE: The H/W

conﬁguration pins and the PHY address pins are not re-read

and the Mil registers are not reset to their default values.

These operations are only done during reset or recoveiy ii-om

hardware powerdown.

Wake-On-LAN Powerdown Mode

ACPI power consumption compliant Wake-On-LAN mode

is implemented on the ET] OllC by using the IEEE standard

Mll registers to put the PIIY into lOBase-T or l()0Base-TX

modes. Clearing the advertisement of l()0OBase-T (M11reg

ister address 9, bits 8, 9) and setting the desired l()Base-T

and lO0Base—'I‘Xadvertisement (MII register address 4, bits

5—8) activates this feature. This must be followed by an

autonegotiation restart via the control register (Mil register

address 0, bit 9).

TruePH YETI 011C Data Sheet

Gigabit Ethernet Transceiver September 2007

Pin Information

Pin Diagram, 128-Pin TQFP

uvss

TXD[3]

TXDI-1|

TXD|5|

TXD[6|

TxD17|

nvss

nvnmo

TCK

vou

nvss

TRST__N

TMS1SYS_ (‘LK_l-IN_N

TD!/LPED EN N

TDO

MAr_n'q_sEl.|u|

M/\(‘ 1+"sum]

M.»\(T_II-‘_SELI'l]

AUTO_>MD|_EN

VDD

nvss

COMA

VDD

nvss

AVDDL

AVSS

AVDDH

(‘l.K_lN/XTAl.__1

X'l‘AL_2

N(‘

RI3SET_N

N("

XI!

115

1‘)

23 1:1 TXD

Z7111 TXD

6 1:1 TXD

25 —-— Tx_ /rxn

124 III TX_ER/TXD

123tit DVSS

_§Z

."‘m5‘

TRD 0

TRD

AVS

AVDD

TRD

A 7

A '

TRD 2

RD 2

A .

D .

AVK

221:1 NC

-X0

-U

-16

-I8

,x_c1.m= \1A_TX__(‘LK/TXC

DDIO

/COMMA

L/P.\{A_RX_CLK

120

11)

117

LS1

iii G"

ill NC

111 DV

8 II1 TX_

1:1 DV'

1:1 CR5

_ iii CO

141:1 NC

U3 ill RXVCLK/'P.\h\_RXC

I2jIZ DV

1:1 DV

111 RX_

1:1 RX

iii KXD

iii RXD

111 RXD

1:1 RXD

11 NC

1 1-1 [H

ETIOI 1C

-¢..

—.v;‘

I1 —

\ s

1112

\ s

nu 2

VSS

V§S

DDL

I\C

rm 0

ERJRXD

_uv/1u<n a fRX_CTL

1:55

109

108

106

I05

+1:1

-alt

_31$

1:1

+3:1

1:1

$11

51:1

L1:1

51:1

H1:1 1

T —-— 5

]__1:1 5

1tut 5

1:3 5

11$ 5!

' 1:1 57

iii $3

1:1 59

1:1 60

tit Gl

ZI1 62

IIIII 6}

1:1 64

L _.

,. ,

TR V58

T {3

A DDL

102

101

100

‘J6

l]<

9-4

<12

7:;

7-:

(-9

(>7

(>6

vu0

uvss

nxnp]

RXms]

RXme]

RXD[7]

ovumo

nv &§

SYS_(‘LK

nvss

v 01>

MIX‘

MDIO

M01 NT_N

uvumo

PRES

LEl)__l.Nwr muss

LED_\ 000/SPEED_lm1<»

VDD

nvss

CTRI._1V0

CTRI._2V5

vun__|usn

DVSS

PHYAD[I1|fLED_'l'XRX

PI-iYAD[1|./|.Eu_|ou

PllYAD[2]

PHYA[)[3]

m-mmg-:1

Figure 6. Pin Diagram for ET101lC in 128-Pin TQFP Package (Top View)

12 I SI Corpm anon

Data Sheet TruePHYET10l1C

September 2007 Gigabit Ethernet Transcelver

TXD[5]Q 1

TXD[6]Q 2

TXD[7]Q 3

DVDDIDQ 4

TCKQ 5

vooQ 5

NCQ 7

NCQ s

NCQ 9

NCQ 10

NCQ 11

TRST_NI 12

TMSlSYS_CLK_EN_NQ 15

TDI/LPED_EN_NQ 14

TDOQ 15

MAC_|F_SEL[0]Q 1s

MAC_|F_SEL[1)Q 17

MAC_|F_SEL{2]Q 1s

VDDQ 19

AVDDLQ 20

AVDDHQ 21

Pill IIlf0l"l113ﬁ0Il (continued)

Pin Diagram, 84-Pin MLCC

s4 Q 7x014)

cm N/XTAL_1Q 22 as Q TXD[3]

XTAL__2i 23 s2 Q TXD2

RESET_NQ 24

21 Q TXD

TRDl04-- 25 anQTxno

TRD[(J}- 26

ENFTXDIB!'TX_CTLlTXD[4)

79 Q TX__

AVDDLQ 27 7s Q Tx_ERrr><0[e

EXPOSED PAD (DVSS AND AVSS)

TR|:11+Q2s 77 Q GTX_CLK/PMA_TX_CLK/TXC

TRD1]-i Z9 76 I DVDDO

7s Q TX_CLK

LS1

74 Q CRS/COMMA

72. Q COL/PM/\_RX_CL|<[1

72 Q RX_CLK/PMA_RX_CLK[OIRxc

ETl0llC

AVDDLQ so

AVDDHQ 3

RSETQ 32

AVDDLQ as

112012+ Q 24 71Q nvon 0

70 Q RX_ER/RXD9

69 - RX_DVlRXD8 IRX__CYL/RXDI4]

TRD2>:35

AVDDLQ 36

TRD3}-PI 37 ea Q RXDO

TRD3-I38 57QRx01

AVDDLQ as as Q RXD21

PHYAD43Q 4n 65 - RXD3]

54 Q ovum0

PHYAD3]- 41

PHYAD2]I 42

63Q vnn

62 Q RXD[4]

61 Q RXD[5]

60 Q RXD[6]

59 Q RXDU]

58Q Dvomo

57Q sv$_cu<

5s Q VDD

55 Q MDC

54 Q M010

53 Q MD\NT__N

52Q nvomo

51 Q PRES

50 Q LED_LNKIPAUSE

49 Q LED_1OGO/SPEED_1000

as Q VDD

47 Q CTRL_1V0

4a Q CTRL_2V5

45 Q VDD_REG

44 Q Pl-lYAI)[0].’l.ED_TXRX

43 Q PI—l'YAD[l1.-'1.ED>lou

Figure 7. Pin Diagram for ETHNIC in 84-Pin MLCC Package (Top View)

LS1Corporation

TruePH YET1011C Data Sheet

Gigabit Ethernet Transceiver September 2007

Pin Information (continued)

Pin Diagram, 68-Pin MLCC

Isa — RX_CTL

671 TXD

__CTL

[62G DVDD0

[61Q TX_CLK

DDO

E __ _

58$ TXD3

(ea- RXC

163- TXC

{es_ TXD

jeeq TXD

[64G TX

Isa- DV

DVDDIO 1 -:’

TCK2 i)

VDD I 3

DVSS_ 4 :

TR$T_N_ 5 ;

TMS/SYS_CLK__EN_N- e 1

TD|fLPED_EN_N 7 :

TDO- a 1 LS!

MAC_1F_SEL[0] 9 : ET1011C

MAC_|F_SEL[1]- 10 1

VDD 11 ‘

COMA121

von 1:1;

AVDDL 14;

AVDDH " 15'

CLK IN/XTAL1 15 '

XTAL_2117 I_ EXPOSFD PAD (DVSS AND

1-I23

RESET_N- 12

TRDO+I19

TRD[0- - 20

AVDDLI 24

AVDDHI 25

RSETD 25

AVDDLI 27

TRD21+_ 23

AVDDLI 21

TRD

157- RXD0

AVSS)

TRD2—I29

Isa — RXD 1

AVDDLD 30 ﬁes- RXD2

TRD3-P131

I54— RXD 3]

TRD31-I 32 Isa- ovnn0

AVDDLI 33 52Z VDD

51C

50C

49¢;

4sC

47C

46C

45C

44C

43$

42CZl

41C

40C]

39C

sac

37C

36C!

35(I

PHYAD3 D

ovnmo

SYS_CLK

vno

MDC

MDIO

MDlNT__N

uvomo

PRES

LED_LNK/PAUSE

LED_10U0fSPEED_1000

voo

CTRL_1V0

CTRL_2\/5

VDD_REG

PHYAD[O]ILED_T>(RX

PHYAD[1]/LED_1D0

PHYAD[2]

Figure 8. Pin Diagram for ETIOHC in 68-Pin MLCC Package (Top View)

14 LS1 Corporation

Data Sheet TruePHYET101lC

September 2007 Gigabit Ethernet Transceiver

Pin Information (continued)

Pin Descriptions, 128-Pin TQFP, 84-Pin MLCC, and 68—PinMLCC

Table 1. ET10l1C Device Signals by Interface, 128-Pin TQFP, 84~Pin and 68—PinMLCC

Name Description Pad Internal 3- Analog Pin # Pin # Pin #

Type Pull-Up/ State I28-Pin 84-Pin 68-Pin

Pull-Down TQFP MLCC MLCC

MAC: GMIl——GigahitMedia-Independent Interface (128-Pin TQFP and 84-Pin MLCC Only)

0"rx_cu< GMII transmit clock

-4

-— 121 77 ——

TX_ER Transmit error

>-1

—- 124 78 —

TX_EN Transmit enable

t_.

A 125 79

'rxn[7;0] Transmit data bits

-1

Pull-dovm —— 7, 6,5,4,3 128,

127, 126 3. 2,1, 84.

83, 82, 81, 80

RX_CLK Receive clock

-— 113 72

RX_ER Receive error

— 110 70

RX_DV Receive data valid

— 10.9 69

RXD[7:0] Receive data bits

-— 97, 98, 99, 100,

105, 106, 107,

108

59, 60. 61, 62,

65, 66, 67. 68

CRS Carrier sense OZ—~ 116 74

COL Collision detect OZ—— 115 73

MAC: RGMII-Reduced GigabitMedia-IndependentInterface

TXC RGMII transmit clock I —- 121 77 63

TXD [3 :01 Transmit data bits 1Pull-down - 3, 128,

127, 126 83, 82. 81, 80 67, 66

'I‘X_CTL Transmit control 1— 125 79 64

RXC Receive clock OZ—- 113 72 60

RXD[3 =0] Receive data bits OZ—— 105.106,

107, 108 65, 66, 67, 68 55.56

RX~CTL Receive eontrol OZ-- 109 69 58

MAC: 1VIIl—1VIedia-IndependentInterface (128-Pin TQFP and 84-Pin MLCC Only)

TX_CLK M11transmit clock OZ— 118 75

TX_ER Transmit error I— I24 78

TX_EN Transmit enable

>-<

— 125 79

TXD[3 :0] Transmit data bits

>—<

Pull-down -— 3, 128,

127, 126 83, 82, 81, 80

RX_CLK Receive clock

-—— 113 72

RX_1£1R Receive error

— 110 70

RX__DV Receive data valid

—-— 109 69

RXD[3:0_] Receive data bits

i 105,106,

107. 108 65. 66, 67, 68

CRS Carrier sense OZW 116 74

COL Collision detect OZ——— 115 73

LS1Corporation 15

TruePHYET101lC Data Sheet

Gigabit Ethernet Transceiver September 2007

Pin Information (continued)

Pin Descriptions, 128-Pin TQFP, 84-Pin MLCC, and 68-Pin MLCC (continued)

Table 1. ET1011C Device Signals by Interface, 128-Pin TQFP, 84-Pin and 68-Pin MLCC (continued)

Name Description Pad Internal 3—State Analog Pin # Pin #

Type Pnll-Up/ 128-Pin 84-Pin

Pull-Down TQFP MLCC

Pin #

68-Pin

MLCC

MAC: TBl—Ten-Bit Interface (128-Pin TQFP and 84-Pin NILCC Only)

PM/\_ TX_CLK T131transmit clock I __ _- i 121 77 

TXD[9:O] Transmit data bits 1 Pull-down

U11

'1‘xn[710] 5,4,3,128, 1,84,

127,126 83,82,141,

80,

— 7 124,125, 7, 6, 78, 79, 3, 2, —

PMA_RX__CLK[()] TB1 receive clock O — Z 113 72

RXD[9:()] Receive data bits O —- Z 110, 109, 97, 70, 69, 59,

98, 99,100, 60, 61. 62,

105, 106, 107, 65, 66, 67,

108 68,

PMA_RX_ c1.1<[1] T131receive clock O — Z 115 73

COMMA Valid comma detect O __ __ 116 74

MAC. RTBl—--Reduced Ten-Bit Interface

TXC RTB1transmit clock I _ _ 121 77 63

TXD13 :0] Transmit data bits 1 Pull-down ~—~ 3, 128, 127, 8

126 3, 82,

81, 80, 68, 67,

66, 65

'r><,c"r1, Transmit control I ._ __ 125 79 64

RXC RTBI receive clock O — Z 113 72 60

RXD[3:0] Receive data bits 0 ,~- Z 105. 108

106,107. 65, 66, 67

68 54, 55,

56. 57

RX_CTL Receive control O ——— Z 109 69 58

MD1:Transformer Interface

‘I'RD[0]+

'l‘RD[O]—

Transmit and receiv

differemial pair

(3 l/O ——  A39 25 19

41 26 20

TRD[1j+

TRD[1 1

Transmit and receive

ciifferential pair

1/O — — A45 28 22

47 29 23

TRD[2]+

TRD[2]

Transmit and receiv

differential pair

61/o -  A54 34 28

56 35 29

TRD[3]+

TRD[3]—

Transmit and receiv

differential pair

61/O — — A60 37 31

62 38 32

RSET Analog reference re

tor sis 1/O ——- — A52 32 26

16 LS1 Corporation

Data Sheet TruePHYET1011C

September 2007 Gigabit Ethernet Transceiver

Pin Information (continued)

Pin Descriptions, 128-Pin TQFP, 84-Pin MLCC, and 68-Pin MLCC (continued)

Table 1. ET10l1C Device Signals by Interface, 128-Pin TQFP, 84-Pin and 68-Pin MLCC (continued)

Type Pull-Up/

Pull-Down 128-Pin

TQFP 84-Pin

MLCC

Name Description Pad Internal 3-State Analog Pin # Pin # Pin #

68-Pin

MLCC

Management InterfaCB

Pl-lYAD[4:O] Pl—lYaddress 4—l l, l. L

l./O

Pull~d0wn — —~ 67, 68,

PHY address 0 l/O Pull-up

69, 7l_

40, 41,

42, 43,

34, 35,

36, 37

Pl-IYAD

[310]

MDC Management interface clock IPull-down 91 55 48

MDlO Management data I/O I/0 Pull~up 90 54 47

MDlN'l‘_N Management interface inter

rupt

O89 53 46

Conﬁguration‘

s EED_l0()0 l00()Base-T speed select Pull-up 82 49 42

Pause mode

,_.l

Pull-down 85 50 43

PAUSE

AU'l‘O_MDl EN Auto-MDI detection enable

>-<

Pull-up 21

M/\CHlF_SEL[O] MAC interface select 0

--4

Pull-down 18 l6 9

MAC_IF_SE [1] MAC interface select 1

>-w

Pull-down 19 17 10

MAC_lF_SEL[2] MAC interface select 2

,_.

Pull-down 20 18

SYS CLK EN N System clock enable

>-1

Pull-up 15 13 6

I‘PED_EN_N Low power energy

detection enable

»-1

Pull-up l6 l4 7

PRES Precision resistor lA87 5l 44

ll Configuration signal

tion and later to sel

LS1 Corporation

ect the polarity to drive the LEDS.

s are multiplexed with the LED controls. During a reset, the status of the conﬁguration pins are latched and used to set the conﬁgura

TruePHYET101lC Data Sheet

Gigabit Ethernet Transceiver September 2007

Pin Information (continued)

Pin Descriptions, 128-Pin TQFP, 84-Pin MLCC, and 68-Pin MLCC (continued)

Table 1. ET|0l1C Device Signals by Interface, 128-Pin TQFP, 84-Pin and 68—PinMLCC (continued)

Name Description Pad Internal 3-State Analog Pin # Pin # Pin #

Type Pull-Up/ I28-Pin 84-Pin 68-Pin

Pull-Down TQFP MLCC MLCC

LED Interface

1.2111000 1000Base-T LED OPull-up — 49 42

LED_1.NK Link established LED OPull~d0wn —~ 50 43

LED_TXRX General-purpose LED l/() Pull-up  44 37

LED_l00 General-purpose LED l/O Pull-down 4 43 36

JTAG

TCK Test clock Pull-up A 5

I\7

TR S'1‘_N Test reset Pull-down  12

TMS Test mode select Pull-up — 13

TD I Test data input Pull-up — l4

TDO Test data output

Pull-up — 15

Clocking and Reset

CLKWIN Reference eloek input l/O A22 l6

XTAL_l Reference crystal input l/O A22 l6

XTAL_2 Reference crystal l/O A23 l7

SYS_CLK System clock () 57 50

RESE'l‘_N Reset l24 l8

COMA Hardware powerdown lPull-down — 12

Regulator Control

CTRL__lvo Regulator control 1.0 V OA47 40

CTRL_2V5 Regulator control 2.5 V OA46 39

1 Conﬁguration signals are 1nultiplexed with the LED controls During a reset, the status of the configuration pins are latched and used to set the configura

uon and later to select the polarity to drive the LEDs.

18 LS1 Corporation

Data Sheet TruePHYET101l C

September 2007 Gigabit Ethernet Transceiver

Pin Information (continued)

Pin Descriptions, 84-Pin MLCC and 68-Pin MCCC (continued)

Table 1. ETl01lC DeviceSignals by Interface, 128-Pin TQFP, 84-Pin and 68-Pin MLCC (continued)

Name Description Pad

Type lnternal 3-State Analog Pin#

Pull-Up/ 128-Pin

Pull-Down TQFP

Pin #

84-Pin

MLCC

Pin #

68-Pin

MLCC

Power, Ground, and No Connect

VDD_REG Regulator 2.5 V or 3.3

V supply

VDD 77 45 38

DVDDIO Digital l/O 2.5 V or 3.3

V supply

Vnn 9, 88, 96,111,

119 4, 52, 58,

64, 71, 76 1,413.51

53,59.

VDD Digital core 1.0 V sup

Ply

VDD ll, 22, 26, 81,

92,102 6, 19, 48,

56, 63 3,11,13

41,49,

nvssl Digital ground Vss 2,8,12,13,23,

27, 76. 80,93,

95,101,103,

112.117, 123

AVDDH Analog power 2.5 V Von 30,51 21,31 15, 25

AVDDL Analog power 1.0 V Von 28, 43, 49.

53, 58, 64 20, 27,30.

33, 36, 39 14, 21.

24, 27,

30, 33

AVSS2 Analog ground Vss 29, 40, 42, 46,

48, 50, 55, 57,

61, 63

NC Reserved—do not con

nect 1,24-,33.35.36,

37, 38, 44, 59.

65, 66, 72, 73,

74,75. 104,114,

120, 122

7,8,9,

10.11

1 Configuranon signals are multiplexed with the LED controls. During a reset, the status of the conﬁguraiion pins are latched and used to set the configura

tion and laler to select the polarity to drive the Ll3Ds.

2. All AVSS and DVSS pins share a common ground pin (pad) in the center of the device.

l,Sl Corporation 19

TruePH YET1011C Data Sheet

Gigabit Ethernet Transceiver September 2007

Pin Information (continued)

Pin Descriptions, 128-Pin TQFP, 84-Pin MLCC, and 68-Pin MLCC (continued)

Table 2. Multiplexed Signals on the ETIOHC

Default Pin # Pin # Pin # Alternate

I28-Pin TQFP 84-Pin MLCC 68-Pin MLCC

COL 115 73 com °

PM/\_RX_CLK[1]7

CRS 116 74 cRs‘~ °

COMMA2

G'l"X_CLK 121 77 <1rx_cu<'

PM/\_Tx_cu<“

63 TXC3' 4

I..ED_1.NK 85 50 43 LED_LNK

PAUSE;

l1El)_11)0O 82 49 42 LED 1000

sPEE1§_1000-‘

LED TXRX 71 44 37 LElJ_TXRX

PH Y/>.n[0]5

LED_100 70 43 36 LED_100

PHYAD[_ 115

RX_CLK 113 72 Rx_cu< 1-“

PM/\_RX_CLK[0]Z

60 RXC3' 4

RX_ER 110 70 Rx_ER'— "

__i___2_i_

RX[)[9]

RX_DV 109 69 RX_DV1- "

RXD[8 12

58 RX_C'l‘L.m

TDI 16 14 7'l‘Dl

LPED_ENwN5

TMS 15 13 6TMS

SYS CLK EN N‘

TX_ER 124 78 1X_Eli‘<5M

'rxr>[911’

'l'X_}:IN 125 79 'I‘X__1-1N1‘ °

TXD[8 )2

64 Tx_c‘r1?- 4

XTALA1 31 22 16 XTAL 1

CLK_IN

_GMH $1g|1a|, 4, RTBI signal.

TB] signal, 5. Reset/conﬁguration signai.

. RGMl1 signal. 6. Mll signal.

LS1Corporation

Data Sheet TruePHYET1011C

September 2007 Gigabit Ethernet Transceiver

Hardware Interfaces

The following hardware interfaces are included on the ETl ()1IC G1gabit Ethernet transceiver:

.1 MAC interfaces:

— GMII (l28—pinTQFP/84-pin MLCC only)

— RGMII

— MII (128-pin TQFP/84-pin MLCC only)

— 'l‘Bl (128-pin TQFP/84-pin MLCC only)

-~ RTBI

fl Media-dependent interface

n Management interface

Several of the pins of the MAC interface are multiplexed, but they are designed to be interchangeable so that the device can

n Conﬁguration interface

ll LED interface

i. Clock and reset signals

n J"l‘AGinterfaec

n Regulator control

n Power and ground signals

change the MAC interface once the transmission capabilities (1000Base-T, l0OBasc-TX, and lOBase-T) are established.

The following diagram shows the various interfaces on each ET101lC and how they connect to the MAC and other support

devices in a typical application.

Gigabit Ethernet PHY

ETl0llC

<srx_cu<

TX_CLK

"rxr>[7=0]

TX_ER

TX_EN

RX___CLK

RXD[7:0]

RX_ER

RX_DV

COL

cRs

MAC__|F_SEL[2:0] PHYAD[4:U]

MDC

MDIO

MD|NT_N

TCK

TR$T__N

TDI

rno

COMA

RESET__N

h XTAL_1

- XTAL_2

ET1011C

u:1)_io0 Q;

LEDéfxkp Y

LED_1000

LED_LNK

TRD[O]+l

TRD[1]+I

TRD[2]+I

TRD[3]+I

RSET

VDD_REG -Q

CTRL__2V5 ‘I 2.5V

CTRL_1V0 Power

I Plane

Figure 9. ETIOHC Gigabit Ethernet Card BlockDiagram

LSI Corporation

:3 éfler

Plane

TruePHYET1011C

Gigabit Ethernet Transceiver Data Sheet

September 2007

Hardware Interfaces (continued)

MAC Interface

The ET10l1C supports RGMII, GM11.M11,RTBI. and TB1

interfaces to the MAC. The MAC intcrfacc mode is selected

via the hardware conﬁguration pins, MAC_1F_SEL[2:()].

Gigabit Media-Independent Interface (GMII)

(128-Pin TQFP and 84-Pin MLCC Only)

The GMII is fully compliant with IEEE 802.3 clause 35. The

GM11interface mode is selected by setting the hardware con

ﬁguration pins lVIAC_1F_SELl>2:l)]= 000.

new

r- .. ..

GTX_cLK

TXD{7 01

TX_EN

Rx_<:|.

MAC PHY

RX_ER

RX_DV

axon oi

CRS

Figure I0. GMII MAC-Pl-IYSignals

Table 3. GMII Signal Description (10lJOBase-TMode) (128-Pin TQFP and 84-Pin MLCC only)

Pin Name Pin # Pin #

I28-Pin 84-Pin

TQFP MLCC

Description Functional Description

GTX_CLK 121 77 Transmit clock The MAC drives this 125 MI-lzclock signal that is held low during

autonegotiation or when operating in modes other than l000Base-T.

TXNER 124 78 Transmit error The MAC drives this signal high to indicate a transmit coding error.

'l‘X_l~l1\l 125 79 Transmit

enable The MAC drives this signal high to indicate that data is available on

the transmit data bus.

'rxo[7=0] 7, 6, 5, 4, 3, 2,1. 84,

3, 128, 83. 82, 81

127, 126 80

Transmit data

bits740 The MAC transmits data synchronized with GTXMCLKto the

ET101 1C for transmission on the media—dependent(transformer)

interface.

RX_C |.14 113 72 Receive clock The ETIOIIC generates a 125 MHZclock to synchronize receive

data.

Rx_ER 110 70 Receive error The ET10 11C drives RX_[-IRto indicate that an error was detected

in the frame that was received and is being transmitted to the MAC.

RX_DV 109 69 Receive data

valid The E'l‘1011Cdrives RX_DV to indicate that it is sending recov

ered and decoded data to the MAC.

RXD[7:0] 97, 98, ‘)9, 59, 60, 61,

100.105. 62. 65, 66,

106. 107, 67, 68

108

Receive data The ET1011C transmits data that is synchronized with RX_CLK to

the MAC.

CRS 116 74 Carrier sense The carrier sense signal (CRS) of the MAC interface is asserted by

the ETl011C whenever the receive medium is nonidle. In hall'

duplex mode, CRS may also be asserted when the transmit medium

is nonidle. The CRS may be enabled on transmit in half-duplex

mode by writing to the PHY conﬁguration register, address 22, bit

15.

CO1. 115 73 Collision

detect In 1(lBase-T, 1OOBase-TX,and 1000Basc-T halt‘-duplex modes,

COL is asserted when both transmit and receive media are nonidle.

22 LS1 Corporation

Data Sheet TruePHYET10l1C

September 2007 GigabitEthernet Transceiver

Hardware Interfaces (continued)

Reduced Gigabit Media-Independent interface (RGMII)

The RGMII interface is fully compliant with the RGMII Rev.

1.3 speciﬁcation. The RGMll interface mode is selected by

setting the hardware conﬁguration pins MAC_lF~SEL[2:0]

= l()t)or 110. (See Table it) on page 30 for further informa

tion on MAC_lF__SELpin operation.)

Table 4. RGMI! Signal Description (1000Base-T Mode)

. .J><__C_M.

T2€Ql§.Fll. .

"rxcrt

MAC PHY

...._Rl£.-.._..

;_ RXDa;o

_ __R)<_¢.Tt-_.

t__.___

Figure ll. RGMII MAC~PHYSignals

Pin Name Pin #

128-Pin

TQFP MLCC

Pin #

84-Pin Pin # Pin Description

68-Pin

MLCC

Functional Description

TXC 121 77 63 Transmit clock The MAC drives this 125 MI-I7.clock signal that is

held low during autonegotiation. To obtain the 1Gbit

transmission rate, the MAC uses both the positive

and negative clock transitions.

rxn[s :0] 3,128, I27, 83, 82, 68, 67, 66, Transmit data bits

126 21, so as

The MAC transmits data synchronized with TXC to

the ETl0llC for transmission on the l'1'lCCli21-Ci€p€l1

dent (transformer) interface. The MAC transmits bits

3:0 on a positive transition QFTXC and bits 7:4 on a

negative transition of TXC.

TX_C'l"l, 125 79 64 Transmit control The MAC transmits control signals across this line

('1‘X__ERand TX_ EN). The MAC transmits 'l“X__EN‘

on a positive transition ol’TXC and TXv_ENand

'l‘X__ER1on the negative transition of TXC.

RXC l l3 72 60 Receive clock The ETl0l ICTgenerates a 125 MHZ clock to syn

chronize receive data. T0 obtain the l gigabit trans

mission ratc, the ET101 lC uses both the positive and

negative clock transitions.

RXD[3 =0] 105, I06, 65, 66, 67, 54, 55, 56, Receive data

107, 108 68 57

The l:ITl0llC transmits data that is synchronized

with RX_CLl< to the MAC. The ETlO1lC transmits

bits 3:0 on a positive transition of RXC and bits 7:4

on the negative transition of RXC.

RX_CTL 109 69 58 Receive control The El l0llC transmits oontrolsignals acrossthis

line (RX_ER and RX_l'£N).The ETl0l 1C transmits

RX_D\/1 on a positive transition of RXC and

RX_El\" and RX__ER‘on the negative transition of

TXC .

l. Reference the GMII interface for description of the following parameters: TX_EN, T ER, RX__DV,RX__EN, and RX_ER.

LSI Corporation 23

TruePHYET10llC Data Sheet

Gigabit Ethernet Transceiver September 2007

Hardware Interfaces (continued)

Media~lndependent Interface (128-Pin TQFP and

84-Pin MLCC Only)

The Mll is fully compliant with IEEE 802.3 clause 22. The

M11interface mode is selected by setting the hardware con

ﬁguration pins MAC_lF_SEL[2:0] = 000.

In l()0Base-TX and 10Base-T mode. the RXD[7:4] pins are

driven low by the ETlO1lC and the TXI)[7:4] pins are

ignored. They should not be left ﬂoating but should be set

either high or low. In the M11interface mode, the GTX__CLK

pin may be held low.

An alternative to the standard M11is provided when operat

ing in l0Base-T or l00Base-TX mode by

setting hardware conﬁguration pins

MAC_lF_SEL[2:0] = 010. in this alternative interface. the

MAC provides a reference clock at 2.5 MHZ or

25 MHZ at the GTX_CLK pin. The ET101lC then uses a

FIFO to resynchronize data presented synchronously with

this reference clock.

TX_CLK

TX_EN

TXD(3 0|

RX_CLK

MAC EUR PHY

Figure 12. M11Signals

Table 5. Ml] Interface (l00Base-TX and l0Base-T) (128-Pin TQFP and 84-Pin MLCC Only)

Pin Name Pin #

128-Pin

TQFP

Pin #

84—Pin

MLCC

Description Functional Description

rx_c 1.14 118 75 Transmit

clock In l00Base-TX mode, the ET10l IC generates 25 M1-12reference clocks

and in 1OBase-Tmode provides 2.5 MHz reference clocks.

MAC_1F_SEL[2:()]= 000-vthis is default behavior.

GTX_CLK 121 77 Alternate

transmit clock 1n 10OBase-TXmode, the MAC generates the 25 M112reference clock and

in 10Base-'1"mode provides a 2.5 MHZreference clock. M/\C_lF_SEL[2:0]

I 010.

TX_ER 124 78 Transmit error Thc MAC drives this signal high to indicate a transmit coding error.

TX_1—lN 125 79 Transmit

enable The MAC drives this signal high to indicate that data is available on the

transmit data bus.

TXD[3:0] 3, 128, 8

127,126 3,82,81,

80 Transmit data

bits The MAC transmits data synchronized with TX_C1..Kto the ET1011C for

transmission on the media-dependent (transformer) interface.

RX_CLK 113 72 Receive clock In 100Base-TX mode, the 1?/F10llC generates 25 MHZ reierence clocks

and in 10Base-T mode provides 2.5 Ml-lz reference clocks.

RX_ER 110 70 Receive error The ET1()l 1Cdrives RX_ER to indicate that an error was detected in the

frame that was received and is being transmitted to the MAC.

RX_DV 109 69 Receive data

valid The E'l‘lOl1C drives RX_DV to indicate that it is sending recovered and

decoded data to the MAC.

r<xo[310] 105,106, (>5,66,67, Receivedata

68 bits

107, 108 The ETlO‘l1C transmits data synchronized with RX_CI.K to the MAC.

CRS 116 74 Carrier sense The carrier sense signal (CRS) of the MAC interface is asserted by the

ET1011Cwhenever the receive medium is nonidle. In half-duplex mode,

CRS may also be asserted when the transmit medium is nonidle. The CRS

may be enabled on transmit in half-duplex mode by writing to the PHY

conﬁguration register. address 22, bit 15.

COL H5 73 Collision In 10I3ase-T, 1()013ase-TX:and lO00Base-'I‘ha1'l‘-duplex modes, COL is

detect asserted when both transmit and receive media are nonidle.

24 LS1 Corporation

Data Sheet TruePHYET1011C

September 2007 Gigabit Ethernet Transceiver

Hardware Il1t€l‘f&1€€S(continued)

Ten-Bit Interface (rm) (128-Pin TQFP and 84-Pin PMA-T‘-°“‘GM“

MLCC Only) YX__ER

The 'l‘Bl is full) compliant with IEEIL802 3 clause 36 It

’ ‘ . . TXD[8l

may be used as an alternative to the GMII in l000Base-T WEN

, TXD[7:O] V

mode. The FBImode is selected by setting the hardware con

ﬁguration pins MAC_IF_SEL[2:0] = 001.

TXD{9]

rxnlm]

PMA_RX__CLK

MAC RX__CLKPHY

rotors] RX_ER

nxorsg Rx_ov

axon 0] RXD[7:U]

MA_RX_CLK[1] cot

COMMA CR5

Figure 13.Ten-Bit lnterface

Table 6. Ten-Bit interface (1000Base-T) (128-Pin TQFP and 84-Pin MLCC Only)

I28-Pin

TQFP 84~Pin

MLCC

Pin Name Pin # Pin # Pin Description Functional Description

PMA_TX_cu< l2l 77 TBI transmit

clock The MAC drives this 125MHz clock signal and should

be held low during autonegotiation or when operating

in modes other than l000Base-T.

TXD[9:0] 124, 125, 7,

6, 5, 4, 3,

128. 127,

126

78, 79, 3, 2,

l, 84, 83, 82.

81,80

Transmit data

bits The MAC transmits data synchronized with

PM/-\_TX_CLKto the ETlOllC for transmission on

the media-dependent (transformer) interface.

PM/\_RX_CLK[‘()] ll3 72 Receive clock The F.Tl()llC generates a 62,5 MHZclock to synchro

nize receive data for the odd oode group. This signal is

180 degrees out of phase from PMA_RX_CLK[l].

RXD[9:O] l l0. 109. 97,

98. 99. I00,

lO5, 106,

107, 108

70, 69

60, 61

65, 66,

59,

62,

67.

Receive data bits The ET1Ol1C transmits data that is synchronized with

PMA_ RX_CLK[()] to the MAC.

PMA_RX_cu<[1] 115 73 Receive clock The ETl()l 1Cgenerates a 62.5 MHZ clock to synchro

nize receive data for the even code group. This signal

is 180 degrees out of phase from PMA_RX__CLl<'.[O].

COMMA H6 74 Comma signal This signal indicates that COMMA has been detected.

LS1Corporation 25

TruePH YET1.01lC Data sheet

Gigabit Ethernet Transceiver Septgmbef 2007

Reduced Ten Bit Interface (RTBI)

The RTBI is fully compliant with RGMII rev 1.3 speciﬁca

conﬁguration pins MAC_lF_SEL[2:0] = 101or Ill. (See

Hardware Interfaces (continued) —-~-~ p Tm ———~—~

i T...i><Rta21

tion. The RTBI mode is selected by setting the hardware n<_cn,

Table 10 on page 30 for further information on MAC 1 PHY i

MAC_ll*‘_S[ZL pin operation.) ‘__M___5g<_o___H

Table 7. RTBI Signal Description (1000Base-T Mode)

R><D@.21-... *

RX _c‘r|. ___

Figure 14.Reduced Ten-Bit Interface

Pin Name Pin #

I28-Pin

TQFP MLCC

Pin #

84-Pin Pin #

68-Pin

MLCC

Pin Description Functional Description

TXC 121 77 63 Transmit clock The MAC drives this I25 Mllz clock signal that is

held low during autonegotiation.

TXD[3:0] 3,128, 83,82,8l

127,126 80 68, 67,

66, 65 Transmit data bits The MAC transmits data synchronized with TXC to

the ETIOl1Cfor transmission on the media-dependent

(transformer) interface. The MAC transmits bits 3:0

on a positive transition of TXC and bits 8:5 on a nega

tive transition of TXC.

'l‘X_CTl. I25 79 64 Transmit control The MAC transmits bit 5 and bit I0 synchronized with

TXC to the ETl0l IC for transmission on the mediat

dependent (transformer) interface. The MAC trans

mits bit 5 on a positive transition ofTXC and bit I0 on

the negative transition of TXC.

RXC I13 72 60 Receive clock The ETIOIIC generates a 125 MHz clock to synchro

nize receive data.

RXD[_3:0] I07, 108 68

I05, 106, 65, 66, 67, 54, 55,

56. 57 Receive data The ETIOI l C transmits data that is synchronized with

RXC to the MAC. The ETIOI IC transmits bits 3:0 on

a positive transition ofRXC and hits 8:5 on the nega

tive transition of RXC.

RX_cT1. 1O9 69 58 Receive control The ETl011C transmits bit 5 and bit 10 synchronized

with RXC to the MAC. The ETIOIIC transmits bit 5

on a positive transition of RXC and hit I0 on the nega

tive transition of RXC.

26 LSI Corporation

Data Sheet TruePH YET1011C

September 2007 Gigabit Ethernet Transceiver

Hardware Interfaces (continued)

Management Interface

Serial Management Interface

The Mil management interface (Ml) provides a simple, two-wire serial interface between the MAC and the PHY to allow

access to control and status infonnation in the internal registers of the ETl01lC. The interface is compliant with IEEE 802.3

clause 22 and is compatible with the clause 45.3, enabling the two systems to co-exist on the same MDIO bus.

Management Frame Structure

Frames transmitted on the Ml have the following structure.

Table8. Management Frame Structure

Read 1. . . 1 01 10 aaaaa rrrrr

Write | l ...l | 01 101 |aaaaa rrrrr

I PRE‘ sr l 01> P PHYAD REGADl TA | DATA IDLE

I I I I 10 in d |4

n PRE (preamble): At the beginning ofeach transaction. the MAC may send a sequence of32 contiguous logic one bits on

MDIO with 32 corresponding cycles on MDC to provide the Pl-lYwith a pattern that it can use to establish synchronization.

The l2TlOl 1Csupports MF preamble suppression and thus the MAC may initiate management frames with the ST (start of

frame) pattern.

ll ST (start of Frame):The start of frame is indicated by a <0l> pattern. This pattern ensures transitions from the default logic

one line state to zero and back to one. When a clause 45 start of frame <O0>is received, the frame is ignored.

-1 OP (operation code): The operation code for a read transaction is <lO>. while the operation code for a write transaction is

<Ol>.

n Pl-WAD (Pl-TYaddress): The PHY address is 5 bits. The ﬁrst PHY address bit transmitted and received is the MSB oi‘the

address. Only the PHY that is addressed will respond to the Ml Operation.

'1 REGAD (register address): The register address is 5 bits. The ﬁrst register address bit transmitted and received is the MSB

of the address.

ll TA (turnaround): The turnaround time is a 2-bit time spacing between the register address ﬁeld and the data held ofa man

agement ﬂame to avoid contention during a read transaction. For a read transaction. the PHY remains in a high-impedance

state for the ﬁrst bit time of the turnaround and drives a zero bit during the second bit time of the turnaround. During a write

transaction, the PHY expects a one for the ﬁrst bit time of the tumaround and a zero for the second bit time of the tum

around.

" DATA (data): The data ﬁeld is 16bits. The ﬁrst data bit transmitted and received is the MSB ofthc register being addressed.

n IDLE (idle condition): The IDLE condition on MDIO is a high-impedance state, and the ETl0l 1C internal pull-up resistor

will pull the MDIO line to logic one.

LS1Corporation 27

TruePHYETl011C Data sheet

Gigabit Ethernet Transceiver Septemher 2007

Hardware Interfaces (continued)

Table9. Management Interface

Pin Name Pin # Pin # Pin # Pin

I28-Pin 84-Pin 68-Pin Description

TQFP MLCC ML€C

Functional Description

PHYAD 67, 68, 69, 40. 4|, 4-2, 34, 35, PHY Address

[410] 70, 71 43. 44 36, 37

(PHYAD

[$101)

The physical address of the l5Tl(lllC is conﬁgured at reset

by the current state of the PHYAl')[4:0] pins. Once these pins

have been latched in at reset, the ETl0llC is accessible via

the management interface at the conﬁgured address. The

default address is set to l by internal pull-up/downs. These

may be overridden by extemal pull-up/downs. The valid

range is Oto 31‘.

Ml)C 9l 55 48 Management The management data clock (MDC) is a reference for the

interface Clock data signal and is generated by the MAC. It can be turned ofl

when the Ml is not being used. This pin has an internal pull

down resistor. MDC is nominally

2.5 MHZ, and can work up to a maximum of 12.5 MHZ.

MD10 90 54 47 The management data input/output (MDIO) is a bidirectional

data signal between the MAC and one or more Pl~lYs.;\/[D10

is a 3-state pin that allows either the MAC or the selected

PHY to drive this signal. This pin has an internal pull-up

resistor. An external pull-up resistor should also be used. the

exact value depending on the number of Pl-[Y5sharing the

MDIO signal. Data signals written by the MAC are sampled

by the PHY synchronously with respect to the MDC. Data

signals written by the PHY are generated synchronously with

respect to the Ml)C.

Management

Data 1/O

This pin requires an external pull-up (1 kQ to ll) kQ).

MDlNT_N 89 53 46 Management This pin is active-low and indicates an unmasked manage

lnterface ment interrupt. This pin requires an external pull-up resistor

Interrupt (1 kt! to 4.7 kQ). Pin is open drain.

l. Pl-lYAD description applies to the 84-MLCC only. For the 68-MLCC. the valid range will be 0---15.

ManagementInterrupt

The ETl01lC is capable of generating hardware interrupts on pin MD1NT_N inresponse to a variety of user-selectable condi

tions. MDINT_N is an open-drain, active-low signal that can be wire—()Redwith several other ETl()l lC devices. A single 2.2

kQ pull-up resistor is recommended for this wire-OR conﬁguration.

When an interrupt occurs, the system can poll the status of the interrupt status register on each device to determine the origin

of the interrupt. There are nine conditions that can be selected to generate an interrupt:

.1 Autoncgotiation status change n Link status change 7| Local/remote l'Xstatus change

ll Autonegotiation page received ll CRC errors ll Automatic speed downshilt occurred

fl FIFO overﬂow/underllow ll Full error counter I1 Ml)lO synchronization lost

The ETl0l lC is conﬁgured to generate an interrupt based on any of these conditions by use ofthe interrupt mask register (Mll

register 24). By setting the corresponding bit in the intenupt mask register for the desired condition, the E'I‘lOl1Cwill gener

ate the desired interrupt. The E'l‘l011C can be polled on the status ofan activated interrupt condition by accessing Mll register

interrupt status register (Mil register 25). If this condition has occurred, the corresponding bit in the interrupt status register

will be set. The interrupt status register is self-clearing on a read operation.

28 LS1 Corporation

Data Sheet TruePHYET1011C

September 2007 Gigabit Ethernet Transceiver

Hardware Interfaces (continued)

Conﬁguration Interface

The hardware conﬁguration pins listed in Table 10 initialize the BT10] 1Cat power-on and reset. The conﬁguration is latched

during initialization and stored. These pins set the default value of their corresponding Mll register bits.

Some conﬁguration inputs are shared with LED pins. The hardware conﬁguration and LED pins are read on initial powerup of

the ETlOl 1C,during a hardware reset and during recovery irom hardware powerdown. The logic value at the pin is sensed

and latched. After RESET_N has been deasscrted (raised high), the shared conﬁguration pins become outputs that are used to

drive L.EDs.(For details on sharing LED and conﬁguration pins, refer to the application note, TruePHY[;'T10I1 Gigabit

Ethernet PH)’ Design and Layout Guide.)

Table 10.Conﬁguration Signals

Pin #

128-Pin

TQFP MLCC

Pin #

84-Pin

Pin Name Pin #

68-Pin

MLCC

Description Functional Description

SPEED_l 000 82 49 42 Speed 1,000 The SPEED_l O00conilguration pin sets the

default advertised speed. The deassertion of

SPEED_l 000 disables advertisement of the

1000Base-T to the remote end. The default is to

advertise all three speeds.

PAUSE 85 50 43 Pause This input sets the pause mode. lf PAUSE is

asserted, full-duplex pause and asymmetric

pause operation are advertised. 0 = Don't adver

tise pause (default).l = Advertise full-duplex

pause and asymmetric pause.

SYS__CLK_EN_N 15 13 6SYS_Cl.K

Enable Enables the system clock.

If SYS_CLK_EN_T\lis asserted when RESETvN

is low, SYS_CLK will be enabled and will con

tinue to be generated while RESET__Nis low. If

SYS_Cl.K_EN_N is not asserted when

RESET_N is low, then SYS_CLK is disabled.

()= SYS__CLl( enabled.

1= SYS_CLK disabled (default).

See Low Power Modes on page 11 for additional

information.

l..PED_EN_N l6 14 7L.owPower

Energy

Detection

Enable

LPED4EN_N enables the low-power energy

deteet (LPED) mode when COMA is asserted.

See Low Power Modes on page ll Foradditional

information.

When the PHY is in LPED mode, it can wake the

MAC/controller (instead of Magic Pucker) by

asserting the MDINT_N pin to indicate the pres

ence of cable energy.

0 = Low-power energy-detect mode enable.

l = Low—poWerenergy-detect mode disabled

(default).

PRES 87 5l 44 Precision

Resistor Connect a 1.0 kQ precision resistor to ground to

set termination for all digital I/Os.

LS1 Corporation 29

TruePHYET1011C

_ Data Sheet

Gigabit Ethernet Transceiver September 2007

Hardware Interfaces (continued)

Table 10.Conﬁguration Signals (continued)

Pin Name Pin # Pin # Pin # Pin Functional Description

128-Pin 84-Pin 68—Pin Description

TQFP MLCC MLCC

SELILZZO] 1; face Mock Configure the MAC during reset as follows

(MAC H.- ooo = GMII/Mll (84-Pin MLCC default).

SEL[l:0]’ 001 = TBI.

Note 1.) TX_.CLK)

011 = Reserved.

101

110 = RTBI (RXC DLL de|ay)1.

M/\C_IF_ 20 18 »~ MAC Inter- This input selects the desired MAC interface mode.

(See 010 = GMII/Mil (clocked by GTX__CLKinstead of

100 = RGMH/RMII (RXC DLL delay; 68-MLCC defauIt)1

RGMIIIRMH(RXC and rxc DLLdelay)1.

_t11 = RTBI (RXC and TXC DLL delay)1.

l. ln the 68-MLCC, MAC_lF_SEl. 2 (1 l) will be set internally. Also, for all package types:

—-MAC >IF _SEI_pins I00 will set MAC interface mode select bits in register 222:0 = l10; ziltcmative RGMII TXC DLL Delay bit 23.6 =

~~~MAC_|F__SELpins = l0l will sut MAC interface mode select hits in register 222:0 = ll]: alternative RGMll TXC DLL Delay bit 23.6 =

~- M/\C__'IF_SEL pins = l 10 will set MAC interface mode select bits in register 22.2:0 —='110; alternative RGMII TXC DLL Delay bit 23,6 T

——»MAC_ll‘-'__SELpins = lll will set MAL‘ interface mode select hits in register 22.210 '* 11l; alternative RGMII TXC DLL Delay bit 23.6

99

LSI Corporation

Data Sheet TruePH YET1011C

September 2007 Gigabit Ethernet Transceiver

Hardware Interfaces (continued)

LEDs Interface

The ET10 llC is capable ofsinking or sourcing current to drive LF.Ds.These LEDs are used to provide link status infomiation

to the user. The ET10l 1Cis capable of automatically sensing the polarity of the LEDs. The device determines the active sense

of the LED based upon the input that is latched during conﬁguration. Thus, if logic 1is read, the device will drive the pin to

ground to activate the LED; otherwise, it will drive the pin to supply to activate the LED.

The LEDs can be programmed to stretch out events to either 28, 60, or IUOms. This makes very short events more visible to

the user. All LEDs can be programmed to be on, off, or blink instead of the default status function. This is useful for alterna

tive function indication under host processor control: for example, a system error during power-on self-check. All LEDs can

be programmed to indicate une ofthirtccn different status functions instead of the default status function:

n 1()OOBase-T fl Transmit or receive activity

fl l0()Base-T X It Full duplex

II lOBase-T .1 Collision

KIl0O0Base-T (on) and l0()B-ase-TX( blink) l’\Link established (on) and activity (blink)

n Link established I1 Link established (on) and receive activity (blink)

n Transmit activity Ii Full duplex (on) and collision (blink)

-1 Receive activity

The LED drivers can be configured by use of LED control register 1,LED control register 2. and LED control register 3 (Mll

registers27429).

Table ll. LED

Pin Name Pin # Pin # Pin # Pin Description Functional Description

128-Pin 84-Pin 68-Pin

LED_l000 42 l00()Base-T LED This LED indicates that the device is operating in

lO0()Base-Tmode. Setting can be overridden.

l\J

-l=~

TQFP MLCC MLCC

LED_LNK 43 Link Established This LED indicates that the link is established. Setting

LED can be overridden.

LED_'I‘XRX | 71 44 37 General-Purpose Set to be oﬂ‘by default.

LED_10(l t 70 43 36 LEIJS

LS] Corporation 31

True.PHYETl0llC Data sheet

Gigabit Ethernet Transceiver September 1007

Hardware Interfaces (continued)

Media-DependentInterface: Transformer Interface

Table 12.Transformer Interface Signals

Pin Name Pin #

128-Pin

TQFP

Pin # Pin # Pin Description Functional Description

84-Pin 68-Pin

MLCC MLCC

'|‘Rl)[O]+

TRD[0] 39

41 25 19

26 20 Transmit and

Receive Differen

tial Pair ()

Connect this signal pair through a transformer to the

media-dependent interface.

In lO00Base-T mode, transmit and receive occur simul

taneously at 'l‘RD{O]ﬂ:.

In l()Base-'1‘ and lO()Base-TX modes, 'l‘RD[()]:t are

used to transmit when operating in the MDI conﬁgura

tion and to receive when operating in the MDI-X con

ﬁguration.

The PHY automatically determines the appropriate

MDI/MDI-X conﬁguration.

'l"Rl)[1 1+

TRD[1]—

47 28 22

29 23 'l‘ransmit/Receive

Differential Pair l Connect this signal pair through a transformer to the

media-dependent interface.

In l0()()Base-T mode, transmit and receive occurs

simultaneously at TRD[l]d:.

ln l0Base—Tand lO0Base-TX modes, TRD[l]i are

used to receive when operating in the MDI conﬁgura

tion and to transmit when operating in the MDI-X con

ﬁguration.

The PHY automatically determines the appropriate

MDI/MDI-X configuration.

TRD[2]+

TRD[2]~ 54

56 34 28

35 29 Transmit/Receive

Differential Pair 2 Connect this signal pair through a transformer to the

media-dependent interface.

In l0O0Base-T mode, transmit and receive occurs

simultaneously at 'l'RD[2]:k.

In 1()Base-Tand l(l0Base-TX modes, TRD[2]i are

unused.

TRD[3]+

'l‘RD[3]—

62 37 31

38 32 Transmit/Receive

Ditfcrential Pair 3 Connect this signal pair through a transfomqer to the

media-dependent interface.

In 1000Base-T mode, transmit and receive occurs

simultaneously at TRD[3]i.

ln l0Base-'1‘ and l00Base-TX modes. 'l‘RD[3]:l:are

unused.

RSET 52 32 26 Analog Reference

Resistor RSF.Tsets an absolute value reference current for the

transmitter.

Connect this signal to analog ground through a preci

sion 6.34 l<§Z1% resistor.

32 LS1 Corporation

Data Sheet TruePH YET.l011C

September 2007 Gigabit Ethernet Transceiver

Hardware Interfaces (continued)

Clocking and Reset

Table 13. Clocking and Reset

Pin Name Pin # Pin # Pin #

128-Pin 84-Pin 68-Pin

TQFP MLCC MLCC

Pin Description Functional Description

CI..K_[N 31 22 16 Reference Clo

Input ck

XTAL__l 3l 22 16 Reference

Crystal Input

Connect this signal to a 25 MHZ clock input

(CLK_lN will only accept a 2.5V signal) or a 25

MHZi 50 ppm tolerance crystal (X'l‘AL__l).

XTALA2 32 23 17 Reference

Crystal Input Connect this signal to a 25 MHz -i 50 ppm tolerance

crystal. Float this signal ifan external clock is used

(Cl ,l<_l"N).

SYS_CLK 94 S7 50 System Clock Use this signal to supply a 125 MHZ clock to the

MAC.

By default, the SYS_CI..Koutput is disabled. The

SYS_Cl,,K output can be enabled by asserting the

SYS_CLK_EN_N pin or via the management inter

face.

RESET_N 34 24 18 Reset Drive l{ESET_N low for 20 us to initiate a hardware

reset. The ET1011C completes all reset operations

within S ms of this signal returning to a high state.

The conﬁguration pins and the physical address con

ﬁguration are read during a hardware reset.

See Low Power Modes on page l l for additional

information.

COMA 25 -—— l 2 Hardware

Powerdown Drive COMA high to initiate a hardware power

down. The ET1011C completes all resct operations

within 5 ms of this signal returning to a low state.

All hardware functions are disabled during a hard

ware powerdown.

The conﬁguration pins and the physical address con

ﬁguration zireread during a hardware powerdown.

See Low Power Modes on page l 1 tor additional

information‘

LS1Corporation 33

TruePH'YET1011C Data Sheet

Gigabit Ethernet Transceiver September 2007

Hardware Interfaces (continued)

JTAG

The ET1()11Chas a standard [EEE 1149.1 JTAG test interface. The interface provides extensive test and diagnostics capabil

ity. lt contains internal circuitry that allows the device to be controlled through the JTAG port to provide on-chip, in-circuit

emulation.

The JTAG interface is a bidirectional serial interface with its own reset strobe (TRST_N). The reset strobe can be used inde

pendently to reset the JTAG state machine but must be used during atpower-on reset (see Reset Timing on page 78).

Table 14.JTAG Test Interface

Pin Name Pin #

128-Pin

TQFP

Pin #

84-Pin

MLCC

Pin #

68-Pin

MLCC

Pin Description Functional Description

TDI 16 14 7Test Data Input This signal is the JTAG serial input. All instructions and

scanned data are input using this pin. This pin has an

internal pull-up resistor.

TDO 17 '15 8Test Data

Output This signal is the JTAG serial output. Scanned data and

status bits are output using this pin. This pin has an inter

nal pull-up resistor.

TCK 1O 5 2Test Clock This signal is the JTAG serial shiﬁ clock. It clocks all ot‘

the data that passes through the port on TDI and TDO.

This pin has an internal pull-up resistor.

TMS 15 13 6Test Mode

Select This signal is the JTAG test mode control. This pin has an

internal pull-up resistor.

TRST_N 14 12 5Test Reset

(JTAG Reset) This signal is active-low and causes the JTAG TAP con

troller to enter the reset state. This pin has an internal

pull-down resistor.

Regulator Control

The F,Tl()11Chas two on-chip regulator controllers. This allows the device to be powered from a single supply, either 3.3 V or

2.5 V.The on-chip regulator control circuits provide output control voltages that can be used to control two external transistors

and thus provide regulated 1.0V and 2.5 V supplies.

Table 15.Regulator Control Interface

Pin Name Pin # Pin # Pin #

128-Pin 84-Pin 68-Pin

TQFP MLCC MLCC

Description Functional Description

CTRL__1V0 Regulator

Control for

1.0 V

‘Thisis the regulator output control voltage for the

1.0 V supply. it is used to control an cxtemal transis

tor and thus provide a regulated 1.0 V supply.

crnugvs 1 19 M 47 40

78 g 46 39

Regulator

Control for

2.5 V

This is the regulator output control voltage for the

2.5 V supply. It is used to control an external transis

tor and thus provide 21regulated 2.5 V supply.

34 LS1 Corporation

Data Sheet TruePHYET101lC

September 2007 Gigabit Ethernet Transceiver

Hardware Interfaces (continued)

Regulator Control (continued)

The ETl01 1Cdigital and analog core operates at 1.0 V.The analog 1/0 operates at 2.5 V The digital l/O can operate at either

3.3 V or 2.5 V.The GK/111interface operates at 3.3 V and the RGMII intertace operates at 2.5 V.The on-chip regulator control

allows the device to be operated from a wide variety of extemal supply combinations. When more than one external supply is

available, one or both of the regulator control circuits may be left unused.

Table 16 lists example combinations of available external supplies and shows how the on-chip regulator control may be used

to provide the required supplies.

Table 16. Supply Voltage Combinations

Supplies DDL DVD

Available External Av AV 1

D DDH VDD_REG Description

3.3 V only 1.0 1.0 2.5 3.3 Digital l/O can be either 3.3 V or 2.5 V.

Regulator control is used to provide 1.0 V and

2.5 V.

2.5 V only l.() 1.0 2.5 2.5 Digital l/O is 2.5 V.

Regulator control is used to provide 1.0 V.

3.3 V and 1.0V 1.0 1.0 2.5 3.3 Digital 1/O can be either 3.3 V or 2.5 V.

Regulator control is used to provide 2.5 V.

2.5Vandl.0V 1.0 1.0 2.5 2.5 Digital 1/O is 2.5 V.

Regulator controls are not connected.

3.3 V and 2.5 V 1.0 1.0 2.5 3.3 Digital 1/() can be either 3.3 V or 2.5 V.

Regulator control is used to provide 1.0 V.

3.3 V, 2.5 V,

and 1.0 V 1.0 1.0 2.5

r 2.5 Digital l/O can be either 3.3 V or 2.5 V.

Regulator controls are not connected.

1 Even ifthe regulator controls are not connected, VDD__REGmust be powered.

Power, Ground, and No Connect

Table 17. Power, Ground, and No Connect

Pin Name Pin Description Functional Description

VDD_REG Von Regulator 2.5 V or 3.3 V supply.

DVDDIO Von Digital l/O 3.3 V or 2.5 V supply.

DVDD VDD IDigital core 1.0 V supply.

DVSS Vss | Digital ground‘.

AVDD1-I Von l Analog power 2.5 V.

AVDDL Von lAnalog power 1.0 V.

AVSS Vss | Analog groundl.

lit» No Connect l Reserved——clonot connect.

l, For 84-pin MLCC and 68-pin MLCC, all AVSS and DVSS pins share a common ground pin (exposed pad) in the center of the device.

LS1Corporation 35

TruePHYET10l1C Data Sheet

Gigabit Ethernet Transceiver September 2007

Cable Diagnostics

The ET10l1C has on-chip cable diagnostics. The cable analysis uses two distinct methods for evaluating the cable: link analy

sis arid time domain reflectometry (TDR) analysis. This analysis can be used to detect cable impairments that may be prevent

ing a gigabit link or affecting perfonnance.

When there is a link active, the link analysis can detect cable length, link quality, pair skew, pair swaps (MDIIMDI-Xconﬁgu

ration). and polarity reversal. When there is no link, TDR can detect cable faults (open circuit, short circuit), distance to the

fault, pair fault is on, cable length, pair skew, and excessive crosstalk. Table l8 summarizes the speciﬁcations of the cable

diagnostic functions.

Table 18. Cable Diagnostic Functions

Feature Description 10 I00 1000 Term Unterm Analysis

Detection oi‘Cable Fault on

Any Pair Cable open / »/

Cable short / J

Indicate distance to

fault i=2 m =l:2m

Line

Probing

Pair swaps -/ ~/ /l Link Analysis

Detect Polarity Reversal \/ *2 /Link Analysis

Good Cable with Link Indicate length :klOlT1 3; 10m Link Analysis

Good Cable Without Link Indicate length i5 m3 :2 m Linc Probing

Pair Skew with Link Detect excessive. >50

1'15

/Link Analysis

Pair Skew Without Link Detect excessive, >50

./3 / Line Probing

Excessive Crosstalk Cable quality or spl

pairs it if \/ Line Probing

1. Pair swaps on C and D as well as pairs A and B are reported.

2. Polarity reversal in l0OBase-TX is not detected because Ml.T-3 signaling is polarity insensitive.

3. If the magnitude of the peak reﬂection is greater than 15% ofan open circuit.

36 LS1Corporation

Data Sheet

Table 19. Register Address Map

Address Description

Control register.

,_.

Status register.

I\-7

PHY identiﬁer register 1.

PHY identiﬁer register 2.

-l=~

Autonegotiation advertisement register.

Autonegotiation link partner ability register.

Autonegotiation expansion register.

Autonegotiation next page transmit register.

Link partner next page register.

1000Basc-T control register.

l0 l00Ol3ase-T status register.

ll——l4 Reserved.

15 Extended status register.

16-—l7 Reserved.

18 PHY control register 2.

l9 Loopback control register.

20 RX error counter register.

21 Management interface (Mi) control register.

22 PHY conﬁguration register.

23 PHY control register.

24 Interrupt mask register".

25 Interrupt status register.

26 PHY status register.

27 LED control register 1.

28 LED control register 2.

29 LED control register 3.

30 Diagnostics control register.

31 Diagnostics status register (TDR mode).

Table 20. Register Type Deﬁnition

Type Description

LL Latching low.

LH Latching high.

WW Read write. Register can be read or written.

RO Read only. Register is read only. Writes to register

are ignored.

SC Self-clearing. Register is self-clearing; if a one is

written, the register will automatically clear to zero

aﬁer the function is completed.

l,Sl Corporation

TruePHYFT1lll1C

September 2007 Gigabit Ethernet Transceiver

TruePHYET10llC Data Sheet

Gigabit Ethernet Transceiver September 2007

Table 21. Control Register—Address 0

Control Register

Bit Name Description Type Default Notes

l5 Reset

<3»

= PHY reset.

= Normal operation.

R/W

l4 Loopback

= Enable loopback.

0 = Disable loopback.

R/W 2

13 Speed Selection

(LSB) Bit 6,13.

ll = Reserved.

l0 = 1000 Mbits/s.

Oi = 100 Mbits/s.

O0= 10 Mbits/s.

R/W Sl’EED__l000 3

lZ Autonegotiati on

Enable

Q»-1

= Enable autonegotiation process.

= Disable autonegotiation process.

K/W 4

l l Powerdown

Qi

= Powerdown.

= Normal operation.

RIW

l0 isolate = lsolatc PHY from Mll.

= Nomtal operation.

<3»

R/W 5

9 Restart Autoneg

tion

9

= Restart autonegotizition process.

Normal operation.

R/W

8 Duplex Mode

O.-

= Full duplex.

= llalf duplex.

R/W 6

7 Collision Test = Enable collision to-st.

O= Disable collision test. R/W O 7

6 Speed Selection

(MSB) See bit 13. R/W Sec bit l3. 3

5:0 Reserved ~ R0 0 —

The reset bit is automatically cleared upon completion of the reset sequence. This bit is set to 1during reset.

This is the master enable for digital and analog loopback as deﬁned by the standard. The exact type of loopback is determined by the loophack control

The speed selection address 0 bits 13 and 6 may be used to conﬁgure the linkmanually. Setting these bits has no effect unless address Obit

12 is clear.

When this bit is cleared, the linkconﬁguration is determined manually.

Setting this bit isolates the PHY from the Mil, GMll, or RGMll interfaces.

This bit may be used to conﬁgure the link manually. Setting this bit has no effect unless address Obit 12 is clear.

Enables IEEE22.2.4.1.9 collisiontest.

LS1 Corporation

Data Sheet TruePH YET l 011C

September 2007 Gigabit Ethernet Transceiver

R€glSt€I‘ DBSCl'ipﬁ0l1 (continued)

Table 22. Status Registcr—Address 1

Status Regster

Bit Name Description Type Default Notes

l5 I00Base-T4 0 = Not lO0Base-T4 capable. RO O l

14 l00Basc-X Full Duplex I I l00Base-X full-duplex capable.

0 = Not l00l3ase-X full-duplex capable.

R(_) l

13 l()0l3ase-X Half Duplex l I l0()Base-X half-duplex capable.

O= Not l0OBase-X half-duplex capable.

R0 1

I2 l0Base-T Full Duplex l = l0Base-T fullsduplex capable.

0 = Not l0Base-T full-duplex capable.

RO l

ll lOl3ase-Tl-IalfDuplcx 1 = 1OBasc-T half-duplex capable.

0 = Not lOBase—Thall’-duplex capable.

RO 1

10 l00Base-T2 Full Duplex 0 = Not l00Base-T2 full-duplex capable. RO O

9ll)OBase-T2Half Duplex 0 = Not l0OBase-T2 half-duplex capable. R0 0

8Extended Status l I Extended status information in register 0l~'h. R0 1

7Reserved RO —

6MI’Preamble Suppression l = Preamble suppressed management frames

accepted.

RO l

5Autonegotiation Complete 1= Autonegotiation process complete.

O= Autonegotiation process not complete.

RO 0 2

4Remote Fault l = Remote fault detected.

O= No remote fault detected. RO O

I_.H

3Autonegotiation Ability l = Autonegotiation capable.

0 = Not autonegotiation capable.

RO 1

2Link Status 1: Link is up.

0 = Link is dc“-11. RO O

Ll. 4

lJabber Detect 1= Jabber condition detected.

0 = Nojabber condition detected. RO 0

l..H

OExtended Capability l = Extended register capabilities. RO l 5

1. The ET101lC does not support 10OBase-T4 or 10OBase-T2;therefore, these register bits willalways be set to zero.

2. Upon completion of autonegotiation, this bit becomes set.

3. This bit indicates that a remote fault has been detected. Once set, it remains set until itis cleared by reading registert via the management

interface or by PHY reset.

4. This bit indicates that a valid linkhas been established. Once cleared due to linkfailure, this bit willremain cleared until register 1 is read via

the management interface.

5. Indicates that the PHY provides an extended set of capabilities that may be accessed through the extended register set. For a PHYthat

incorporates a GMII/RGMII,the extended register set consists of all management registers except registers 0, 1, and 15.

LS! Corporation 39

TruePH YET.l.01lC Data Sheet

Gigabit Ethernet Transceiver September 2007

Table 23. PHY Identifier Register 1--—Address2

PI-IYIdentiﬁer Register 1

Default i Notes

15:0 PHY Identiﬁer Bits Organizationaily unique identiﬁer (OUI), bits 3:18.

3 :1 8

Bit i Name I Description ‘ Type |

I \ "° I 0><02s2 ‘ 1

Table 24.PHY Identiﬁer Register 2—Address 3

PHY Identiﬁer Register 2

Bit | Name | Description

Default I Notes

19:24

15:10 \ PHY Identiﬁer Bits }Organizationaliy unique identiﬁer (OUI), bits 19:24.

7°

111100 1

7-1

000001 

320 Revision Number Revision number = 4.

9:4 i Model Number | Model number I l.

7°

0100 ——

1. The LS1 OUI is 00-05-3D.

40 I.Sl Corporation

Data Sheet TruePHYET10l1C

September 2007 Gigabit Ethernet Transceiver

Table 25.Autonegotiation Advertisement Register—Address 4

Autonegotiation Advertisement Register 1

Bit Name Description TYPE Default Notes

l5 Next Page l = Advertise next page ability supported.

OI Advertise next page ability not supported.

R/W 0

14 Reserved -— RO O

l = Advertise remote fault detectedr

0 = Advertise no remote fault detected.

13 Remote Fault R/W O

12 Reserved i RO 0

ll Asymmetric Pause 1 = Advertise asymmetric pause ability.

0 = Advertise no asymmetric pause ability.

R/W PAUSE l

10 Pause Capable l = Capable offull-duplex pause operation.

O= Not capable of pause operation.

RIW PAUSE 1

9 lO0Base-T4 Capabil- 1= l00Base-T4 capable.

ity 0 = Not l00Base-T4 capable.

R/W 02

8 l00Base-TX Full- 1 = l0OBase-TX full-duplex capable.

Duplex Capable 0 = Not l00Base-TX full-duplex capable.

R/W l

7 l00Base-TX Half~ 1 = l00Base-TX half-duplex capable.

Duplex Capable O= Not l00Base—'l‘Xhalf-duplex capable.

R/W 1

6 lOBase-T Full- l = l0Base-T full-duplex capable.

Duplex Capable 0 = Not 1OBase-Tfull-duplex capable.

R/W 1

5 l0Base-T Haltl l = l0Base-T halt‘-duplexcapable.

Duplex Capable 0 = Not l0Base-T half-duplex capable.

R/W l

4:0 Selector Field 0000i = IEEE 802.3 CSMA/CD. R/W 00001

1. Value read from PAUSE on reset.

2. The ET1011C does not support 1OOBase-T4,so the default value of this register bit is zero.

Note: Any write to this register prior to the completion of autonegotiation isfollowed by a restart ofautonegonationi Also note that this register is not updated

following autonegotiution.

LS1Corporation 4]

TruePHYET101] C Data Sheet

Gigabit Ethernet Transceiver September 2007

Table 26. Autoncgotiation Link Partner Ability Register—Address 5

Autonegotiation Link Partner Ability Register

Bit Name Description Type Default Notes

15 Next page

C>>—

= Link partner does not have next page ability.

= Link partner has next page ability. R0 O —

14 Acknowledge

Q;-i

= Link partner has received link code word.

= Link partner has not received link code word.

13 Remote Fault

$|—A

= Link partner has detected remote fault.

= Link partner has not detected remote fault.

l2 Reserved

ll Asymmetric Pause

Q>

= Link partner desired asymmetric pause.

= Link partner does not desire asymmetric pause.

ll) Pause Capable Link partner capable of full-duplex pause opera

tion.

()= Link partner is not capable of pause operation.

9l00Basc-T4 Capa

bility 1I Link partner is l00Basc-T4 capable.

O= Link partner is not l00Base-T4 capable.

8l0OBase-TX Full

Duplex Capable l = Link partner is 1(]0Base-TX full-duplex capable.

0 = Link partner is not 100Base-TX full-duplex capa

blc.

7l00Base-TX Half

Duplex Capable l = Link partner is l00Base-TX half-duplex capable.

0 = Link partner is not lO0Base-TX halt‘-duplex capa

blc.

6l0Base-T Full

Duplex Capable mlI Link partner is 1OBase-Tfull-duplex capable.

0 = Link partner is not 10Basc-T full-duplex capable.

5l0Base-T l-lalf

Duplcx Capable l = Link partner is 10Base-T half-duplex capable.

0 = Link partner is not 10Basc-T half-duplex capable.

4-:0 Protocol Selector

Field Link partner protocol selector ﬁeld.

42 LS] Corporation

Data Sheet TruePHYETl0l1C

September 2007 Gigabit Ethernet Transceiver

Table 27. Autonegotiation Expansion Register—~Address6

Autouegotiation Expansion Register

Bit Name Description Type Default Notes

15:5 Reserved RO

4 Parallel Detection

Fault

Q._=

= Parallel link fault detected.

= Parallel link fault not detected. RO

Ll cl

3 Link Partner Next

Page Ability

@>->

= Link partner has next page capability.

= Link partner does not have next page capability.

RO O

ity

2 Next Page Capabil

Q._.

= Local device has next page capability.

I Local device does not have next page capability.

LH 1

l Page Received

©»—

I New page has been received from link partner.

= New page has not been received.

LH 0

0 Link Partner Auto

negotiation Ability

S-1

= Link partner has autonegotiation capability.

I Link partner does not have autonegotiation capa

bility.

RO O

Table 28. Autonegotiatiun N€Xt Page Transmit Rcgister—Address 7

Autonegotiation Next Page Transmit Register

Bit Name Description Type Default Notes

15 Next Page l = Additional next pages follow.

0 = Sending last next page.

R/W 0

14 Reserved RO 0

.l3 Message Page

Q.

= Formatted page.

= Unformattcd page.

R/W 1

12 Acknowledge 2

@>—~

= Complies with message.

= Cannot comply with message.

R’W K)

11 Toggle l = Previous value of transmitted link code word Wﬁnﬁ

logic zero.

0 = Previous value of transmitted link code word was

logic one.

RO 0

10:0 Message/

Unformatted Code

Field

Next page message code or unformatted data. R/\V l

LS1Corporation 43

TruePHYET10l1C

Gigabit Ethernet Transceiver Data Sheet

September 2007

Table29. Link Partner Next Page Register--Address 8

Link Partner Next Page Register

Bil Name Description Type Default Notes

l5 Next Page

O»

= Additional next pages follow.

= Sending last next page.

RO () __

l4 Acknowledge

®r

Z Acknowledge.

= N0 acknowledge.

RO U T

13 Message Page

Q»-t

= Formatted page.

= Unformatted page.

R/W 0 _._

l2 Acknowledge 2

¢>._.t

Complies with message.

= Cannot comply with message.

R/W O 1

ll Toggle = Previous value of transmitted link code word was

logic zero.

0 Previous value oftransmitted link code word was

logic one.

RO Q _

10:0 Messagel

Unfonnattcd Code

Field

Next page message code or unfomtatted data. R/W 0 4..

44 LS1 Corpomtion

Data Sheet TruePHYET1011C

September 2007 Gigabit Ethernet Transceiver

Table 30. 1000 Base-T Control Register-—Address 9

1000Base-TControl Register

Bit Name Description Type Default Notes

15:13 Test Mode 000 = Normal mode.

O01= Test mode l—transmit waveform test.

0] 0 = 'l‘estmode 2 master transmitjitter test.

011 = Test mode 3—s1avetransmitjitter test (slave mode).

100 = Test mode 4-—transmit distortion test.

101,110,111: Reserved.

R/W O00 —

12 Master/ Slave

Conﬁguration

Enable

l = Enable master/slave conﬁguration.

0 = Automatic master/slave conﬁguration‘

R/W Q __

l l Master/Slave

Conﬁguration

Value

1I Conﬁgure PHY as master.

O= Conﬁgure PHY as slave.

RlW () 1

l0 Port Type

C

= Prefer multipoit device (master).

= Prefer single-port device (slave).

R/W Q __

9 Advertise

l000Basc-"I" Full

duplex Capability

.

= Advertise lO0OBase-T Full-duplex capability.

ll= Advertise no l()00Base-T ﬁill-duplex capability.

R/W SPEED_l 000 2

8 Advertise

l00()Base-T Half

duplex Capability

1 = Advertise 'l000Base-'l' half-duplex capability.

0 = Advertise no 1000Base-T half-duplex capability.

R/W SPEED_1000 2

7:0 Reserved RO

l Setting this bit has no effect unless address 9. bit 12 is set.

2. Value read from SPEED_1000 pin at reset.

Note; Logically, bits 12:8 can be regarded as an extension of the technology ability ﬁeld of register 4.

LSI Corporation 45

TruePHYET] 011C Data Sheet

Gigabit Ethernet Transceiver September 2007

Table 31. l000Base-T Status Reg"ister—Address 10

l000Base-T Status Register

Bit Name Description Type Default Notes

l5 Master/

Slave Conﬁgura

tion Fault

l = Master/slave conﬁguration fault detected.

0 = No master/slave conﬁguration fault detected. RO,

LH,

O l

l4 Master/ Slave

Conﬁguration

Resolution

1= Local PHY resolved to master.

0 = Local PHY resolved to slave. RO () 2

l3 Local Receiver

Status l = Local receiver okay.

O= Local receiver not okay.

RO 0 _

l2 Remote Receiver

Status

Q»-4

I Remote receiver okay.

= Remote receiver not okay.

R0 0 _

ll Link Partner

l000l3asc-T Full

duplex lIapabil

ity

Q._.

= Link partner not l0OOBasc-Tfull-duplex capable.

= Link partner is capable of lO00Base-T full duplex. RO 0 3

10 Link Partner

l0()0Base-T

Half-duplex

Capability

l = Link partner is l000Base-T half-duplex capable.

0 = Link partner not lO(l()Base-'1"half-duplex capable.

R0 O 3

9:8 Reserved RO

7:0 Idle Error Count MSB of idle error count. RO () 4

1. Once set, this bit remains set untilcleared by the followingactions:

|‘lRead of register l0 via the rnanagement interface.

n Reset.

IiCompletion of autonegotiation.

rtEnable of autoncgotiation.

2. This bit is not valid when bit 15 is set.

3. Note that logically,bits 11:10 may be regarded as an extension of the technology ability ﬁeld of register 5.

4. These bits contain a cumulative count of the errors detected when the receiver is receiving idles and both local and remote receiver status

are OK.The count is held at 255 inthe event of overﬂowand is reset to zero by reading register 10 via the management interface or by reset.

46 LSI Corporation

Data Sheet TruePHYET10l1C

September 2007 Gigabit Ethernet Transceiver

Table 32. Reserved Registers-—~Addresses 11——14

Reserved Registers

Bit | Name ‘ Description I Type Default Notes

15:0 |Rescrvcd l -— | — — 

Table 33. Extended Status Register—Address 15

Extended Status Register

Bit Name I Description Type Default Nates

15 l000Base-X Pull- 0 = Not l00OBase-X full-duplex capable. R0 0 -—

duplex

14 l000Base-X Ha1f- 0 = Not l000Base-X half-duplex capable. R0 0 —

duplex

13 l000Base-T Full- = l000Base-T full-duplex capable. RO 1

duplex I Not l()()()Base-Tfull-duplex capable.

Q-—

l2 l00()Base-T Halli I l00()Base-'1"half-duplex capable. R0 l —

duplex = Not 1000Base-T half-duplex capable.

Q.

ll :0 | Reserved | —— | 0 —’

I. Value is a result of (SPEED__l000) pin at reset.

Table 34. Reserved Registers—Addresses 16-17

Reserved Registers

Bit | Name | Description Type Default | Notes

15:0 | Reserved | -— — —— I —

LS1Corporation 47

TruePHYET101lC

Gigabit Ethernet Transceiver Data Sheet

September 2007

Table35. PHYControl Register 2—Address 18

PHY Control Register 2

Bit Name Description Type Default Notes

15 Resolved —

14 Count False Car

rier Events 1I Rx error counter counts false carrier

events.

0 I Rx error counter does not count false car

rier events.

IUW 01

13 Count Symbol 1= Rx error counter counts symbol errors.

Errors O= Rx cnor counter counts CRC errors. R/W O1

12:11 Reserved —

10 Automatic I Enable automatic MDl/MDI-X detection.

M[)l/M.DI-X = Disable automatic MDI/MDI-X detection.

@_.

R!W 1

9 MDI/MDI-X = Manual MD]-X conﬁguration.

Conﬁguration = Manual MI)l conﬁguration.

Q...

R/W 0See

Table 36.

8:3 Reserved —

2 Enable l = Enable diagnostics,

Diagnostics 0 1 Disable diagnostics.

R/W 0 2

1:0 Reserved ~— — ——- -—

1. Count symbol errors (18.13) and count false carrier events (18.14) control the type of errors that the Rx error counter (20. 15.0) counts (settings are shown

below). The default is to count CRC errors.

Count False Count SymbolErrors Rx Error Counter

Carrier Events

1 Cotmts symbol errors and false carrier events.

0 Counts CRC errors and false carrier events

I Counts symbol errors.

0 I Counts CRC errors.

2. This bit enables Pl-IYdiagnostics. which include IP phone detection and TDR cable diagnostics. it is not recommended to enable this bit in normal opera

tion (when thc link is active}. This bit does not need to be set for link analysis cable diagnostics.

48 LS1 Corporation

Data Sheet TruePHYET101l C

September 2007 Gigabit Ethernet Transceiver

Bit 9. PH‘! Control Register 2, manually sets the MDI/MDI-X conﬁguration ifautcmatic MDIX is disabled, as indicated

below.

Table 36. MDI/MDI-X Conﬁguration

Automatic MD!/MDI-X MDI/MDI-X MD!/MDI-X Mode

Conﬁguration

O-Di

iAutomatic MDI/MDI-X detection.

0 iMDI conﬁguration (NlC/DTE).

l I MDI-X conﬁguration (switch).

The mapping of the transmitter and receiver to pins for MDI and MDI-X conﬁguration for lOBase-T, iO()Base-TX.and

l0()0Base-T is shown below. Note that even in manual MDI/MD]-X configuration, the PHY automatically detects and cor

rects for C and D pair swaps.

Table 37. MD!/MD]-X Pin Mapping

Pin MDI Pin Mapping MD!-X Pin Mapping

10Base-T 100Base-TX i 1000Base-T l0Base-T 100Base—TX i l000Base-T

TRD[l)]+/~ Transmit +/— Transmit +/~ Transmit A+/— Receive +l* Receive +/- Transmit B+/A

Receive B+/~ Receive A+/~

'I‘RD[1]+/~- Receive +/— Receive +/7- Transmit B+/~ Transmit +l— Transmit +/- Transmit A+/—

Receive A+I— Receive B+/A

TRD[2]+/- - — Transmit 0+/e — — Transmit D+/

Receive D+/- Receive C+/

TRD[3]+/- - - TransmitD+I- -- -~ TransmitC+/

Receive C+/- Receive D+/

LSI Corpuration 49

TruePHY ET1011C

Gigabit Ethernet Transceiver Data Sheet

September 2007

Table 38. Loopback Control Register—Address 19

Loopback Control Register

Bit Name Description Type Default Notes

l5 Mil l = Mil loopback selected.

O= Mil loopback not selected.

R/W 1 ....

I4: I3 Reserved

12 All Digital l = All digital loopback selected.

0 = All digital loopback not selected.

R/W [) _

ll Replica 1 Replica loopback selected.

0 = Replica loopback not selected.

R/W 0 l

10 Line Driver l = Line driver loopback selected.

0 = Line driver loopback not selected.

R/W Q __.

9:8 Reserved

7External Cable l = External cable loopback enabled.

0 = External cable loopback disabled.

R/W () __

6:1 Reserved

0Force Link Status 1= Force link status okay in Mli loopback.

2 = Force link status not okay in Mil loopback.

R/W 0 2

1. Replica loopback is not available in l0Base-T.

2. This bit can be used to force link status okay during Mil loopback. ln Mil loopback, the link status bit will not he set unless force link status is used. in all

other loopback modes, the link status hit will be set when the link comes up.

Loophack“ode Settings

The followingtable shows how the loopback bit (0.14) and the cablediagnosticmode bit (23.13) should be set for

each loopback mode. Italso indicates whether the loopback mode sets the linkstatus bitand when the PHY is

ready to receive data.

Table 39. Loopback Bit (0.14)and Cable Diagnostic Mode Bit (23.13) Settings for Loopback Mode

Loopback Bit 0.14 Bit 23.13 = I Bit 26.6 PHY Ready for Data

Loopback Cable Diagnostic Mode Link Status Set

Required Required

Mil Yes N0 19.0 Alter atfew ms

All Digital Yes Yes Yes Link Status

Replica Yes Y€S Yes

Yes Yes Yes Link Status l

Link Status |

Linc Driver

l Ext Cable No Yes Yes Link Status l

50 i.,Sl Corporation

Data Sheet TruePH YETI 011C

September 2007 Gigabit Ethernet Transceiver

Table 40. RX Error Counter Register——Address20

RX Error Counter Register

Bit 1 Name l Description IType Defaultl Notes

15:0 Rx Error Counter 16-bit Rx error counter. R0, O Reference Reg

ister 18 (bits I3

and l4) for error

type descrip

lions

Table41. Management Interface (Ml) Control Register-Address 21

Management Interface (Ml) Control Register

Bit i Name | Description R Type

15:3 Reserved | —— I 4

2 Ignore 10G Frames l = Management frames with ST = <00> are ignored. R/W

0 = Management frames with ST <0()>are treated as

wrong frames Default ‘ Notes \

1 __

1 |Reserved ~~ I —

0Preamble Suppres- 1= Ml preamble is ignored. R/W

sion Enable 0 = Ml preamble is required. T iii

LS1Corporation 51

TruePHYETl0l1 C Data Sheet

Gigabit Ethernet Transceiver Septembet 2007

Table 42. PHY Conﬁguration Register—Arldress 22

PHY Configuration Register

Bit Name Description Type Default Notes

l5 CRS Trzinsmil Enable I = Enable CRS on transmit in half-duplex mode.

(J= Disable CRS on transmit.

R/W 0

14 Reserved

13:12 Transmit FIFO depth

(10()0Base-T)

00 = i8.

Ol=il6.

10=i24.

ll =i32.

R/W Ol

11:10 Automatic Speed

Downshift Mode O0= Disable automatic speed downshilt.

10= 100Base-TX downshift enabled.

xl = 100Base-TX and 10Base-T enabled.

R/W ll 1

9 TBI Detect Select l = CRS pin outputs comma detect.

(J= CRS pin outputs link status detect

R/W 0

8 T131Rate Select l = Output l25 Mllz clock on RX_CLK while

COL is held low (full rate).

0 ==Output even/odd clocks on RX_CLK/COL

R/W 0

7 Alternate Next~Page l = Enables manual control of lOO0Base-Tnext

pages only.

0 = Normal operation of lO0OBase-Tnext page

exchange

R/W 0

6 Group MDlO Mode

Enable 1 = Enable group MDIO mode.

0 I Disable Group MDIO mode.

R/W ()

5 Transmit Clock EnablGl I Enable output of l()00Base-'l‘transmit clock

('l‘X_CLK pin).

0 = Disable output.

R/W 0

4 System Clock Enable 1 = Enable output of‘125 MHZ reference clock

(SYS_CLK pin).

0 = Disable output of 125 MHz reference clock.

R/W sYs_cu<_i=.N_N 2

3 Reserved

2:0 MAC Interface Mode

Select O00= GMII/MIL

001 = TBI.

R/W See bit 23.6 (next

page) and

010 = GMII/MI] clocked by GTX_CLK instead of Note 1, Table 10,

'l‘X_CLK. page 30.

O11= Reserved.

100 = RGMII (trace delay).

101 = RTBI (trace delay).

110= RGMl1(DLL delay).

lll = RTBI (DLL delay).

'

I. lf automatic speed downshift is enabled and the l-‘HYfails to autonegotiate at l0OOBase-'1‘,the PHY will fall hack to attempt connection at 100Base-TX

and, subsequently, l0Base-To This cycle will repeat lfthe link is broken at any speed, the PHY Wlllrestart this process by reatteiiipting, connection at the

highest possible speed (e.g.. l00OBase~T).

2. Value is read from inversion ofSYS__Cl,K_ EN N at reset

3. For the 63-pin MLCC, only RGMIl and RTBI inodes;'options are supported.

52 LSl Corporation

Data Sheet TruePHYET101lC

September 2007 Gigabit Ethernet Transceiver

Table 43. Pl-lYControl Register—Address Z3

PI-IYControl Register

Bit Name Description Type Default Notes

15 [P Phone Detected

Q»-1

= IP phone detected.

1 IP phone not detected.

RO O 1

14 IP Phone Detect

Enable

<3_t

= Enable automatic ll" phone detect.

= Disable automatic 1Pphone detect.

R/W.

SC 0 2

13 Cable Diagnostic

Mode

<;._.

= Link analysis mode.

= TDR mode. R/W 1 3

12:11 Automatic Speed 00 = 1

Downshiﬁ/\t‘ternpts 01 = 2

Before Downshift 10 =

1&0)

ll=

R/W ll 

10:7 Reserved —

6Alternative RGM11 1 1 TXC DLl.. delay in RGMII mode is opposite ofRXC.

TXC DLL Delay O= TXC DLL delay in RGMI1 mode is same as RXC.

RfW See Note 1, 4

Table l0.

page 30.

5Jabber

(l0Base-T)

O»-d

= Disablejabber.

= Normal operation.

R/W Q _

4SQE

(10Base-T) =

Q

= Enable heartbeat.

Disable heartbeat. R/W O —

3TP_LOOPBACK e oop ' g p e

(10Base-'1‘)

O-1

=Disabl TPl back durin half-du l x.

= Normal operation.

R/W 1 _..

2Preamble Genera- one e p ‘ nera 0 0

tion Enable

= F bl reamble ge ti n F r 10Base-'1‘.

= Disable preamble generation for 10Base-'1'.

R/W 1 __.

lReserved —

0Force Interrupt 1= Assert l\/ll)lN'1‘_Npin.

0 = Deassett MD1NT_N pin.

R/W Q ___

This bit is only valid when the PHY is in PHY standby mode (26.15 e 1)and after the IP phone detect enable bit (23.14) has been set and has seltleleared

to indicate that the ll‘ phone detection algorithm has completed.

Setting this bit enables the automatic 1Pphone detection algoriﬂim and clears the IP phone detected bit (23. 15).Diagnostics must be enabled (18.2= 1),

cable diagnostic TDR mode must be selected (23.13 I 0), and the Pl-lYmust be in PHY standby mode (26.15 = llto do 11‘phone detection. IP phone detect

enable self-clears when the [P phone detection algorithm is complete, the result is then indicated in IP phone detected

This bit sets the cable diagnostics mode. The default is link analysis mode wherein the PHY brings up atlink with a remote partner. For analysis of cable

faults, the Pl-lY can be put in TDR mode. ln TDR mode, the P1lY will not respond to link pulses from a remote link partner and will not bring up a link.

This bit allows independent control over TXC and RXC DLL delay. Settings are shown below:

22.220

RGMII Mode Delay Description

RXC

10x

TXC

Ons Ons RGM11(trace delay).

llx Zns 2 ns | not/111(txc and RXC 01.1. delay).

10x

-o

2ns Ons | RGMII (rxc DLL delay).

llx Ons Zns l RGMl1(RXCmt delay).

LS1Corporation 53

TI‘llePHYETIIJIIC Data Sheet

Gigabit Ethernet Transceiver September 2007

Table 44. Interrupt Mask Register-—~Address24

Interrupt MaskRegister

Bit Name Description Type Default Notes

15:1I Reserved

10 TDRIIP Phone

(3.4

= Interrupt enabled.

= Interrupt disabled.

R/W Q _.

9 MDIO Sync Lost

<;_.

= Interrupt enabled.

= Interrupt disabled.

R/W 0 _

8 Autunegotiation

Status Change

<3._

= Interrupt enabled.

I IIIILCITUPIdisabled.

R/W I) —

7 CRC Errors

Q»-1

= Interrupt enabled.

= Interrupt disabled.

R/W () __

6 Next Page Received

@>-A

= Interrupt enabled.

I Interrupt disabled.

R/W [) _ .._.

5 En-or Counter Full

Z Interrupt enabled.

= Interrupt disabled.

R/W Q ___

4 FIFO OverIl0w/

Underﬂow

Q»-A

= Interrupt enabled.

= Interrupt disabled.

R/W O i

3 Receive Status

Change

@._t

= Interrupt enabled.

= Interrupt disabled.

R/W 0 ._._

2 Link Status Change

Q»-I

= Interrupt enabled.

= Interrupt disabled.

R/W 0 __

I Automatic Speed

Downshift

Q

= Interrupt enabled.

= Interrupt disabled.

R/W 0 ._

0 l\/IDINT_N Enable

C-1

= Ml)IN'l‘_N'enab1ed‘.

= MDlNT_N disabled.

R/W O ___

I. MDINT _Nis asserted (zvelive-low)if Mll interrupt pending 1 I.

54 LSI Corporation

Data Sheet TruePHYET101lC

September 2007 Gigahit Ethernet Transceiver

Table 45. Interrupt Status Register-—Address25

Interrupt Status Register

Bit Name Description 1‘/re Default Notes

15:11 Reserved

10 TDR/IP Phone

Q_\

= Event has completed.

= Event has not completed.

RO,

0 .

9 MDIO Sync Lost

®>-

= Event has occurred.

= Event has not occurred. R0,

LH 0 l

8 Autonegotiation

Status Change

<3»

= Event has occurred.

= Event has not occurred. R0,

0 —

7 CRC Errors

Q-4

= Event has occurred.

= Hvent has not occurred. R0,

[) _..._

6 Next Page Received

Q..

: Event has occurred.

= Event has not occurred. R0,

Q .__

5 Error Counter Full

@._t

= Event has occurred.

= Event has not occurred. RO,

LH Q .._

4 FIFO Overtlow/

Underﬂow

Q>._

= Event has occurred.

Event has not occurred.

RO.

() __

3 Receive Status

Change

Qt-u

: Event has occurred.

= Event has not occurred. R0,

I) ~—

2 Link Status Chang6

= Event has occurred.

Event has not occurred. R0,

LH 0 __

1 Automatic Speed

Downshift

Q.

I Event has occurred.

= Event has not occurred. R0,

O —

ing

0 Mll Interrupt Pend

()1-~

= lntcmtpt pending.

= No interrupt pending.

R0,

0 2

l. lf the management frame preamble 1Ssuppressed (MF preamble suppression, register O,bit 6), it is possible for the PHY to lose synchronization if there is

a glitch at the interface. The PHY can recover ifa single frame with apreanible is sent to the PHY. The MDIO sync lost interrupt can he used to detect loss

of s§'nchronization and, thus, enable recovery.

2. An event has occurred and the corresponding interrupt mask bit is enabled (set = 1).

l.Sl Corporation 55

TTUQPHYETIQIIC Data Sheet

Gigabit Ethernet Transceiver September 2007

Table 46. PHY Status Register—Address 26

PHY Status Register

Bit Name Description Type Default Notes

15 PHY in Standby

Mode 1 = PHY in standby mode.

0 = PHY not in standby mode.

O 1

'l4:l3 Autonegotiation

Fault Status l0 = Master/slave autonegotiation fault.

01 = Parallel detect autonegoliation fault.

00 = N0 autonegotiation fault.

l2 Autonegotiation

Status 1= Autoncgotiation is complete.

O= Autonegotiation not complete.

ll MDI-X Status l = MDI-X conﬁguration.

I)= MDI conﬁguration.

10 Polarity Status 1 = Polarity is normal (l0Base-T only).

O= Polarity is inverted (10Base-'1"only).

9:8 Speed Status ll -'=Undetermined.

10 : 'l0()0Base—T.

01 l00Base-TX.

00 = l()Base—T.

7Duplex Status

Q-1

= Full duplex.

: I-lalfduplex.

6Link Status

Q>—

= Link is up.

= Link is down.

5Transmit Status

p—l

= PllY is transmitting a packet.

()= PHY is not transmitting a packet.

4Receive Status

<3»

= PHY is receiving atpacket.

I PHY is not receiving a packet.

3Collision Status

@._

= Collision is occurring.

= Collision not occurring.

2Autonegotiation

Enabled

@._.

= Both partners have autonegotiation enabled.

I Both partners do not have autonegotiation enabled.

lPAUSE Enabled

(3

= Link partner advertised PAUSE mode enabled.

= Link partner advertised PAUSE mode disabled.

0Asymmetric Direc

tion

Q»

= Link partner advertised direction is symmetric.

= Link partner advertised that direction is asymmetric.

1.This bit indicates that the PilY is in standby mode and is ready to perform IP phone detection or 'l"DR cable diagnostics. The PHY enters standby mode

when cable diagnostic TDR mode is selected (23. I3 = 0) and the link is dropped. A software reset (0.15) or software power down (0. Il) can be used to

force the link to drop.

56 LS1 Corporation

Data Sheet TruePHYET10llC

September 2007 Gigabit Ethernet Transceiver

Table47.LEDControl Register l-Address 27

LED Control Register l

Bit Name Description Type Default Notes

15 Two-Color Mode

LED_1o0o/LEo_100

O.“

= Two-color mode for LF.l)_i0O0 and LED_100.

= Normal mode for LED_l 000 and l,ED_l O0.

R/W Ol

14 Two-Color Mode

LED_LlNK/LED_TXRX

Q»-t

= Two-color mode for LED_LINK and LED_TXRX.

= Normal mode for l.ED_LINK and LED_TXRX.

R/W U1

13 LED__TXRXExtended

Modes

Q»-1

= Extended modes for LED_TXRX.

= Standard modes for LEl)_TXRX.

R/W 02

l2 LED_l,lNK Extended

Modes I Extended modes for LED_I.lNK.

0 = Standard modes for LED_LINK.

R/W 02

l 1 l,ED__lO0 Extended

Modes

Q.

= Extended modes for LED_l00.

I Standard modes for LED_l()0.

R/W 02

l0 LED_1000 Extended

Modes

@>_~

= Extended modes for LED_I 000.

= Standard modes for LED_1()00.

R/W 0Z

9:8 Reserved

7:4 LED Blink Pattern Pause LED blink pattem pause cycles. R/W OX0

3:2 LED Pulse

Duration 00 = Stretch LED events to 28 ms.

01 = Stretch LED events to 60 ms.

10 '=Stretch LED events to 100 ms.

ll = Reserved.

R/W 00

I Reserved

O Pulse Stretch 0 l = Enable pulse stretching of LEI) functions: transmit

activity, receive activity. and collision

O= Disable pulse stretching of LED functions: transmit

activity, receive activity, and collision.

R/W l

l. iftwo-color mode 1Senabled for pair LED_l_lNl\' and LED _"l"XRX,the signal output for LED_LlNK is equal to (l.ED_LlNK and Li.iD_TXRX). For the

cuss where LED_LlNK and LED_TXRX are not mutually exclusive (e g , duplex and oollisionl this mode can simplify the extemal circuitry because it

ensures either LED_LINK or LED_TXRX is on, and not both at the some time. The same rule applies to pair LED_l000 and l.ED_l00.

2. The LED function is programmed using this bit and register 28.

LS1Corporation 57

TruePHY ET1011C

Gigabit Ethernet Transceiver Data Sheet

September 2007

Table 48. LED Control Register 2—Address 28

LED Control Register 2

Bit Name Description Type Default Notes

15:12 LED_'1'XRX As per 11:8. RW 1111 —~

11:8 LED_l..1N1( Standard modes

0000 = l000Base-'1‘.

0001 = l00Base-TX.

0010 = 1OBase-T.

0011 = 100013356-Ton, 100Base-TX blink.

0100 = Link established.

0101 = Transmit.

0110 = Receive.

0111 = Transmit or receive activity.

1000 = Full duplex.

1001 = Collision.

1010 = Link established (on) and activity (blink).

1011= Link established (on) and receive (blink).

1100= Full duplex (on) and collision (blink).

1101 = Blink.

1110 = On.

1111 = Off.

Extended modes

0000 = 10Base—Tor 100Base-TX.

0001 = Resewed.

0010 1 Reserved.

0011 = Reserved.

01.00 I 10001-Ease-‘1"(on) and activity (blink).

0101 = 10Base-T or 100Base-TX (on) and activity

(blink).

011x = Reserved.

R/W 01()O —

7:4 1.1-,'1)_100 As per 11:8. RW 1111 -—

3.0 1.1;-)D_1000 As per 11:8. R/W 0000 —

Table49. LED Control Register 3-Address 29

LED Control Register 3

Bit 1 Name 1 Description Default | Notes

15:14 LED Blink Pattern

Address Select LED blink pattern register set.

O0I Select register set for 1.ED_1.1NK.

01 = Select register set for 1.ED_TXRX.

10= Select register set 1'0:-1.El)_l000.

11= Select register set for LED_100.

Type i

R/W

13:8 LED Blink Pattcm

Frequency LED blink pattern clock frequency divide ratio. R/W

7:0 ILED Blink Pattern LED blink pattern. R/w}

00 -—

ilxlf l

0x2: 1 I

1.The default pattem is a 512 ms blink

58 LS1Corporation

Data Sheet TruePHYETl0ll C

September 2007 Gigabit Ethernet Transceiver

Table 50. Diagnostics Control Register (TDR Mode)—Adtlress 30

Diagnostics Control Register (TDR Mode)

Bit Name Description Type Default Notes

15:I4 TDR Request ll = Automatic TDR analysis in progress.

10 = Single-pair TDR analysis in progress.

01 = TDR analysis complete, results valid.

O0= TDR analysis complete, results invalid.

R/W 00 1

13:12 TDR Tx Dim Transmit dimension for single-pair TDR analysis.

O0= TDR transmit on pair A.

Oi = TDR transmit on pair B.

10 = TDR transmit on pair C.

ll = TDR transmit on pair D.

R/W ()0 2

ll:lO TDR Rx Dim Receive dimension for single-pair TDR analysis.

O0= TDR rcccivc on pair A.

()1= TDR receive on pair B.

10 = TDR receive on pair C.

I I = TDR receive on pair D.

R/W 00 2

9:2 Distance to Fault Distance to open or short fault. R/W 03.4

l :0 Reserved

1 Automatic TDR analysis is enabled by setting TDR request to (ll ). All 10 combinations of pairs are analyzed in sequence, and the results are available in

registers 30 and 31. TDR analysis for a single-pair combination can be enabled by setting TDR request to {I0} Diagnostics must be enabled (18.2 = I),

cable diagnostic TDR must be mode selected (23.13 = O),and the PHY must be in Pl-lY standby mode (26.15 '—l) to perform TDR operations. Bit l5 sch"

clears when the TDR operation is complete. When TDR is complete, bit 14 indicates whether the results are valid.

2. TDR transmit and receive dimensions are only valid for single-pair TDR analysis. They are ignored for automatic TDR analysis when all l0 pair combina

tions arc analyzed.

3. This is the distance to an open, short, or strong impedance mismatch fault on the chosen pair for single~pairTDR analysis. For automatic TDR analysis, this

returns the distance to the last open, short, or strong impedance mismatch fault found. The automatic algorithm searches for faults in the order of short

between C and D. B and D. B and C, A and D, A and C, A and B; and faults on pair D. pair C, pair B. and pair A. Iflhere is no fault, the result will be Oxff

and should he ignored.

4. The 8-bit integer value can be linearly converted to distance in meters. The value 0x08 (or less) corresponds to a distance of 0 m, and the value Oxtecorre~

sponds to a distance of 200 m (180 ni for Cat-3 cable). The following equation can be used to convert the integer value to meters:

distance (m) i l.l79 X(x- 8) XNVP

Where,

NVP I normalized velocity ofpropagation (typically 0.69 for CATS, C/\'l'5e. and CAT6;0.62 for CAT3). For CATS/Sc/'6cable. a simple

approximation (accurate to 0.1%) is (x '—8) x 13/16.

LS1Corporation 59

TruePHYETlD11C Data Sheet

Gigabit Ethernet Transceiver September 2007

Table 51. Diagnostics Status Register (TDR Mode)—Address 31

Diagnostics Status Register (TDR Mode)

Bit Name Description Type Default Notes

15:14 TDR Fault Type

Pair A

(or fault type for

single pair combi

nation)

11= Short found on pair A.

10 = Open found on pair A.

01 = Strong impedance mismatch found on pair A.

O0= Good termination found on pair A.

R/W ()0 l

13:12 TDR Fault Type

Pair B 11 = Short found on pair B.

10 I Open "foundon pair B.

01 = Strong impedance mismatch found on pair B

00 I Good termination found on pair B.

R/W 00 —

11:10 TDR Fault Type

Pair C 1I = Short found on pair C.

10 = Open found on pair C.

Ol = Strong impedance mismatch found on pair C

O0= Good termination found on pair C.

R/W 00 

9:8 TDR Fault Type

Pair D ll = Short found on pair D.

I0 = Open found on pair D.

O1= Strong impedance mismatch found on pair I).

()0= Good termination found on pair D.

R/W 00 7

7Short Between

Pairs A and B I = Short between pairs A and B.

O= No short between pairs A and B.

R/W O _._

6Short Between

Pairs A and (I l = Short between pairs A and C.

0 = N0 short between pairs A and C.

RIW 0 _

5Short Between

Pairs A and l) 1 1 Short between pairs A and D.

O= N0 short between pairs A and 1).

R/W 0 _.

4Short Between

Pairs B and C 1 = Short between pairs B and C.

0 = No short between pairs Band C.

R/W () __

3Short Between

Pairs B and D 1 = Short between pairs B and D.

0 = N0 short between pairs B and D.

R/W O _.

2Short Between

Pairs C and D 1= Short between pairs C and D.

0 = No short between pairs C and D.

R/W 0 _

1 :0 Reserved

1. For automatic TDR analysis. this returns the fault type on pair A. For single-pair TDR analysis, this returns the fault type on the pair combination under test,

i.c., as speciﬁed in the TDR Tx Dim and Rx Dim (30.13:12 and 30.11110,respectively).

60 LS1 Corporation

Data Sheet TruePHYETl0ll C

September 2007 Gigabit Ethernet Transceiver

Table 52. Diagnostics Control Register (Link Analysis Mode)—Address 30

DiagnosticsControl Register (Link Analysis Mode)

Bit Name Description Type Default Notes

l5:l2 Reserved

l 1 Pair Swap on Pairs C

and D 1= Pairs C and D are swapped (l00OBase-T only).

0 = Pairs C and D are not swapped (l 000i-Base-Tonly).

R/W 0See

Table 53.

l0:5 Cable Length Cable length when link is active. R/W O1

4 Polarity on Pair D l I Polarity on pair D is normal (l000Basc-T only).

0 = Polarity on pair D is inverted (l0O0Base-T only).

R/W 0

3 Polarity on Pair C l = Polarity on pair C is normal (1000Base-'l‘ only).

O= Polarity on pair C is inverted (l000l3asc-T only).

R/W 0

2 Polarity on Pair B 1= Polarity on pair B is normal (l000Base-'l" only).

0 = Polarity on pair B is inverted (lO00Base-T only).

R/W 0

l Polarity on Pair A l = Polarity on pair A is normal (1000Base-'1‘only).

0 = Polarity on pair A is inverted (l0()0Base-T only‘).

R/W O

O Excessive Pair Skew 1 = Excessive pair skew (lOO0Base-T only).

0 = Not excessive pair skew (l0O0Base-T only).

R/W 02

1. This is the cable length estimate when the link is active (maximum of I55 rn). The values of 0x00 to Oxifcorrespond to 0 m—l $5 m in S m increments.

The values of 0x20 to 0x3e are reserved for future use, e.g., cable lengths of 160 m—315 m. The result may be invalid for a l0Base-T lllll\'.if the result is

invalid, a value of0x3f is returned.

2. lalxcessivepair skew is detected by determining that the scrambler has not acquired. ll is possible for other scrambler acquisition errors to be mistaken for

excessive pair skew.

The following table shows the mapping ofthe transmitter and receiver for MDI and MD]-X conﬁguration

for 100()Basc-T when pairs C and D are not swapped and are swapped.

Table 53. MDI/MD]-X Conﬁguration for 1000Base-Twith C and D Swapped/Not Swappcd

Pin Pair C and D Are Not Swapped Pair C and DAre Swapped

lVlDlConﬁguration MDI-X

Conﬁguration MDI Conﬁguration Conﬁguration

MDI-X

TRD_[0:7]_|i0'|+/— Transmit A+/-Receive Transmit B+/—

B+/— Receive /\+/~

Transmit A+/— Transmit B+/—

Receive B+/~ Receive A+/-—

TRD_[0:7]_[l ]+/— Transmit B+/-Receive Transmit A+/~

Receive 13+/~

A+/—

Transmit B+/— Transmit A+/~

Receive A+/A Receive B+/'

'l‘Rl)_[0:7]_[2']+/ Transmit D+/

Receive C+/—

Tiansmit C+/—

Rcceive D+/—

TransmitC+/- TransmitD+/

Receive C+/A Receive D+/—

'1*no__[0=7]_[3]+/ Transmit C+/~

Receive D+/—

Transmit D+/—

Receive C+/Y Receive D+/~

Transmit D+/— Transmit C+/—

Receive C+/4

LSI Corporation 61

TruePHYET10llC Data Sheet

Gigabit Ethernet Transceiver September 2007

Electrical Speciﬁcations

Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress rat

ings only. Functional opcration of the device is not implied at these or any other conditions in excess of those given in the

operations sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device

reliability.

Table 54. Absolute Maximum Ratings

Parameter Symbol Min Max

Supply Voltage (2.5 V analog) AVDDH 4.2 | Unit

Supply Voltage (1.0 V analog) AVDDL 1.2

Supply Voltage (3.3 V/2.5 V digital) D\/DDlO 4.2

Supply Voltage (1.0 V digital) Von l.2

ESD Protection Vest:

Storage Temperature TSTORE -40 2000

l 25 °C

Recommended Operating Conditions

Table55. ETl0l1C Recommended Operating Conditions

Parameter Symbol Min Tyv Max Unit

Supply Voltage (2.5 V analog) AVDDH 2.38 2.5 2.62

Supply Voltage (l .0 V analog)‘ /\\/poi. 0.95 l.0orl.l l.l5

Supply Voltage (3.3 V digital)2 DVoD|o 3.14 3.3 3.46

Supply Voltage (2.5 V digital? DV Doio 2.38 2.5 2.62

Supply Voltage (1.0 v digital)‘ Von 0.95 l.O0rl.l 1.15

Ambient Operating Temperature-—Commercial TA 070 °C

Ambient Operating Temperature———lndustrial TA -40 85 °C

Maximum Junction Temperature TJ 0l25 “C

Thermal Characteristics. 128 TQFP (JDEC 3 in. x 4.5

in. 4-layer PCB):

0 m/s airﬂow

l m/s airﬂow

2.5 m/s airﬂow

TJB

TJC

\|I.lT

“C/W

TJA 37

TJA 32

Tm 30

Thermal Characteristics, 84-pin MLCC and

68-pin MLCC (IDEC 3 in. x 4.5 in. 4-layer PCB):

0 m/s Airﬂow

l m/s Airflow

2.5 m/s Airﬂow

TJB

Ti <1

um

°C./W

TJA 24

Tm 23

Tm 21

l. Forthe l28-pin TQFP package operating over the industrial temperature range. the maximum voltage is reduced from l.l5 V to 1.05. V.The center tap

voltage range is changed to l.8V only.

2. The part can operate at either 3.3 V (typically for an GMII interface) or 2.5 V (typically for an RGMII interface).

62 LS1Corporation

Data Sheet TruePHYET101lC

September 2007 Gigabit Ethernet Transceiver

Electrical Speciﬁcations (continued)

DeviceElectrical Characteristics

Device electrical characteristics refer to the behavior of the device under speciﬁed conditions imposed on the user for proper

operation of the device. Unless otherwise noted, the parameters below are valid for the conditions described in the previous

section, Recommended Operating Conditions.

Table 56. Device Characteristics—3.3 V Digital I/O Supply (DVDDIO)

Parameter Symbol Min TYP Max Unit

Input Leakagel (digital pins without pull-up or pull-down) llLeak -l0 I0 u/\

Input Leakage (digital pins with pull-up or pull-down) lILcak -lO0 100 uA

Input Low Voltage Vn. v0.3 0.8 V

Input High Voltage Vin 2.0 3.6 V

Output Low Voltagez Vot 0.4 V

Output High Voltagc3 Von 2.4 V

Differential Output Voltage (analog MDI pins l000Base-'1‘) V 0131H-‘ 0.67 0.75 0.82 V

Differential Output Voltage (analog MDI pins IO0Basc-TX) VODII-"F 0.95 1.0 1.05 V

Differential Output Voltage (analog MDI pins 10Base-T) VODII-‘F 2.2 2.5 2.8 V

Table 57. Device Characteristics—2.5 V Digital l/O Supply (DVDDIO)

Parameter Symbol Min WP Max Unit

Input Leakage (digital pins without pull—upor pull-down) In. -10 10 uA

Input Leakage (digital pins with pull-up or pull-down) lu. -100 100 uA

Input Low Voltage V 11.. -0.3 0.7 V

Input High Voltage VII-I l.7 2.8 V

Output Low Voltage; VOL 0.4 V

Output High Voltage3 Von 2.0 V

I)it'ferential Output Voltage (analog MD] pins lO0OBase-T) VODIFF 0.67 0.75 0.32 V

Differential Output Voltage (analog MDI pins lO0Base-TX) VODII-‘F 0.95 1.0 1.05 V

I)iﬂerentia1 Output Voltage (analog MDI pins lOBase—T) VODIFF 2.2 2.5 2.8 V

I RESET N pin IILeak max=1mA when DVVDIO is more than 0.8V above the AVDDII supply.

2. All pinsitested with IOL=4mA except for the following pins: RXD[3:0]==3mAin Mll mode only; MDlNT__Nand MDlO=9mA, 'I‘DO1l4mA.

3. All pins tested iwth IOH==3mAexcept for the following pins; RXD[3:0]=2mA in MII mode; MDINT__Nand MDIO=6mA with VOlImin'—].9S\/,

TDO:8m/\ with VOI-lmin=l.95V. PHYADOand PI-IYADI=5rna with VOHmin=l.95V.

LSI Corporation

TruePHYET10l1C Data Sheet

Gigahit Ethernet Transceiver September 2007

Electrical Speciﬁcations (continued)

Device Electrical Characteristics (continued)

Table58. ETl011C Current Consumption 1000Base-T

Parameter Symbol Condition Min TYP Max Unit

Supply Voltage (2.5 V analog) lavoon Tx/Rx

random data 62 in/\

Supply Voltage (1.0 V analog) lAVDDL Tx/Rx

random data 205 mA

Supply Voltage

(3.3 V digital - GMII mode) or

(2.5 V digital - RGMll mode)

lovooio Tx/Rx

random data 30

20 mA

Supply Voltage (1.0 V digital) l\/on TX/Rx

random data 131 mA

Center Tap Voltage (1.8 V or 2.5 V analog) ICTAP Tx/Rx

random data 183 mA

Table 59. ET1011C Current Consumption 1l]0Base-TX

Parameter Symbol Condition Min Tyn Max Unit

Supply Voltage (2.5 V analog) lavoon Tx/Rx

random data 20 mA

Supply Voltage (1.0 V analog) lA\/DDL Tx/Rx

random data 55 m/\

Supply Voltage

(3.3 V digital - Mll mode) or

(2.5 V digital - RGMII mode)

lovnmo TX/RX

random data 22

Supply Voltage (1.0 V digital) lvoo Tx/Rx

random data 23 mA

Center Tap Voltage (1.8 V or 2.5 V analog) lCTAP TX/Rx

random data 40 mA

Table 60. ET101lC Current Consumption 10Base-T

Parameter Symbol Condition Min Typ Max Unit

Supply Voltage (2.5 V analog) lAVDl)H Tx/Rx

random data 20 mA

Supply Voltage (1.0 V analog) IAVDDL TX/Rx

random data 55 mA

Supply Voltage

(3.3 V digital - Mll mode) or

(2.5 V digital - RGMII mode)

1ox-131510 TX/Rx

random data 20

Supply Voltage (1.0 V digital) lwm Tx/Rx

random data ll mA

Center Tap Voltage (1.8 V or 2.5 V analog) Iornr Tx/Rx

random data 60 mA

64 LS1Corporation

Data Sheet TruePHYET] 011C

September 2007 Gigabit Ethernet Transceiver

Electrical Speciﬁcations (continued)

Device Electrical Characteristics (continued)

Table 61. ET1l)11CCurrent Consumption 10Base-T Idle

Parameter Symbol Condition Min Typ Max Unit

Supply Voltage (2.5 V analog) lAVDDl-l ldle 20 mA

Supply Voltage (1.0 V analog) lAVl')DL Idle 55 mA

Supply Voltage

(3.3 V digital - Mil mode) or

(2.5V digital - RGMII mode)

lI)\'DDlO ldle 16

l0 mA

Supply Voltage (l .0 V digital) l\/on Idle ll mA

Center Tap Voltage (1.8 V or 2.5 V analog) lCTAP Idle lmA

Table62.ETl01lC Current Consumption Hardware Powerdown

Parameter Symbol Condition Min TYP Max Unit

Supply Voltage (2.5 V analog) lAVDDH Hardware

Powerdown 2mA

Supply Voltage (1.0 V analog) lA\’Dl)l. Hardware

Powerdown 6mA

Supply Voltage (3.3 V or 2.5 V digital) lDVl')DlO Hardware

Powerdown 7m/\

Supply Voltage (1.0 V digital) lvon Hardware

Powerdown 3mA

Center Tap Voltage (1.8 V or 2.5 V analog) lC'I'AP Hardware

Powerdown 0mA

Table 63. ETl01lC Current Consumption Low Power Energy Detect (LPED)

Parameter Symbol Condition Min Ty!» Max Unit

Supply Voltage (25 V analog) lAvonH LPED 4mA

Supply Voltage (1.0 V analog) lAVDDL LPED 6mA

Supply Voltage (3.3 V or 2.5 V digital) l.DVD]')lO LPED 7mA

Supply Voltage (1.0 V digital) lvoo LPED 3mA

Center Tap Voltage (1.8 V or 2.5 V analog) ICTAP LPED 0m/-\

LS1Corporation 6:

TruePHYET10llC Data Sheet

Gigabit Ethernet Transceiver September 2007

Ei6Cfl’iC3i Speciﬁcations (continued)

Device Electrical Characteristics (continued)

Table 64. ETl0llC Current Consumption Standby Powerdown and Standby Powerdown with LPED

Parameter Symbol Condition Min Typ Max Unit

Supply Voltage (2.5 V analog) IAVDDH Standby

Powerdown Mode

with LPED

A 5 ~— mA

Supply Voltage (1.0 V analog) iAVDDL Standby

Powerdown Mode

with LPED

— 20 - mA

Supply Voltage (3.3 V or 2.5 V digital) iDVl)l)l0 Standby

Powerdown Mode

with LPED

~» 12 — mA

Supply Voltage (1.0 V digital) Ivpo Standby

Powerdown Mode

with LPED

~— 13 —— mA

Center Tap Voltage (l 48V or 2.5 V analog) ICTAP Standby

Powcrdown Mode

with LPED

-~ O 4 mA

Table65. ETl0llC Current Consumption Software Powerdown

Parameter Symbol Condition Min Typ Max Unit

Supply Voltage (2.5 V analog) lAVunn Software

Powerdown — 20 — mA

Supply Voltage (l.O V analog) IAVDDL Software

Powerdown ~ 59 -—— mA

Supply Voltage (3.3V or 2.5 V digital) iDVDDlO Software

Powerdown —~ ll —- rnA

Supply Voltage (1.0 V digital) lvnn Soliware

Powerdown — ll -- mA

Center Tap Voltage (1.8 V or 2.5 V analQ2) l("mp Soﬁware

Powerclown ~ 0 — mA

66 LS1Corporation

Data Sheet TruePHYETl01lC

September 2007 Gigabit Ethernet Transceiver

Timing Specification

GMII l000Base-T Transmit Timing (128-Pin TQFP and 84-Pin MLCC Only)

GTX_CLK

5 GTX_C LKc\/ms I

( >

i GTX_CLKmm| 5 GTX_CLNﬁW

K >< Z

__. __. -.¢ -______-_____- ;__.-._-____-___.¢ --_____-__..__

, I

GTX_CLKF*~'=*—>1I<— § -*’-GTX_CLKmsa

o<o[7;o]

TX

TX ER ______ ____ . . ___. . . ___. . . . ____. ___. . _. _ _. _ __. . . _-;_;-__-____---_---__----

EN . ,-j I

GTX_CLKSUE4-:4 §<-——--—m E

Figure I5. GMII l000Base-T Transmit Timing

Table 66. GMII l000Base-T Transmit Timing

GTX CLMww

Symbol Parameter Min T p Max Unit

GTX_CLKcYcu-: GTX_CLl< Cycle Time 7.5

8.5 HS

GTX_CLKi~noH G'l‘X_CLK High Time 2.5 US

GTX_CLKLOw GTX__CLKLow Time 2.5 US

GTX_CLKR1sE GTX_CLK Rise Time 1.0 HS

GTX_CLKmu. GTX_CLK Fall Time 1.0 HS

(iTX_CLKsu 2.0 HS

i (1‘TX_CLKn01.o

IGMII Input Signal Setup Time to GTX_CLK

GMII Input Signal Hold Time to GTX_CLK 0.() US

LSI Corporation

TruePi‘IYET101lC Data Sheet

Glgablt Ethernet Transceiver September 2007

Timing Speciﬁcations (continued)

GMII 1000Base-TReceive Timing (128-Pin TQFP and 84-Pin MLCC Only)

. RX_C LKCYCLE .

K >5

E RX__cLKH\GH , RX_CLKw~ E

K )( 2

. . . ____-.: ______-_______ .j..1__<____.._._--__-¢...-.-__-____--- _--....____

. ‘_

RX_CLK . .

RX_Cl_KFALk——-—-—);§(-- ;<-—--RX'cL|,(R|sE

_. . . . . _. _. . _. ___, . . . . _____. . __________ ___. . . _. _..---»__,_-.____-..-_____. _..

RXD[7:0]

RX_

RXEN . _

ER ‘.. . . _. . - - _ . .._v__.

; 1 Z RX_CLK.HOLD L

RX CLKS F~"i—> '

__ U

Figure 16. GM]! 1l]00Base-T Receive Timing

Table 67. GMII l0l]0Base-T Receive Timing

Symbol l Parameter Min Typ Max Unit

RX_Cl.KcYcLE | RX_cu< Cycle Time 7.5 8.0 — HS

RX_CLKmsn | RX_CLK High Time 2.5 -— HS

RX__CLKLOw | RX_CLK Low Time 2.5 -— ns

R'l‘X~CLl<.1usE I RXMCLK Rise Time HS

>

RX_CI.KFA1.1. I R.X_Cl.K Fall Time HS

RX_CLKsU GMII Output Signal Setup Time to RX_CLK 2.5 — T13

RX_CLKu0u> IGMII Output Signal Hold Time to RX_CLK 0.5 — HS

68 LS1 Corporation

Data Sheet TruePHYET1011C

September 2007 Gigabit Ethernet Transceiver

Timing Speciﬁcations (continued)

RGMII 1000Base-TTransmit Timing

Trace Delay

rxc

AT TRANSMHTER 1

TskewT

TXD[B:5l[3:0]

rxn(r;4][s;o1

TX_EN

qrx_crt_) >< iiiiiiii

-—~>j I TskewR

TXC

AT RECEIVER

Figure 17.RGMII 10l]0Base~TTransmit Timing-~Trace Delay

Table 68. RGMII l0UUBase-TTransmit Timing

rxen TXERR ;; ;

>< TXD[4]><rxo[e] ><

Symbol i Parameter Min i Typ Max Unit

'l'sl<ewT l Data to Clock Output Skew (at transmit'ter)—Trace Delay‘ —

500 0 500 PS

TskewR Data to Clock Input Skew (at receiver)-Trace Delay‘ l1.8 2.6 l’lS

Tcyc Clock Cycle Durationz 7.2 88.8 l'lS

Duty_G i Duty Cycle for Gigabit3 45 50 55 %

Duty_T l Duty Cycle for l0Base-T/1O0Basc-TX3 40 50 60 %

'l‘r/Tt' [Rise/Fall Time (20%-20%) | 0.75 l'lS

l. This implies that PCB design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns and less than 2.0 ns will be added to

the associated clock signal. To enable internal delay, see M11register 22 bits 2:0.

2. For l()Base-T and l00Basc-TX, Tcyc scales to 400 ns 4-40 ns and 40 ns Q4 ns, respectively.

3_Duty cycle may be shrunk/slretclied during Speedchanges or while transitioning to a received packefs clock domain as long as minimum duty cycle is not

violated and stretching occurs for no more than three Tcyc of the l0\\/estspeed transitioned between

LSI Corporation 69

TDMEPHYETl 011C ‘ Data Sheet

Glgablt Ethernet Transcelver September 2007

Timing Speciﬁcations (continued)

Internal Delay

TXC

AT TRANSMITTER . .’

I 1 -‘ VI

““““"'\ '-‘- "\

/ \ ' \:

/ \ / '~i

=\.

Q, rxc WITH

INTERNAL

DELAY

._._..J __-_/ ._l_._I

rx0[a;5][s;o1

rxo[1;41[a;o3 rxn{s;o1>é§gE§,fi} T$etupT

——v£ TholdT

TX_EN

(rx_cr|.) TXEN TXERR 5

X TXDH]><TXD[9]>< ><

TXC

AT RECEWER

TsewpR i<—

E4-— Thbld

Figure 18. RGMII l000Base-T Transmit Timing—-Internal Delay

Table 69. RGMII l000Base-T Transmit Timing

Symhnl Parameter Min Tyv Max Unit

Tsetupl‘ Data to Clock Output Setup (at transmitter—integi~ated

delay)

1.2 2.0 — ns

Thold'l' Clock to Data Output Hold (at transmltter—integrated delay)‘ 1.2 2.0 -— ns

TserupR Data to Clock Input Setup (at receiver——integrateddelay)‘ 1.0 2.0 i ns

TholdR Data to Clock Input Hold (at receiver—integrated delay)1 1.0 2.0 -- ns

Tcyc Clock Cycle Durationz 7.2 88.8 ns

Duty_G Duty Cycle for Gigabit3 45 50 55 %

Duty__T Duty Cycle for l()Basc-T/l0()l3asc-TX3 40 50 60 %

Tr/Tl' Rise/Fall Time (2()%—8O%) 0.75 ns

The FHY uses internal delay to compensate by delaying both incoming and outgoing clocks by ~2 Ons

For l0Basc-T and lO0Basc-TX, Tcyc scales to 400 ns 1-40 ns and 40 ns +_4 ns. respectively

Duty cycle may be shrunk/stretched during speed changes or while transitioning to a received packefs clock domain as long as minimum duty cycle ISnot

violated and stretching occurs for no more than three Tcyc ofthe lowest speed transitioned between.

70 LSI Corporation

Data Sheet TruePH YET10ll C

September 2007 Gigabit Ethernet Transceiver

Timing Speciﬁcations (continued)

RGMII 1000Base-T Receive Timing

Trace Delay

RXC

AT TRANSMITTER

—>1 TskewT

RXD[8:5][3:0]

RXD|_'I:4][3:0]

RX_EN

(RX_CTL)

—>j ' TskewR

RXC ' =

AT RECEIVER

Figure 19. RGMII 1000Base-T Receive Timing—-Trace Delay

Table 70. RGMII l000Base-T Receive Timing

RX_DV RXERR -E 5

>< >< ><

Symbol T Parameter Min Typ Max Unit

Tskew'l' 500 PS

Tskewk Data to Clock lnpul Skew (at receiver)-—Frace Delay]

IData to Clock Output Skew (at transmittcr)~—-Trace Delay‘ —

' 1

._

bcO

2.6 HS

Tcyc Clock Cycle Durationz 7.2

8.8 l1S

Dut:y__G I Duty Cycle for Gigabit3 45

55 %

Duty_T Duty Cycle for l0Base- I‘/100Base-TX3 40 60

\=>

°\

'l‘r/Tf Rise/TallTime (20%-80%)

LII

0.75 l'lS

1. This implies that PCB design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns and less than 2.0 ns will he added to

the associated clock signal. Tn enable imemal delay, sce MII register 22 bits 2:0.

2. For l0Base-T and l0OBase-'l‘X, Tcyc scales lo 400 ns i 40 ns and 40 ns 1:4 ns, respecnvely

3‘ Duty cycle may be shrunk/stretched during speed changes or while transitioning to a received pu/skefs clock domain as long as minimum duty cycle is not

violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned between.

LS1Corporation 7l

TYMQPHYETIUIIC Data Sheet

Gigabit Ethernet Transceiver September 2007

Timing Speciﬁcations (continued)

Internal Delay

'—""'\ ‘W""\ '

4 \ 1 \ 1

RXC . . ' RXC WITH

1 \ / ‘ _/

AT TRANSMFITER . ' \ 1 ‘— INTERNAL

I I \ _/ DELAY

._._.J ._._.J ._._..J

RXD[8:5][3:O]

RXD[7:4-][3:0] RXD[3:0] >< TsetupT ><

—>1 §<- TholdT

RX_EN

(RX_CTL) RX_DV RXERR I 1

XWXWX X X X

RXC

AT RECEIVER :

Tsetu pR

Figure 20. RGMII 1000Base-TReceive Timing—lnternal Delay

Table 71. RGMII l00llBase-T Receive Timing

14* Thold

Symbol Parameter Min Tyv Max Unit

TsetupT Data to Clock Output Setup (at transrnitter—iritegrated

delay)‘

1.2 2.0 —-— |’lS

TholdT Clock to Data Output Hold (zittransmitter-—integraled

delay)‘

1.2 2.0 —— HS

LO 2.0 - ns

'l'setupR Data to Clock Input Setup (at receiver-—lntegrated delay)‘

TholdR Data to Clock Input Hold (at receiver—integ1'ated dela}/)1 l.() 2.0 ~ ns

Tcyc I Clock Cycle Duration‘ 7.2 88.8 ns

l Duty Cycle for Gigabit-" 45 50 55 %

| l)uty_G

l Duty__'l‘ | Duty Cycle for l0l3ase-T/lO()Basc-TX" 40 50 60 %

l Tr/l'f | RisefFall Time (20%—80%) 0.75 ns

l. The PHY uses internal delay to compensate by delaying both incoming and outgoing clocks by ~2_Ons

2. For l0Base-'l" and l00Base-TX, ‘l"cycscales to 400 ns 5:40 ns and 40 ns 1 4 ns, respectively.

3 Duty cycle may he Shl"l.ll'll{/Sll'€5tCl1€dduring speed changes or while transitioning to a received packefs clocl-;domain as long as minimum duty cycle is not

violated and stretching occurs for no more than three Toys of the lowest speed transitioned between.

72 LS1Corporation

Data Sheet

September 2007 TruePHYET1011C

Gigabit Ethernet Transceiver

Timing Speciﬁcations (continued)

MII l00Base-TX Transmit Timing

TX___CLK

TXD[3ZO]

TX_EN

TX_ER1 , ,§I

- - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- ---.--a--

. TX__C L KCVCLE

I TX_CLK»<\sn 3 TX_,C1-KI-OW

_. . . ____4 __________--.

I,1

>4 H

_ .

4,. ______. _. ____-‘ ___

. ___. __ , _____. . . . _. . ---i-A ..-_-__-__-._-_ ,.-__.

Tx~CLKF'\"L€i :"""_ :"""'TX CLKRisE

1. 'I‘X_ER is not available on the 68-pin MLCC.

Figure 21. MII 100Base-TX Transmit Timing

Table 72. MII l00Base-TX Transmit Timing

TX CLKHOLD

TX_CLKsu E<——-—>‘ §<»--—-i—-————->' E

Symbol Parameter Min TYP Max Unit

TX__CLKcvcuz TX_CLK Cycle Time 40 l'iS

'1“X__CLKn1<;n TX_CLK Iiigh Time 20 HS

TX_C l4KLQW TX_CLK Low Time 20 HS

TX__CI ,KRISE TX_CLK Rise Time 5HS

T X__CLKl-‘ALL TX_CLK Fall Time 5I15

TX_Cl.Ksu i Ml] Input Signal Setup Time to TX_CI,K 15 l'lS

TX_CLKHOLD | MII Input Signal Hold Time to TX_Cl,K 0HS

LSI Corporation

TruePHYET1011C

Gigabit Ethernet Transceiver Data Sheet

September 2007

Timing Speciﬁcations (continued)

MII 100Base-TX Receive Timing

1 RX_C LKcvc LE

K)1

i RX_CLK111s+< 1 RX__CLKuJw

)(

' 111

5..

1 '1

RX_C LK

_. . . . . ____. ___ LJ_______._-.___.¢

. 1

__. _. _. ___. _. . . . _______L¢'__-_------____'_J-_-_~

RX_CLK1=111k_>i j<_ 5 CLKRISE

11 1

RXD[3:0]""""""""""""""""""""""""""""""" __

RX_EN

RX ER 

— .1,

_. ____ . ___ _. _______. _. . . ___. . ____. . _. _ _. . . _. __._.F_r_______-._...--.__'-__

Figure 22. MII l00Base-TX Receive Timing

Table 73. Mll l00Base-TX Receive Timing

_ - 3 . RX__CLK11o1.0 .

RX_CLKsu;<—i>'g

Symbol ‘ Parameter Min Typ Max Unit

R)(_CI..KcYc1.E 1RX_CLK Cycle Time 40 HS

RX_CLKH1011 | RX_CLK High Time 20 HS

RX_CI..K1.0W | RX_CI,K Low Time 20 HS

RTX_CLKR1sF. | RX_Cl,K Rise Time 1HS

RX_CLKFAL1_ RX_CLK Fail Time 1HS

RX_CLKsu Mil Output Signal Setup Time to R.X_CLK ]() HS

RX__CLKH01_n MII Output Signal Hold Time to RX_CLK 10 HS

74 LS1Corporation

Data Sheet

September 2007 TruePHYET101l C

Gigabit Ethernet Transceiver

Timing Speciﬁcations (continued)

M1110Base-T Transmit Timing

| TX_CLKCYCLE >'

' TX_CLK>-new 3 TX_C|-KLOW 

K >:<

_______.; |

-.1 .

. > ,

TX_C LK

| v

I .

TX—CLkALL% T" §‘iTX__CLKR1sE

.v_¢ ______. _. . . . ..'._-_ _. . . . . . __. _.

____. . . . . . . .__ ;.1.____._._____.Ll _‘..____....

TXD[3I0]

TX_EN

TX_ER 1 _

-\._----___

_,._

Figure 23. MII l0Base-T Transmit Timing

Table 74. Ml] 1llBase-TTransmit Timing

, J 5 . TX_CLK)iQLD .

TX_CLKsu :<i—-—-> 1

Q Symlwl Parameter Min TYP Max

TX_CLKcYCi_E TX__CLKCycle Time 400 I'lS

TX_CLKi11GH TX_C LK High Time 200

Unit

TX_CLK1.,0w TX__CLKLow Time ZOO HS

TX (ILK Rise Time

TX_CLKRisF. _ 1HS

TX_CLKFALL | TX_CLK Fall Time 1I15

TX_CLKsu | Mli Input Signal Setup Time to TX_CLK 15 1'15

TX CLKHQLD

i | MII Input Signal Hold Timc to TX_(ZLK 0l'1S

LSI Corporation 75

TruePHYET10llC

Gigabit Ethernet Transceiver Data Sheet

September 2007

Timing Speciﬁcations (continued)

MI] 10Base-T Receive Timing

. RX___Ci_KCYCLE

1 RX_CLK>~usH : RX_C LKLOW

. . ______4 __-___._______ ;J.____________

RX_CLK

)( X

_.; -_

1|!

RX_CLKF»\LL——*§ §<——— §<—Rx_c|_KR.sE

RXD[3:0] __________________________________________ -

RX_EN

RX_ER

Figure 24. Mll 10Base-T Receive Timing

Table 75. Mll l0Base-T Receive Timing

_ - 1 l RX__CLKHOl_D ;

RX_CLKsu 2<—-————>'1

Symbol Parameter Min Typ Max Unit

RX_CLKc\/cu: l RX_CLl<Cycle Time  400 HS

RX_CLKH1GH RX_CLK High Time 200 HS

RX_CLKLow RX_CLK Low Time ‘ 200 HS

RTX_CLKR1s1=.' RX__CLK Rise Tirnc — 1HS

RX_CLK]-‘ALL i RX_CLK Fall Time — lHS

RX_CLKsu HS

‘ Mll Output Signal Setup Time to RX_CLK 10

, 10

RX__CLKi-[OLD Mil Output Signal Hold Time to RX_CI K HS

76 LS1Corporation

Data Sheet TruePHYETl01l C

September 2007 Gigabit Ethernet Transceiver

Timing Speciﬁcations (continued)

Serial Management Interface Timing

MDC

MDCcYc|_E .

i MDCHIGH : MDCLQW Z

4- ................... --..--.. .;_.;.................. .........;..;.

§<—|\/lDCR\sE

MDIO (INPUT)

.......................................................................... -.............;.;..i

MDCHOLD

MDCsu

................................................................. .. ; ................4..........

|v|0|o (OUTPUT) ...... A4 -...»,.. ....... ....,___......

MDCDE LAY

Figure 25. Serial Management Interface Timing

Table 76.Serial Management Interface Timing

Symbol i Parameter I Min TYP Max Unit

I\/IDCCYCLE l MDC Cycle Time 100 HS

MDC!-non IMDC High Time 40 1'15

MI)C|.0w MDC Low Time 40 HS

IVIDCRISE ' MDC Rise Time 5HS

MDC;-1\LL l MDC Fall Time 5HS

MDCsU MDIO Signal Setup Time to MDC 10 HS

lVlDCH0l.D MDIO Signal Hold Time to MDC 10 HS

M DC DELAY MDIO Delay Time from MDC 80 l'lS

LSI Corporation

TruePHYET1011C Data Sheet

Gigabit Ethernet Transceiver September 2007

Timing Sp6CiﬁCﬂti0IlS (continued)

Reset Timing

K RESETPL|LSE_LEN j §_ RESETCFGJREAD

RESET N

RESETHSE

LED_xx LEDpins are Inputs I LEDpins are Outputs

SYS_CLK

I COMAPULSE LEN CoMAc1=a READ

K _ Y 1 '

COMA ~f

€“*cOMA¢ALL

LED_xx LEDpins are Inputs LEDpins are Outputs

SYS CLK

1<_COMAw_sYs_cu:c

COMA |»_svs_cu<_v¢|m

:<-i—i*I

Figure 26. Reset Timing

Table 77. Reset Timing

Symbol t Parameter Min Typ Max Unit

20 _ pg

1 RESETPULSEWLEN [ RESET_N Pulse Length

1 RI1-ISE'l‘R1si=. | RESET_N Rise Time 1.0 — HS

RFSET( rm READ RE§l"T_N D€dS5€TliO1'1to Configuration Read ITIS

COMAPuL;5_|.E1~.' | COMA Pulse Length 20 __ H3

CON]/\FAI.L 1COMA Fall Time 1.0 —— [IS

COMA'ro sx/s,c1.|< 1COMA Deassertion to SYS_CLK 1.0 _ “S

COMA'r0__sYs_cLK_w.1.iDI COMA Dctassertion to SYS_CI,K Valid ITIS

1“

COMAcFG_READ {COMA Deasscﬂion to Configuration Read IIIS

V‘

78 LSI Corporation

Data Sheet TruePH YET1011C

September 2007 Gigabit Ethernet Transceiver

Timing Speciﬁcations (continued)

Clock Timing

I XTAL__1 cvctz

: XTAL__1w@»| E XTAL_1t@w

-ix

2‘ .

. __. ___-__|___...-__-..._----.. _...._--......._.__..___.¢_\. ____..._

| I 1 »

XTA L_1 - |

vl --.

XTA|__1FAu. XTAL_'lR\sE

Figure Z7.Clock Timing

Table 78. Clock Timing

Symbol Parameter Min TYP Max Unit

X'l‘AL_lcYc|_E XTAL_1 Cycle Time 39.998 40 40.002 l'lS

XT./\L_iHlGH XTAL_1 High Time

I5 20 25 HS

XTAI,._Ii.0\v XT/\L_l Low Time 15 20 25 I15

XTAL_l RISE XTAL_1 Rise Time 3HS

XTAL 1i=Ai.1. IXTAL ]Fa1lTime 3HS

Q | XTAL:] InputClockmm (RMS) 20 pS

— | XTAL_1 Input Clock Frequency 25 MHZ

i — \ X'l‘AL_1 Input Clock Accuracy SO PP1“

LS1Corporation

TTHEPHYETIOIIC Data Sheet

Gigabit Ethernet Transceiver september 2007

Timing Speciﬁcations (continued)

JTAG Timing

TCK

TDI

TMS

TDO

TCKc~rcLE

. .

.. . .. _._.¢ .-....._____-_

E TCKHHGH g TC Kww

. t

. ______ . __. . . _. . . . . _.-.'.t \._-_.________. ,_.

TCKFAU-_-)E :g-TCKRISE

-"H 5' E? TCKHOLD

T¢Ks~ 2

II:IIIllIX iiiiiiiiiiiiiiiiiiiiiii

Figure 2s. JTAG Timing

Table 79. JTAG Timing

TC KDELAV

Symbol i Parameter Min Typ Max Unit

TCKCYCLE ITCK Cycle Time 20 X15

'l‘Cl<;n1csn "rc1<High Time 10 T15

TC K|_0w TCK Low Time 10 HS

TCKR|s12 TCK Rise Time lHS

TCKFALL 1TCK Fall Time 1HS

TCl~’.sL' TD], TMS Setup Time noTCK 2.7 I13

TCKHOLD TDI, TMS Hold Time to TCK 0.8 TIS

TCKDELAY TDO Delay Time from TCK 8.1 l'lS

80 LS1Corporation

Data Sheet

September 2007 TruePHY ET.1011C

Gigabit Ethernet Transceiver

PBCk2lg€ Diagram, 128-Pin TQFP (Dimensionsareinmillimeters.)

Note: Package outlines are unofficial and for reference only.

1-1

-1

-111

-1

38-1

16.00i 0.20

14.00 1' 0.20

PlN #1 1DEN'1'lFlER ZONE

128 103

I -1

‘ -1

-1

‘ E111:

-1

I -1

|__ _ ____ _ -1

-1

\-___._______-_-Z/ 1

-1

jﬂ-1

[ DETAIL./\ /— DETAILB

I ' —T - 1.6+;MAX

I IllI|||l|l|||||ll|||||||||||||||l!|lll|l|||||l||||IIII 1 swmc.PLANE

\ / ' ' ' ' ' ' ' ' ' ' ' ' ' ' -_' ' ' ' -- -- _Ti‘

xT' ’ —>ll<—°-5°TY? l 0.05/0.15 E

GAGE PLANE

102

20.00

i 0.20

22.00

iO.20

-_______._.Y_

1.40i 0.05

1.00 REF

0.25

0.45/O. 75

[(1.106/'0.'ZOO

SEATINGPLANE 0.19/0'27 _'| 1

LS1Corporation

DETAIL A

Data

Sheet

September

2007

TruePHY

ET1011C

Gigabit

Ethernet

Transceiver

Package

Diagram,

84-Pin

MLCC

(Dimensions

are

millimeters.)

Note:

Package

outlines

are

unofficial

and

for

reference

only.

mn8\._¢zE«E

zm>u

man

“To

zafiuum

_.o.o

_:|||

nN.o

>m:>

mam

uz¢.E

uzfifiw

3m:>

zafium

uBm\._¢zE~_u»

JCZHSMMH

fit

>m:>

mm;

mango

y-......---_-_....-..-_-......-_-_-......;”

mm:

gig

To.

m_n_Fzmo_

S“

8..

LS1

Corporation

uSm3<zEmu..

zm>u

«E

uEm\._¢zEmE.

«E

....m

om.o

.zzE~_E

_..

/I.

4|.

wag

u-u

zezuw

■■

_ilI

.i|

mad

>m:>

zE.Em

>m:>

mew

>mH>

map

uz<.a

uztfim

-‘s

,.---..-....----......-----....-----..

Data

Sheet

September

2007

Package

Diagram,

68—Pin

MLCC

(Dimensions

are

millimeters.)

Note:

Package

outlines

are

unofiicial

and

for

reference

only.

LS1

Corporation

TruePHYETl0l1C Data Sheet

Gigabit Ethernet Transceiver September 2007

Ordering Information

Table 80. Ordering Information

Device/Package Description Part Number‘ Comcode

ET 1011C

84-pin MLCC Commercial GbE Transceiver, Lead-Free L-ET1011C2-C-D 711017464

Commercial GbE Transceiver, Lead-Free L-ET1011C2-C-DT 711017465

Industrial GbE Transceiver, Lead-Free L-ET1011C2-C1-D 711017462

Industrial GbE Transceiver. Lead-Free L-ET1011C2-Cl-DT 711017463

BT10! 1C

68-pin MLCC

E'l'1 01 1C

128~pin TQFP2

N.

-17‘

21'.

Commercial GbE Transceiver, Lead-Free I.-ETl011C2-M-D 711017468

Commercial GbE Transceiver, Lead-Free L-ET1011C2-M~D'l‘ 711017469

Industrial GbE ‘lransceiver. Lead-Free I.-ETl01lC2-MI-D 711017466

Industrial GbE Transceiver, Lead-Free L-ETl 0l1C2-Ml-DT 711017467

Commercial GbE Transceiver, Lead-Free L-ET10l1N1C-T-DB 711010940

lead-free, -DT I Tape and Reel.

5 is revision 3, "C" silicon (not revismn 4, "C2" Hind is not recommended for new designs.

LS1Corporation

TruePHYET101lC Data Sheet

Gigabit Ethernet Transceiver September 2007

IEEE is a regisiered trademark of the Institute of Electrical and Electronics Engineers, lnc.

Magic Packer 1Sa registered trademark of Advanced Micro Devices, Inc.

For additional informaiiun. contact your LSIAccount Manager or the following:

INTERNET: Home: http:IIwww.lsi.com

E-MAIL: docmaster@agere.com

N. AMERICA: LSI Corporation, Coporate Headquarters‘ 1621 Barber Lane, Mipilas, CA. 95035

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LSIand ma LSI Iago are trademarks of LSI Corporation. Allother brand and prnduct names may be rrademarks of iheir respective companies. TruePHY is a irademark of Agere Systems inc

AilRights Reserved § ¢ 1»

September 2007

DSD6-161GPHY-4(Replaces D806-161PHY-3. D506-i61GPHY-2, DS06-161GPHY-1and DSO5- 4 Q3

OSSGPHY) Q