M95512-W M95512-R M95512-DR M95512-DF 512-Kbit serial SPI bus EEPROM Datasheet - production data Features * Compatible with the Serial Peripheral Interface (SPI) bus SO8 (MN) 150 mil width * Memory array - 512 Kb (64 Kbytes) of EEPROM - Page size: 128 bytes * Write - Byte Write within 5 ms - Page Write within 5 ms TSSOP8 (DW) 169 mil width * Additional Write lockable page (Identification page) * Write Protect: quarter, half or whole memory array * High-speed clock: 16 MHz UFDFPN8 2 x 3 mm (MC) * Single supply voltage: - 2.5 V to 5.5 V for M95512-W - 1.8 V to 5.5 V for M95512-R and M95512DR - 1.7 V to 5.5 V for M95512-DF * Operating temperature range: from -40C up to +85C WLCSP (CS) (preliminary data) * Enhanced ESD protection * More than 4 million Write cycles * More than 200-year data retention * Packages - RoHS compliant and halogen-free (ECOPACK(R)) June 2013 This is information on a product in full production. DocID11124 Rev 21 1/50 www.st.com 1 Contents M95512-W M95512-R M95512-DR M95512-DF Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 3.1 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 5 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 6 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.2 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.3 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.1 2/50 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DocID11124 Rev 21 M95512-W M95512-R M95512-DR M95512-DF 6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.5 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.6 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.6.1 7 Contents Cycling with Error Correction Code (ECC) . . . . . . . . . . . . . . . . . . . . . . 25 6.7 Read Identification Page (available only in M95512-D devices) . . . . . . . 26 6.8 Write Identification Page (available only in M95512-D devices) . . . . . . . 27 6.9 Read Lock Status (available only in M95512-D devices) . . . . . . . . . . . . . 28 6.10 Lock ID (available only in M95512-D devices) . . . . . . . . . . . . . . . . . . . . . 29 Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 DocID11124 Rev 21 3/50 List of tables M95512-W M95512-R M95512-DR M95512-DF List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. 4/50 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 M95512-D instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Operating conditions (M95512-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Operating conditions (M95512-R and M95512-DR, device grade 6) . . . . . . . . . . . . . . . . . 32 Operating conditions (M95512-DF, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DC characteristics (previous M95512-W products, device grade 6). . . . . . . . . . . . . . . . . . 34 DC characteristics (M95512-W products, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . 35 DC characteristics (M95512-R and M95512-DR products, device grade 6). . . . . . . . . . . . 36 DC characteristics (M95512-DF products, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . 37 AC characteristics (previous M95512-W products, device grade 6) . . . . . . . . . . . . . . . . . . 38 AC characteristics (M95512-W products, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . 39 AC characteristics (M95512-R and M95512-DF, device grade 6) . . . . . . . . . . . . . . . . . . . 40 SO8N - 8-lead plastic small outline, 150 mils body width, mechanical data . . . . . . . . . . . 42 TSSOP8 - 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 43 UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 M95512-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package mechanical data. 46 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 DocID11124 Rev 21 M95512-W M95512-R M95512-DR M95512-DF List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 WLCSP connections for M95512-DFCS6TP/K (top view, marking side, with bumps on the underside) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Read Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Write identification page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Read Lock Status sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 SO8N - 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 42 TSSOP8 - 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 43 UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package outline. . . . . . . 44 M95512-DFCS6TP/K - WLCSP 8-bump wafer-level chip scale package outline . . . . . . . 45 DocID11124 Rev 21 5/50 Description 1 M95512-W M95512-R M95512-DR M95512-DF Description The M95512 devices are Electrically Erasable PROgrammable Memories (EEPROMs) organized as 65536 x 8 bits, accessed through the SPI bus. The M95512-W can operate with a supply voltage from 2.5 V to 5.5 V, the M95512-R and M95512-DR can operate with a supply voltage from 1.8 V to 5.5 V, and the M95512-DF can operate with a supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of -40 C / +85 C. The M95512-D offers an additional page, named the Identification Page (128 bytes). The Identification Page can be used to store sensitive application parameters which can be (later) permanently locked in Read-only mode. Figure 1. Logic diagram VCC D Q C S M95xxx W HOLD VSS AI01789C The SPI bus signals are C, D and Q, as shown in Figure 1 and Table 1. The device is selected when Chip Select (S) is driven low. Communications with the device can be interrupted when the HOLD is driven low. Table 1. Signal names Signal name 6/50 Function Direction C Serial Clock Input D Serial Data Input Input Q Serial Data Output Output S Chip Select Input W Write Protect Input HOLD Hold Input VCC Supply voltage - VSS Ground - DocID11124 Rev 21 M95512-W M95512-R M95512-DR M95512-DF Description Figure 2. 8-pin package connections (top view) M95xxx S Q W 1 2 3 4 VSS 8 7 6 5 VCC HOLD C D AI01790D 1. See Section 10: Package mechanical data for package dimensions, and how to identify pin-1. Figure 3. WLCSP connections for M95512-DFCS6TP/K (top view, marking side, with bumps on the underside) VCC D C HOLD W Q VSS S MS19789V3 Caution: As EEPROM cells lose their charge (and so their binary value) when exposed to ultra violet (UV) light, EEPROM dice delivered in wafer form or in WLCSP package by STMicroelectronics must never be exposed to UV light. DocID11124 Rev 21 7/50 Memory organization 2 M95512-W M95512-R M95512-DR M95512-DF Memory organization The memory is organized as shown in the following figure. Figure 4. Block diagram HOLD W S High voltage generator Control logic C D Q I/O shift register Address register and counter Data register Status register Y decoder 1/4 1/2 Size of the Read only EEPROM area 1 page Identification page X decoder MS19733V1 8/50 DocID11124 Rev 21 M95512-W M95512-R M95512-DR M95512-DF 3 Signal description Signal description During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held high or low (according to voltages of VIH, VOH, VIL or VOL, as specified in Section 9: DC and AC parameters). These signals are described next. 3.1 Serial Data Output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). 3.2 Serial Data Input (D) This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock (C). 3.3 Serial Clock (C) This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) change from the falling edge of Serial Clock (C). 3.4 Chip Select (S) When this input signal is high, the device is deselected and Serial Data Output (Q) is at high impedance. The device is in the Standby Power mode, unless an internal Write cycle is in progress. Driving Chip Select (S) low selects the device, placing it in the Active Power mode. After power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction. 3.5 Hold (HOLD) The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven low. DocID11124 Rev 21 9/50 Signal description 3.6 M95512-W M95512-R M95512-DR M95512-DF Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either high or low, and must be stable during all Write instructions. 3.7 VCC supply voltage VCC is the supply voltage. 3.8 VSS ground VSS is the reference for all signals, including the VCC supply voltage. 10/50 DocID11124 Rev 21 M95512-W M95512-R M95512-DR M95512-DF 4 Connecting to the SPI bus Connecting to the SPI bus All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes low. All output data bytes are shifted out of the device, most significant bit first. The Serial Data Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such as the Read from Memory Array and Read Status Register instructions) have been clocked into the device. Figure 5. Bus master and memory devices on the SPI bus VSS VCC R SDO SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK VCC C Q D SPI Bus Master SPI Memory Device R CS3 VCC C Q D VSS C Q D VCC VSS SPI Memory Device R VSS SPI Memory Device R CS2 CS1 S W HOLD S W HOLD S W HOLD AI12836b 1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate. Figure 5 shows an example of three memory devices connected to an SPI bus master. Only one memory device is selected at a time, so only one memory device drives the Serial Data Output (Q) line at a time. The other memory devices are high impedance. The pull-up resistor R (represented in Figure 5) ensures that a device is not selected if the Bus Master leaves the S line in the high impedance state. In applications where the Bus Master may leave all SPI bus lines in high impedance at the same time (for example, if the Bus Master is reset during the transmission of an instruction), the clock line (C) must be connected to an external pull-down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled high): this ensures that S and C do not become high at the same time, and so, that the tSHCH requirement is met. The typical value of R is 100 k. DocID11124 Rev 21 11/50 Connecting to the SPI bus 4.1 M95512-W M95512-R M95512-DR M95512-DF SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the following two modes: * CPOL=0, CPHA=0 * CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 6, is the clock polarity when the bus master is in Stand-by mode and not transferring data: * C remains at 0 for (CPOL=0, CPHA=0) * C remains at 1 for (CPOL=1, CPHA=1) Figure 6. SPI modes supported CPOL CPHA 0 0 C 1 1 C D MSB Q MSB AI01438B 12/50 DocID11124 Rev 21 M95512-W M95512-R M95512-DR M95512-DF 5 Operating features 5.1 Supply voltage (VCC) 5.1.1 Operating supply voltage (VCC) Operating features Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 9: DC and AC parameters). This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS device pins. 5.1.2 Device reset In order to prevent erroneous instruction decoding and inadvertent Write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC reaches the POR threshold voltage. This threshold is lower than the minimum VCC operating voltage (see Operating conditions in Section 9: DC and AC parameters). At power-up, when VCC passes over the POR threshold, the device is reset and is in the following state: * in Standby Power mode, * deselected, * Status Register values: - The Write Enable Latch (WEL) bit is reset to 0. - The Write In Progress (WIP) bit is reset to 0. - The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits). It is important to note that the device must not be accessed until VCC reaches a valid and stable level within the specified [VCC(min), VCC(max)] range, as defined under Operating conditions in Section 9: DC and AC parameters. 5.1.3 Power-up conditions When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see Figure 5). In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edgesensitive as well as level-sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select (S) must have been high, prior to going low to start the first operation. The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage defined under Operating conditions in Section 9: DC and AC parameters, and the rise time must not vary faster than 1 V/s. DocID11124 Rev 21 13/50 Operating features 5.1.4 M95512-W M95512-R M95512-DR M95512-DF Power-down During power-down (continuous decrease of the VCC supply voltage below the minimum VCC operating voltage defined under Operating conditions in Section 9: DC and AC parameters), the device must be: 5.2 * deselected (Chip Select S should be allowed to follow the voltage applied on VCC), * in Standby Power mode (there should not be any internal write cycle in progress). Active Power and Standby Power modes When Chip Select (S) is low, the device is selected, and in the Active Power mode. The device consumes ICC. When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in progress, the device then goes into the Standby Power mode, and the device consumption drops to ICC1, as specified in DC characteristics (see Section 9: DC and AC parameters). 5.3 Hold condition The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. To enter the Hold condition, the device must be selected, with Chip Select (S) low. During the Hold condition, the Serial Data Output (Q) is high impedance, and the Serial Data Input (D) and the Serial Clock (C) are Don't Care. Normally, the device is kept selected for the whole duration of the Hold condition. Deselecting the device while it is in the Hold condition has the effect of resetting the state of the device, and this mechanism can be used if required to reset any processes that had been in progress.(a) (b) Figure 7. Hold condition activation c HOLD Hold condition Hold condition ai02029E a. This resets the internal logic, except the WEL and WIP bits of the Status Register. b. In the specific case where the device has shifted in a Write command (Inst + Address + data bytes, each data byte being exactly 8 bits), deselecting the device also triggers the Write cycle of this decoded command. 14/50 DocID11124 Rev 21 M95512-W M95512-R M95512-DR M95512-DF Operating features The Hold condition starts when the Hold (HOLD) signal is driven low when Serial Clock (C) is already low (as shown in Figure 7). The Hold condition ends when the Hold (HOLD) signal is driven high when Serial Clock (C) is already low. Figure 7 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (C) being low. 5.4 Status Register The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a detailed description of the Status Register bits. 5.5 Data protection and protocol control The device features the following data protection mechanisms: * Before accepting the execution of the Write and Write Status Register instructions, the device checks whether the number of clock pulses comprised in the instructions is a multiple of eight. * All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. * The Block Protect (BP1, BP0) bits in the Status Register are used to configure part of the memory as read-only. * The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits in the Status Register. For any instruction to be accepted, and executed, Chip Select (S) must be driven high after the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising edge of Serial Clock (C). Two points should be noted in the previous sentence: * The "last bit of the instruction" can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for Read Status Register (RDSR) and Read (READ) instructions). * The "next rising edge of Serial Clock (C)" might (or might not) be the next bus transaction for some other device on the SPI bus. Table 2. Write-protected block size Status Register bits Protected block Protected array addresses 0 none none 0 1 Upper quarter C000h - FFFFh 1 0 Upper half 8000h - FFFFh 1 1 Whole memory 0000h - FFFFh BP1 BP0 0 DocID11124 Rev 21 15/50 Instructions 6 M95512-W M95512-R M95512-DR M95512-DF Instructions Each instruction starts with a single-byte code, as summarized in Table 3. If an invalid instruction is sent (one not contained in Table 3), the device automatically deselects itself. Table 3. Instruction set Instruction Description Instruction format WREN Write Enable 0000 0110 WRDI Write Disable 0000 0100 RDSR Read Status Register 0000 0101 WRSR Write Status Register 0000 0001 READ Read from Memory Array 0000 0011 WRITE Write to Memory Array 0000 0010 Table 4. M95512-D instruction set Instruction Description WREN Write Enable 0000 0110 WRDI Write Disable 0000 0100 RDSR Read Status Register 0000 0101 WRSR Write Status Register 0000 0001 READ Read from Memory Array 0000 0011 WRITE Write to Memory Array 0000 0010 Read Identification Page Reads the page dedicated to identification. 1000 0011(1) Write Identification Page Writes the page dedicated to identification. 1000 0010(1) Read Lock Status Reads the lock status of the Identification Page. 1000 0011(2) Lock ID Locks the Identification page in read-only mode. 1000 0010(2) 1. Address bit A10 must be 0, all other address bits are Don't Care. 2. Address bit A10 must be 1, all other address bits are Don't Care. 16/50 Instruction format DocID11124 Rev 21 M95512-W M95512-R M95512-DR M95512-DF 6.1 Instructions Write Enable (WREN) The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for the device to be deselected, by Chip Select (S) being driven high. Figure 8. Write Enable (WREN) sequence S 0 1 2 3 4 5 6 7 C Instruction D High Impedance Q AI02281E DocID11124 Rev 21 17/50 Instructions 6.2 M95512-W M95512-R M95512-DR M95512-DF Write Disable (WRDI) One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure 9, to send this instruction to the device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven high. The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events: * Power-up * WRDI instruction execution * WRSR instruction completion * WRITE instruction completion. Figure 9. Write Disable (WRDI) sequence S 0 1 2 3 4 5 6 7 C Instruction D High Impedance Q AI03750D 18/50 DocID11124 Rev 21 M95512-W M95512-R M95512-DR M95512-DF 6.3 Instructions Read Status Register (RDSR) The Read Status Register (RDSR) instruction is used to read the Status Register. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 10. Figure 10. Read Status Register (RDSR) sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction D Status Register Out Status Register Out High Impedance Q 7 6 5 4 3 2 1 0 MSB 7 6 5 4 3 2 1 0 7 MSB AI02031E The status and control bits of the Status Register are as follows: 6.3.1 WIP bit The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0, no such cycle is in progress. 6.3.2 WEL bit The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1, the internal Write Enable Latch is set. When set to 0, the internal Write Enable Latch is reset, and no Write or Write Status Register instruction is accepted. The WEL bit is returned to its reset state by the following events: 6.3.3 * Power-up * Write Disable (WRDI) instruction completion * Write Status Register (WRSR) instruction completion * Write (WRITE) instruction completion BP1, BP0 bits The Block Protect (BP1, BP0) bits are non volatile. They define the size of the area to be software-protected against Write instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 2) becomes protected against Write (WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. DocID11124 Rev 21 19/50 Instructions 6.3.4 M95512-W M95512-R M95512-DR M95512-DF SRWD bit The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal enable the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. Table 5. Status Register format b7 SRWD b0 0 0 0 BP1 BP0 WEL WIP Status Register Write Protect Block Protect bits Write Enable Latch bit Write In Progress bit 20/50 DocID11124 Rev 21 M95512-W M95512-R M95512-DR M95512-DF 6.4 Instructions Write Status Register (WRSR) The Write Status Register (WRSR) instruction is used to write new values to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must have been previously executed. The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low, followed by the instruction code, the data byte on Serial Data input (D) and Chip Select (S) driven high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise, the Write Status Register (WRSR) instruction is not executed. The instruction sequence is shown in Figure 11. Figure 11. Write Status Register (WRSR) sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction Status Register In 7 D High Impedance 6 5 4 3 2 1 0 MSB Q AI02282D Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the selftimed Write cycle that takes tW to complete (as specified in AC tables under Section 9: DC and AC parameters). While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed Write cycle tW, and 0 when the Write cycle is complete. The WEL bit (Write Enable Latch) is also reset at the end of the Write cycle tW. The Write Status Register (WRSR) instruction enables the user to change the values of the BP1, BP0 and SRWD bits: * The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as read-only, as defined in Table 2. * The SRWD (Status Register Write Disable) bit, in accordance with the signal read on the Write Protect pin (W), enables the user to set or reset the Write protection mode of the Status Register itself, as defined in Table 6. When in Write-protected mode, the Write Status Register (WRSR) instruction is not executed. The contents of the SRWD and BP1, BP0 bits are updated after the completion of the WRSR instruction, including the tW Write cycle. The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in the Status Register. Bits b6, b5, b4 are always read as 0. DocID11124 Rev 21 21/50 Instructions M95512-W M95512-R M95512-DR M95512-DF Table 6. Protection modes W SRWD signal bit 1 0 0 0 1 1 0 1 Mode Write protection of the Status Register Memory content Protected area(1) Unprotected area(1) Status Register is writable (if the WREN instruction Softwarehas set the WEL bit). protected Write-protected The values in the BP1 (SPM) and BP0 bits can be changed. Ready to accept Write instructions Status Register is Hardware writeHardwareprotected. protected The values in the BP1 (HPM) and BP0 bits cannot be changed. Ready to accept Write instructions Write-protected 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register. See Table 2. The protection features of the device are summarized in Table 6. When the Status Register Write Disable (SRWD) bit in the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register (provided that the WEL bit has previously been set by a WREN instruction), regardless of the logic level applied on the Write Protect (W) input pin. When the Status Register Write Disable (SRWD) bit in the Status Register is set to 1, two cases should be considered, depending on the state of the Write Protect (W) input pin: * If Write Protect (W) is driven high, it is possible to write to the Status Register (provided that the WEL bit has previously been set by a WREN instruction). * If Write Protect (W) is driven low, it is not possible to write to the Status Register even if the WEL bit has previously been set by a WREN instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area, which are Software-protected (SPM) by the Block Protect (BP1, BP0) bits in the Status Register, are also hardware-protected against data modification. Regardless of the order of the two events, the Hardware-protected mode (HPM) can be entered by: * either setting the SRWD bit after driving the Write Protect (W) input pin low, * or driving the Write Protect (W) input pin low after setting the SRWD bit. Once the Hardware-protected mode (HPM) has been entered, the only way of exiting it is to pull high the Write Protect (W) input pin. If the Write Protect (W) input pin is permanently tied high, the Hardware-protected mode (HPM) can never be activated, and only the Software-protected mode (SPM), using the Block Protect (BP1, BP0) bits in the Status Register, can be used. 22/50 DocID11124 Rev 21 M95512-W M95512-R M95512-DR M95512-DF 6.5 Instructions Read from Memory Array (READ) As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data Input (D). The address is loaded into an internal address register, and the byte of data at that address is shifted out, on Serial Data Output (Q). Figure 12. Read from Memory Array (READ) sequence S 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 C Instruction 16-Bit Address 15 14 13 D 3 2 1 0 MSB Data Out 1 High Impedance 7 Q 6 5 4 3 2 Data Out 2 1 0 7 MSB AI01793D If Chip Select (S) continues to be driven low, the internal address register is incremented automatically, and the byte of data at the new address is shifted out. When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a single READ instruction. The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip Select (S) signal can occur at any time during the cycle. The instruction is not accepted, and is not executed, if a Write cycle is currently in progress. 6.6 Write to Memory Array (WRITE) As shown in Figure 13, to send this instruction to the device, Chip Select (S) is first driven low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on Serial Data Input (D). The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input data. The self-timed Write cycle, triggered by the Chip Select (S) rising edge, continues for a period tW (as specified in AC characteristics in Section 9: DC and AC parameters), at the end of which the Write in Progress (WIP) bit is reset to 0. DocID11124 Rev 21 23/50 Instructions M95512-W M95512-R M95512-DR M95512-DF Figure 13. Byte Write (WRITE) sequence S 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 C Instruction 16-Bit Address 15 14 13 D 3 2 Data Byte 1 0 7 6 5 4 3 2 1 0 High Impedance Q AI01795D In the case of Figure 13, Chip Select (S) is driven high after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. However, if Chip Select (S) continues to be driven low, as shown in Figure 14, the next byte of input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal Write cycle. Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If more bytes are sent than will fit up to the end of the page, a condition known as "roll-over" occurs. In case of roll-over, the bytes exceeding the page size are overwritten from location 0 of the same page. The instruction is not accepted, and is not executed, under the following conditions: Note: 24/50 * if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before), * if a Write cycle is already in progress, * if the device has not been deselected, by driving high Chip Select (S), at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in), * if the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits. The self-timed write cycle tW is internally executed as a sequence of two consecutive events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is read as "0" and a programmed bit is read as "1". DocID11124 Rev 21 M95512-W M95512-R M95512-DR M95512-DF Instructions Figure 14. Page Write (WRITE) sequence S 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 C Instruction 16-Bit Address 15 14 13 D 3 2 Data Byte 1 1 0 7 6 5 4 3 2 0 1 S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Data Byte 2 7 D 6 5 4 3 2 Data Byte 3 1 0 7 6 5 4 3 2 Data Byte N 1 0 6 5 4 3 2 1 0 AI01796D 6.6.1 Cycling with Error Correction Code (ECC) M95512 and M95512-D devices offer an Error Correction Code (ECC) logic. The ECC is an internal logic function which is transparent for the SPI communication protocol. The ECC logic is implemented on each group of four EEPROM bytes(c). Inside a group, if a single bit out of the four bytes happens to be erroneous during a Read operation, the ECC detects this bit and replaces it with the correct value. The read reliability is therefore much improved. Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently. In this case, the ECC function also writes/cycles the three other bytes located in the same group(c). As a consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over the four bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined in Table 13. c. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer. DocID11124 Rev 21 25/50 Instructions 6.7 M95512-W M95512-R M95512-DR M95512-DF Read Identification Page (available only in M95512-D devices) The Identification Page (128 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. Reading this page is achieved with the Read Identification Page instruction (see Table 4). The Chip Select signal (S) is first driven low, the bits of the instruction byte and address bytes are then shifted in, on Serial Data Input (D). Address bit A10 must be 0, upper address bits are Don't Care, and the data byte pointed to by the lower address bits [A6:A0] is shifted out on Serial Data Output (Q). If Chip Select (S) continues to be driven low, the internal address register is automatically incremented, and the byte of data at the new address is shifted out. The number of bytes to read in the ID page must not exceed the page boundary, otherwise unexpected data is read (e.g.: when reading the ID page from location 90d, the number of bytes should be less than or equal to 38d, as the ID page boundary is 128 bytes). The read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip Select (S) signal can occur at any time during the cycle. The first byte addressed can be any byte within any page. The instruction is not accepted, and is not executed, if a write cycle is currently in progress. Figure 15. Read Identification Page sequence S 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 C Instruction 16-bit address 15 14 13 D 3 2 1 0 MSB Data Out 1 High impedance 7 Q 6 5 4 3 2 Data Out 2 1 0 7 MSB Ai15966 26/50 DocID11124 Rev 21 M95512-W M95512-R M95512-DR M95512-DF 6.8 Instructions Write Identification Page (available only in M95512-D devices) The Identification Page (128 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. Writing this page is achieved with the Write Identification Page instruction (see Table 4). The Chip Select signal (S) is first driven low. The bits of the instruction byte, address bytes, and at least one data byte are then shifted in on Serial Data Input (D). Address bit A10 must be 0, upper address bits are Don't Care, the lower address bits [A6:A0] address bits define the byte address inside the identification page. The instruction sequence is shown in Figure 16. Figure 16. Write identification page sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 C Instruction D 24-bit address 23 22 21 Data byte 3 2 1 0 7 6 5 4 3 2 1 0 High impedance Q MS30909V1 DocID11124 Rev 21 27/50 Instructions 6.9 M95512-W M95512-R M95512-DR M95512-DF Read Lock Status (available only in M95512-D devices) The Read Lock Status instruction (see Table 4) is used to check whether the Identification Page is locked or not in Read-only mode. The Read Lock Status sequence is defined with the Chip Select (S) first driven low. The bits of the instruction byte and address bytes are then shifted in on Serial Data Input (D). Address bit A10 must be 1, all other address bits are Don't Care. The Lock bit is the LSB (least significant bit) of the byte read on Serial Data Output (Q). It is at "1" when the lock is active and at "0" when the lock is not active. If Chip Select (S) continues to be driven low, the same data byte is shifted out. The read cycle is terminated by driving Chip Select (S) high. The instruction sequence is shown in figure below. Figure 17. Read Lock Status sequence S 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 C Instruction 16-bit address 15 14 13 D 3 2 1 0 MSB Data Out 1 High impedance 7 Q 6 5 4 3 2 Data Out 2 1 0 7 MSB Ai15966 28/50 DocID11124 Rev 21 M95512-W M95512-R M95512-DR M95512-DF 6.10 Instructions Lock ID (available only in M95512-D devices) The Lock ID instruction permanently locks the Identification Page in read-only mode. Before this instruction can be accepted, a Write Enable (WREN) instruction must have been executed. The Lock ID instruction is issued by driving Chip Select (S) low, sending the instruction code, the address and a data byte on Serial Data Input (D), and driving Chip Select (S) high. In the address sent, A10 must be equal to 1, all other address bits are Don't Care. The data byte sent must be equal to the binary value xxxx xx1x, where x = Don't Care. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise, the Lock ID instruction is not executed. Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed write cycle whose duration is tW (as specified in AC characteristics in Section 9: DC and AC parameters). The instruction sequence is shown in Figure 18. The instruction is discarded, and is not executed, under the following conditions: * If a Write cycle is already in progress, * If the Block Protect bits (BP1,BP0) = (1,1), * If a rising edge on Chip Select (S) happens outside of a byte boundary. Figure 18. Lock ID sequence S 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 C Instruction 16-bit address D 15 14 13 3 2 Data byte 1 0 7 6 5 4 3 2 1 0 High impedance Q Ai15967 DocID11124 Rev 21 29/50 Power-up and delivery state M95512-W M95512-R M95512-DR M95512-DF 7 Power-up and delivery state 7.1 Power-up state After power-up, the device is in the following state: * Standby power mode, * deselected (after power-up, a falling edge is required on Chip Select (S) before any instructions can be started), * not in the Hold condition, * the Write Enable Latch (WEL) is reset to 0, * Write In Progress (WIP) is reset to 0. The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous power-down (they are non-volatile bits). 7.2 Initial delivery state The device is delivered with the memory array bits and identification page bits set to all 1s (each byte = FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0. 30/50 DocID11124 Rev 21 M95512-W M95512-R M95512-DR M95512-DF 8 Maximum rating Maximum rating Stressing the device outside the ratings listed in Table 7 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 7. Absolute maximum ratings Symbol TSTG TLEAD Parameter Min. Max. Unit Ambient operating temperature -40 130 C Storage temperature -65 150 C Lead temperature during soldering See note (1) C VO Output voltage -0.50 VCC+0.6 V VI Input voltage -0.50 6.5 V VCC Supply voltage -0.50 6.5 V IOL DC output current (Q = 0) - 5 mA IOH DC output current (Q = 1) - 5 VESD Electrostatic discharge voltage (human body model)(2) - 4000 mA (3) V 1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb-free assembly), the ST ECOPACK(R) 7191395 specification, and the European directive on Restrictions of Hazardous Substances (RoHS) 2011/65/EU. 2. Positive and negative pulses applied on different combinations of pin connections, according to AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1=100 pF, R1=1500 , R2=500 ). 3. 3000 V for devices identified by process letters KA. DocID11124 Rev 21 31/50 DC and AC parameters 9 M95512-W M95512-R M95512-DR M95512-DF DC and AC parameters This section summarizes the operating conditions and the DC/AC characteristics of the device. Table 8. Operating conditions (M95512-W, device grade 6) Symbol VCC TA Parameter Min. Max. Unit Supply voltage 2.5 5.5 V Ambient operating temperature -40 85 C Table 9. Operating conditions (M95512-R and M95512-DR, device grade 6) Symbol VCC TA Parameter Min. Max. Unit Supply voltage 1.8 5.5 V Ambient operating temperature -40 85 C Table 10. Operating conditions (M95512-DF, device grade 6) Symbol VCC TA Parameter Min. Max. Unit Supply voltage 1.7 5.5 V Ambient operating temperature -40 85 C Max. Unit Table 11. AC measurement conditions Symbol CL Parameter Min. Load capacitance 30 Input rise and fall times - pF ns Input pulse voltages 0.2 VCC to 0.8 VCC V Input and output timing reference voltages 0.3 VCC to 0.7 VCC V Figure 19. AC measurement I/O waveform Input voltage levels 0.8 VCC Input and output timing reference levels 0.7 VCC 0.3 VCC 0.2 VCC AI00825C 32/50 DocID11124 Rev 21 M95512-W M95512-R M95512-DR M95512-DF DC and AC parameters Table 12. Capacitance Test conditions(1) Min. Max. Unit VOUT = 0 V - 8 pF Input capacitance (D) VIN = 0 V - 8 pF Input capacitance (other pins) VIN = 0 V - 6 pF Symbol COUT CIN Parameter Output capacitance (Q) 1. Sampled only, not 100% tested, at TA = 25 C and a frequency of 5 MHz. Table 13. Cycling performance by groups of four bytes Symbol Ncycle Parameter(1) Write cycle endurance (2) Test conditions Min. Max. TA 25 C, VCC(min) < VCC < VCC(max) - 4,000,000 TA = 85 C, VCC(min) < VCC < VCC(max) - Unit Write cycle(3) 1,200,000 1. Cycling performance for products identified by process letters KB. 2. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3] where N is an integer. The Write cycle endurance is defined by characterization and qualification. 3. A Write cycle is executed when either a Page Write, a Byte Write, a WRSR, a WRID or an LID instruction is decoded. When using the Byte Write, the Page Write or the WRID instruction, refer also to Section 6.6.1: Cycling with Error Correction Code (ECC). Table 14. Memory cell data retention Parameter Data retention(1) Test conditions TA = 55 C Min. Unit 200 Year 1. For products identified by process letters KB. The data retention behavior is checked in production. The 200-year limit is defined from characterization and qualification results. DocID11124 Rev 21 33/50 DC and AC parameters M95512-W M95512-R M95512-DR M95512-DF Table 15. DC characteristics (previous M95512-W products, device grade 6) Symbol Parameter Test conditions in addition to those defined in Table 8 (1) Min. Max. Unit ILI Input leakage current VIN = VSS or VCC - 2 A ILO Output leakage current S = VCC, VOUT = VSS or VCC - 2 A C = 0.1 VCC/0.9 VCC at 5 MHz, VCC = 2.5 V, Q = open - 3 ICC Supply current (Read) C = 0.1 VCC/0.9 VCC at 5 MHz, VCC = 5 V, Q = open - 5 Supply current (Write) During tW, S = VCC, 2.5 V < VCC < 5.5 V - 6 mA ICC1 Supply current (Standby Power mode) S = VCC, 2.5 V <VCC < 5.5 V VIN = VSS or VCC - 5 A VIL Input low voltage -0.45 0.3 VCC V VIH Input high voltage 0.7 VCC VCC+1 V VOL Output low voltage VCC = 2.5 V and IOL = 1.5 mA or VCC = 5 V and IOL = 2 mA - 0.4 V VOH Output high voltage VCC = 2.5 V and IOH = -0.4 mA or VCC = 5 V and IOH = -2 mA 0.8 VCC - V ICC0(2) mA 1. Not for new designs (previous products identified by process letters AB operate with a clock frequency of 5 MHz max). 2. Characterized only, not tested in production. 34/50 DocID11124 Rev 21 M95512-W M95512-R M95512-DR M95512-DF DC and AC parameters Table 16. DC characteristics (M95512-W products, device grade 6) Symbol Parameter Test conditions in addition to those defined in Table 8 (1) Min. Max. Unit ILI Input leakage current VIN = VSS or VCC - 2 A ILO Output leakage current S = VCC, voltage applied on Q = VSS or VCC - 2 A ICC Supply current (Read) C = 0.1 VCC/0.9VCC at 10 MHz, VCC = 2.5 V, Q = open - 4 mA C = 0.1 VCC/0.9VCC at 16 MHz, VCC = 5 V, Q = open - 8 mA During tW, S = VCC, 2.5 V < VCC < 5.5 V - 2 mA S = VCC, VCC = 2.5 V, VIN = VSS or VCC - 2(3) A S = VCC, VCC = 5.5 V, VIN = VSS or VCC - 3(4) A ICC0(2) Supply current (Write) ICC1 Supply current (Standby Power mode) VIL Input low voltage -0.45 0.3 VCC V VIH Input high voltage 0.7 VCC VCC+1 V VOL Output low voltage VCC = 2.5 V and IOL = 1.5 mA or VCC = 5 V and IOL = 2 mA - 0.4 V VOH Output high voltage VCC = 2.5 V and IOH = -0.4 mA or VCC = 5 V and IOH = -2 mA 0.8 VCC - V 1. For devices identified by process letter KB. 2. Characterized only, not tested in production. 3. 2 A for devices from date code 301 (year 2013, W01), 5 A for previous devices. 4. 3 A for devices from date code 301 (year 2013, W01), 5 A for previous devices. DocID11124 Rev 21 35/50 DC and AC parameters M95512-W M95512-R M95512-DR M95512-DF Table 17. DC characteristics (M95512-R and M95512-DR products, device grade 6) Symbol Parameter Test conditions in addition to those defined in Table 9 (1) Min Max Unit ILI Input leakage current VIN = VSS or VCC - 2 A ILO Output leakage current S = VCC, voltage applied on Q = VSS or VCC - 2 A ICC Supply current (Read) C = 0.1 VCC/0.9 VCC at max clock frequency(2), VCC = 1.8 V, Q = open - 2.5 mA ICC0(3) Supply current (Write) During tW, S = VCC, 1.8 V < VCC < 2.5 V - 1.5 mA ICC1 Supply current (Standby Power mode) S = VCC, VCC = 1.8 V, VIN = VSS or VCC - 1(4) A VIL Input low voltage -0.45 0.3 VCC V VIH Input high voltage 0.7 VCC VCC+1 V VOL Output low voltage IOL = 0.15 mA, VCC = 1.8 V - 0.3 V VOH Output high voltage IOH = -0.1 mA, VCC = 1.8 V 0.8 VCC - V 1. If the application uses the M95512-R or M95512-DR with 2.5 V VCC < 5.5 V and -40 C < TA < +85 C, please refer to Table 16 and Table 15 instead of the above table. 2. Max clock frequency is 5 MHz (was 2 MHz for previous products identified with process letters AB). 3. Characterized only, not tested in production. 4. 1 A for devices from date code 301 (year 2013, W01), 3 A for previous devices. 36/50 DocID11124 Rev 21 M95512-W M95512-R M95512-DR M95512-DF DC and AC parameters Table 18. DC characteristics (M95512-DF products, device grade 6) Symbol Parameter Test conditions in addition to those defined in Table 10 (1) Min Max Unit ILI Input leakage current VIN = VSS or VCC - 2 A ILO Output leakage current S = VCC, voltage applied on Q = VSS or VCC - 2 A ICC Supply current (Read) C = 0.1 VCC/0.9 VCC at 5 MHz, VCC = 1.7 V, Q = open - 2.5 mA ICC0(2) Supply current (Write) During tW, S = VCC, 1.7 V < VCC < 2.5 V - 1.5 mA ICC1 Supply current (Standby Power mode) S = VCC, VCC = 1.7 V, VIN = VSS or VCC - 1(3) A VIL Input low voltage -0.45 0.3 VCC V VIH Input high voltage 0.7 VCC VCC+1 V VOL Output low voltage IOL = 0.15 mA, VCC = 1.7 V - 0.3 V VOH Output high voltage IOH = -0.1 mA, VCC = 1.7 V 0.8 VCC - V 1. If the application uses the M95512-DF device with 2.5 V VCC < 5.5 V and -40 C < TA < +85 C, please refer to Table 16 instead of the above table. 2. Characterized only, not tested in production. 3. 1 A for devices identified from date code 301 (year 2013, W01), 3 A for previous devices DocID11124 Rev 21 37/50 DC and AC parameters M95512-W M95512-R M95512-DR M95512-DF Table 19. AC characteristics (previous M95512-W products, device grade 6) Test conditions: refer to Table 8 and Table 11 (1) Symbol Alt. Min. Max. Unit fC fSCK Clock frequency D.C. 5 MHz tSLCH tCSS1 S active setup time 90 - ns tSHCH tCSS2 S not active setup time 90 - ns tSHSL tCS S deselect time 100 - ns tCHSH tCSH S active hold time 90 - ns S not active hold time 90 - ns tCHSL Parameter tCH (2) tCLH Clock high time 90 - ns tCL(2) tCLL Clock low time 90 - ns tCLCH (3) tRC Clock rise time - 1 s tCHCL (3) tFC Clock fall time - 1 s tDVCH tDSU Data in setup time 20 - ns tCHDX tDH Data in hold time 30 - ns tHHCH Clock low hold time after HOLD not active 70 - ns tHLCH Clock low hold time after HOLD active 40 - ns tCLHL Clock low setup time before HOLD active 0 - ns tCLHH Clock low setup time before HOLD not active 0 - ns Output disable time - 100 ns Clock low to output valid - 60 ns tSHQZ(3) tDIS tCLQV tV tCLQX tHO Output hold time 0 - ns tQLQH (3) tRO Output rise time - 50 ns tQHQL (3) tFO Output fall time - 50 ns tHHQV tLZ HOLD high to output valid - 50 ns tHLQZ (3) tHZ HOLD low to output High-Z - 100 ns tW tWC Write time - 5 ms 1. Not for new designs (previous products are identified by process letters AB). 2. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max). 3. Characterized only, not tested in production. 38/50 DocID11124 Rev 21 M95512-W M95512-R M95512-DR M95512-DF DC and AC parameters Table 20. AC characteristics (M95512-W products, device grade 6) Test conditions: refer to Table 8 and Table 11 (1) Min. Symbol Alt. Max. Min. Max. Parameter Unit 2.5 V to 5.5 V 4.5 V to 5.5 V D.C. 10 D.C. 16 MHz fC fSCK Clock frequency tSLCH tCSS1 S active setup time 30 - 20 - ns tSHCH tCSS2 S not active setup time 30 - 20 - ns tSHSL tCS S deselect time 40 - 25 - ns tCHSH tCSH S active hold time 30 - 20 - ns S not active hold time 30 - 20 - ns tCHSL tCH (2) tCLH Clock high time 45 - 25 - ns tCL (2) tCLL Clock low time 45 - 25 - ns (3) tRC Clock rise time - 2 - 2 s tCHCL(3) tFC Clock fall time - 2 - 2 s tDVCH tDSU Data in setup time 10 - 10 - ns tCHDX tDH Data in hold time 10 - 10 - ns tHHCH Clock low hold time after HOLD not active 30 - 25 - ns tHLCH Clock low hold time after HOLD active 30 - 20 - ns tCLHL Clock low setup time before HOLD active 0 - 0 - ns tCLHH Clock low setup time before HOLD not active 0 - 0 - ns Output disable time - 40 - 25 ns Clock low to output valid - 40 - 25 ns tCLCH tSHQZ(3) tDIS tCLQV tV tCLQX tHO Output hold time 0 - 0 - ns tQLQH (3) tRO Output rise time - 40 - 10 ns tQHQL (3) tFO Output fall time - 40 - 10 ns tHHQV tLZ HOLD high to output valid - 40 - 25 ns tHLQZ(3) tHZ HOLD low to output High-Z - 40 - 25 ns tW tWC Write time - 5 - 5 ms 1. For devices identified by process letter KB. 2. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max). 3. Characterized only, not tested in production. DocID11124 Rev 21 39/50 DC and AC parameters M95512-W M95512-R M95512-DR M95512-DF Table 21. AC characteristics (M95512-R and M95512-DF, device grade 6) Test conditions: refer to Table 9 or Table 10 and Table 11 (1)(2) Min. Min. Max. Symbol Alt. fC fSCK Clock frequency D.C. 2 D.C. 5 MHz tSLCH tCSS1 S active setup time 200 - 60 - ns tSHCH tCSS2 S not active setup time 200 - 60 - ns tSHSL tCS S deselect time 200 - 90 - ns tCHSH tCSH S active hold time 200 - 60 - ns S not active hold time 200 - 60 - ns tCHSL Parameter Max. Previous(3) products Current products Unit tCH(4) tCLH Clock high time 200 - 80 - ns (4) tCL tCLL Clock low time 200 - 80 - ns (5) tRC Clock rise time - 1 - 2 s tCHCL(5) tFC Clock fall time - 1 - 2 s tDVCH tDSU Data in setup time 40 - 20 - ns tCHDX tDH Data in hold time 50 - 20 - ns tHHCH Clock low hold time after HOLD not active 140 - 60 - ns tHLCH Clock low hold time after HOLD active 90 - 60 - ns tCLHL Clock low setup time before HOLD active 0 - 0 - ns tCLHH Clock low setup time before HOLD not active 0 - 0 - ns Output disable time - 250 - 80 ns Clock low to output valid - 150 - 80 ns tCLCH tSHQZ(5) tDIS tCLQV tV tCLQX tHO Output hold time 0 - 0 - ns tQLQH (5) tRO Output rise time - 100 - 80 ns tQHQL (5) tFO Output fall time - 100 - 80 ns tHHQV tLZ HOLD high to output valid - 100 - 80 ns tHLQZ(5) tHZ HOLD low to output High-Z - 250 - 80 ns tW tWC Write time - 5 - 5 ms 1. The test flow guarantees the AC parameter values defined in this table (when VCC = 1.8 V or VCC = 1.7 V) and the parameter values defined in AC characteristics tables for M95512-W (when VCC > 2.5 V). 2. If the application uses the device at 2.5 V VCC 5.5 V and -40 C TA +85 C, please refer to Table 20 instead of the above table. 3. Not for new designs (previous products are identified by process letters AB) 4. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max) 5. Characterized only, not tested in production. 40/50 DocID11124 Rev 21 M95512-W M95512-R M95512-DR M95512-DF DC and AC parameters Figure 20. Serial input timing tSHSL S tCHSL tCH tSLCH tCHSH tSHCH C tDVCH tCHCL tCL tCLCH tCHDX D Q LSB IN MSB IN High impedance AI01447d Figure 21. Hold timing S tHLCH tCLHL tHHCH C tCLHH tHLQZ tHHQV Q HOLD AI01448c Figure 22. Serial output timing S tCH tSHSL C tCLQV tCLCH tCHCL tCL tSHQZ tCLQX Q tQLQH tQHQL ADDR D LSB IN AI01449f DocID11124 Rev 21 41/50 Package mechanical data 10 M95512-W M95512-R M95512-DR M95512-DF Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 23. SO8N - 8-lead plastic small outline, 150 mils body width, package outline h x 45 A2 A c ccc b e 0.25 mm GAUGE PLANE D k 8 E1 E 1 L A1 L1 SO-A 1. Drawing is not to scale. Table 22. SO8N - 8-lead plastic small outline, 150 mils body width, mechanical data inches(1) millimeters Symbol Typ Min Max Typ Min Max A - - 1.750 - - 0.0689 A1 - 0.100 0.250 - 0.0039 0.0098 A2 - 1.250 - - 0.0492 - b - 0.280 0.480 - 0.0110 0.0189 c - 0.170 0.230 - 0.0067 0.0091 ccc - - 0.100 - - 0.0039 D 4.900 4.800 5.000 0.1929 0.1890 0.1969 E 6.000 5.800 6.200 0.2362 0.2283 0.2441 E1 3.900 3.800 4.000 0.1535 0.1496 0.1575 e 1.270 - - 0.0500 - - h - 0.250 0.500 - 0.0098 0.0197 k - 0 8 - 0 8 L - 0.400 1.270 - 0.0157 0.0500 L1 1.040 - - 0.0409 - - 1. Values in inches are converted from mm and rounded to four decimal digits. 42/50 DocID11124 Rev 21 M95512-W M95512-R M95512-DR M95512-DF Package mechanical data Figure 24. TSSOP8 - 8-lead thin shrink small outline, package outline D 8 5 c E1 1 E 4 A1 A L A2 L1 CP b e TSSOP8AM 1. Drawing is not to scale. Table 23. TSSOP8 - 8-lead thin shrink small outline, package mechanical data inches(1) millimeters Symbol Typ Min Max Typ Min Max A - - 1.200 - - 0.0472 A1 - 0.050 0.150 - 0.0020 0.0059 A2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b - 0.190 0.300 - 0.0075 0.0118 c - 0.090 0.200 - 0.0035 0.0079 CP - - 0.100 - - 0.0039 D 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 - - 0.0256 - - E 6.400 6.200 6.600 0.2520 0.2441 0.2598 E1 4.400 4.300 4.500 0.1732 0.1693 0.1772 L 0.600 0.450 0.750 0.0236 0.0177 0.0295 L1 1.000 - - 0.0394 - - - 0 8 - 0 8 N 8 8 1. Values in inches are converted from mm and rounded to four decimal digits. DocID11124 Rev 21 43/50 Package mechanical data M95512-W M95512-R M95512-DR M95512-DF Figure 25. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package outline e D b L1 L3 Pin 1 E E2 K L A D2 eee A1 ZW_MEeV2 1. Drawing is not to scale. 2. The central pad (area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be connected to any other voltage or signal line on the PCB, for example during the soldering process. Table 24. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data inches(1) millimeters Symbol Typ Min Max Typ Min Max A 0.550 0.450 0.600 0.0217 0.0177 0.0236 A1 0.020 0.000 0.050 0.0008 0.0000 0.0020 b 0.250 0.200 0.300 0.0098 0.0079 0.0118 D 2.000 1.900 2.100 0.0787 0.0748 0.0827 D2 (rev MC) - 1.200 1.600 - 0.0472 0.0630 E 3.000 2.900 3.100 0.1181 0.1142 0.1220 E2 (rev MC) - 1.200 1.600 - 0.0472 0.0630 e 0.500 - - 0.0197 - - K (rev MC) - 0.300 - - 0.0118 - L - 0.300 0.500 - 0.0118 0.0197 L1 - - 0.150 - - 0.0059 L3 - 0.300 - - 0.0118 - eee(2) - 0.080 - - 0.0031 - 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring. 44/50 DocID11124 Rev 21 M95512-W M95512-R M95512-DR M95512-DF Package mechanical data Figure 26. M95512-DFCS6TP/K - WLCSP 8-bump wafer-level chip scale package outline bbb Z D e1 e3 Y X Reference Reference e2 Detail A E e G aaa A A2 (4X) Wafer back side F Side view Bumps side Bump A1 eee Z b Occc Oddd Z Seating plane M Z XY M Z Detail A Rotated 90 1Cf_ME_V1 1. Drawing is not to scale. DocID11124 Rev 21 45/50 Package mechanical data M95512-W M95512-R M95512-DR M95512-DF Table 25. M95512-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package mechanical data inches(1) millimeters Symbol Typ Min Max Typ Min Max A 0.540 0.500 0.580 0.0213 0.0197 0.0228 A1 0.190 - - 0.0075 - - A2 0.350 - - 0.0138 - - b 0.270 - - 0.0106 - - D 1.271 - 1.291 0.0500 - 0.0508 E 1.937 - 1.957 0.0763 - 0.0770 e 1.000 - - 0.0394 - - e1 0.866 - - 0.0341 - - e2 0.500 - - 0.0197 - - e3 0.433 - - 0.0170 - - F 0.202 - - 0.0080 - - G 0.469 - - 0.0185 - - N 8 aaa 0.110 - - 0.0043 - - bbb 0.110 - - 0.0043 - - ccc 0.110 - - 0.0043 - - ddd 0.060 - - 0.0024 - - eee 0.060 - - 0.0024 - - 1. Values in inches are converted from mm and rounded to four decimal digits. 46/50 DocID11124 Rev 21 M95512-W M95512-R M95512-DR M95512-DF 11 Part numbering Part numbering Table 26. Ordering information scheme Example: Device type M95 = SPI serial access EEPROM M95512 W MN 6 T P /K Device function 512 = 512 Kbit (65536 x 8) 512-D = 512 Kbit plus Identification page Operating voltage W = VCC = 2.5 to 5.5 V R = VCC = 1.8 to 5.5 V F = VCC = 1.7 to 5.5 V Package(1) MN = SO8 (150 mil width) DW = TSSOP8 (169 mil width) MC = UFDFPN8 (MLP8) CS = WLCSP Device grade 6 = Industrial temperature range, -40 to 85 C Device tested with standard test flow Option blank = Standard packing T = Tape and reel packing Plating technology G or P = RoHS compliant and halogen-free (ECOPACK(R)) Process(2) /K= Manufacturing technology code 1. All packages are ECOPACK2(R) (RoHS compliant and halogen-free). 2. The process letters apply to WLCSP devices only. The process letters appear on the device package (marking) and on the shipment box. Please contact your nearest ST Sales Office for further information. DocID11124 Rev 21 47/50 Revision history 12 M95512-W M95512-R M95512-DR M95512-DF Revision history Table 27. Document revision history Date Revision Changes 01-Apr-2011 14 Added: - Table 14: Capacitance. - Note (1) under Table 23: DC characteristics (current and new M95080-R and M95080-DR products) - Notes (1) and (2) in Section 4.3: Hold condition - Note (1) under Table 36: AC characteristics (M95080-R, M95080-DR device grade 6) Updated: - Section 3: Connecting to the SPI bus - Section 7: ECC (error correction code) and write cycling Moved from Section 4.5: Data protection and protocol control to Section 4.4: Status register: - Table 2: Write-protected block size Deleted: - Table 25: Available M95512 products (package, voltage range, temperature grade) - Table 26: Available M95512-DR products (package, voltage range, temperature grade) 19-Jul-2011 15 Renamed Figure 2. Added UFDFPN8 MC package. Updated disclaimer. 16 Datasheet split into: - M95512-W, M95512-R, M95512-DF (this datasheet) for standard products (range 6), - M95512-125 datasheet for automotive products (range 3). 17 Added reference M95512-DR. Deleted: - UFDFPN8 (MLP8): MB version package Updated: - Cycling and data retention limits (KB devices): 4 million cycles and 200year data retention - Section 1: Description - Figure 3: reference dot moved close to VCC ball - Figure 26: M95512-DFCS6TP/K - WLCSP 8-bump wafer-level chip scale package outline - Table 25: M95512-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package mechanical data 28-Mar-2012 28-Jun-2012 48/50 DocID11124 Rev 21 M95512-W M95512-R M95512-DR M95512-DF Revision history Table 27. Document revision history (continued) Date 18-Sep-2012 24-Sep-2012 06-Dec-2012 03-Jun-2013 Revision Changes 18 Fixed some errors in Figure 3: WLCSP connections for M95512DFCS6TP/K (top view, marking side, with bumps on the underside). Restored missing table: Table 10: Operating conditions (M95512-DF, device grade 6). Replaced various suffixes in UFDFPN8 package name (cover page) by (MLP8) so that this package be consistently named UFDFPN8 (MLP8) as a block, all over the document. Changed "Test conditions" description (first line in table) in the following tables: Table 15, Table 16, Table 17, Table 18, Table 19, Table 20, Table 21, and footnote 1. of Table 17. 19 (Restored Revision History) Added Note 1 in Table 16: DC characteristics (M95512-W products, device grade 6). Added Note 1 in Table 20: AC characteristics (M95512-W products, device grade 6). 20 Updated: - Section 7.2: Initial delivery state - ICC1 values in Table 16, Table 17 and Table 18 - Note 1 in Table 15: DC characteristics (previous M95512-W products, device grade 6) 21 Replaced "ball" by "bump" in the entire document. Updated: - Package figure on cover page - Features: high-speed clock frequency changed from 10 to 16 MHz. - Note (1) under Table 7: Absolute maximum ratings - ICC row in Table 16: DC characteristics (M95512-W products, device grade 6) - Table 20: AC characteristics (M95512-W products, device grade 6) DocID11124 Rev 21 49/50 M95512-W M95512-R M95512-DR M95512-DF Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2013 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 50/50 DocID11124 Rev 21