AD10242
FEATURES
2 Matched ADCs with Input Signal Conditioning
Selectable Bipolar Input Voltage Range
(ⴞ0.5 V, ⴞ1.0 V, ⴞ2.0 V)
Full MIL-STD-883B Compliant
80 dB Spurious-Free Dynamic Range
Trimmed Channel-Channel Matching
APPLICATIONS
Radar Processing
Communications Receivers
FLIR Processing
Secure Communications
Any I/Q Signal Processing Application
The AD10242 operates with ±5.0 V for the analog signal condi-
tioning with a separate 5.0 V supply for the analog-to-digital
conversion. Each channel is completely independent, allowing
operation with independent encode or analog inputs. The AD10242
also offers the user a choice of analog input signal ranges to mini-
mize additional signal conditioning required for multiple functions
within a single system. The heart of the AD10242 is the AD9042,
which is designed specifically for applications requiring wide
dynamic range.
The AD10242 is manufactured on Analog Devices’
MIL-PRF-38534 MCM line and is completely qualified. Units
are packaged in a custom, cofired, ceramic 68-lead gull wing
package and specified for operation from –55°C to +125°C.
Contact the factory for additional custom options including those
that allow the user to ac couple the ADC directly, bypassing the
front end amplifier section. Also see the AD9042 data sheet for
additional details on ADC performance.
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate of 40 MSPS.
2. Dynamic performance specified over entire Nyquist band;
spurious signals @ 80 dBc for –1 dBFS input signals.
3. Low power dissipation: <2 W off ±5.0 V supplies.
4. User defined input amplitude.
5. Packaged in 68-lead ceramic leaded chip carrier.
GENERAL DESCRIPTION
The AD10242 is a complete dual signal chain solution including
on-board amplifiers, references, ADCs, and output buffering
providing unsurpassed total system performance. Each channel is
laser trimmed for gain and offset matching and provides channel-
to-channel crosstalk performance better than 80 dB. The AD10242
utilizes two each of the AD9632, OP279, and AD9042 in a cus-
tom MCM to gain space, performance, and cost advantages over
solutions previously available.
FUNCTIONAL BLOCK DIAGRAM
OP279
OP279 AD9042
AD9632
9
12
TIMING
A
IN
3A
IN
2A
IN
1
D11B (MSB)
D10B
D9B
D8B
D7B
D0B
(LSB)
D1B D2B D3B D4B D5B D6B
D9A D10A D11A
(MSB)
(LSB) D0A
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
ENC
AD10242
5
V
REF
OUTPUT BUFFERING
UNEG
UCOM
UPOS
OP279
OP279 AD9042
AD9632
7
12
TIMING
A
IN
2A
IN
1
V
REF
OUTPUT BUFFERING
A
IN
3
UPOSUNEG UCOM
ENC
ENC
ENC
Dual, 12-Bit, 40 MSPS MCM A/D Converter
with Analog Input Signal Conditioning
a
REV. C
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
REV. C
–2–
AD10242–SPECIFICATIONS
Electrical Characteristics
(AVCC = +5 V; AVEE = –5.0 V; DVCC = +5 V; applies to each ADC, unless otherwise noted.)
Test Mil AD10242BZ/TZ
Parameter Temp Level Subgroup Min Typ Max Unit
RESOLUTION 12 Bits
DC ACCURACY
No Missing Codes Full VI 1, 2, 3 Guaranteed
Offset Error 25°CI 1 –0.5 ±0.05 +0.5 % FS
Full VI 2, 3 –2.0 ±1.0 +2.0 % FS
Offset Error Channel Match Full V ±0.1 %
Gain Error
1
25°CI 1 –1.0 ±0.5 +1.0 % FS
Full VI 2, 3 –1.5 ±0.8 +1.5 % FS
Gain Error Channel Match Full V ±0.1 %
ANALOG INPUT (A
IN
)
Input Voltage Range
A
IN
1Full I ±0.5 V
A
IN
2Full I ±1.0 V
A
IN
3Full I ±2V
Input Resistance
A
IN
1Full IV 12 99 100 101 Ω
A
IN
2Full IV 12 198 200 202 Ω
A
IN
3Full IV 12 396 400 404 Ω
Input Capacitance
2
25°CIV 12 0 4.0 7.0 pF
Analog Input Bandwidth
3
Full V 60 MHz
ENCODE INPUT
4, 5
Logic Compatibility TTL/CMOS
Logic “1” Voltage Full I 1, 2, 3 2.0 5.0 V
Logic “0” Voltage Full I 1, 2, 3 0 0.8 V
Logic “1” Current (V
INH
= 5 V) Full I 1, 2, 3 625 800 µA
Logic “0” Current (V
INL
= 0 V) Full I 1, 2, 3 –400 –300 µA
Input Capacitance 25°CV 12 7.0 pF
SWITCHING PERFORMANCE
Maximum Conversion Rate
6
Full VI 4, 5, 6 40 50 MSPS
Minimum Conversion Rate
6
Full V 12 5 MSPS
Aperture Delay (t
A
)25°CV 1.0 ns
Aperture Delay Matching 25°CV ±2.0 ns
Aperture Uncertainty (Jitter) 25°CV 1 ps rms
ENCODE Pulsewidth High 25°CIV 12 12 10 ns
ENCODE Pulsewidth Low 25°CIV 12 10 41 ns
Output Delay (t
OD
)Full IV 12 10 12 14 ns
SNR
7
Analog Input @ 1.2 MHz 25°CV 68 dB
@ 4.85 MHz 25°CI 4 63 66 dB
Full II 5, 6 62 66 dB
@ 9.9 MHz 25°CI 4 63 65 dB
Full II 5, 6 62 65 dB
@ 19.5 MHz 25°CI 4 60 63 dB
Full II 5, 6 59 62 dB
SINAD
8
Analog Input @ 1.2 MHz 25°CV 67 dB
@ 4.85 MHz 25°CI 4 62 65 dB
Full II 5, 6 61 64 dB
@ 9.9 MHz 25°CI 4 60 64 dB
Full II 5, 6 60 63 dB
@ 19.5 MHz 25°CI 4 58 61 dB
Full II 5, 6 58 60 dB
Test Mil AD10242BZ/TZ
Parameter Temp Level Subgroup Min Typ Max Unit
SPURIOUS-FREE DYNAMIC RANGE
9
Analog Input @ 1.2 MHz 25°CI 81 dBFS
@ 4.85 MHz 25°CI 47080 dBFS
Full II 5, 6 70 79 dBFS
@ 9.9 MHz 25°CI 46370 dBFS
Full II 5, 6 63 69 dBFS
@ 19.5 MHz 25°CI 46067 dBFS
Full II 5, 6 60 66 dBFS
TWO-TONE IMD REJECTION
10
F1, F2 @ –7 dBFS Full II 4, 5, 6 70 76 dBc
CHANNEL-TO-CHANNEL ISOLATION
11
25°CIV12 75 80 dB
TRANSIENT RESPONSE 25°CV 10 ns
LINEARITY
Differential Nonlinearity 25°CIV12 0.3 1.0 LSB
(Encode = 20 MHz) Full IV 12 0.5 1.25 LSB
Integral Nonlinearity 25°CV 0.3
LSB
(
Encode
= 20 MHz) Full V 0.5 LSB
OVERVOLTAGE RECOVERY TIME
12
V
IN
= 2.0 × FS Full IV 12 50 100 ns
V
IN
= 4.0 × FS
Full IV 12 75 200 ns
DIGITAL OUTPUTS
Logic Compatibility CMOS
Logic “1” Voltage
13
Full I 1, 2, 3 3.5 4.2 V
Logic “0” Voltage
14
Full I 1, 2, 3 0.45 0.65 V
Output Coding Twos Complement
POWER SUPPLY
AV
CC
Supply Voltage Full VI 5.0 V
I (AV
CC
) Current Full V 260 mA
AV
EE
Supply Voltage Full VI –5.0 V
I (AV
EE
) Current Full V 55 mA
DV
CC
Supply Voltage Full VI 5.0 V
I (DV
CC
) Current Full V 25 mA
I
CC
(Total) Supply Current Full I 1, 2, 3 350 400 mA
Power Dissipation (Total) Full I 1, 2, 3 1.75 2.0 W
Power Supply Rejection Ratio (PSRR) Full I 7, 8 0.01 0.02 % FSR/% V
S
Pass-Band Ripple to 10 MHz Full IV 12 0.2 dB
NOTES
1
Gain tests are performed on A
IN
3 over specified input voltage range.
2
Input capacitance specifications combine AD9632 die capacitance and ceramic package capacitance.
3
Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.
4
ENCODE driven by single-ended source; ENCODE bypassed to ground through 0.01 µF capacitor.
5
ENCODE may also be driven differentially in conjunction with ENCODE; see Encoding the AD10242 section for details.
6
Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%.
7
Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 40.0 MSPS.
8
Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 40.0 MSPS.
9
Analog Input signal equals –1 dBFS; SFDR is the ratio of converter full scale to worst spur.
10
Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. f1 = 10.0 MHz
± 100 kHz, 50 kHz ≤ f1 – f2 ≤ 300 kHz.
11
Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel (A
IN
1).
12
Input driven to 2× and 4× A
IN
1 range for >4 clock cycles. Output recovers in band in specified time with Encode = 40 MSPS. No foldover guaranteed.
13
Outputs are sourcing 10 µA.
14
Outputs are sinking 10 µA.
All specifications guaranteed within 100 ms of initial power-up regardless of sequencing.
Specifications subject to change without notice.
AD10242
–3–
REV. C
AD10242
–4– REV. C
ABSOLUTE MAXIMUM RATINGS
1
Parameter Min Max Unit
ELECTRICAL
V
CC
Voltage 0 7 V
V
EE
Voltage –7 0 V
Analog Input Voltage V
EE
V
CC
V
Analog Input Current –10 +10 mA
Digital Input Voltage (ENCODE) 0 V
CC
V
ENCODE, ENCODE Differential Voltage 4 V
Digital Output Current –40 +40 mA
ENVIRONMENTAL
2
Operating Temperature (Case) –55 +125 °C
Maximum Junction Temperature 175 °C
Lead Temperature (Soldering, 10 sec) 300 °C
Storage Temperature Range (Ambient) –65 +150 °C
NOTES
1
Absolute maximum ratings are limiting values to be applied individually, and beyond
which the serviceability of the circuit may be impaired. Functional operability is not
necessarily implied. Exposure to absolute maximum rating conditions for an
extended period of time may affect device reliability.
2
Typical thermal impedances for “Z” package: θ
JC
= 11°C/W; θ
JA
= 30°C/W.
Table I. Output Coding
MSB LSB Base 10 Input
0111111111111 2047 +FS
0000000000001 +1
0000000000000 0 0.0 V
1111111111111 –1, 4095
1000000000000 –2047, 2048 –FS
EXPLANATION OF TEST LEVELS
Test Level
I–100% Production Tested.
II – 100% production tested at 25°C, and sample tested at
specified temperatures. AC testing done on sample basis.
III – Sample Tested Only.
IV – Parameter is guaranteed by design and characterization
testing.
V–Parameter is a typical value only.
VI – All devices are 100% production tested at 25°C; sample
tested at temperature extremes.
ORDERING GUIDE
M
odel Temperature Range Package Description Package Option
AD10242BZ –40°C to +85°C (Case) 68-Lead Ceramic Leaded Chip Carrier Z-68A
AD10242TZ –55°C to +125°C (Case) 68-Lead Ceramic Leaded Chip Carrier Z-68A
AD10242TZ/883B –55°C to +125°C (Case) 68-Lead Ceramic Leaded Chip Carrier Z-68A
5962-9581501HXA –55°C to +125°C (Case) 68-Lead Ceramic Leaded Chip Carrier Z-68A
AD10242/PCB 25°CEvaluation Board with AD10242BZ
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD10242 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
AD10242
–5–
REV. C
10
11
12
13
14
15
16
17
18
19
20
22
23
24
25
26
21
27 4328 29 30 31 32 33 34 35 36 37 38 39 40 41 42
9618765 676665 64 63 62432168
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
NC = NO CONNECT
AD10242
GNDA
GNDA
UPOSA
AVEE
AVCC
NC
NC
(LSB) D0A
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
GNDA
GNDA
ENCODEA
ENCODEA
DVCC
D9A
D10A
(MSB) D11A
NC
NC
(LSB) D0B
D1B
D2B
D3B
D4B
D5B
D6B
GNDB
GNDB
GNDB
GNDB
UPOSB
UNEGB
UCOMB
GNDB
GNDB
ENCODEB
ENCODEB
DVCC
D11B (MSB)
D10B
D9B
D8B
D7B
GNDB
GNDA
AINA3
AINA2
AINA1
GNDA
UCOMA
UNEGA
GNDA
SHIELD
GNDB
AVEE
AVCC
GNDB
AINB3
AINB2
AINB1
GNDB
PIN CONFIGURATION
68-Lead Ceramic Leaded Chip Carrier
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Function
1SHIELD Internal Ground Shield between Channels.
2, 5, 9–11, 26–27 GNDA A Channel Ground. A and B grounds should be connected as close to the device as possible.
3UNEGA Unipolar Negative.
4UCOMA Unipolar Common.
6A
IN
A1 Analog Input for A Side ADC (Nominally ±0.5 V).
7A
IN
A2 Analog Input for A Side ADC (Nominally ±1.0 V).
8A
IN
A3 Analog Input for A Side ADC (Nominally ±2.0 V).
12 UPOSA Unipolar Positive.
13 AV
EE
Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V).
14 AV
CC
Analog Positive Supply Voltage (Nominally 5.0 V).
15, 16, 34, 35 NC No Connect.
17–25, 31–33 D0A–D11A Digital Outputs for ADC A. (D0 LSB.)
28 ENCODEA ENCODE is the complement of ENCODE.
29 ENCODEA Data conversion is initiated on the rising edge of the ENCODE input.
30, 50 DV
CC
Digital Positive Supply Voltage (Nominally 5.0 V).
36–42, 45–49 D0B–D11B Digital Outputs for ADC B. (D0 LSB.)
43–44, 53–54, GNDB B Channel Ground. A and B grounds should be connected as close to the device
58–61, 65, 68 as possible.
51 ENCODEB Data conversion is initiated on the rising edge of the ENCODE input.
52 ENCODEB ENCODE is the complement of ENCODE.
55 UCOMB Unipolar Common.
56 UNEGB Unipolar Negative.
57 UPOSB Unipolar Positive.
62 A
IN
B1 Analog Input for B Side ADC (Nominally ±0.5 V).
63 A
IN
B2 Analog Input for B Side ADC (Nominally ±1.0 V).
64 A
IN
B3 Analog Input for B Side ADC (Nominally ±2.0 V).
66 AV
CC
Analog Positive Supply Voltage (Nominally 5.0 V).
67 AV
EE
Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V).
AD10242
–6– REV. C
Overvoltage Recovery Time
The amount of time required for the converter to recover to
0.02% accuracy after an analog input signal of the specified
percentage of full scale is reduced to midscale.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in power
supply voltage.
Signal-to-Noise and Distortion (SINAD)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics but excluding dc.
Signal-to-Noise Ratio (SNR, without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic. SFDR may be reported in
dBc (i.e., degrades as signal levels are lowered) or in dBFS
(always related back to converter full scale).
Transient Response
The time required for the converter to achieve 0.02% accu-
racy when a one-half full-scale step function is applied to the
analog input.
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value of
the worst third order intermodulation product; reported in dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value of
the peak spurious component. The peak spurious component
may or may not be an IMD product. Two-tone SFDR may be
reported in dBc (i.e., degrades as signal levels are lowered) or
in dBFS (always related back to converter full scale).
DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in Logic “1” state to achieve rated
performance; pulsewidth low is the minimum time that the
ENCODE pulse should be left in low state. At a given clock
rate, these specifications define an acceptable
encode
duty cycle.
Harmonic Distortion
The ratio of the rms signal amplitude to the rms value of the
worst harmonic component.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line” deter-
mined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between the 50% point of the rising edge of the ENCODE
command and the time when all output data bits are within valid
logic levels.
AD10242
–7–
REV. C
ENC D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1/2
AD10242
SHOWN
TTL CLOCK
f
10MHz
ALL 5V SUPPLY PINS BYPASSED
TO GND WITH A 0.1␮F CAPACITOR
A
IN3
A
IN2
A
IN1
ENC
Figure 2. Equivalent Burn-In Circuit
A
IN
ENCODE
N
N – 2
N + 2 N + 3 N + 4 N + 5
tA
= 1.0ns TYP
tOD
= 12ns TYP
N + 1
N – 1 N N + 1 N + 2
DIGITAL
OUTPUTS
Figure 1. Timing Diagram
EQUIVALENT CIRCUITS
AIN3
R4
200⍀
AIN2
AIN1
TO AD9632
R3
100⍀
R2
21⍀
R1
79⍀
Figure 3. Analog Input Stage
TIMING
CIRCUITS
ENCODE
ENCODE
AVCC
AVCC
R1
17k⍀
R2
8k⍀
R2
8k⍀
R1
17k⍀
AVCC
Figure 4. Encode Inputs
DVCC
VREF
DVCC
CURRENT
MIRROR
CURRENT
MIRROR
D0–D11
Figure 5. Digital Output Stage
–8– REV. C
AD10242–Typical Performance Characteristics
FREQUENCY – MHz
0
POWER RELATIVE TO FULL SCALE – dB
–60
–100
02024681012141618
–10
–50
–70
–90
–30
–40
–80
–20
ENCODE = 40MSPS
A
IN
= 4.85MHz
A
IN
= –1dBFS
SNR = 66.4dB
SFDR = 72.8dBc
TPC 1. Single Tone @ 4.85 MHz
FREQUENCY – MHz
0
–60
–100
02024681012141618
–10
–50
–70
–90
–30
–40
–80
–20
ENCODE = 40MSPS
AIN = 9.9MHz
AIN = –1dBFS
SNR = 66.0dB
SFDR = 65.7dBc
POWER RELATIVE TO FULL SCALE – dB
TPC 2. Single Tone @ 9.9 MHz
FREQUENCY – MHz
0
POWER RELATIVE TO FULL SCALE – dB
–60
–100
02024681012141618
–10
–50
–70
–90
–30
–40
–80
–20
ENCODE = 40MSPS
A
IN
= 19.5MHz
A
IN
= –1dBFS
SNR = 64.3dB
SFDR = 63.3dBc
TPC 3. Single Tone @ 19.5 MHz
FREQUENCY – MHz
POWER RELATIVE TO FULL SCALE – dB
0
–60
–100
02024681012141618
–10
–50
–70
–90
–30
–40
–80
–20
ENCODE = 40MSPS
A
IN
1 = 9.8MHz
A
IN
1 = –7dBFS
A
IN
2 = 10.1MHz
A
IN
2 = –7dBFS
SFDR = 76.0dBc
TPC 4. Two-Tone FFT @ 9.8 MHz/10.1 MHz
FREQUENCY – MHz
POWER RELATIVE TO FULL SCALE – dB
0
–60
–100 02024681012141618
–10
–50
–70
–90
–30
–40
–80
–20
ENCODE = 40MSPS
A
IN
1 = 19.5MHz
A
IN
1 = –7dBFS
A
IN
2 = 19.7MHz
A
IN
2 = –7dBFS
SFDR = 70.6dBc
TPC 5. Two-Tone FFT @ 19.5 MHz/19.7 MHz
ANALOG INPUT FREQUENCY – MHz
66
58
520
10
76
68
64
60
72
70
62
74
ENCODE = 40MSPS
A
IN
= –1dBFS
T = +125 C
T = +25 C
T = –55 C
WORST-CASE HARMONIC – dB
TPC 6. Harmonics vs. A
IN
AD10242
–9–
REV. C
ANALOG INPUT FREQUENCY – MHz
64.0
61.5
520
10
67.0
64.5
63.0
66.0
65.0
62.0
ENCODE = 40MSPS
A
IN
= –1dBFS
T = +125 C
T = +25 C
T = –55 C
62.5
63.5
65.5
SNR – dB
66.5
TPC 7. SNR vs. A
IN
SAMPLE RATE – MSPS
70
58
55010
66
62
AIN = 9.9MHz
AIN = –1dBFS
SFDR
64
68
60
SNR, WORST SPUR – dB, dBc
15 20 25 30 35 40 45
SNR
TPC 8. SNR and Harmonics vs. Encode Rate
TEMPERATURE – C
–2.0
–55 125
GAIN
25
OFFSET
45 65 85 1055–15–35
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
ERROR – % FS
TPC 9. Offset and Gain Error vs. Temperature
ANALOG INPUT FREQUENCY – MHz
–10
10
IN A1
25 30 35 4020
15
–20
–30
–40
–50
–60
–70
–80
–90
0
ENCODE = 40MSPS
AIN = –1dBFS
ISOLATION – dB
IN B1
IN B3 IN A3
TPC 10. Isolation vs. Frequency
ANALOG INPUT POWER LEVEL – dBFS
60
0
–70 –60
40
20
ENCODE = 40MSPS
AIN = 9.98MHz
SFDR (dBFS)
30
50
10
–50 –40 –30 –20 –10 0
70
80
90
SFDR (dBc)
SFDR = 75dB
WORST-CASE SPURIOUS – dBc, dBFS
TPC 11. Single Tone SFDR (A
IN
@ 9.98) vs. Power Level
ANALOG INPUT POWER LEVEL – dBFS
60
0
–70 –60
40
20
ENCODE = 40MSPS
AIN = 19.9MHz
SFDR (dBFS)
30
50
10
–50 –40 –30 –20 –10 0
70
80
90
SFDR (dBc)
SFDR = 75dB
100
WORST-CASE SPURIOUS – dBc, dBFS
TPC 12. Single Tone SFDR (A
IN
@ 19.9) vs. Power Level
AD10242
–10– REV. C
THEORY OF OPERATION
Refer to the functional block diagram. The AD10242 employs
three monolithic ADI components per channel (AD9632, OP279,
and AD9042), along with multiple passive resistor networks
and decoupling capacitors to fully integrate a complete 12-bit
analog-to-digital converter.
The input signal is first passed through a precision laser trimmed
resistor divider, allowing the user to externally select operation
with a full-scale signal of ±0.5 V, ±1.0 V, or ±2.0 V by choosing
the proper input terminal for the application. The result of
the resistor divider is to apply a full-scale input of approximately
0.4 V to the noninverting input of the internal AD9632 amplifier.
The AD9632 provides the dc-coupled level shift circuit required
for operation with the AD9042 ADC. Configuring the amplifier
in a noninverting mode, the ac signal gain can be trimmed to
provide a constant input to the ADC centered around the inter-
nal reference voltage of the AD9042. This allows the converter
to be used in multiple system applications without the need for
external gain and level shift circuitry normally requiring trim.
The AD9632 was chosen for its superior ac performance and
input drive capabilities. These two specifications have limited
the ability of many amplifiers to drive high performance ADCs.
As new amplifiers are developed, pin compatible improve-
ments are planned to incorporate the latest operational ampli-
fier technology.
The OP279 provides the buffer and inversion of the internal
reference of the AD9042 in order to supply the summing node
of the AD9632 input amplifier. This dc voltage is then summed
with the input voltage and applied to the input of the AD9042
ADC. The reference voltage of the AD9042 is designed to track
internal offsets and drifts of the ADC and is used to ensure
matching over an extended temperature range of operation.
APPLYING THE AD10242
Encoding the AD10242
The AD10242 is designed to interface with TTL and CMOS
logic families. The source used to drive the ENCODE pin(s)
must be clean and free from jitter. Sources with excessive jitter
will limit SNR and overall performance.
0.01␮F
TTL OR CMOS
SOURCE ENCODE
ENCODE
AD10242
Figure 6. Single-Ended TTL/CMOS Encode
The AD10242 encode inputs are connected to a differential
input stage (see Figure 4). With no input connected to either
the ENCODE or ENCODE input, the voltage dividers bias the
inputs to 1.6 V. For TTL or CMOS usage, the encode source
should be connected to ENCODE (Pins 29 and/or 51). ENCODE
(Pins 28 and/or 52) should be decoupled using a low inductance
or microwave chip capacitor to ground. Devices such as AVX
05085C103MA15, a 0.01 µF capacitor, work well.
Performance Improvements
It is possible to improve the performance of the AD10242
slightly by taking advantage of the internal characteristics of the
amplifier and converter combination. By increasing the 5 V
supply slightly, the user may be able to gain up to a 5 dB improve-
ment in SFDR over the entire frequency range of the converter.
It is not recommended to exceed 5.5 V on the analog supplies
since there are no performance benefits beyond that range and
care should be taken to avoid the absolute maximum ratings.
ANALOG INPUT FREQUENCY – MHz
60
0
510
40
20
ENCODE = 40MSPS
AIN = 1dBFS
SNR (dB)
30
50
10
20 29.2 34.5 52.5 60.95
70
80
SFDR (dBFS)
SNR, WORST SPUR – dB, dBc
TPC 13. SNR/Harmonics to A
IN
> Nyquist MSPS
INPUT FREQUENCY – MHz
0.5
3.0
05
2.0
1.5
1.0
2.5
10 15 20 25 30 40
0
–0.5
45 50 5535
FUNDAMENTAL LEVELS – dBFS
ENCODE = 40MSPS
TPC 14. Gain Flatness vs. Input Frequency
AD10242
–11–
REV. C
If a logic threshold other than the nominal 1.6 V is required,
the following equations show how to use an external resistor,
Rx, to raise or lower the trip point (see Figure 4, R1 = 17 kΩ,
R2 = 8 kΩ).
VRRx
RR RRx R Rx
1
52
12 1 2
=++
to lower logic threshold.
0.01␮F
ENCODE
SOURCE ENCODE
ENCODE
AD10242
Rx
Vl
5V
R1
R2
Figure 7. Lower Threshold for Encode
VR
RRRx
RRx
1
52
21
1
=
++
to raise logic threshold.
0.01␮F
ENCODE
SOURCE ENCODE
ENCODE
AD10242
R
x
V
l
5V
R1
R2
AV
CC
Figure 8. Raise Logic Threshold for Encode
While the single-ended encode will work well for many applica-
tions, driving the encode differentially will provide increased
performance. Depending on circuit layout and system noise, a
1 dB to 3 dB improvement in SNR can be realized. It is recom-
mended that the encode signal be ac-coupled into the ENCODE
and ENCODE pins.
The simplest option is shown below. The low jitter TTL signal
is coupled with a limiting resistor, typically 100 Ω, to the primary
side of an RF transformer (these transformers are inexpensive
and readily available; part number in Figures 9 and 10 is from
Mini-Circuits). The secondary side is connected to the ENCODE
and ENCODE pins of the converter. Since both encode inputs
are self-biased, no additional components are required.
TTL ENCODE
ENCODE
AD10242
100⍀T1–1T
Figure 9. TTL Source—Differential Encode
If no TTL source is available, a clean sine wave may be substi-
tuted. In the case of the sine source, the matching network is
shown below. Since the matching transformer specified is a 1:1
impedance ratio, the load resistor R should be selected to match
the source impedance. The input impedance of the AD9042
is negligible in most cases.
ENCODE
ENCODE
AD10242
R
T1–1T
SINE
SOURCE
Figure 10. Sine Source—Differential Encode
If a low jitter ECL clock is available, another option is to ac-couple
a differential ECL signal to the encode input pins, as shown
in Figure 11. The capacitors shown here should be chip capaci-
tors but do not need to be of the low inductance variety.
ENCODE
ENCODE
AD10242
ECL
GATE
0.1␮F
0.1␮F
–VS
510⍀510⍀
Figure 11. Differential ECL for Encode
As a final alternative, the ECL gate may be replaced by an ECL
comparator. The input to the comparator could then be a logic
signal or a sine signal.
ENCODE
ENCODE
AD10242
0.1␮F
0.1␮F
–V
S
50⍀
AD96687 (1/2)
510⍀510⍀
Figure 12. ECL Comparator for Encode
Care should be taken not to overdrive the encode input pin when
ac-coupled. Although the input circuitry is electrically protected
from overvoltage or undervoltage conditions, improper circuit
operations may result from overdriving the encode input pin.
AD10242
–12– REV. C
USING THE FLEXIBLE INPUT
The AD10242 has been designed with the user’s ease of opera-
tion in mind. Multiple input configurations have been included on
board to allow the user a choice of input signal levels and input
impedance. While the standard inputs are ±0.5 V, ±1.0 V, and
±2.0 V, the user can select the input impedance of the AD10242
on any input by using the other inputs as alternate locations for
GND or an external resistor. The following chart summarizes the
impedance options available at each input location:
A
IN
1 = 100 Ω when A
IN
2 and A
IN
3 are open.
A
IN
1 = 75 Ω when A
IN
3 is shorted to GND.
A
IN
1 = 50 Ω when A
IN
2 is shorted to GND.
A
IN
2 = 200 Ω when A
IN
3 is open.
A
IN
2 = 100 Ω when A
IN
3 is shorted to GND.
A
IN
2 = 75 Ω when A
IN
2 to A
IN
3 has an external resistor of
A
IN
2 = 300 Ω, with A
IN
3 shorted to GND.
A
IN
2 = 50 Ω when A
IN
2 to A
IN
3 has an external resistor of A
IN
2
=100 Ω, with A
IN
3 shorted to GND.
A
IN
3 = 400 Ω.
A
IN
3 = 100 Ω when A
IN
3 has an external resistor of 133 Ω to GND.
A
IN
3 = 75 Ω when A
IN
3 has an external resistor of 92 Ω to GND.
A
IN
3 = 50 Ω when A
IN
3 has an external resistor of 57 Ω to GND.
While the analog inputs of the AD10242 are designed for
dc- coupled
bipolar inputs, the AD10242 has the ability to
use unipolar inputs in a user selectable mode through the addi-
tion of an external resistor. This allows for 1 V, 2 V, and 4 V
full-scale unipolar signals to be applied to the various inputs
(A
IN
1, A
IN
2, and A
IN
3, respectively). Placing a 2.43 kΩ resis-
tor (typical, offset calibration required) between UPOS and
UCOM shifts the reference voltage setpoint to allow a unipolar
positive voltage to be applied at the inputs of the device. To cali-
brate offset, apply a midscale dc voltage to the converter while
adjusting the unipolar resistor for a midscale output transition.
AIN2
UPOS AD10242
2.43k⍀
UCOM
AIN3
AIN1
Figure 13. Unipolar Positive
To operate with –1 V, –2 V, or –4 V full-scale unipolar signals,
place a 2.67 kΩ resistor (typical, offset calibration required)
between UNEG and UCOM. This again shifts the reference volt-
age setpoint to allow a unipolar negative voltage to be applied at
the inputs of the device. To calibrate offset, apply a midscale dc
voltage to the converter while adjusting the unipolar resistor for
a midscale output transition.
A
IN
2
UNEG
AD10242
2.67k⍀
UCOM
A
IN
3
A
IN
1
Figure 14. Unipolar Negative
GROUNDING AND DECOUPLING
Analog and Digital Grounding
Proper grounding is essential in any high speed, high resolution
system. Multilayer printed circuit boards (PCBs) are recom-
mended to provide optimal grounding and power schemes. The
use of ground and power planes offers distinct advantages:
1. The minimization of the loop area encompassed by a signal
and its return path.
2. The minimization of the impedance associated with ground
and power paths.
3. The inherent distributed capacitor formed by the power
plane, PCB insulation, and ground plane.
These characteristics result in both a reduction of electro-
magnetic interference (EMI) and an overall improvement in
performance.
It is important to design a layout that prevents noise from cou-
pling to the input signal. Digital signals should not be run in
parallel with input signal traces and should be routed away from
the input circuitry. The AD10242 does not distinguish between
analog and digital ground pins as the AD10242 should always
be treated like an analog component. All ground pins should be
connected together directly under the AD10242. The PCB
should have a ground plane covering all unused portions of the
component side of the board to provide a low impedance path
and manage the power and ground currents. The ground plane
should be removed from the area near the input pins to reduce
stray capacitance.
LAYOUT INFORMATION
The schematic of the evaluation board (Figure 15) represents a
typical implementation of the AD10242. The pinout of the
AD10242 is very straightforward and facilitates ease of use
and the implementation of high frequency/high resolution
design practices. It is recommended that high quality ceramic
chip capacitors be used to decouple each supply pin to ground
directly at the device. All capacitors except the one placed on
ENCODE can be standard high quality ceramic chip capacitors.
The capacitor used on the ENCODE pin must be a low induc-
tance chip capacitor as referenced previously.
AD10242
–13–
REV. C
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
9618765 686766656463624321
10
11
12
13
14
15
16
17
18
19
20
22
23
24
25
26
21
27 4328 29 30 31 32 33 34 35 36 37 38 39 40 41 42
DUT
AD10242
D0A
D11B
AINA3
AINA2
AINA1
AINB3
AINB2
AINB1
GND
GND
GND
GND
GND
TP5
TP6
GND
GND
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
D10B
D9B
D8B
D7B
GND
–5.2V
+5VA
GND
GND
GND
GND
GND
GND
GND
TP2
TP3
TP4
GND
GND
ENCB
ENCB
+5VD
GND
ENCA
ENCA
+5VD
D9A
D10A
D11A
GND
GND
D0B
D1B
D2B
D3B
D4B
D5B
D6B
GND
GND
TP1
–5.2V
+5VA
(MSBB) D11B
D10B
D9B
D8B
D7B
GNDB
GNDB
GNDB
GNDB
UNIPOSB
UNINEGB
UNICOMB
GNDB
GNDB
ENCB
ENCB
+5VDB
D0A (LSBA)
GNDA
GNDA
GNDA
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
NCA
NCA
UNIPOSA
–5.2VAA
+5VAA
AINA3
AINA2
AINA1
AINB3
AINB2
AINB1
GNDB
GNDB
UNICOMA
UNINEGA
SHIELD
+5VAB
–5.2VAB
GNDA
GNDA
GNDA
GNDA
GNDB
ENCA
ENCA
+5VDA
D9A
D10A
D11A (MSBA)
NCB
NCB
D0B (LSBB)
D1B
D2B
D3B
D4B
D5B
D6B
GNDB
5
86
3
2
R7
49.9⍀
R3
470⍀
R5
470⍀
VHIGH
PULSE A
IN U3
AD8036Q
SMA
J11 SMA
J12
PULSE A
OUT
VLOW
5VA
5VA
C1
0.1␮F14
U1
K1115
7
8H2DM
J15
H2DM
J17
BUFLATA
SMA
JC
SMA
J1 SMA
JA
C14
0.1␮F
R10
470⍀
R9
470⍀
2
3
8
U5
AD9696KN
E5
57
12
12
A SECTION
T1
T1–1T
2
1
34
6
ENCAB
ENCA
1 : 1
GND
R1
100⍀
VCC
OUT
VEE
51⍀
SMA
J2
AINA1
SMA
J3
AINA2
SMA
J4
AINA3
SMA
J5
AINB1
SMA
J6
AINB2
SMA
J7
AINB3
U4
C17
0.1␮F
U3
C18
0.1␮F
DUT
C9
0.1␮F
C23
10␮F
U5
C12
0.1␮F
U6
C3
0.1␮F
DUT
C8
0.1␮F
+5VD
U3
C15
0.1␮F
U4
C16
0.1␮F
C24
10␮F
U5
C13
0.1␮F
U6
C4
0.1␮F
DUT
C11
0.1␮F
–5.2V
DUT
C10
0.1␮F
DUT
C7
0.1␮F
C25
10␮F
DUT
C6
0.1␮F
+5V
VHIGH
U4
C22
0.1␮F
U3
C21
0.1␮F
VLOW
U3
C19
0.1␮F
U4
C20
0.1µF
+5VA +5VA
E1
VHIGH VHIGH
VLOW VLOW
GND GND
E3
–5.2V
–5.2V
E2
B JACKS
TP2 TP2
TP1 TP1
TP3 TP3
TP4 TP4
TP5 TP5
TP7 ENCAB
TP6 TP6
TP8 ENCA
TP9 ENCBB
TP10 ENCB
TEST POINTS
+5VD 140
(MSB) D11B 239
D10B 338
D8B 536
D9B 437
D7B 635
D6B 734
D4B 932
D5B 833
10 31
11 30
D2B 13 28
D3B 12 29
D1B
(LSB) D0B 15 26
GND 17 24
GND 16 25
14 27
GND 18 23
GND 20 21
GND 19 22
H40DM
J10
BUFLATB
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
5VD 140
(MSB) D11A 239
D10A 338
D8A 536
D9A 437
D7A 635
D6A 734
D4A 932
D5A 833
10 31
BUFLATA 11 30
D2A 128
D3A 12 29
13
D1A
(LSB) D0A 15 26
GND 17 24
GND 16 25
14 27
GND 18 23
GND 20 21
GND 19 22
H40DM
J9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
E4
5VA
5VA
C2
0.1␮F14
U2
K1115
7
8H2DM
J16
H2DM
J18
BUFLATB
SMA
J8 SMA
JB SMA
JD
C5
0.1␮F
R12
470⍀
R11
470⍀
2
3
8
U5
AD9696KN
E5
57
12
12
B SECTION
OUT
T2
T1–1T
2
1
34
6
ENCBB
ENCB
1 : 1
GND
R2
100⍀
51⍀
NOTES;
1) UNIPOLAR OPERATION
A SIDE + CONNECT 2.43k⍀ RES. FROM TP1 TO TP5.
A SIDE – CONNECT 2.67k⍀ RES. FROM TP5 TO TP6.
B SIDE + CONNECT 2.43k⍀ RES. FROM TP2 TO TP4.
B SIDE – CONNECT 2.67k⍀ RES. FROM TP4 TO TP3.
2) ABOVE UNIPOLAR RESISTOR VALUES ARE
NOMINAL AND MAY HAVE TO BE ADJUSTED
DEPENDING ON OFFSET OF DUT.
3) ENCODE SOURCES
A)FOR NORMAL OPERATION, A 40MHz TTL CLOCK
OSCILLATOR IS INSTALLED IN U1 AND U2. THERE
IS A 51⍀ RESISTOR BETWEEN J15 AND J16.
J17 AND J18 ARE OPEN.
B)FOR EXTERNAL SQUARE WAVE ENCODE, INPUT
SIGNAL AT J1 AND J8, REMOVE U1, U2, JUMPERS
J15 AND J16. CONNECT JUMPERS J17 AND J18.
C)FOR EXTERNAL SINE WAVE ENCODE, INPUT
SIGNAL AT J1 AND J8, REMOVE U1, U2, R9, R11,
JUMPERS J15 AND J16.
CONNECT JUMPERS J17 AND J18.
4) POWER (5VD) FOR DIGITAL OUTPUTS OF THE
AD10242 IS SUPPLIED VIA PIN 1 OF EITHER J9 OR J10
(THE DIGITAL INTERFACES). TO POWER THE EVAL.
BOARD WITH ONE 5V SUPPLY, JUMPER A WIRE
FROM E1 TO E4 (CONNECTED AT FACTORY).
5
86
3
2
R8
49.9⍀
R4
470⍀
R6
470⍀
VHIGH
PULSE B
IN U4
AD8036Q
SMA
J13 SMA
J14
PULSE B
OUT
VLOW
VCC
VEE
Figure 15. Evaluation Board Schematic
AD10242
–14– REV. C
Care should be taken when placing the digital output runs.
Because the digital outputs have such a high slew rate, the
capacitive loading on the digital outputs should be minimized.
Circuit traces for the digital outputs should be kept short and
connect directly to the receiving gate. Internal circuitry buffers
the outputs of the AD9042 ADC through a resistor network to
eliminate the need to externally isolate the device from the
receiving gate.
EVALUATION BOARD
The AD10242 evaluation board (see Figure 16) is designed to
provide optimal performance for evaluation of the AD10242
analog-to-digital converter. The board encompasses everything
needed to ensure the highest level of performance for evaluating
the AD10242.
Power to the analog supply pins is connected via banana jacks.
The analog supply powers the crystal oscillator, the associated
components and amplifiers, and the analog section of the
AD10242. The digital outputs of the AD10242 are powered via
Pin 1 of either J9 or J10 found on the digital interface con-
nector. To power the evaluation board with one 5 V supply, a
jumper wire is required from test point E1 to E4. Contact the
factory if additional layout or applications assistance is required.
Figure 16. Evaluation Board Mechanical Layout
AD10242
–15–
REV. C
OUTLINE DIMENSIONS
68-Lead Ceramic Leaded Chip Carrier [CLCC]
(Z-68A)
Dimensions shown in inches and (millimeters)
TOE DOWN
ANGLE
0–8 DEGREES
DETAIL A
1.190 (30.23)
1.180 (29.97) SQ
1.170 (29.72)
TOP VIEW
(PINS DOWN)
PIN 1
10
26
961
60
43
27
44
0.800
(20.32)
BSC
0.960 (24.38)
0.950 (24.13) SQ
0.940 (23.88)
0.055 (1.40)
0.050 (1.27)
0.045 (1.14)
0.020 (0.51)
0.017 (0.44)
0.014 (0.36)
0.235 (5.97)
MAX
DETAIL A
0.010 (0.25)
0.008 (0.20)
0.007 (0.18)
0.060 (1.52)
0.050 (1.27)
0.040 (1.02)
1.070
(27.18)
MIN
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Revision History
Location Page
1/03—Data Sheet changed from REV. B to REV. C.
Changes to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Change to Encoding the AD10242 section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6/01—Data Sheet changed from REV. A to REV. B.
AD9631 references changed to AD9632 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
C00665–0–1/03(C)
PRINTED IN U.S.A.
–16–