0 QPRO XQ4000E/EX QML High-Reliability FPGAs R DS021 (v2.2) June 25, 2000 0 2 Product Specification Product Features * Certified to MIL-PRF-38535, appendix A QML (Qualified Manufacturers Listing) * * Also available under the following Standard Microcircuit Drawings (SMD) XC4005E 5962-97522 XC4010E 5962-97523 XC4013E 5962-97524 XC4025E 5962-97525 XC4028EX 5962-98509 For more information contact the Defense Supply Center Columbus (DSCC) http://www.dscc.dla.mis/v/va/smd/smdsrch.html System featured Field-Programmable Gate Arrays - Select-RAMTM memory: on-chip ultra-fast RAM with * Synchronous write option * Dual-port RAM option - Abundant flip-flops - Flexible function generators - Dedicated high-speed carry logic - Wide edge decoders on each edge - Hierarchy of interconnect lines - Internal 3-state bus capability - Eight global low-skew clock or signal distribution networks System Performance beyond 60 MHz Flexible Array Architecture Low Power Segmented Routing Architecture Systems-Oriented Features - IEEE 1149.1-compatible boundary scan logic support - Individually programmable output slew rate - Programmable input pull-up or pull-down resistors - 12 mA sink current per XQ4000E/EX output * * * * * * * * * * Configured by Loading Binary File - Unlimited reprogrammability Readback Capability - Program verification - Internal node observability Backward Compatible with XC4000 Devices Development System runs on most common computer platforms - Interfaces to popular design environments - Fully automatic mapping, placement and routing - Interactive design editor for design optimization Available Speed Grades: - XQ4000E -3 for plastic packages only -4 for ceramic packages only - XQ4028EX -4 for all packages More Information For more information refer to Xilinx XC4000E and XC4000X series Field Programmable Gate Arrays product specification. This data sheet contains pinout tables for XQ4010E only. Refer to Xilinx web site for pinout tables for other devices. (Pinouts for XQ4000E/EX are identical to XC4000E/EX.) (http://www.xilinx.com/partinfo/databook.htm) (c) 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS021 (v2.2) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 1 R QPRO XQ4000E/EX QML High-Reliability FPGAs Table 1: XQ4000E/EX Field Programmable Gate Arrays Device Max. Max. Logic RAM Bits Gates (No (No RAM) Logic) Typical Gate Range (Logic and RAM)(1) CLB Matrix Total CLBs Number of Flip-Flops Max. Decode Inputs per Side Max. User I/O Packages XQ4005E 5,000 6,272 3,000 - 9,000 14 x 14 196 616 42 112 PG156, CB164 XQ4010E 10,000 12,800 7,000 - 20,000 20 x 20 400 1,120 60 160 PG191, CB196, HQ208 XQ4013E 13,000 18,432 10,000 - 30,000 24 x 24 576 1,536 72 192 PG223, CB228, HQ240 XQ4025E 25,000 32,768 15,000 - 45,000 32 x 32 1,024 2,560 96 256 PG299, CB228 XQ4028EX 28,000 32,768 18,000 - 50,000 32 x 32 1,024 2,560 96 256 PG299, CB228, HQ240, BG352 Notes: 1. Max values of Typical Gate Range include 20-30% of CLBs used as RAM. XQ4000E Switching Characteristics XQ4000E Absolute Maximum Ratings(1) Symbol Description Units VCC Supply voltage relative to GND -0.5 to +7.0 V VIN Input voltage relative to GND(2) -0.5 to VCC + 0.5 V -0.5 to VCC + 0.5 V -65 to +150 C output(2) VTS Voltage applied to High-Z TSTG Storage temperature (ambient) TSOL Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 C Junction temperature Ceramic package +150 C Plastic package +125 C TJ Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 2. Maximum DC excursion above V CC or below Ground must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0V or overshoot to VCC + 2.0V, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. 2 www.xilinx.com 1-800-255-7778 DS021 (v2.2) June 25, 2000 Product Specification R QPRO XQ4000E/EX QML High-Reliability FPGAs XQ4000E Recommended Operating Conditions(1,2) Symbol VCC VIH VIL Description Max Units Supply voltage relative to GND, TJ = -55C to +125C Plastic 4.5 5.5 V Supply voltage relative to GND, TC = -55C to +125C Ceramic 4.5 5.5 V High-Level Input Voltage TTL inputs 2.0 VCC V CMOS inputs 70% 100% VCC TTL inputs 0 0.8 V CMOS inputs 0 20% VCC - 250 ns Low-Level Input Voltage TIN Min Input signal transition time Notes: 1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per C. 2. Input and output measurement threshold are 1.5V for TTL and 2.5V for CMOS. XQ4000E DC Characteristics Over Recommended Operating Conditions Symbol VOH VOL ICCO IL CIN IRIN IRLL Description Min Max Units 2.4 - V VCC - 0.5 - V High-level output voltage @ IOH = -4.0 mA, VCC min TTL outputs High-level output voltage @ IOH = -1.0 mA, VCC min CMOS outputs Low-level output voltage @ IOL = 12.0 mA, VCC min(1) TTL outputs - 0.4 V CMOS outputs - 0.4 V - 50 mA -10 +10 A Quiescent FPGA supply current(2) Input or output leakage current Input capacitance (sample tested) Pad pull-up (when selected) at VIN = 0V (sample - 16 pF tested)(3) -0.02 -0.25 mA Low(3) 0.2 2.5 mA Horizontal longline pull-up (when selected) at logic Notes: 1. With 50% of the outputs simultaneously sinking 12 mA, up to a maximum of 64 pins. 2. With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND, and the FPGA configured with the development system Tie option. 3. Characterized Only. DS021 (v2.2) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 3 R QPRO XQ4000E/EX QML High-Reliability FPGAs XQ4000E Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Note: -3 Speed Grade only applies to XQ4010E and XQ4013E Plastic Package options only. -4 Speed Grade applies to all XQ devices and is only available in Ceramic Packages only. XQ4000E Global Buffer Switching Characteristics Symbol TPG TSG Description From pad through primary buffer, to any clock K From pad through secondary buffer, to any clock K -3(1) -4(2) Device Max Max Units XQ4005E - 7.0 ns XQ4010E 6.3 11.0 ns XQ4013E 6.8 11.5 ns XQ4025E - 12.5 ns XQ4005E - 7.5 ns XQ4010E 6.8 11.5 ns XQ4013E 7.3 12.0 ns XQ4025E - 13.0 ns Notes: 1. For plastic package options only. 2. For ceramic package options only. 4 www.xilinx.com 1-800-255-7778 DS021 (v2.2) June 25, 2000 Product Specification R QPRO XQ4000E/EX QML High-Reliability FPGAs XQ4000E Horizontal Longline Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. Symbol These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000E devices unless otherwise noted. The following guidelines reflect worst-case values over the recommended operating conditions. Description -3 -4 Device Max Max Units XQ4005E - 5.0 ns XQ4010E 6.4 8.0 ns XQ4013E 7.2 9.0 ns XQ4025E - 11.0 ns XQ4005E - 6.0 ns XQ4010E 6.9 10.5 ns XQ4013E 7.7 11.0 ns XQ4025E - 12.0 ns XQ4005E - 7.0 ns XQ4010E 7.3 8.5 ns XQ4013E 7.5 8.7 ns XQ4025E - 11.0 ns XQ4005E - 1.8 ns XQ4010E 1.5 1.8 ns XQ4013E 1.5 1.8 ns XQ4025E - 1.8 ns XQ4005E - 23.0 ns XQ4010E 22.0 29.0 ns XQ4013E 26.0 32.0 ns XQ4025E - 42.0 ns XQ4005E - 10.0 ns XQ4010E 11.0 13.5 ns XQ4013E 13.0 15.0 ns XQ4025E - 18.0 ns TBUF Driving a Horizontal Longline (LL): TIO1 TIO2 TON TOFF TPUS TPUF I going High or Low to LL going High or Low, while T is Low. Buffer is constantly active.(1) I going Low to LL going from resistive pull-up High to active Low. TBUF configured as open-drain.(1) T going Low to LL going from resistive pull-up or floating High to active Low. TBUF configured as open-drain or active buffer with I = Low.(1) T going High to TBUF going inactive, not driving LL. T going High to LL going from Low to High, pulled up by a single resistor.(1) T going High to LL going from Low to High, pulled up by two resistors.(1) Notes: 1. These values include a minimum load. Use the static timing analyzer to determine the delay for each destination. DS021 (v2.2) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 5 R QPRO XQ4000E/EX QML High-Reliability FPGAs XQ4000E Wide Decoder Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. Symbol TWAF TWAFL TWAO TWAOL These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000E devices unless otherwise noted. The following guidelines reflect worst-case values over the recommended operating conditions. Description(1,2) Full length, both pull-ups, inputs from IOB I-pins Full length, both pull-ups, inputs from internal logic Half length, one pull-up, inputs from IOB I-pins Half length, one pull-up, inputs from internal logic -3 -4 Device Max Max Units XQ4005E - 9.5 ns XQ4010E 9.0 15.0 ns XQ4013E 11.0 16.0 ns XQ4025E - 18.0 ns XQ4005E - 12.5 ns XQ4010E 11.0 18.0 ns XQ4013E 13.0 19.0 ns XQ4025E - 21.0 ns XQ4005E - 10.5 ns XQ4010E 10.0 16.0 ns XQ4013E 12.0 17.0 ns XQ4025E - 19.0 ns XQ4005E - 12.5 ns XQ4010E 12.0 18.0 ns XQ4013E 14.0 19.0 ns XQ4025E - 21.0 ns Notes: 1. These delays are specified from the decoder input to the decoder output. 2. Fewer than the specified number of pull-up resistors can be used, if desired. Using fewer pull-ups reduces power consumption but increases delays. Use the static timing analyzer to determine delays if fewer pull-ups are used. 6 www.xilinx.com 1-800-255-7778 DS021 (v2.2) June 25, 2000 Product Specification R QPRO XQ4000E/EX QML High-Reliability FPGAs XQ4000E CLB Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000E devices unless otherwise noted. -3 Symbol Description -4 Min Max Min Max Units Combinatorial Delays TILO F/G inputs to X/Y outputs - 2.01 - 2.7 ns TIHO F/G inputs via H to X/Y outputs - 4.3 - 4.7 ns THH0O C inputs via SR through H to X/Y outputs - 3.3 - 4.1 ns THH1O C inputs via H to X/Y outputs - 3.6 - 3.7 ns THH2O C inputs via DIN through H to X/Y outputs - 3.6 - 4.5 ns CLB Fast Carry Logic TOPCY Operand inputs (F1, F2, G1, G4) to C OUT - 2.6 - 3.2 ns TASCY Add/Subtract input (F3) to COUT - 4.4 - 5.5 ns TINCY Initialization inputs (F1, F3) to COUT - 1.7 - 1.7 ns TSUM CIN through function generators to X/Y outputs - 3.3 - 3.8 ns TBYP CIN to COUT, bypass function generators - 0.7 - 1.0 ns - 2.8 - 3.7 ns Sequential Delays TCKO Clock K to outputs Q Setup Time before Clock K TICK F/G inputs 3.0 - 4.0 - ns TIHCK F/G inputs via H 4.6 - 6.1 - ns THH0CK C inputs via H0 through H 3.6 - 4.5 - ns THH1CK C inputs via H1 through H 4.1 - 5.0 - ns THH2CK C inputs via H2 through H 3.8 - 4.8 - ns TDICK C inputs via DIN 2.4 - 3.0 - ns TECCK C inputs via EC 3.0 - 4.0 - ns TRCK C inputs via S/R, going Low (inactive) 4.0 - 4.2 - ns TCCK CIN input via F/G 2.1 - 2.5 - ns TCHCK CIN input via F/G and H 3.5 - 4.2 - ns DS021 (v2.2) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 7 R QPRO XQ4000E/EX QML High-Reliability FPGAs XQ4000E CLB Switching Characteristic Guidelines (continued) -3 Symbol Description -4 Min Max Min Max Units Hold Time after Clock K TCKI F/G inputs 0 - 0 - ns TCKIH F/G inputs via H 0 - 0 - ns TCKHH0 C inputs via H0 through H 0 - 0 - ns TCKHH1 C inputs via H1 through H 0 - 0 - ns TCKHH2 C inputs via H2 through H 0 - 0 - ns TCKDI C inputs via DIN/H2 0 - 0 - ns TCKEC C inputs via EC 0 - 0 - ns TCKR C inputs via SR, going Low (inactive) 0 - 0 - ns Clock TCH Clock High time 4.0 - 4.5 - ns TCL Clock Low time 4.0 - 4.5 - ns 4.0 - 5.5 - ns - 4.0 - 6.5 ns 11.5 - 13.0 - ns Set/Reset Direct TRPW Width (High) TRIO Delay from C inputs via S/R, going High to Q Master Set/Reset(1) TMRW Width (High or Low) TMRQ Delay from Global Set/Reset net to Q - 18.7 - 23.0 ns TMRK Global Set/Reset inactive to first active clock K edge - 18.7 - 23.0 ns FTOG Toggle Frequency(2) - 125 - 111 MHz Notes: 1. Timing is based on the XC4005E. For other devices see the static timing analyzer. 2. Export Control Max. flip-flop toggle rate. 8 www.xilinx.com 1-800-255-7778 DS021 (v2.2) June 25, 2000 Product Specification R QPRO XQ4000E/EX QML High-Reliability FPGAs XQ4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000E/EX devices unless otherwise noted. Single-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics -3 Symbol TWCS Write Operation Description Size Min Max Min Max Units 16x2 14.4 - 15.0 - ns 32x1 14.4 - 15.0 - ns 16x2 7.2 1 ms 7.5 1 ms ns 32x1 7.2 1 ms 7.5 1 ms ns Address setup time before clock K 16x2 2.4 - 2.8 - ns 32x1 2.4 - 2.8 - ns Address hold time after clock K 16x2 0 - 0 - ns 32x1 0 - 0 - ns 16x2 3.2 - 3.5 - ns 32x1 1.9 - 2.5 - ns 16x2 0 - 0 - ns 32x1 0 - 0 - ns WE setup time before clock K 16x2 2.0 - 2.2 - ns 32x1 2.0 - 2.2 - ns WE hold time after clock K 16x2 0 - 0 - ns 32x1 0 - 0 - ns 16x2 8.8 - - 10.3 ns 32x1 10.3 - - 11.6 ns Address write cycle time (clock K period) TWCTS TWPS Clock K pulse width (active edge) TWPTS TASS TASTS TAHS TAHTS TDSS DIN setup time before clock K TDSTS TDHS DIN hold time after clock K TDHTS TWSS TWSTS TWHS TWHTS TWOS -4 Data valid after clock K TWOTS Notes: 1. Timing for the 16x1 RAM option is identical to 16x2 RAM timing. 2. Applicable Read timing specifications are identical to Level-Sensitive Read timing. Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics -3 Symbol Write Operation Description Size(1) Min -4 Max Min Max 15.0 Units TWCDS Address write cycle time (clock K period) 16x1 14.4 ns TWPDS Clock K pulse width (active edge) 16x1 7.2 1 ms 7.5 1 ms ns TASDS Address setup time before clock K 16x1 2.5 - 2.8 - ns TAHDS Address hold time after clock K 16x1 0 - 0 - ns TDSDS DIN setup time before clock K 16x1 2.5 - 2.2 - ns TDHDS DIN hold time after clock K 16x1 0 - 0 - ns TWSDS WE setup time before clock K 16x1 1.8 - 2.2 - ns TWHDS WE hold time after clock K 16x1 0 - 0.3 - ns TWODS Data valid after clock K 16x1 - 7.8 - 10.0 ns Notes: 1. Applicable Read timing specifications are identical to Level-Sensitive Read timing. DS021 (v2.2) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 9 R QPRO XQ4000E/EX QML High-Reliability FPGAs XQ4000E CLB RAM Synchronous (Edge-Triggered) Write Timing Waveform TWPS WCLK (K) TWSS TWHS TDSS TDHS TASS TAHS WE DATA IN ADDRESS TILO TILO TWOS DATA OUT OLD NEW DS021_01_060100 XQ4000E CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing Waveform TWPDS WCLK (K) TWHS TWSS WE TDSDS TDHDS TASDS TAHDS DATA IN ADDRESS TILO DATA OUT TILO TWODS OLD NEW DS021_02_060100 10 www.xilinx.com 1-800-255-7778 DS021 (v2.2) June 25, 2000 Product Specification R QPRO XQ4000E/EX QML High-Reliability FPGAs XQ4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000E devices unless otherwise noted. -3 Symbol Single Port RAM -4 Size Min Max Min Max Units 16x2 8.0 - 8.0 - ns 32x1 8.0 - 8.0 - ns 16x2 4.0 - 4.0 - ns 32x1 4.0 - 4.0 - ns 16x2 2.0 - 2.0 - ns 32x1 2.0 - 2.0 - ns 16x2 2.0 - 2.5 - ns 32x1 2.0 - 2.0 - ns 16x2 2.2 - 4.0 - ns 32x1 2.2 - 5.0 - ns 16x2 2.0 - 2.0 - ns 32x1 2.0 - 2.0 - ns 16x2 3.1 - 4.5 - ns 32x1 5.5 - 6.5 - ns 16x2 - 1.8 - 2.7 ns 32x1 - 3.2 - 4.7 ns 16x2 3.0 - 4.0 - ns 32x1 4.6 - 6.1 - ns 16x2 - 6.0 - 10.0 ns 32x1 - 7.3 - 12.0 ns 16x2 - 6.6 - 9.0 ns 32x1 - 7.6 - 11.0 ns 16x2 6.0 - 8.0 - ns 32x1 6.8 - 9.6 - ns 16x2 5.2 - 7.0 - ns 32x1 6.2 - 8.0 - ns Write Operation TWC Address write cycle time TWCT TWP Write Enable pulse width (High) TWPT TAS Address setup time before WE TAST TAH Address hold time after end of WE TAHT TDS DIN setup time before end of WE TDST TDH DIN hold time after end of WE TDHT Read Operation TRC Address read cycle time TRCT TILO Data valid after address change (no Write Enable) TIHO Read Operation, Clocking Data into Flip-Flop TICK Address setup time before clock K TIHCK Read During Write TWO Data valid after WE goes active (DIN stable before WE) TWOT TDO Data valid after DIN (DIN changes during WE) TDOT Read During Write, Clocking Data into Flip-Flop TWCK WE setup time before clock K TWCKT TDCK Data setup time before clock K TDOCK Notes: 1. Timing for the 16x1 RAM option is identical to 16x2 RAM timing. DS021 (v2.2) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 11 R QPRO XQ4000E/EX QML High-Reliability FPGAs XQ4000E CLB Level-Sensitive RAM Timing Characteristics WRITE TWC ADDRESS TAS TWP TAH WE TDS DATA IN TDH REQUIRED READ WITHOUT WRITE TILO X,Y OUTPUTS VALID VALID READ, CLOCKING DATA INTO FLIP-FLOP TICK TCH CLOCK TCKO XQ,YQ OUTPUTS VALID (OLD) VALID (NEW) READ DURING WRITE TWP WRITE ENABLE TDH DATA IN (stable during WE) TWO X,Y OUTPUTS DATA IN (changing during WE) VALID VALID OLD NEW TWO X,Y OUTPUTS VALID (PREVIOUS) TDO VALID (OLD) VALID (NEW) READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP TWP WRITE ENABLE TWCK TDCK DATA IN CLOCK TCKO XQ,YQ OUTPUTS DS021_03_060100 12 www.xilinx.com 1-800-255-7778 DS021 (v2.2) June 25, 2000 Product Specification R QPRO XQ4000E/EX QML High-Reliability FPGAs XQ4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O) Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and Symbol TICKOF worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all XQ4000E devices unless otherwise noted. Description Global clock to output (fast) using OFF (Max) TPG OFF Device XQ4005E XQ4010E XQ4013E XQ4025E -3 10.9 11.0 - -4 14.0 16.0 16.5 17.0 Units ns ns ns ns XQ4005E XQ4010E XQ4013E XQ4025E 14.9 15.0 - 18.0 20.0 20.5 21.0 ns ns ns ns XQ4005E XQ4010E XQ4013E XQ4025E 0.2 0 - 2.0 1.0 0.5 0 ns ns ns ns XQ4005E XQ4010E XQ4013E XQ4025E 5.5 6.5 - 4.6 6.0 7.0 8.0 ns ns ns ns XQ4005E XQ4010E XQ4013E XQ4025E 7.0 7.0 - 8.5 8.5 8.5 9.5 ns ns ns ns XQ4005E XQ4010E XQ4013E XQ4025E 0 0 - 0 0 0 0 ns ns ns ns Global Clock-to-Output Delay DS021_04_060100 TICKO Global clock to output (slew-limited) using OFF (Max) TPG OFF Global Clock-to-Output Delay DS021_04_060100 TPSUF Input setup time, using IFF (no delay) (Min) Input Setup and Hold Time D IFF TPG DS021_05_060100 TPHF Input hold time, using IFF (no delay) (Min) Input Setup and Hold Time D IFF TPG DS021_05_060100 TPSU Input setup time, using IFF (with delay) (Min) Input Setup and Hold Time D IFF TPG DS021_05_060100 TPH Input hold time, using IFF (with delay) (Min) Input Setup and Hold Time D TPG IFF DS021_05_060100 Notes: 1. OFF = Output Flip-Flop 2. IFF = Input Flip-Flop or Latch DS021 (v2.2) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 13 R QPRO XQ4000E/EX QML High-Reliability FPGAs XQ4000E IOB Input Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all XQ4000E devices unless otherwise noted. -3 Symbol Description Propagation Delays (TTL -4 Device Min Max Min Max Units Inputs)(1) TPID Pad to I1, I2 All devices - 2.5 - 3.0 ns TPLI Pad to I1, I2 via transparent input latch, no delay All devices - 3.6 - 4.8 ns TPDLI Pad to I1, I2 via transparent FCL and input latch, with delay XQ4005E - - - 10.8 ns XQ4010E - 10.8 - 11.0 ns XQ4013E - 11.2 - 11.4 ns XQ4025E - - - 13.8 ns Propagation Delays (CMOS Inputs)(1) TPIDC Pad to I1, I2 All devices - 4.1 - 5.5 ns TPLIC Pad to I1, I2 via transparent input latch, no delay All devices - 8.8 - 6.8 ns TPDLIC Pad to I1, I2 via transparent FCL and input latch, with delay XQ4005E - - - 16.5 ns XQ4010E - 14.0 - 17.5 ns XQ4013E - 14.4 - 18.0 ns XQ4025E - - - 20.8 ns Propagation Delays (TTL Inputs) TIKRI Clock (IK) to I1, I2 (flip-flop) All devices - 2.8 - 5.6 ns TIKLI Clock (IK) to I1, I2 (latch enable, active Low) All devices - 4.0 - 6.2 ns Hold Times(2) TIKPI Pad to clock (IK), no delay All devices 0 - 0 - ns TIKPID Pad to clock (IK), with delay All devices 0 - 0 - ns TIKEC Clock enable (EC) to clock (K), no delay All devices 1.5 - 1.5 - ns TIKECD Clock enable (EC) to clock (K), with delay All devices 0 - 0 - ns Notes: 1. Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table. 2. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. 14 www.xilinx.com 1-800-255-7778 DS021 (v2.2) June 25, 2000 Product Specification R QPRO XQ4000E/EX QML High-Reliability FPGAs XQ4000E IOB Input Switching Characteristic Guidelines (continued) -3 Symbol Description Setup Times (TTL -4 Device Min Max Min Max Units Inputs)(1,2) TPICK Pad to clock (IK), no delay All devices 2.6 - 4.0 - ns TPICKD Pad to clock (IK), with delay XQ4005E - - 10.9 - ns XQ4010E 9.8 - 11.3 - ns XQ4013E 10.2 - 11.8 - ns XQ4025E - - 14.0 - ns Setup Times (CMOS Inputs)(1,2) TPICKC Pad to clock (IK), no delay All devices 3.3 - 6.0 - ns TPICKDC Pad to clock (IK), with delay XQ4005E - - 12.0 - ns XQ4010E 10.5 - 13.0 - ns XQ4013E 10.9 - 13.5 - ns XQ4025E - - 16.0 - ns (TTL or CMOS) TECIK Clock enable (EC) to clock (IK), no delay All devices 2.5 - 3.5 - ns TECIKD Clock enable (EC) to clock (IK), with delay XQ4005E - - 10.4 - ns XQ4010E 9.7 - 10.7 - ns XQ4013E 10.1 - 11.1 - ns XQ4025E - - 14.0 - ns Global Set/Reset(3) TRRI Delay from GSR net through Q to I1, I2 All devices - 7.8 - 12.0 ns TMRW GSR width All devices 11.5 - 13.0 - ns TMRI GSR inactive to first active clock (IK) edge All devices 11.5 - 13.0 - ns Notes: 1. Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table. 2. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. 3. Timing is based on the XC4005E. For other devices see the XACT timing calculator. DS021 (v2.2) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 15 R QPRO XQ4000E/EX QML High-Reliability FPGAs XQ4000E IOB Output Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Develop- ment System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless otherwise noted. Values apply to all XQ4000E devices unless otherwise noted. -3 Symbol Description -4 Min Max Min Max Units - 6.5 - 7.5 ns Propagation Delays (TTL Output Levels) TOKPOF Clock (OK) to pad, fast TOKPOS Clock (OK) to pad, slew-rate limited - 9.5 - 11.5 ns TOPF Output (O) to pad, fast - 5.5 - 8.0 ns TOPS Output (O) to pad, slew-rate limited - 8.6 - 12.0 ns TTSHZ 3-state to pad High-Z, slew-rate independent - 4.2 - 10.0 ns TTSONF 3-state to pad active and valid, fast - 8.1 - 10.0 ns TTSONS 3-state to pad active and valid, slew-rate limited - 11.1 - 13.7 ns Propagation Delays (CMOS Output Levels) TOKPOFC Clock (OK) to pad, fast - 7.8 - 9.5 ns TOKPOSC Clock (OK) to pad, slew-rate limited - 11.6 - 13.5 ns TOPFC Output (O) to pad, fast - 9.7 - 10.0 ns TOPSC Output (O) to pad, slew-rate limited - 13.4 - 14.0 ns TTSHZC 3-state to pad High-Z, slew-rate independent - 4.3 - 5.2 ns TTSONFC 3-state to pad active and valid, fast - 7.6 - 9.1 ns TTSONSC 3-state to pad active and valid, slew-rate limited - 11.4 - 13.1 ns Setup and Hold Times TOOK Output (O) to clock (OK) setup time 4.6 - 5.0 - ns TOKO Output (O) to clock (OK) hold time 0 - 0 - ns TECOK Clock enable (EC) to clock (OK) setup 3.5 - 4.8 - ns TOKEC Clock enable (EC) to clock (OK) hold 1.2 - 1.2 - ns TCH Clock High 4.0 - 4.5 - ns TCL Clock Low 4.0 - 4.5 - ns - 11.8 - 15.0 ns Clock Global Set/Reset(3) TRRO Delay from GSR net to pad TMRW GSR width 11.5 - 13.0 - ns TMRO GSR inactive to first active clock (OK) edge 11.5 - 13.0 - ns Notes: 1. Output timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the "Additional XC4000 Data" section on the Xilinx web site, www.xilinx.com/partinfo/databook.htm. 2. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. 3. Timing is based on the XC4005E. For other devices see the XACT timing calculator. 16 www.xilinx.com 1-800-255-7778 DS021 (v2.2) June 25, 2000 Product Specification R QPRO XQ4000E/EX QML High-Reliability FPGAs XC4000E Boundary Scan (JTAG) Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF-S. The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E devices unless otherwise noted. -3 Symbol Description Min -4 Max Min Max Units Setup Times TTDITCK Input (TDI) to clock (TCK) 30.0 30.0 ns TTMSTCK Input (TMS) to clock (TCK) 15.0 15.0 ns TTCKTDI Input (TDI) to clock (TCK) 0 0 ns TTCKTMS Input (TMS) to clock (TCK) 0 0 ns Hold Times Propagation Delay TTCKPO Clock (TCK) to pad (TDO) 30.0 30.0 ns Clock TTCKH Clock (TCK) High 5.0 5.0 ns TTCKL Clock (TCK) Low 5.0 5.0 ns FMAX Frequency 15.0 15.0 MHz Notes: 1. Input setup and hold times and clock-to-pad times are specified with respect to external signal pins. 2. Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the "Additional XC4000 Data" section of the Programmable Logic Data Book. 3. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. DS021 (v2.2) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 17 R QPRO XQ4000E/EX QML High-Reliability FPGAs XQ4028EX Switching Characteristics Definition of Terms In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device families. Values are subject to change. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final. Except for pin-to-pin input and output parameters, the A.C. parameter delay specifications included in this document are derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction temperature conditions. All specifications subject to change without notice. XQ4028EX Absolute Maximum Ratings(1) Symbol Description Units VCC Supply voltage relative to GND -0.5 to +7.0 V VIN Input voltage relative to GND(2) -0.5 to VCC + 0.5 V VTS Voltage applied to High-Z output(2) -0.5 to VCC + 0.5 V VCCt Longest supply voltage rise time from 1V to 4V 50 ms TSTG Storage temperature (ambient) -65 to +150 C TSOL Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 C Junction temperature Ceramic package +150 C Plastic package +125 C TJ Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 2. Maximum DC excursion above V CC or below Ground must be limited to either 0.5V or 10 mA, whichever is easier to achieve. Maximum total combined current on all dedicated inputs and Tri-state outputs must not exceed 200 mA. During transitions, the device pins may undershoot to -2.0V or overshoot toV CC +2.0V, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. 18 www.xilinx.com 1-800-255-7778 DS021 (v2.2) June 25, 2000 Product Specification R QPRO XQ4000E/EX QML High-Reliability FPGAs XQ4028EX Recommended Operating Conditions(1) Symbol VCC VIH Descriptiont Supply voltage relative to GND, TJ = -55C to +125C Supply voltage relative to GND, TC = -55C to +125C High-level input voltage(2) Min Max Units Plastic 4.5 5.5 V Ceramic 4.5 5.5 V TTL inputs 2.0 VCC V 70% 100% VCC TTL inputs 0 0.8 V CMOS inputs 0 20% VCC - 250 ns CMOS inputs VIL TIN Low-level input voltage Input signal transition time Notes: 1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per C. 2. Input and output measurement threshold are 1.5V for TTL and 2.5V for CMOS. XQ4028EX DC Characteristics Over Recommended Operating Conditions Symbol VOH VOL VDR ICCO IL CIN Description Min Max Units 2.4 - V VCC - 0.5 - V High-level output voltage at IOH = -4 mA, VCC min TTL outputs High-level output voltage at IOH = -1 mA CMOS outputs Low-level output voltage at IOL = 12 mA, VCC min(1) TTL outputs - 0.4 V CMOS outputs - 0.4 V 3.0 - V - 25 mA -10 10 A Plastic packages - 10 V Ceramic packages - 16 V Data retention supply voltage (below which configuration data may be lost) Quiescent FPGA supply current(2) Input or output leakage current Input capacitance (sample tested) IRPU Pad pull-up (when selected) at VIN = 0V (sample tested) 0.02 0.25 mA IRPD Pad pull-down (when selected) at VIN = 5.5V (sample tested) Horizontal longline pull-up (when selected) at logic Low(3) 0.02 0.25 mA 0.3 2.0 mA IRLL Notes: 1. With up to 64 pins simultaneously sinking 12 mA. 2. With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND. DS021 (v2.2) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 19 R QPRO XQ4000E/EX QML High-Reliability FPGAs XQ4028EX Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature) Global Buffer Switching Characteristics. -4 Symbol Description Max Units TGLS From pad through Global Low Skew buffer, to any clock K 9.2 ns TGE From pad through Global Early buffer, to any clock K in same quadrant 5.7 ns XQ4028EX Horizontal Longline Switching Characteristic Guidelines -4 Symbol Description Max Units TBUF Driving a Horizontal Longline TIO1 I going High or Low to horizontal longline going High or Low, while T is Low. Buffer is constantly active. 13.7 ns TON T going Low to horizontal longline going from resistive pull-up or floating High to active Low. TBUF configured as open-drain or active buffer with I = Low. 14.7 ns TBUF Driving Half a Horizontal Longline THIO1 I going High or Low to half of a horizontal longline going High or Low, while T is Low. Buffer is constantly active. 6.3 ns THON T going Low to half of a horizontal longline going from resistive pull-up or floating High to active Low. TBUF configured as open-drain or active buffer with I = Low. 7.2 ns Notes: 1. These values include a minimum load of one output, spaced as far as possible from the activated pull-up(s). Use the static timing analyzer to determine the delay for each destination. 20 www.xilinx.com 1-800-255-7778 DS021 (v2.2) June 25, 2000 Product Specification R QPRO XQ4000E/EX QML High-Reliability FPGAs XQ4028EX CLB Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000EX devices unless otherwise noted. CLB Switching Characteristics -4 Symbol Description Min Max Units Combinatorial Delays TILO F/G inputs to X/Y outputs - 2.2 ns TIHO F/G inputs via H' to X/Y outputs - 3.8 ns TITO F/G inputs via transparent latch to Q outputs - 3.2 ns THH0O C inputs via SR/H0 via H to X/Y outputs - 3.6 ns THH1O C inputs via H1 via H to X/Y outputs - 3.0 ns THH2O C inputs via DIN/H2 via H to X/Y outputs - 3.6 ns TCBYP C inputs via EC, DIN/H2 to YQ, XQ output (bypass) - 2.0 ns CLB Fast Carry Logic TOPCY Operand inputs (F1, F2, G1, G4) to C OUT - 2.5 ns TASCY Add/Subtract input (F3) to COUT - 4.1 ns TINCY Initialization inputs (F1, F3) to COUT - 1.9 ns TSUM CIN through function generators to X/Y outputs - 3.0 ns TBYP CIN to COUT, bypass function generators - 0.60 ns TNET Carry net selay, COUT to CIN - 0.18 ns Sequential Delays TCKO Clock K to flip-flop outputs Q - 2.2 ns TCKLO Clock K to latch outputs Q - 2.2 ns Setup Time before Clock K TICK F/G inputs 1.3 - ns TIHCK F/G inputs via H 3.0 - ns THH0CK C inputs via H0 through H 2.8 - ns THH1CK C inputs via H1 through H 2.2 - ns THH2CK C inputs via H2 through H 2.8 - ns TDICK C inputs via DIN 1.2 - ns TECCK C inputs via EC 1.2 - ns TRCK C inputs via S/R, going Low (inactive) 0.8 - ns TCCK CIN input via F/G 2.2 - ns TCHCK CIN input via F/G and H 3.9 - ns 0 - ns Hold Time after Clock K TCKI F/G inputs DS021 (v2.2) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 21 R QPRO XQ4000E/EX QML High-Reliability FPGAs CLB Switching Characteristics (Continued) -4 Symbol Min Max Units F/G inputs via H 0 - ns TCKHH0 C inputs via SR/H0 through H 0 - ns TCKHH1 C inputs via H1 through H 0 - ns TCKHH2 C inputs via DIN/H2 through H 0 - ns TCKDI C inputs via DIN/H2 0 - ns TCKEC C inputs via EC 0 - ns TCKR C inputs via SR, going Low (inactive) 0 - ns TCKIH Description Clock TCH Clock High time 3.5 - ns TCL Clock Low time 3.5 - ns TRPW Width (High) 3.5 - ns TRIO Delay from C inputs via S/R, going High to Q - 4.5 ns ns Set/Reset Direct Global Set/Reset 22 TMRW Minimum GSR pulse width - 13.0 TMRQ Delay from GSR input to any Q - 22.8 FTOG Toggle frequency (MHz) (for export control) - 143 www.xilinx.com 1-800-255-7778 MHz DS021 (v2.2) June 25, 2000 Product Specification R QPRO XQ4000E/EX QML High-Reliability FPGAs XQ4028EX CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000EX devices unless otherwise noted. -4 Symbol Write Operation TWCS Single Port RAM Size Min Max Units 16x2 11.0 - ns 32x1 11.0 - ns Clock K pulse width (active edge) 16x2 5.5 - ns 32x1 5.5 - ns Address setup time before clock K 16x2 2.7 - ns 32x1 2.6 - ns Address hold time after clock K 16x2 0 - ns 32x1 0 - ns DIN setup time before clock K 16x2 2.4 - ns 32x1 2.9 - ns DIN hold time after clock K 16x2 0 - ns 32x1 0 - ns WE setup time before clock K 16x2 2.3 - ns 32x1 2.1 - ns WE hold time after clock K 16x2 0 - ns 32x1 0 - ns Data valid after clock K 16x2 - 8.2 ns 32x1 - 10.1 ns Address write cycle time (clock K period) TWCTS TWPS TWPTS TASS TASTS TAHS TAHTS TDSS TDSTS TDHS TDHTS TWSS TWSTS TWHS TWHTS TWOS TWOTS Notes: 1. Applicable Read timing specifications are identical to Level-Sensitive Read timing. Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics -4 Symbol Write Operation Dual Port RAM Size(1) Min Max Units TWCDS Address write cycle time (clock K period) 16x1 11.0 ns TWPDS Clock K pulse width (active edge) 16x1 5.5 - ns TASDS Address setup time before clock K 16x1 3.1 - ns TAHDS Address hold time after clock K 16x1 0 - ns TDSDS DIN setup time before clock K 16x1 2.9 - ns TDHDS DIN hold time after clock K 16x1 0 - ns TWSDS WE setup time before clock K 16x1 2.1 - ns TWHDS WE hold time after clock K 16x1 0 - ns TWODS Data valid after clock K 16x1 - 9.4 ns Notes: 1. Timing for the 16x1 RAM option is identical to 16x2 RAM timing. 2. Applicable Read timing specifications are identical to Level-Sensitive Read timing. DS021 (v2.2) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 23 R QPRO XQ4000E/EX QML High-Reliability FPGAs XQ4028EX CLB RAM Synchronous (Edge-Triggered) Write Timing Waveform TWPS WCLK (K) TWSS TWHS TDSS TDHS TASS TAHS WE DATA IN ADDRESS TILO TILO TWOS DATA OUT OLD NEW DS021_01_060100 XQ4028EX CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing Waveform TWPDS WCLK (K) TWHS TWSS WE TDSDS TDHDS TASDS TAHDS DATA IN ADDRESS TILO DATA OUT TILO TWODS OLD NEW DS021_02_060100 24 www.xilinx.com 1-800-255-7778 DS021 (v2.2) June 25, 2000 Product Specification R QPRO XQ4000E/EX QML High-Reliability FPGAs XQ4028EX CLB RAM Asynchronous (Level-Sensitive) Write and Read Operation Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000EX devices unless otherwise noted. -4 Symbol Single Port RAM Size Min Max Units 16x2 10.6 - ns 32x1 10.6 - ns 16x2 5.3 - ns 32x1 5.3 - ns 16x2 2.8 - ns 32x1 2.8 - ns 16x2 1.7 - ns 32x1 1.7 - ns 16x2 1.1 - ns 32x1 1.1 - ns 16x2 6.6 - ns 32x1 6.6 - ns 16x2 4.5 - ns 32x1 6.5 - ns 16x2 - 2.2 ns 32x1 - 3.8 ns 16x2 1.5 - ns 32x1 3.2 - ns 16x2 - 6.5 ns 32x1 - 7.4 ns 16x2 - 7.7 ns 32x1 - 8.2 ns 16x2 7.1 - ns 32x1 9.2 - ns 16x2 5.9 - ns 32x1 8.4 - ns Write Operation TWC Address write cycle time TWCT TWP Write Enable pulse width (High) TWPT TAS Address setup time before WE TAST TAH Address hold time after end of WE TAHT TDS DIN setup time before end of WE TDST TDH DIN hold time after end of WE TDHT Read Operation TRC Address read cycle time TRCT TILO Data valid after address change (no Write Enable) TIHO Read Operation, Clocking Data into Flip-Flop TICK Address setup time before clock K TIHCK Read During Write TWO Data valid after WE goes active (DIN stable before WE) TWOT TDO Data valid after DIN (DIN changes during WE) TDOT Read During Write, Clocking Data into Flip-Flop TWCK WE setup time before clock K TWCKT TDCK Data setup time before clock K TDOCK Notes: 1. Timing for the 16x1 RAM option is identical to 16x2 RAM timing. DS021 (v2.2) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 25 R QPRO XQ4000E/EX QML High-Reliability FPGAs XQ4028EX CLB Level-Sensitive RAM Timing Waveforms WRITE TWC ADDRESS TAS TWP TAH WE TDS DATA IN TDH REQUIRED READ WITHOUT WRITE TILO X,Y OUTPUTS VALID VALID READ, CLOCKING DATA INTO FLIP-FLOP TICK TCH CLOCK TCKO XQ,YQ OUTPUTS VALID (OLD) VALID (NEW) READ DURING WRITE TWP WRITE ENABLE TDH DATA IN (stable during WE) TWO X,Y OUTPUTS DATA IN (changing during WE) VALID VALID OLD NEW TWO X,Y OUTPUTS VALID (PREVIOUS) TDO VALID (OLD) VALID (NEW) READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP TWP WRITE ENABLE TWCK TDCK DATA IN CLOCK TCKO XQ,YQ OUTPUTS DS021_03_060100 Figure 1: 26 www.xilinx.com 1-800-255-7778 DS021 (v2.2) June 25, 2000 Product Specification R QPRO XQ4000E/EX QML High-Reliability FPGAs XQ4028EX Pin-to-Pin Output Parameter Guidelines worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all XQ4000EX devices unless otherwise noted. Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and XQ4028EX Output Flip-Flop, Clock to Out(1,2) -4 Symbol Description Max Units TICKOF Global low skew clock to output using OFF(3) 16.6 ns TICKEOF Global early clock to output using OFF(3) 13.1 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at TTL threshold with 50 pF external capacitive load. 3. OFF = Output Flip-Flop XQ4028EX Output Mux, Clock to Out(1,2) -4 Symbol TPFPF TPEFPF Description Global low skew clock to TTL output (fast) using Global early clock to TTL output (fast) using OMUX3) OMUXF(3) Max Units 15.9 ns 12.4 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at ~50% V CC threshold with 50 pF external capacitive load. For different loads, see graph below. 3. OMUX = Output MUX XQ4028EX Output Level and Slew Rate Adjustments The following table must be used to adjust output parameters and output switching characteristics. -4 Symbol Description Max Units TTTLOF For TTL output FAST add 0 ns TTTLO For TTL output SLOW add 2.9 ns TCMOSOF For CMOS FAST output add 1.0 ns TCMOSO For CMOS SLOW output add 3.6 ns DS021 (v2.2) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 27 R QPRO XQ4000E/EX QML High-Reliability FPGAs XQ4028EX Pin-to-Pin Input Parameter Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all XQ4000EX devices unless otherwise noted XQ4028EX Global Low Skew Clock, Setup and Hold -4 Symbol Description Min Units TPSD Input setup time, using Global Low Skew clock and IFF (full delay) 8.0 ns TPHD Input hold time, using Global Low Skew clock and IFF (full delay) 0 ns Notes: 1. IFF = Flip-Flop or Latch XQ4028EX Global Early Clock, Setup and Hold for IFF -4 Symbol Description Min(2) Units TPSEP Input setup time, using Global Early clock and IFF (full delay) 6.5 ns TPHEP Input hold time, using Global Early clock and IFF (full delay) 0 ns Notes: 1. IFF = Flip-Flop or Latch 2. Setup parameters are for BUFGE #s 3, 4, 7 and 8. Add 1.6 ns for BUFGE #s 1, 2, 5 and 6. XQ4028EX Global Early Clock, Setup and Hold for FCL -4 Symbol Description Min(2) Units TPFSEP Input setup time, using Global Early clock and FCL (partial delay) 3.4 ns TPFHEP Input hold time, using Global Early clock and FCL (partial delay) 0 ns Notes: 1. FCL = Fast Capture Latch 2. For CMOS input levels, see the XQ4028EX Input Threshold Adjustments. 3. Setup time is measured with the fastest route and the lightest load. Use the static timing analyzer to determine the setup time under given design conditions. 4. Hold time is measured using the farthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer to determine the setup and hold times under given design conditions. 5. Setup parameters are for BUFGE #s 3, 4, 7 and 8. Add 1.2 ns for BUFGE #s 1, 2, 5 and 6. XQ4028EX Input Threshold Adjustments The following table must be used to adjust input parameters and input switching characteristics. -4 Symbol TTTLI TCMOSI 28 Description For TTL input add For CMOS input add www.xilinx.com 1-800-255-7778 Max Units 0 ns 0.3 ns DS021 (v2.2) June 25, 2000 Product Specification R QPRO XQ4000E/EX QML High-Reliability FPGAs XQ4028EX IOB Input Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Develop- ment System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000EX devices unless otherwise noted. -4 Symbol Description Min Units 3.2 ns Clocks TOKIK Delay from FCL enable (OK) active to IFF clock (IK) active edge Propagation Delays TPID Pad to I1, I2 2.2 ns TPLI Pad to I1, I2 via transparent input latch, no delay 3.8 ns TPPLI Pad to I1, I2 via transparent input latch, partial delay 13.3 ns TPDLI Pad to I1, I2 via transparent input latch, full delay 18.2 ns TPFLI Pad to I1, I2 via transparent FCL and input latch, no delay 5.3 ns TPPFLI Pad to I1, I2 via transparent FCL and input latch, partial delay 13.6 ns Propagation Delays (TTL Inputs) TIKRI Clock (IK) to I1, I2 (flip-flop) 3.0 ns TIKLI Clock (IK) to I1, I2 (latch enable, active Low) 3.2 ns TOKLI FCL enable (OK) active edge to I1, I2 (via transparent standard input latch) 6.2 ns Global Set/Reset TMRW Minimum GSR pulse width 13.0 ns TRRI Delay from GSR input to any Q 22.8 ns Notes: 1. FCL = Fast Capture Latch, IFF = Input Flip-Flop or Latch 2. For CMOS input levels, see the "XQ4028EX Input Threshold Adjustments" on page 28. 3. For setup and hold times with respect to the clock input pin, see the Global Low Skew Clock and Global Early Clock Setup and Hold tables on page 28. DS021 (v2.2) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 29 R QPRO XQ4000E/EX QML High-Reliability FPGAs XQ4028EX IOB Input Switching Characteristic Guidelines (Continued) -4 Symbol Description Min Units Setup Times TPICK Pad to Clock (IK), no delay 2.5 ns TPICKP Pad to Clock (IK), partial delay 10.8 ns TPICKD Pad to Clock (IK), full delay 15.7 ns TPICKF Pad to Clock (IK), via transparent Fast Capture Latch, no delay 3.9 ns TPICKFP Pad to Clock (IK), via transparent Fast Capture Latch, partial delay 12.3 ns TPOCK Pad to Fast Capture Latch Enable (OK), no delay 0.8 ns TPOCKP Pad to Fast Capture Latch Enable (OK), partial delay 9.1 ns 0.3 ns Setup Times (TTL or CMOS Inputs) TECIK Clock Enable (EC) to Clock (IK) Hold Times TIKPI Pad to Clock (IK), no delay 0 ns TIKPIP Pad to Clock (IK), partial delay 0 ns TIKPID Pad to Clock (IK), full delay 0 ns TIKPIF Pad to Clock (IK) via transparent Fast Capture Latch, no delay 0 ns TIKFPIP Pad to Clock (IK) via transparent Fast Capture Latch, partial delay 0 ns TIKFPID Pad to Clock (IK) via transparent Fast Capture Latch, full delay 0 ns TIKEC Clock Enable (EC) to Clock (IK), no delay 0 ns TIKECP Clock Enable (EC) to Clock (IK), partial delay 0 ns TIKECD Clock Enable (EC) to Clock (IK), full delay 0 ns TOKPI Pad to Fast Capture Latch Enable (OK), no delay 0 ns TOKPIP Pad to Fast Capture Latch Enable (OK), partial delay 0 ns Notes: 1. For CMOS input levels, see the "XQ4028EX Input Threshold Adjustments" on page 28. 2. For setup and hold times with respect to the clock input pin, see the Global Low Skew Clock and Global Early Clock Setup and Hold tables on page 28. 30 www.xilinx.com 1-800-255-7778 DS021 (v2.2) June 25, 2000 Product Specification R QPRO XQ4000E/EX QML High-Reliability FPGAs FXQ4028EX IOB Output Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Develop- ment System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless otherwise noted. Values apply to all XQ4000EX devices unless otherwise noted. -4 Symbol Description Min Max Units Propagation Delays (TTL Output Levels) TOKPOF Clock (OK) to pad, fast - 7.4 ns TOPF Output (O) to pad, fast - 6.2 ns TTSHZ 3-state to pad High-Z, slew-rate independent - 4.9 ns TTSONF 3-state to pad active and valid, fast - 6.2 ns TOKFPF Output MUX select (OK) to pad - 6.7 ns TCEFPF Fast path output MUX input (EC) to pad - 6.2 TOFPF Slowest path output MUX input (EC) to pad - 7.3 Setup and Hold Times TOOK Output (O) to clock (OK) setup time 0.6 - ns TOKO Output (O) to clock (OK) hold time 0 - ns TECOK Clock enable (EC) to clock (OK) setup 0 - ns TOKEC Clock enable (EC) to clock (OK) hold 0 - ns Clocks TCH Clock High 3.5 - ns TCL Clock Low 3.5 - ns Global Set/Reset TMRW Minimum GSR pulse width 13.0 - ns TRRI Delay from GSR input to any pad 30.2 - ns Notes: 1. Output timing is measured at TTL threshold, with 35 pF external capacitive loads. 2. For CMOS output levels, see the "XQ4028EX Output Level and Slew Rate Adjustments" on page 27. DS021 (v2.2) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 31 R QPRO XQ4000E/EX QML High-Reliability FPGAs CB191/196 Package for XQ4010E Pin Description PG191 CB196 Bound Scan GND D4 P1 - PGCK1_(A16*I/0) C3 P2 122 I/O_(A17) C4 P3 125 I/0 B3 P4 128 - - P5(1) - I/O C5 P6 131 I/O_(TDI) A2 P7 134 I/O_(TCK) B4 P8 137 I/O C6 P9 140 I/O A3 P10 143 I/O B5 P11 146 I/O B6 P12 149 GND C7 P13 - I/O A4 P14 152 I/O A5 P15 155 I/O_(TMS) B7 P16 158 I/O A6 P17 161 I/O C8 P18 164 I/O A7 P19 167 I/O B8 P20 170 I/O A8 P21 173 I/O B9 P22 176 I/O C9 P23 179 GND D9 P24 - VCC D10 P25 - I/O C10 P26 182 I/O B10 P27 185 I/O A9 P28 - I/O A10 P29 191 I/O A11 P30 194 I/O C11 P31 197 I/O B11 P32 200 I/O A12 P33 203 Notes: 1. Indicates unconnected package pins. 2. Contributes only one bit (.I) to the boundary scan register. Boundary Scan Bit 0 = TD0.T Boundary Scan Bit 1 = TD0.0 Boundary Scan Bit 487 = BSCAN.UPD 32 Pin Description PG191 CB196 Bound Scan I/O B12 P34 206 I/O A13 P35 209 GND C12 P36 - I/O B13 P37 212 I/O A14 P38 215 I/O A15 P39 218 I/O C13 P40 221 I/O B14 P41 224 I/O A16 P42 227 I/O B15 P43 230 I/O C14 P44 233 I/O A17 P45 236 SCGK2_(I/O) B16 P46 239 M1 C15 P47 242 GND D15 P48 - M0 A18 P49 245(2) VCC D16 P50 - M2 C16 P51 246(2) PGCK2_(I/O) B17 P52 247 I/O_(HDC) E16 P53 250 - - P54(1) - I/O C17 P55 253 I/0 D17 P56 256 I/O B18 P57 259 I/O_(LDC) E17 P58 262 I/O F16 P59 265 I/O C18 P60 268 I/O D18 P61 271 I/O F17 P62 274 GND G16 P63 - I/O E18 P64 277 I/O F18 P65 280 I/O G17 P66 283 I/O G18 P67 286 Notes: 1. Indicates unconnected package pins. 2. Contributes only one bit (.I) to the boundary scan register. Boundary Scan Bit 0 = TD0.T Boundary Scan Bit 1 = TD0.0 Boundary Scan Bit 487 = BSCAN.UPD www.xilinx.com 1-800-255-7778 DS021 (v2.2) June 25, 2000 Product Specification R QPRO XQ4000E/EX QML High-Reliability FPGAs Pin Description PG191 CB196 Bound Scan Pin Description PG191 CB196 Bound Scan I/O H16 P68 286 PGCK3_(I/O) U16 P102 370 I/O H17 P69 291 - - P103(1) - I/O H18 P70 295 I/O T14 P104 376 I/O J18 P71 298 I/O U15 P105 376 I/O J17 P72 301 I/O_(D6) V17 P106 379 I/O_(/ERR_/INIT) J16 P73 304 I/O V16 P107 382 VCC J15 P74 - I/O T13 P108 385 GND K15 P75 - I/O U14 P109 388 I/O K16 P76 307 I/O V15 P110 391 I/O K17 P77 310 I/O V14 P111 394 I/O K18 P78 313 GND T12 P112 - I/O L18 P79 316 I/O U13 P113 397 I/O L17 P80 319 I/O V13 P114 400 I/O L16 P81 322 I/O_(D5) U12 P115 403 I/O M18 P82 325 I/O_(/CSO) V12 P116 406 I/O M17 P83 328 I/O T11 P117 409 I/O N18 P84 331 I/O U11 P118 412 I/O P18 P85 334 I/O V11 P119 415 GND M16 P86 - I/O V1 P120 418 I/O N17 P87 337 I/O_(D4) U10 P121 421 I/O R18 P88 340 I/O T10 P122 424 I/O T18 P89 343 VCC R10 P123 - I/O P17 P90 349 GND R9 P124 - I/O N16 P91 349 I/O_(D3) T9 P125 427 I/O T17 P92 352 I/O_(/RS) U9 P126 430 I/O R17 P93 355 I/O V9 P127 433 I/O P16 P94 358 I/O V8 P128 436 I/O U18 P95 361 I/O U8 P129 439 SGCK3_(I/O) T16 P96 364 I/O T8 P130 442 GND R16 P97 - I/O_(D2) V7 P131 445 DONE U17 P98 - I/O U7 P132 448 VCC R15 P99 - I/O V6 P133 451 /PROG V18 P100 - I/O U6 P134 454 I/O_(D7) T15 P101 367 GND T7 P135 - Notes: 1. Indicates unconnected package pins. 2. Contributes only one bit (.I) to the boundary scan register. Boundary Scan Bit 0 = TD0.T Boundary Scan Bit 1 = TD0.0 Boundary Scan Bit 487 = BSCAN.UPD DS021 (v2.2) June 25, 2000 Product Specification Notes: 1. Indicates unconnected package pins. 2. Contributes only one bit (.I) to the boundary scan register. Boundary Scan Bit 0 = TD0.T Boundary Scan Bit 1 = TD0.0 Boundary Scan Bit 487 = BSCAN.UPD www.xilinx.com 1-800-255-7778 33 R QPRO XQ4000E/EX QML High-Reliability FPGAs Pin Description PG191 CB196 Bound Scan Pin Description PG191 CB196 Bound Scan I/O V5 P136 457 I/O K1 P169 53 I/O V4 P137 460 I/O_(A6) K2 P170 56 I/O U5 P138 463 I/O_(A7) K3 P171 59 I/O T6 T139 446 GND K4 P172 - I/O_(D1) V3 P140 469 VCC J4 P173 - I/O_(RCLK-/BUSY/RDY) V2 P141 472 I/O_(A8) J3 P174 62 I/O U4 P142 475 I/O_(A9) J2 P175 65 I/O T5 P143 478 I/O J1 P176 68 I/O_(D0*_DIN) U3 P144 481 I/O H1 P177 71 SGCK4_(DOUT*_I/O) T4 P145 484 I/O H2 P178 74 CCLK V1 P146 - I/O H3 P179 77 VCC R4 P147 - I/O_(A10) G1 P180 80 TDO U2 P148 - I/O_(A11) G2 P181 83 GND R3 P149 - I/O F1 P182 86 I/O_(A0*_WS) T3 P150 2 I/O E1 P183 89 PGCK4_(I/O*_A1) U1 P151 5 GND G3 P184 - - - P152(1) - I/O F2 P185 92 I/O P3 P153 8 I/O D1 P186 96 I/O R2 P154 11 I/O C1 P187 98 I/O_(CS1*_A2) T2 P155 14 I/O E2 P188 101 I/O_(A3) N3 P156 17 I/O_(A12) F3 P189 104 I/O P2 P157 20 I/O_(A13 D2 P190 107 - I/O T1 P158 23 - - P192(1) I/O R1 P159 26 I/O E3 P193 113 I/O N2 P160 29 I/O_(A14) C2 P194 116 GND M3 P161 - SGCK1(A15*I/O) B2 P195 119 I/O P1 P162 32 VCC D3 P196 - I/O N1 P163 35 I/O_(A4) M2 P164 38 I/O_(A5) M1 P165 41 I/O L3 P166 44 Notes: 1. Indicates unconnected package pins. 2. Contributes only one bit (.I) to the boundary scan register. Boundary Scan Bit 0 = TD0.T Boundary Scan Bit 1 = TD0.0 Boundary Scan Bit 487 = BSCAN.UPD I/O L2 P167 47 Additional XQ4010E Package Pins I/O L1 P168 50 Notes: 1. Indicates unconnected package pins. 2. Contributes only one bit (.I) to the boundary scan register. Boundary Scan Bit 0 = TD0.T Boundary Scan Bit 1 = TD0.0 Boundary Scan Bit 487 = BSCAN.UPD 34 CB196 www.xilinx.com 1-800-255-7778 No Connect Pins P5 P54 P103 P152 P192 - - - DS021 (v2.2) June 25, 2000 Product Specification R QPRO XQ4000E/EX QML High-Reliability FPGAs Ordering Information XQ 4010E -4 PG 191 M Temperature Range M = Ceramic (TC = -55C to +125C) N = Plastic (TJ = -55C to +125C) MIL-PRF-38535 (QML) Processing Device Type Number of Pins XQ4005E XQ4010E XQ4013E XQ4025E XQ4028EX Package Type CB = Top Brazed Ceramic Quad Flat Pack PG = Ceramic Pin Grid Array HQ = Plastic Quad Flat Pack BG = Plastic Ball Grid Array Speed Grade -3 -4 Revision History The following table shows the revision history for this document Date Version 05/19/98 2.1 Updates. 06/25/00 2.2 Updated timing specifications to match with commercial data sheet. Updated format. DS021 (v2.2) June 25, 2000 Product Specification Description www.xilinx.com 1-800-255-7778 35 R QPRO XQ4000E/EX QML High-Reliability FPGAs 36 www.xilinx.com 1-800-255-7778 DS021 (v2.2) June 25, 2000 Product Specification