RTH020 DATA SHEET REV C RTH020 10 GHz Bandwidth 1 GS/s Dual Track-and-Hold Features 10 GHz Small-Signal Input Bandwidth 9 GHz Mid-Scale Input Bandwidth (0.5 Vpp) 6 GHz Full-Scale Input Bandwidth (1 Vpp) 200 - 1000 MHz Sampling Rate -62 dB Hold Mode Distortion (0.5 GHz 1 Vpp VIN) -47 dB Hold Mode Distortion (3.0 GHz 0.5 Vpp VIN) < 100 fs Aperture Jitter < 250 ps Acquisition Time < 50 ps Rise Time (20 - 80%) Differential Analog Input/Output 100 - 1000 MHz Output Data Rate Output Held more than Half Clock Cycle Track Mode Select Applications Test Instrumentation Equipment RF Demodulation Systems Radar Software Radio Digital Receiver Systems High-Speed DAC Deglitching THA for Differential ADCs Digital Sampling Oscilloscopes Figure 1. Functional Diagram Product Description RTH020's unprecedented bandwidth and aperture jitter enable 1-GS/s accurate sampling of DC to multi-GHz signals. The differential-todifferential dual track-and-hold cascades two track-and-hold circuits, TH1 and TH2. It is a monolithic circuit fabricated in an 80-GHz fT GaAs HBT process. The RTH020 provides a held output for more than half a clock cycle, easing bandwidth requirements of subsequent circuitry relative to the case of a single trackand-hold (TH). The option to independently clock TH1 and TH2 (as low as 100 MHz) further relaxes this requirement for sub-sampling applications. Absolute Maximum Ratings Supply Voltages VCC to GND ........................................... -1 V to +6 V VEE to GND ........................................... -6 V to +1 V VCC to VEE ........................................... -1 to +11 V Input Voltages INP, INN to GND .........................................-1 to +1 V CLK1, CLK1B, CLK2, CLK2B to GND ........... -1 to +1 V TMS to GND .......................................... -6 V to +1 V Output Voltages Vterm (Output Termination Voltage) to GND .. -2.5 to +3 V Temperature Operating Temperature .......................... -30 to +70 C Case Temperature ................................ -15 to +85 C Junction Temperature ................................... +125 C Lead, Soldering (10 Seconds) ........................ +220 C Storage .............................................. -40 to 125 C Page 1 RTH020 DATA SHEET REV C Electrical Specification (Static) PARAMETER SYMBOL DC TRANSFER FUNCTION Gain Offset Voltage Common-Mode Rejection CMRR TEMPERATURE DRIFT Warm-up Time2 Gain Drift Offset Voltage Drift ANALOG SIGNAL INPUTS Full Scale Range FSR Common Mode Voltage VCM Input Resistance Input Capacitance CLOCK INPUTS, CLK1(B) AND CLK2(B) Amplitude3 Common Mode Voltage Input Resistance Input Capacitance DIGITAL INPUT, TRACK-MODE SELECT TMS High TMS Low Max. Current Draw ANALOG OUTPUT Ext. Termination Voltage Vterm Ext. Termination Resistor Rterm Common Mode Voltage Average Current Maximum Current POWER SUPPLY REQUIREMENTS Positive Supply Voltage VCC VCC Current ICC Negative Supply Voltage VEE VEE Current IEE Power Dissipation 1 2 3 TEST LEVEL MIN TYP MAX UNITS 1 2 2 -2.2 -2.0 Absolute Value 0.25 Vpp at INP and INN, in phase1 -1.8 8 dB mV dB After Power-up After Warm-up After Warm-up 2 4 4 10 s ppm/C V/C Each Lead to GND Each Lead to GND 4 2 2 2 -100 46 200 1000 0 50 250 100 54 300 mVpp mV fF Each Lead to GND Each Lead to GND 2 2 2 2 200 -250 46 200 600 0 50 250 1000 250 54 300 mVpp mV fF Open TMS -1.4V Into Lead, High 3 3 3 -0.5 -1.5 0 Open 0.75 1 -1.2 V V mA 3 3 2 3 3 0 0 50 -0.6 12 20 2 Required From Outputs To Vterm Relative to Vterm Into Each Output Lead Into Output Lead V V mA mA VCC = 5 V, VEE = -5.2 V 1 1 1 1 1 CONDITIONS, NOTE -60 -0.7 4.75 -5.45 1.4 5.0 75 -5.2 225 1.55 -0.5 5.25 -4.95 1.7 V mA V mA W Measured with low frequency sinusoidal input of same amplitude and phase at INP and INN. See Definition of Terms. The part functions immediately and reaches specification after warm-up time. For > 500 MHz sinusoidal CLK1(B), 500 to 700 mVpp (-2 to 1 dBm,pp) amplitude is recommended for combined aperture jitter and clock feed-through performance. At lower clock frequencies, use high amplitude for minimum jitter. See Theory of Operation. Page 2 RTH020 DATA SHEET REV C Electrical Specification (Dynamic) PARAMETER SYMBOL CONDITIONS, NOTE DYNAMIC TRACK MODE PERFORMANCE, SINEWAVE INPUT Track Bandwidth -3dB Gain, TH1 & TH2 In Track Mode Gain Flatness Deviation Integrated Noise Input Referred Noise Floor Input Referred DYNAMIC HOLD MODE PERFORMANCE, SINEWAVE INPUT4 Bandwidth, Small Signal bw -3dB Gain, Small Signal (< 0.1 Vpp) Bandwidth, Half Signal -3dB Gain, -6 dBfs (0.5 Vpp) Bandwidth, Large Signal BW -3dB Gain, Large Signal (1 Vpp) Gain Flatness Deviation Integrated Noise Input Referred Noise Floor Input Referred TH1 Hold Feedthrough5 500 MHz 1 Vpp Input TH1 Hold Feedthrough5 1 GHz 1 Vpp Input TH2 Hold Feedthrough6 500 MHz 1 Vpp Input TH2 Hold Feedthrough6 1 GHz 1 Vpp Input -THD/SFDR 20 MHz 1 Vpp Input -THD/SFDR 520 MHz 1 Vpp Input -THD/SFDR 1020 MHz 1 Vpp Input -THD/SFDR 1520 MHz 1 Vpp Input -THD/SFDR 3020 MHz 1 Vpp Input -THD/SFDR 5020 MHz 1 Vpp Input -THD/SFDR 20 MHz 0.5 Vpp Input -THD/SFDR 520 MHz 0.5 Vpp Input -THD/SFDR 1020 MHz 0.5 Vpp Input -THD/SFDR 1520 MHz 0.5 Vpp Input -THD/SFDR 3020 MHz 0.5 Vpp Input -THD/SFDR 5020 MHz 0.5 Vpp Input -THD/SFDR 5020 MHz 0.25 Vpp Input -THD/SFDR 5020 MHz 0.015 Vpp Input 4 5 6 TEST LEVEL MIN 2 2 4 4 1 1 1 1 4 4 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TYP MAX 1000 0.5 400 3.9 9.5 8.5 5.5 10 9 6 550 5.3 -72 -68 72/73 60/61 52/55 42/45 36/38 23/26 78/80 63/66 59/62 49/50 46/48 33/35 39/40 53/58 73/74 62/64 53/56 43/46 38/39 24/27 81/85 65/67 60/63 50/50 47/48 34/35 40/41 53/59 10.5 9.5 6.5 1 UNITS MHz dB V nV/ns GHz GHz GHz dB V nV/ns dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB For out-of-phase clocking of TH1 and TH2 with 50% duty cycle, using a low jitter 500-MHz 0-dBm sinusoidal clock passed through a passive single-to-differential balun. Distortion numbers may worsen by several dB if single-ended clocking is used. Measured with TH2 in track mode and comparing the DTH output for TH1 in track and hold mode. See Theory of Operation. Measured with TH1 in track mode. See Theory of Operation. Page 3 RTH020 DATA SHEET REV C Electrical Specification (Switching) PARAMETER SYMBOL CONDITIONS, NOTE TRACK-TO-HOLD SWITCHING AND HOLD STATE, TH1 Aperture Delay ta After V(CLK1) - V(CLK1B) Goes Neg. Jitter Free 1-GHz 0.5-Vpp CLK1(B)7,8 Aperture Jitter t At Hold Capacitors. ttrack1,min Settling Time to 1 mV ts Observed Differential Pedestal/VIN9 Diff. Droop Rate/VIN Hold Noise10 Per Sqrt(Hold Time) Minimum CLK1 Freq. fclk1,min 50% Duty Cycle Clock Maximum CLK1 Freq. fclk1,max 50% Duty Cycle Clock Maximum Hold Time11 thold1,max HOLD-TO-TRACK SWITCHING AND TRACK STATE, TH1 Acquisition Time to 1 tacq At Hold Caps, FSR Step At Input mV12 12 Max. Acq. Slew Rate dvdt,max At Hold Caps, FSR Step At Input Rise Time12 tr 20 - 80% Minimum Track Time ttrack1,min thold1,max Observed Required Accumulated Track Time Recovery Time After thold1,max Violation TRACK-TO-HOLD SWITCHING AND HOLD STATE, TH2 Aperture Delay ta2 After V(CLK2) - V(CLK2B) Goes Neg. Settling Time to 1 mV13 ts2 At DTH Output. ttrack2,min Observed Differential Pedestal/VIN14 Diff. Droop Rate/VIN Hold Noise10 Per Sqrt(Hold Time) Minimum CLK2 Freq. fclk2,min 50% Duty Cycle Clock Maximum CLK2 Freq. fclk2,max 50% Duty Cycle Clock Maximum Hold Time11 thold2,max HOLD-TO-TRACK SWITCHING AND TRACK STATE, TH2 Minimum Track Time after ttrack2,min thold2,max Observed TH1 in Hold Mode15 Required Accumulated Track Time Recovery Time After thold2,max Violation 7 8 9 10 11 12 13 14 15 TEST LEVEL MIN TYP MAX UNITS 4 3 70 +60 100 130 ps fs 4 300 ps 4 4 4 2 2 3 -2 -1 50 % %/ns V/ns MHz MHz ns 1000 5 8 4 250 4 3 2 15 2 3 ps 50 V/ns ps ns 4 ns 100 1250 20 ps ps % %/ns V/ns MHz MHz ns 0.4 3 4 4 4 4 4 2 2 3 200 1250 12 +60 300 0.25 -0.12 25 1000 10 15 0.5 ns 4 ns The clock source jitter and the aperture jitter combine in an rms manner to yield the total sampling jitter. See Definition of Terms. Device aperture jitter increases as the V(CLK1) - V(CLK1B) slew rate at the zero crossing decreases. See Theory of Operation. The differential pedestal error is proportional to the input signal. For TH1 it corresponds to a track-to-hold gain ~ -0.17 dB. This gain loss may be observed at the DTH output if TH2 is in track mode during the TH1 track-to-hold transition. The variance of the hold noise is proportional to the hold time, thold. For example, for TH1, a 4-ns hold time, thold1, gives about 100 V accumulated hold noise. TH1 and TH2 hold noise, up to the output sampling instant, should be rms added to the hold mode integrated noise of the DTH. Maximum hold time is determined by droop of single-ended hold capacitor voltages. The resulting shift of internal operating voltages is not directly observable at the DTH outputs but eventually causes device performance degradation. TH1 tacq, dvdt,max, and tr also apply to the reconstructed DTH output if sub-sampling a fast-edge repetitive wave form. Output is settled ta2 + ts2 after CLK2(B) downward transition. The differential pedestal error is proportional to the input signal. For TH2 it corresponds to a track-to-hold gain ~ 0.02 dB. ttrack2,min > ts, since the buffered TH1 output onto the TH2 hold capacitors lags behind the TH1 hold capacitor signal. Page 4 RTH020 DATA SHEET REV C Test Levels TEST LEVEL 1 2 3 4 1 TEST PROCEDURE 100% production tested at Ta = 25 C1 Sample tested at Ta = 25 C unless other temperature is specified1 Quaranteed by design and/or characterization testing Typical value only All tests are continuous, not pulsed. Therefore, Tj (junction temperature) > Tc (case temperature) > Ta (ambient temperature). This is the normal operating condition and is more stressful than a pulsed test condition. Pin Description and Pin Out P/I/O P P P I I I I I I I O O NAME GND VEE VCC TMS INP CLK1 CLK2 CLK1B CLK1B INN OUTN OUTP FUNCTION Power Supply Ground Negative Power Supply, -5.2V 5% Positive Power Supply, 5.0V 5% Track Mode Select Analog Input Clock Input 1, High = Track Mode Clock Input 2, High = Track Mode Complementary Clock Input 1 Complementary Clock Input 2 Complementary Analog Input Complementary Analog Output Analog Output Figure 2. RTH020HSD pin configuration (top view, not to scale) 13-lead ceramic/CuWbase high-speed digital (HSD) package Definitions of Terms Acquisition Time (tacq). The delay between the time that a track-and-hold circuit (TH) enters track mode and the time that the TH hold capacitor nodes track the input within some specified precision. The acquisition time sets a lower limit on the required track time during clocked operation. Aperture Delay (ta). The average (or mean value) of the delay between the hold command (input clock switched from hold to track state) and the instant at which the analog input is sampled. The time is positive if the clock path delay is longer than the signal path delay. It is negative if the signal path delay is longer than the clock path delay. Aperture Jitter ( t). The standard deviation of the delay between the hold command (input clock switched from track-to-hold state) and the instant at which the analog input is sampled, excluding clock source jitter. It is the total jitter if the clock source is jitter free (ideal). Jitter diverges slowly as measurement time increases because of "1/f" noise, important at low frequencies (< 10 kHz). The specified jitter takes into account the white noise sources only (thermal and shot noise). For high-speed samplers this is reasonable, since even long data records span a time shorter than the time scale important for 1/f noise. For white-noise caused jitter, the clock and aperture jitter can be added in an rms manner to obtain the total sampling jitter. Page 5 RTH020 DATA SHEET REV C If the underlying voltage noise mechanism of the sampling jitter has a white spectrum, the sampled signal will display a white noise floor as well. In this case, the required aperture jitter, t, to achieve a certain SNR, for a full-scale sinewave at frequency, f, is given by (B. Razavi, Principles of Data Conversion, IEEE Press, 1995, Appendix 2.1): SNR (dB) = -20 log(2ft ) If this TH is used in front of an n-bit ADC, then the ideal ADC SNDR is given by: SNDR ( dB ) = 10 log( 3 / 2) + 20 log( 2) n = 1.76 + 6.02 n In order that the TH jitter performance not limit the ADC performance, the jitter must fulfill: t 1 6 2 n f . Note that this is independent of the sampling rate, so undersampling does not improve jitter tolerance. The averaging that is often combined with undersampling in test equipment, does improve jitter tolerance (and tolerance to other white noise effects). The criterion above is sharper than the standard (incorrect) time-domain slope estimate by a factor 6. The reason is that n-bit quantization requires an rms error of (quantization step)/12, which is considerably smaller than the quantization step error implicitly allowed in the usual time-domain estimates (another 2 comes from the energy of a sine wave relative to its amplitude squared). The time-domain maximum slope argument can be appropriate for non-sinusoidal inputs, such as those encountered in instrumentation. If the rms error, V, in the maximum slope region, slope FSR/(rise time), is used to define an effective number of bits, n, then the jitter simply needs to fulfill: t rise time 2n Clock Jitter. The standard deviation of the instants of the mid-point of the relevant (rising or falling) edge of the clock source relative to the ideal instants (best fit). This jitter can be derived from the phase noise of the clock source, where the lower frequency bound of integration should correspond to the duration of a measurement record that the source will be used for. Common-Mode Rejection Ratio (CMRR). Proportionality coefficient of the differential output and the common mode component of input signal. If an ideal symmetric input is available, CMR is the ratio of the differential output to the input on either input pin. A highquality 50-ohm splitter may be used to generate the symmetrical inputs. Full Scale Range (FSR). The maximum difference between the highest and lowest input levels for which various device performance specifications hold, unless otherwise noted. Gain. Ratio of output signal magnitude to input signal magnitude. For sinewave inputs, it is the ratio of the amplitude of the first (main) harmonic output (HD1) to the amplitude of the input. Input Bandwidth (BW, bw). The input frequency at which the gain for sinewave inputs is reduced by 3 dB (factor 1/2) relative to its average value at low frequencies. The low frequency range is defined as the range including DC over which the gain stays essentially constant. The high frequency range is characterized by an increase in gain variation versus frequency, at least including the eventual monotonic decrease of the gain ("roll-off"). The input bandwidth tends to be input amplitude dependent. It is normally largest for very small inputs (small signal bandwidth, bw) and smallest for FSR inputs (large signal bandwidth, BW). Settling Time (ts). The delay between the time that a track-and-hold circuit (TH) enters hold mode and the time that the TH hold capacitor nodes settle to within some specified precision. The settling time sets a lower limit on the required hold time during clocked operation. Spectrum. The finite Fourier transform (FFT) of the discrete-time-sampled TH output. Ideally, this is obtained with a very high-resolution ADC quantizing the TH output with a clock rate locked to the TH clock (the ADC may be clocked at a slower rate than the TH). In the case of a dual Page 6 RTH020 DATA SHEET REV C TH (DTH), we can also use the beat frequency test, where the input frequency is close to an integer multiple of the clock frequency, and the DTH output is fed directly into a spectrum analyzer. The DTH output then contains little high frequency energy and the low frequency part of the spectrum analyzer sweep accurately represents the TH spectrum that would have been obtained with the ADC method. Spurious Free Dynamic Range (SFDR). The ratio of the magnitude of the first (main) harmonic, HD1, and the highest other harmonic (or nonharmonic other tone, if present), as observed in the TH spectrum. The input is FSR, unless otherwise noted. SFDR in dB is given by 20 log(SFDR as amplitude ratio), and is generally positive. Total Harmonic Distortion (THD). The ratio of the square root of the sum of the harmonics 2 to 5 to the amplitude of the first (main) harmonic in the TH spectrum. THD in dB is given by 20 log(THD as amplitude ratio), and is generally negative. Figure 3. Timing diagram for out-of-phase clocking of TH1 and TH2 Page 7 RTH020 DATA SHEET REV C Theory of Operation The DTH chip contains two TH's, TH1 and TH2, in series, together with clock shaping circuitry, BUFFER1 and BUFFER2, and a 50-ohm output driver, OUTBUF (Figure 1). To maximize dynamic range and insensitivity to noise, all nonDC internal circuits and all non-DC inputs and outputs are differential. TH1 determines the dynamic sampled-mode performance of the DTH. Its sampling bridges exploit the ultra-high speed of the Schottky diodes available in the GaAs HBT process. TH1 clock inputs, CLK1 and CLK1B, should be driven by a low-jitter clock source. TH2 is similar to TH1, except that its bandwidth requirement is lower and its gain is closer to unity. The DTH receives a differential analog input signal at inputs INP and INN, which is sampled on the TH1 hold capacitors upon a falling transition of its differential clock voltage V(CLK1) - V(CLK1B), after an aperture delay, ta, see Figure . TH1's aperture delay is positive, nominally 60 ps. The sampling instant is affected by clock source jitter (off-chip) and aperture jitter (caused by onchip noise). From the Definition of Terms, the required total sampling jitter for sampling a 1GHz 1-Vpp sine wave with 10-bit accuracy is 127 fs. The aperture jitter of the RTH020 is less than 100 fs for a 1-GHz 0.5-Vpp TH1 clock, CLK1(B). Using rms addition of jitter, the clock source jitter must be less than 80 fs (over the measurement record time) for direct 10-bit sampling of GHz range signals. Given a noise variance, V, of the on-chip clock buffer, its aperture jitter, t, is inversely proportional to the clock buffer gain and the slew rate of the incoming clock at the zero-crossing point: V t = . gain x slew rate For low slew rates or frequencies, the clock buffer gain is constant and its aperture jitter is inversely proportional to the input clock slew rate, improving with increasing slew rate. For high slew rates or high frequencies, the jitter increases again, because the buffer gain drops steeply. For the RTH020, the clock buffer gain is still roughly constant up to 1 GHz, so that the aperture jitter is inversely proportional with the slew rate of the incoming clock. In the above equation, we have V/gain 0.15 mV. The RTH020 aperture jitter at various slew rates can then be estimated. For example, a 1-GHz 0.5Vpp sinusoidal CLK1(B) signal corresponds to a slew rate ~ 1.6 V/ns, correctly yielding an aperture jitter < 100 fs. The held and buffered output of TH1, VTH1, is sampled on the TH2 hold capacitors upon a falling transition of its differential clock voltage V(CLK2) - V(CLK2B), after an aperture delay closely equal to that of TH1. This allows simple out-of-phase clocking of TH1 and TH2 by having opposite phases for CLK1(B) and CLK2(B). Aperture jitter of TH2 is irrelevant, since the slew rate of the TH2 input is equal to the TH1 differential droop rate, about 1000x lower than the input slew rate for TH1 for a 1-GHz 1-Vpp sine wave. TH2 can be in track mode before TH1 switches to hold, but a minimum track time of TH2 after TH1 enters hold mode must be observed to ensure that TH2 has fully acquired the TH1 output (ttrack2,min). Hold mode feedthrough, or in-to-out hold-mode gain in dB, again is important for TH1 and not for TH2, since any distortion on the held TH1 signal by a rapidly varying TH1 input will be sampled by TH2, and can not be removed. RTH020's TH1 hold mode feedthrough performance is more than sufficient for 10-bit sampling of GHz range signals. After a TH1 postamplifier, TH2 produces an output VTH2. For out-of-phase clocking, the delay from the hold instant of TH1 to the ideal sampling time of circuitry after TH2 is close to one full clock cycle, for example 1 ns at a 1-GHz sampling rate. The TH2 output is flat for more than half a clock cycle, which eases the bandwidth requirement of subsequent circuitry. Page 8 RTH020 DATA SHEET REV C This is true, even though a small glitch will be present at the transition from track to hold of TH2 and the output is only 10-bit accurate during the latter part of half a clock cycle. Lower limits for the sampling rates of TH1 and TH2 are set by single-ended hold-mode droop rates, and lead to the specification of maximum hold times (thold1,max and thold2,max). For longer hold times, the DTH must be allowed sufficient recovery time during track phase (or a sequence of track phases), so it can return to normal operation mode. The bandwidth of subsequent circuitry can be minimal if TH2 is clocked at its lowest recommended frequency, 100 MHz. Since TH1 should be clocked at least at 200 MHz, and possibly faster to meet jitter requirements, CLK1(B) and CLK2(B) can be chosen different, as long as they are locked to each other with a proper phase relationship. Minimum required single-pole bandwidth at the output for 10-bit precision is (10ln2/2) x fCLK2, or approximately 1.1fCLK2. In practice, <200 MHz bandwidth of subsequent circuitry would be sufficient, if fCLK2 is 100 MHz. One digital input, Track Mode Select (TMS), is provided to put both TH's in track mode, independent of the clock signals. The bandwidth of the DTH is substantially lower in this mode than in the sampled mode. The TMS is useful for low sample-rate operation, including DC testing. Signal Descriptions The RTH020 inputs are terminated on-chip with 50 to GND. This automatically protects against off-chip high-impedance high-voltage disturbances. The absolute maximum rated voltage at input termination resistors is 1 V, at 20 mA current. The RTH020 is designed for 1Vpp differential input signals, and can accept common-mode offsets up to 100 mV. If operated in single-ended mode, terminate the complementary input off-chip with 50 to the same common mode as the driven input. The single-ended FSR is half that of the differential FSR. Distortion in the single-ended mode can be up to 6 dB higher than in differential mode, and differential input should be used for optimal performance. The INP and INN inputs are equivalent, except for the polarity of their effect on OUTP and OUTN. All four clock input signals are terminated onchip with 50 to GND. For lowest clock source jitter, use a sinusoidal clock source. Use differential clock signals for optimal performance. Large CLK1(B) amplitude benefits aperture jitter performance, small CLK1(B) and CLK2(B) amplitudes minimizes distortion due to clock feed-through in the higher clock frequency range (500 to 1000 MHz). Independent of the clock waveform, clock slew rates < 2 V/ns are recommended to minimize clock feed-through related distortion. In case of single-ended clocking the complementary input(s) can be terminated directly to GND (lowest noise, clock waveform distortion is not critical). Distortion for single-ended clocks can be several dB higher than for differential clocks, and differential clocks should be used for optimal performance. The track-mode select, TMS, can simply be left open for the (default) sampled-mode operation of the RTH020. Grounding the TMS puts both track-and-holds, TH1 and TH2, in track-mode. In this state, the TMS draws up to 0.75 mA of current. Due to its highly differential design, the RTH020 requires relatively modest power supply decoupling. The 0.01 F capacitors VEE-toGND and VEE-to-VCC (Figure 4) should be placed as close to the package as possible. Larger low frequency power supply decoupling capacitors, VEE-to-GND and VCC-to-GND, should be placed within 1 inch of the RTH020. Depending on the expected noise on the supplies more capacitors in parallel may need to be used. With low-impedance supplies that are very quiet (no digital circuitry), the RTH020 can also perform well with no external decoupling at all. Page 9 RTH020 DATA SHEET REV C Typical Operating Circuit Figure 4. Typical interface circuit (sampled mode, connect TMS to GND for track mode) All differential inputs are terminated on-chip with 50 to GND Die Plot and Pad Arrangement The inputs and output of the RTH020 are arranged in signal-ground-signal (SGS) configurations on opposite sides of the die (Figure 5). The clock signals come in under an orthogonal direction, which reduces inductive coupling to the signal path, both for bond wires and for package leads. The part does not require other components inside the package, since sufficient bypass capacitance is supplied on-chip. Figure 5. RTH020 die photo and pad arrangement Die size: 75 x 55 x 7 mils (1.899 x 1.375 x 0.178 mm) Pad pitch: 5.91 mil (0.150 mm) Page 10 RTH020 DATA SHEET REV C Package Information The high-speed digital (HSD) package is a 13lead full-custom package. The leads are trimmed to 0.040 inch (1.02 mm) length. The thermal impedance (junction to base) is approximately 7.5 C/W. 13X .005 9X .050 13X .040 .111 MAX. 2X .055 PIN 1 .260 .095 .031 .015 2X .030 13X .010 Figure 6. RTH020HSD package outline, dimensions shown in inches, tolerance 0.003 inch Ordering Information PART NUMBER RTH020HSD RTH020DIE EVRTH020HSD TFRTH020HSD 16 PACKAGE TYPE 13-Lead HSD Package 16 Die Evaluation Kit with RF Board Test Fixture with RF Board/RF Socket TEMPERATURE RANGE -30 to +70 C 0 to +100 C -30 to +70 C -30 to +70 C Die performance is as good as or better than that of the packaged part. Page 11