=, CYPRESS Features CMOS for optimum speed/power High speed 18 ns address set-up 12 ns clock to output Low power 495 mW (commercial) 660 mW (military) Synchronous and asynchronous output enables CY7C235A 1K x 8 Registered PROM Slim, 300-mil, 24-pin plastic or her- metic DIP or 28-pin LCC and PLCC @ 5V 10% Vcc, commercial and military e TTL-compatible VO Direct replacement for bipolar PROMs e Capable of withstanding greater than 2001V static discharge Functional Description The CY7C235A is a high-performance utilize proven EPROM floating gate tech- nology and byte-wide intelligent program- ming algorithms. The CY7C235A replaces bipolar devices pin for pin and offers the advantages of lower power, superior performance, and high programming yield. The EPROM cell requires only 12.5V for the super- voltage, and low current requirements allow for gang programming. The EPROM cells allow for each memory lo- cation to be tested 100%, as each loca- tion is written into, erased, and repeat- * On-chip edge-triggered registers 1024 word by 8 bit electrically program- edly exercised prior to encapsulation. Programmable asynchronous mable read only memory packaged ina Each PROM is also tested for AC per- registers (INIT) slim 300-mil plastic or hermetic DIP, formance to guarantee that the product EPROM technology, 100% 28-pin leadless chip carrier, or 28-pin plas- will meet AC specification limits after programmable tic leaded chip carrier. The memory cells customer programming. Logic Block Diagram Pin Configurations NK DIP INIT > 0, }a Ag _] LN Pa Os Ag 4 noo sou PROGRAMMABLE T Vi wuinprexeal | Ar [| Os Ag | oO 8-BIT a5 EDGE- O% 4s appness =| TRIGGERED DECODER [| Su] REGISTER . # % Ag J = 3 Az O2 COLUMN c2a5A-2 A, ] ADDRESS LCC/PLCC Aa ' Top View Os 2eetSeg he 25e E cP - iNT Le A Es Ay cP Es Ag NC NC 209 O7 Op 194 Og E 12 1314 151637 18 C235A-1 * a oe 2559 cossa-s Selection Guide 7C235A-18 7C235A 25 7C235A-30 7C235A40 Minimum Address Set-Up Time (ns) 18 25 30 40 Maximum Clock to Output (ns) 12 12 1S 20 Maximum Operating Commercial 90 90 90 90 Current (mA) Military 120 120 120CYPRESS CY7C235A Maximum Ratings (Above which the useful life may be impaired. For uscr guidelines, Static Discharge Voltage ........- 0.0000 eee eee >2001V not tested.) (per MIL-STD-883. Method 3015) Storage Temperature ........ 20.0. 0000 65C ta +130C Latch-Up Current 20 .0..0... 0.00 0c eee eee >200 mA Ambient Temperature with Operating Range Power Applied ............0.0.-0000-- 35C to +125C + . Ambient Supply Voltage to Ground Potential . . (Pin 34 to Pin 12 for DIP) ............--.. U5V to ~ 7.0V Range Temperature Vou DC Voltage Applied ty Outputs Commercial OFC to + 70C SV 10% in High Z State ............0....000, .. TUSYV to 7.0V Industriall!) ~ 40C to +85C 5V +10% DC Input Voltage ..... ae 3.0 to 4 7.0V Military] 85C to F128 C SV #10 DC Program Voltage (Pins 7.18, 20 for DIP) ......... 3.0V Electrical Characteristics Over Operating Rangel? Parameter Description Test Conditions Mina Max. Unit Vou Output HIGH Voltage Voc = Min. Ion = 4.0 mA 2.4 Vv Vin = Vin or Vit VoL Output LOW Voltage Vic = Min, IoL = 16 mA 0.4 Vv Vin = Vie or Vit Vu Input HIGH Level Guaranteed Input Logical HIGH Voltage for 2.0 Vv Ali Inputsl4] Vit Inpul LOW Level Guaranteed Input Logical LOW Voltage for All 0.8 v Inputs Ix Input Leakage Current GND < Vin < Vcc -10 +10 WA Vep Input Clamp Diode Voltage Note 5 loz Output Leakage Current GND < Vout <= Vcc Output Disabled|*] -10 +10 LA los Output Short Circuit Current Vic = Max. Vout = 0.0V/6] 20 90 mA lec Power Supply Current lour = 0 mA, Commercial 90 mA Vic = Max. Military 120 Vpp Programming Supply Voltage 12 13 Vv Ipp Programming Supply Current 50 mA Vine Input HIGH Programming Voltage 3.U Vv Vitp {Input LOW Programming Voltage 0.4 Vv Capacitance!) Parameter Description Test Conditions Max. Unit CIN Input Capacitance Ty = 28C. f = 1 MHz, Voc =5.0V 10 pF Cour Output Capacitance 10 pF Notes: 1. Contact a Cypress tepresentative for industrial temperatus - range specifications. 2. Ty is the instant on case temperature. 3. See the last page of tl is specification for Group A subgroup te -ting in- formation. 4. For devices using the synchronous enable. the device must be clocked after applying these voltages to perform this measurement. 5. See Intreduction to CMOS PROMs in this Data Book for general in- formation on testing. 6. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.CY7C235A > BP Crernss AC Test Loads and Waveforms!>! Ai 2502 R41 250!) SV SV 0 ALL INPUT PULSES OUTPUT OUTPUT 3.0V R2 R2 50 pF 1 1672 5 pF I 1672 GND lL IncLUDING-L INCLUDING + = t- <5ns =5ns JIG AND = JiG AND = = SCOPE SCOPE C2a5A-4 C235A-5 (a} Normal Load (b) High Z Load Equivalent to: THEVENIN EQUIVALENT 40082 OUTPUT owa 2.0V Operating Modes The CY7C235A incorporites a D-type, master-slave register on chip, reducing the cost and size of pipelined microprogramn ed systems and applications where accessed PROM data is sto ed temporarily in a register. Additional flexibility is provided wth synchronous (Es) and asynchronous (E) output enables : nd asynchronous initialzatio 1 (INIT). Upon power-up, the synchronous enable (Es) flip-flop will bc in the set cundition causing the outputs (Qy O-) to be in the OFF or high-impedance state. Data is read by applying the memory lo- cation to the address input (Ap Ag) and a logic LOW to the n- able (Es) input. The stored data is accessed and loaded into he master flip-flops of the data register during the address set up time. At the next LOW-to-HIGH transition of the clock (CP), data is transferred to the slave flip-flops. which drive the out tut buffers, and the accessed data will appear at the outputs (O. O7), provided the asynchronous enable (E) is also LOW, The outputs may be disab:ed at any time by switching the asynch- ronous enable (E) to a logic HIGH, and may be returned to he active state by switching (ie enable to a logic LOW. Regardless of the condition of E, the outputs will go to the (FF or high-impedance state upon the next positive clock edge ater the synchronous enable (F's) input is switched to a HIGH leve . If the synchronous enable pin is switched to a logic LOW, the sut se- quent positive clock edge will return the output to the active stite if E is LOW. Following a positive clock edge. the address and + vn- chronous enable inputs ate free to change sinve no change in 'he output will oceur until thy next LOW-to-HIGH transition of the clock. This unique feature allows the CY7C235A decoders ind sense amplifiers to access the next location while previously id- dressed data remains stable on the outputs. System timing is simplified in that the on-chip cdge-triggered vg- ister allows the PROM clock to be derived directly from the ys- tem clock without introducing race conditions. The on-chip regis- ter timing requirements are similar to those of discrete registers available in the market. The CY7C235A has an asynchronous initialize input (FNIT) The initialize function is useful during power-up and time-out se- quences and can facilitate implementation of other sophisticated functions such as a built-in jump start address. When activ ated the initialize control input causes the contents of a user pro- grammed L025th 8-bit word ta be loaded into the on-chip register, Each bit is programmable and the initialize function can be used to load any desired combination of Is and Os into the register. [In the unprogrammed state, activating [NIT will generate a register CLEAR (all outputs LOW). ff.all the bits of the initialize word are programmed. activating FNTT performs a register PRE SET (all outputs HIGH). Applying a LOW to the INTF input causes an immediate load of the programmed initialize word into the muster and slave flip- flops of the register, independent of all other inputs, including the clock (CP). The initialize data will appear at the device vutputs after the outputs are enabled by bringing the asynchronous enable (E) LOW. When power is applicd the (internal) synchronous enable flip-flop will be in a state such that the outputs will be in the high-impe- dance state. In order to enable the outputs, a clock must oveur and the Eg input pin must be LOW at least a set-up time prior to the clock LOW-to-HIGH transition. The E input may then be used to enable the outputs. When the asynchronous initialize input, INIT. is LOW, the data in the initialize byte will be asynchronously loaded into the output register. H will not, however, uppear on the output pins until they are enabled, as deseribed in the preceding paragraph.CY7C235A CYPRESS Switching Characteristics Over Operating Rangel? I 7C235A18 | 7C235A~25 | 7C235A30 | 7C235A-40 Parameter Description Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit tsa Address Set-Up to Clock HIGH 18 25 30 40 ns tHa Address Hold from Clock HIGH 0 0 0 0 ns tco Clock HIGH to Valid Output 12 12 iS 20 ns tpwe Clock Pulse Width 12 12 15 20 ns IsEs Es Set-Up to Clock HIGH 10 10 10 15 ns thes Es Hold from Clock HIGH 5 5 5 5 ns tol Delay from INIT to Valid Output 20 25 25 35 ns tri INIT Recovery to Clock HIGH 15 20 20 20 ns tpwi INIT Pulse Width 15 20 20 25 tis tcos Inactive to Valid Output from Clock HIGHI7] 15 20 20 25 ns tuzc Inactive Output from Clock HIGHI7] 15 20 20 25 ns tpoE Valid Output from E LOW 15 20 20 25 ns tHze Inactive Output from E HIGH 15 20 20 25 ns Note: 7. Applies only when the synchronous (Es) function is used. Switching Waveforms!) Ao Ato Es ses | tHEs tses | tHes cP tpwo tewo tpwe Qo - O7CY7C235A SP myress Programming Information Programming support is available from Cypress as well as froma see the PROM Programming Information located at the end of number of third-party software vendors. For detailed program- this section. Programming algorithms can be obtained from any ming information, including a listing of software packages, please Cypress representative. Table 1. Mode Selection Pin Functionl] Read or Output Disable Ao, A3 ~ Ag Al Ay cP Es E INIT 07 - Oo Mode Other Ag, Az Ag At Ar | PGM VFY E Vpp Dy Do Read Ap. A3 Ag | Ar | Aa x Vi. Vit Vin O7 ~ Op Output Disable Ag, Ay ~ Ay Ay A2 x Vin x Vin High Z Output Disable Ag, A3 Ag Al A2 x x Vin Vin High Z Initialize Ag, A3 Ag Ay Ad x x Vit Vit Init Byte Program Ag Ax- Ao | Ar | Az | Virp | Vine | Vinp Vpp D7 - Do Program Verify Ap, Aa Ao Al A2 Vine Vitp Vine Vpp O7 - Oo Program Inhibit Ao, Aa Ag Ay A; Vine Vine Vinp Vpp High Z Intelligent Program Ag, Aa Ag Ay Ad Vine View Vine Vpp D7 Do Program Initialize Byte Ay, Ag - Ao | Vep | Vine | Vine Vinp Vinp Vpp Dz - Do Blank Check Ag, A3 Ag Ay Ad Vine VILp Vinp Vpp Zeros Note: 8. X = don't care but not to exceed Veco 45%. DIP LCC/PLCC Top View Top View 9 9 LEZZL FZ 4321 282726 Figure 1. Programming PinoutsTypical DC and AC Characteristics g 0.98 NORMALIZED NORMALIZED log, NORMALIZED CLOCK-TO-OUTPUT TIME 4.0 0.8 0.6 1.02 1,00 0.96 0.94 0.92 0.90 0.88 ~ 55 7 CY7C235A i CYPRESS NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE Ta = 25C 1 = fax a 45 5.0 5.5 SUPPLY VOLTAGE (V) 6.0 CLOCK TO OUTPUT TIME vs. TEMPERATURE 25 125 AMBIENT TEMPERATURE (C) NORMALIZED SUPPLY CURRENT vs. CLOCK PERIOD Vec = 5.5V Ty = 25C 25 50 75 CLOCK PERIOD {ns) 100 NORMALIZED SUPPLY CURRENT, CLOCK TO OUTPUT TIME vs. AMBIENT TEMPERATURE = vs. Vee 1.2 = 16 5 E14 Bil PS 2 , a 2 12 3 10 3 $ , g 0 [a ? a $ og a N 08 z Ta = 25C 08 Z 06 i ~55 25 18 9 40 45 50 55 60 AMBIENT TEMPERATURE (C) SUPPLY VOLTAGE (V) NORMALIZED SET-UP TIME NORMALIZED SET-UP TIME vs. SUPPLY VOLTAGE vs. TEMPERATURE 1.2 1.6 uu pS = a a F 1.0 > 1.4 a PN 6 2 a by oa nN a 1.2 a NA NX N Zz 10 3 = o Ta = 25C , Zz 0.4 | 06 40 45 50 55 60 ~ 55 25 125 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (C) TYPICAL ACCESS TIME CHANGE OUTPUT SINK CURRENT vs. OUTPUT LOADING vs. OUTPUT VOLTAGE 30.0 gz 175 E = 150 ee 125 20.0 & < 2 100 = 15.0 5 a a Vog = 5.0V a 106 5 50 Ta = 25C 5.0 Ta = 28C & Voc = 4.5V a8 0.0 0 0 200 400 600 B00 1000 00. 610 #20 30 40 CAPACITANCE (pF) OUTPUT VOLTAGE (V) C235A-9CY7C235A CYPRESS Ordering Information|! Speed (ns) Package Operating tsa | tco Ordering Code Name Package Type Range 18 | 12 | CY7C235A-18DC D14 24-Lead (300-Mil) CerDIP Commercial CY7C235A18IC J64 28-Lead Plastic Leaded Chip Carrier CY7C235A18PC P13 24-Lead (300-Mil) Molded DIP 25 | 12 | CY7C235A-25DC DI4 24-Lead (300-Mil) CerDIP Commercial CY7C235A255C 564 28-Lead Plastic Leaded Chip Carrier CY7C235A25PC P13 24-Lead (300-Mil) Molded DIP CY7C235A25DMB} D14 24-Lead (300-Mil) CerDIP Military CY7C235A-25LMB La4 28-Square Leadless Chip Carrier 30, | 15 | CY7C235A-30DC D14 24-Lead (300-Mil) CerDIP Commercial CY7C235A30JC J64 28-Lead Plastic Leaded Chip Carrier CY7C235A30PC P13 24-Lead (300-Mil) Molded DIP CY7C235A-30DMB] D14 24-Lead (300-Mil) CerDIP Military CY7C235A30LMB L64 28-Square Leadless Chip Carrier 40 } 20 | CY7C235A40DC Di4 24-Lead (300-Mil) CerDIP Commercial CY7C235A405C J64 28-Lead Plastic Leaded Chip Carrier CY7C235A 40PC P13 24-Lead (300-Mil) Molded DIP CY7C235A40DMB{ D14 24-Lead (300-Mil) CerDIP Military CY7C235A40LMB L64 28-Square Leadless Chip Carrier ote: 9. Most of the above products are available in industrial temperature range, Contact a Cypress representative for specifications and product availability. MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Subgroups Vou 1, 2,3 VoL 1, 2,3 Vin 1,2,3 Vi. 1,2,3 Tix 1, 2, 3 loz 1, 2, 3 Icc 1,2,3 Switching Characteristics Parameter Subgroups tsa 7, 8, 9, 10, 11 tHa 7, 8, 9, 10, 11 tco 7, 8,9, 10, 11 Document #: 3800229-C