November 2011 Doc ID 16892 Rev 20 1/38
1
M24128-BW
M24128-BR M24128-BF
128 Kbit serial I²C bus EEPROM
Features
■Supports the I2C bus modes:
– 400 kHz Fast-mode
– 100 kHz Standard-mode
■Single supply voltages:
– 2.5 V to 5.5 V (M24128-BW)
– 1.8 V to 5.5 V (M24128-BR)
– 1.7 V to 5.5 V (M24128-BF)
■Write Control input
■Byte and Page Write
■Random and Sequential Read modes
■Self-timed programming cycle
■Automatic address incrementing
■Enhanced ESD/latch-up protection
■More than 1 Million write cycles
■More than 40-year data retention
■Packages
–ECOPACK2
® (RoHS-compliant and
Halogen-free)
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
WLCSP (CS)
UFDFPN8
(MB, MC)
www.st.com
Contents M24128-BW, M24128-BR, M24128-BF
2/38 Doc ID 16892 Rev 20
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.1 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.6 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.7 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.8 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.9 ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . . . 17
4.10 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 18
4.11 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.12 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.13 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.14 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.15 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
M24128-BW, M24128-BR, M24128-BF Contents
Doc ID 16892 Rev 20 3/38
5 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
List of tables M24128-BW, M24128-BR, M24128-BF
4/38 Doc ID 16892 Rev 20
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Address most significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Address least significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. Operating conditions (M24xxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 8. Operating conditions (M24xxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 9. Operating conditions (M24xxx-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 11. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 12. DC characteristics (M24xxx-W, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 13. DC characteristics (M24xxx-W, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 14. DC characteristics (M24xxx-R - device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 15. DC characteristics (M24xxx-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 16. AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 17. SO8 narrow – 8 lead plastic small outline, 150 mils body width,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 18. TSSOP8 – 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 30
Table 19. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 20. WLCSP, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 21. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 22. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
M24128-BW, M24128-BR, M24128-BF List of figures
Doc ID 16892 Rev 20 5/38
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. WLCSP connections (top view, marking side, with balls on the
underside) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Maximum RP value versus bus parasitic capacitance (C) for an I2C bus . . . . . . . . . . . . . . 10
Figure 6. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . 28
Figure 15. TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 16. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 × 3mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 17. WLCSP, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Description M24128-BW, M24128-BR, M24128-BF
6/38 Doc ID 16892 Rev 20
1 Description
The M24128-BW, M24128-BR and M24128-BF devices are I2C-compatible electrically
erasable programmable memories (EEPROM). They are organized as 16384 × 8 bits.
Figure 1. Logic diagram
I2C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The
devices carry a built-in 4-bit device type identifier code (1010) in accordance with the I2C
bus definition.
The device behaves as a slave in the I2C protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are initiated by a Start condition, generated
by the bus master. The Start condition is followed by a device select code and Read/Write
bit (RW) (as described in Ta b l e 2 ), terminated by an acknowledge bit.
When writing data to the memory, the device inserts an acknowledge bit during the 9th bit
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
!)F
%% 3$!
6##
-XXX
7#
3#,
633
M24128-BW, M24128-BR, M24128-BF Description
Doc ID 16892 Rev 20 7/38
Figure 2. 8-pin package connections
1. See Package mechanical data section for package dimensions, and how to identify pin-1.
Figure 3. WLCSP connections (top view, marking side, with balls on the
underside)
Table 1. Signal names
Signal name Function Direction
E0, E1, E2 Chip Enable Input
SDA Serial Data I/O
SCL Serial Clock Input
WC Write Control Input
VCC Supply voltage
VSS Ground
3$!633
3#,
7#%
% 6##
%
!)F
VCC E1 E0
WC E2
SDA SCL VSS
ai14799
Signal description M24128-BW, M24128-BR, M24128-BF
8/38 Doc ID 16892 Rev 20
2 Signal description
2.1 Serial Clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this
signal is used by slave devices to synchronize the bus to a slower clock, the bus master
must have an open drain output, and a pull-up resistor must be connected from Serial Clock
(SCL) to VCC. (Figure 5 indicates how the value of the pull-up resistor can be calculated). In
most applications, though, this method of synchronization is not employed, and so the pull-
up resistor is not necessary, provided that the bus master has a push-pull (rather than open
drain) output.
2.2 Serial Data (SDA)
This bidirectional signal is used to transfer data in or out of the device. It is an open drain
output that may be wire-OR’ed with other open drain or open collector signals on the bus. A
pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 5 indicates how
the value of the pull-up resistor can be calculated).
2.3 Chip Enable (E0, E1, E2)
These input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2, b1) of the 7-bit device select code. These inputs must be tied to VCC
or VSS, to establish the device select code as shown in Figure 4. When not connected (left
floating), these inputs are read as low (0,0,0).
Figure 4. Device select code
2.4 Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven high. When unconnected, the signal is internally read as VIL, and
Write operations are allowed.
When Write Control (WC) is driven high, device select and Address bytes are
acknowledged, Data bytes are not acknowledged.
Ai12806
VCC
M24xxx
VSS
Ei
VCC
M24xxx
VSS
Ei
M24128-BW, M24128-BR, M24128-BF Signal description
Doc ID 16892 Rev 20 9/38
2.5 VSS ground
VSS is the reference for the VCC supply voltage.
2.6 Supply voltage (VCC)
2.6.1 Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Ta b l e 7 , Ta bl e 8 and
Ta bl e 9 ). In order to secure a stable DC supply voltage, it is recommended to decouple the
VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the
VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (tW).
2.6.2 Power-up conditions
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
defined in Ta bl e 7 , Ta b le 8 and Ta bl e 9 . The rise time must not vary faster than 1 V/µs.
2.6.3 Device reset
In order to prevent inadvertent Write operations during power-up, a power on reset (POR)
circuit is included. At power-up (continuous rise of VCC), the device does not respond to any
instruction until VCC has reached the power on reset threshold voltage (this threshold is
lower than the minimum VCC operating voltage defined in Ta bl e 8 and Ta bl e 9 ). Until VCC
passes over the POR threshold, the device is reset and in Standby Power mode.
In a similar way, during power-down (continuous decay of VCC), as soon as VCC drops below
the POR threshold voltage, the device is reset and stops responding to any instruction sent
to it.
2.6.4 Power-down conditions
During power-down (continuous decay of VCC), the device must be in Standby Power mode
(mode reached after decoding a Stop condition, assuming that there is no internal Write
cycle in progress).
Signal description M24128-BW, M24128-BR, M24128-BF
10/38 Doc ID 16892 Rev 20
Figure 5. Maximum RP value versus bus parasitic capacitance (C) for an I2C bus
Figure 6. I2C bus protocol
1
10
100
10 100 1000
Bus line capacitor (pF)
Bus line pull-up resistor
(k )
When tLOW = 1.3 µs (min value for
fC = 400 kHz), the Rbus × Cbus
time constant must be below the
400 ns time constant line
represented on the left.
I²C bus
master M24xxx
Rbus
VCC
Cbus
SCL
SDA
ai14796b
Rbus × Cbus = 400 ns
Here Rbus × Cbus = 120 ns
4 kΩ
30 pF
SCL
SDA
SCL
SDA
SDA
Start
Condition
SDA
Input
SDA
Change
AI00792B
Stop
Condition
123 789
MSB ACK
Start
Condition
SCL 123 789
MSB ACK
Stop
Condition
M24128-BW, M24128-BR, M24128-BF Signal description
Doc ID 16892 Rev 20 11/38
Table 2. Device select code
Device type identifier(1)
1. The most significant bit, b7, is sent first.
Chip Enable address(2)
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
RW
b7 b6 b5 b4 b3 b2 b1 b0
Device select code1010E2E1E0RW
Table 3. Address most significant byte
b15 b14 b13 b12 b11 b10 b9 b8
Table 4. Address least significant byte
b7 b6 b5 b4 b3 b2 b1 b0
Memory organization M24128-BW, M24128-BR, M24128-BF
12/38 Doc ID 16892 Rev 20
3 Memory organization
The memory is organized as shown in Figure 7.
Figure 7. Block diagram
AI06899
WC
E1
E0 Control Logic High Voltage
Generator
I/O Shift Register
Address Register
and Counter
Data
Register
1 Page
X Decoder
Y Decoder
SCL
SDA
E2
M24128-BW, M24128-BR, M24128-BF Device operation
Doc ID 16892 Rev 20 13/38
4 Device operation
The device supports the I2C protocol. This is summarized in Figure 6. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always a slave in all
communications.
4.1 Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer command. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition, and will not respond unless one is given.
4.2 Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven high. A Stop condition terminates communication between the device and the
bus master. A Read command that is followed by NoAck can be followed by a Stop condition
to force the device into the Standby mode. A Stop condition at the end of a Write command
triggers the internal Write cycle.
4.3 Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
4.4 Data Input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
Device operation M24128-BW, M24128-BR, M24128-BF
14/38 Doc ID 16892 Rev 20
4.5 Memory addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Ta b l e 2 (on Serial Data (SDA), most significant bit first).
The device select code consists of a 4-bit device type identifier, and a 3-bit Chip Enable
“Address” (E2, E1, E0). To address the memory array, the 4-bit device type identifier is
1010b.
Up to eight memory devices can be connected on a single I2C bus. Each one is given a
unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the device select code is
received, the device only responds if the Chip Enable Address is the same as the value on
the Chip Enable (E0, E1, E2) inputs.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
Table 5. Operating modes
Mode RW bit WC(1)
1. X = VIH or VIL.
Bytes Initial sequence
Current Address
Read 1 X 1 Start, device select, RW = 1
Random Address
Read
0X 1Start, device select, RW = 0, Address
1 X reStart, device select, RW = 1
Sequential Read 1 X ≥ 1 Similar to Current or Random Address
Read
Byte Write 0 VIL 1 Start, device select, RW = 0
Page Write 0 VIL ≤ 64 Start, device select, RW = 0
M24128-BW, M24128-BR, M24128-BF Device operation
Doc ID 16892 Rev 20 15/38
Figure 8. Write mode sequences with WC = 1 (data write inhibited)
Stop
Start
Byte Write Dev select Byte address Byte address Data in
WC
Start
Page Write Dev select Byte address Byte address Data in 1
WC
Data in 2
AI01120d
Page Write
(cont'd)
WC (cont'd)
Stop
Data in N
ACK ACK ACK NO ACK
R/W
ACK ACK ACK NO ACK
R/W
NO ACK NO ACK
Device operation M24128-BW, M24128-BR, M24128-BF
16/38 Doc ID 16892 Rev 20
4.6 Write operations
Following a Start condition the bus master sends a device select code with the Read/Write
bit (RW) reset to 0. The device acknowledges this, as shown in Figure 9, and waits for two
address bytes. The device responds to each address byte with an acknowledge bit, and
then waits for the data Byte.
Writing to the memory may be inhibited if Write Control (WC) is driven high. Any Write
instruction with Write Control (WC) driven high (during a period of time from the Start
condition until the end of the two address bytes) will not modify the memory contents, and
the accompanying data bytes are not acknowledged, as shown in Figure 8.
Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant
Byte (Ta bl e 3 ) is sent first, followed by the Least Significant Byte (Ta b le 4 ). Bits b15 to b0
form the address of the byte in memory.
When the bus master generates a Stop condition immediately after the Ack bit (in the “10th
bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle is
triggered. A Stop condition at any other time slot does not trigger the internal Write cycle.
After the Stop condition, the delay tW, and the successful completion of a Write operation,
the device’s internal address counter is incremented automatically, to point to the next byte
address after the last one that was modified.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
4.7 Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven high, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in Figure 9.
4.8 Page Write
The Page Write mode allows up to 64 bytes to be written in a single Write cycle, provided
that they are all located in the same ‘row’ in the memory: that is, the most significant
memory address bits (b13-b6) are the same. If more bytes are sent than will fit up to the end
of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to
become overwritten in an implementation dependent way.
The bus master sends from 1 to 64 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck.
After each byte is transferred, the internal byte address counter (inside the page) is
incremented. The transfer is terminated by the bus master generating a Stop condition.
M24128-BW, M24128-BR, M24128-BF Device operation
Doc ID 16892 Rev 20 17/38
Figure 9. Write mode sequences with WC = 0 (data write enabled)
4.9 ECC (error correction code) and write cycling
The new M24128 devices offer an ECC (error correction code) logic which compares each
4-byte word with its six associated EEPROM ECC bits. As a result, if a single bit out of 4
bytes of data happens to be erroneous during a read operation, the ECC detects it and
replaces it by the correct value. The read reliability is therefore much improved by the use of
this feature.
Note however that even if a single byte has to be written, 4 bytes are internally modified
(plus the ECC word), that is, the addressed byte is cycled together with the three other bytes
making up the word. It is therefore recommended to write by packets of 4 bytes in order to
benefit from the larger amount of write cycles.
All M24128 devices are qualified at 1 million (1 000 000) write cycles; the new M24128
devices offering the ECC improvement are qualified using a cycling routine that writes to the
device by multiples of 4-byte words.
Stop
Start
Byte Write Dev Select Byte address Byte address Data in
WC
Start
Page Write Dev Select Byte address Byte address Data in 1
WC
Data in 2
AI01106d
Page Write
(cont'd)
WC (cont'd)
Stop
Data in N
ACK
R/W
ACK ACK ACK
ACK ACK ACK ACK
R/W
ACKACK
Device operation M24128-BW, M24128-BR, M24128-BF
18/38 Doc ID 16892 Rev 20
Figure 10. Write cycle polling flowchart using ACK
4.10 Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (tw) is
shown in Ta bl e 1 6 , but the typical time is shorter. To make use of this, a polling sequence can
be used by the bus master.
The sequence, as shown in Figure 10, is:
1. Initial condition: a Write cycle is in progress.
2. Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
3. Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Write cycle
in progress
AI01847d
Next
operation is
addressing the
memory
Start condition
Device select
with RW = 0
ACK
Returned
YES
NO
YESNO
ReStart
Stop
Data for the
Write operation
Device select
with RW = 1
Send address
and receive ACK
First byte of instruction
with RW = 0 already
decoded by the device
YESNO Start
condition
Continue the
Write operation
Continue the
Random Read operation
M24128-BW, M24128-BR, M24128-BF Device operation
Doc ID 16892 Rev 20 19/38
Figure 11. Read mode sequences
1. The seven most significant bits of the device select code of a Random Read (in the 1st and 4th bytes) must
be identical.
Start
Dev select * Byte address Byte address
Start
Dev select Data out 1
AI01105d
Data out N
Stop
Start
Current
Address
Read
Dev select Data out
Random
Address
Read
Stop
Start
Dev select * Data out
Sequential
Current
Read
Stop
Data out N
Start
Dev select * Byte address Byte address
Sequential
Random
Read
Start
Dev select * Data out 1
Stop
ACK
R/W
NO ACK
ACK
R/W
ACK ACK ACK
R/W
ACK ACK ACK NO ACK
R/W
NO ACK
ACK ACK ACK
R/W
ACK ACK
R/W
ACK NO ACK
Device operation M24128-BW, M24128-BR, M24128-BF
20/38 Doc ID 16892 Rev 20
4.11 Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device’s internal address counter is
incremented by one, to point to the next byte address.
4.12 Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 11) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The
device acknowledges this, and outputs the contents of the addressed byte. The bus master
must not acknowledge the byte, and terminates the transfer with a Stop condition.
4.13 Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges
this, and outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 11, without acknowledging the Byte.
4.14 Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 11.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory address
00h.
4.15 Acknowledge in Read mode
For all Read commands, the device waits, after each byte read, for an acknowledgment
during the 9th bit time. If the bus master does not drive Serial Data (SDA) low during this
time, the device terminates the data transfer and switches to its Standby mode.
M24128-BW, M24128-BR, M24128-BF Initial delivery state
Doc ID 16892 Rev 20 21/38
5 Initial delivery state
The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).
6 Maximum rating
Stressing the device outside the ratings listed in Ta b l e 6 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the Operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.
Table 6. Absolute maximum ratings
Symbol Parameter Min. Max. Unit
TAAmbient operating temperature –40 130 °C
TSTG Storage temperature –65 150 °C
TLEAD Lead temperature during soldering see note (1)
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
°C
VIO Input or output range –0.50 6.5 V
IOL DC output current (SDA = 0) - 5 mA
VCC Supply voltage –0.50 6.5 V
VESD Electrostatic discharge voltage (human body model)(2)
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500 Ω, R2=500 Ω)
–4000 4000 V
DC and AC parameters M24128-BW, M24128-BR, M24128-BF
22/38 Doc ID 16892 Rev 20
7 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 7. Operating conditions (M24xxx-W)
Symbol Parameter Min. Max. Unit
VCC Supply voltage 2.5 5.5 V
TA
Ambient operating temperature (device grade 6) –40 85 °C
Ambient operating temperature (device grade 3) –40 125 °C
Table 8. Operating conditions (M24xxx-R)
Symbol Parameter Min. Max. Unit
VCC Supply voltage 1.8 5.5 V
TAAmbient operating temperature –40 85 °C
Table 9. Operating conditions (M24xxx-F)
Symbol Parameter Min. Max. Unit
VCC Supply voltage 1.7 5.5 V
TA
Ambient operating temperature (device grade 6) –40 85 °C
Ambient operating temperature (device grade 5) –20 85 °C
Table 10. AC test measurement conditions
Symbol Parameter Min. Max. Unit
CLLoad capacitance 100 pF
Input rise and fall times 50 ns
Input levels 0.2VCC to 0.8VCC V
Input and output timing reference levels 0.3VCC to 0.7VCC V
M24128-BW, M24128-BR, M24128-BF DC and AC parameters
Doc ID 16892 Rev 20 23/38
Figure 12. AC test measurement I/O waveform
Table 11. Input parameters
Symbol Parameter Test condition Min. Max. Unit
CIN Input capacitance (SDA) 8 pF
CIN Input capacitance (other pins) 6 pF
ZWCL(1)
1. Characterized only.
WC input impedance VIN < 0.3VCC 50 200 kΩ
ZWCH(1) WC input impedance VIN > 0.7VCC 500 kΩ
tNS(1) Pulse width ignored
(Input filter on SCL and SDA) 100 ns
Table 12. DC characteristics (M24xxx-W, device grade 6)
Symbol Parameter Test condition
(in addition to those in Tabl e 7 )Min. Max. Unit
ILI
Input leakage current
(SCL, SDA, E2, E1, E0)
VIN = VSS or VCC
device in Standby mode ± 2 µA
ILO Output leakage current SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC ± 2 µA
ICC Supply current (Read) 2.5 V < VCC < 5.5 V, fc = 400 kHz 2 mA
ICC0 Supply current (Write) During tW, 2.5 V < VCC < 5.5 V 5(1)
1. Characterized value, not tested in production.
mA
ICC1
Standby supply current Device not selected(2), VIN = VSS
or VCC, VCC = 5.5 V
2. The device is not selected after power-up, after a Read command (after the Stop condition) or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write command).
5µA
Standby supply current Device not selected(2), VIN = VSS
or VCC, VCC = 2.5 V 2µA
VIL
Input low voltage (SDA,
SCL, WC)–0.45 0.3VCC V
VIH
Input high voltage
(SCL, SDA) 0.7VCC 6.5 V
Input high voltage
(WC, E0, E1, E2) 0.7VCC VCC+0.6 V
VOL Output low voltage IOL = 2.1 mA, VCC = 2.5 V or
IOL = 3 mA, VCC = 5.5 V 0.4 V
AI00825B
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Input and Output
Timing Reference Levels
Input Levels
DC and AC parameters M24128-BW, M24128-BR, M24128-BF
24/38 Doc ID 16892 Rev 20
Table 13. DC characteristics (M24xxx-W, device grade 3)
Symbol Parameter Test condition
(in addition to those in Table 7 )Min. Max. Unit
ILI
Input leakage current (SCL, SDA,
E2, E1, E0)
VIN = VSS or VCC
device in Standby mode ± 2 µA
ILO Output leakage current SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC ± 2 µA
ICC Supply current (Read) 2.5 V < VCC < 5.5 V, fc = 400 kHz 2 mA
ICC0 Supply current (Write) During tW, 2.5 V < VCC < 5.5 V 5(1) mA
ICC1 Standby supply current Device not selected(2), VIN = VSS or
VCC, 2.5 V < VCC < 5.5 V 10 µA
VIL Input low voltage (SDA, SCL, WC) –0.45 0.3VCC V
VIH
Input high voltage (SCL, SDA) 0.7VCC 6.5 V
Input high voltage (WC, E0, E1, E2) 0.7VCC VCC+0.6 V
VOL Output low voltage IOL = 2.1 mA, VCC = 2.5 V or
IOL = 3 mA, VCC = 5.5 V 0.4 V
1. Characterized value, not tested in production.
2. The device is not selected after power-up, after a Read command (after the Stop condition) or after the completion of the
internal write cycle tW (tW is triggered by the correct decoding of a Write command).
Table 14. DC characteristics (M24xxx-R - device grade 6)
Symbol Parameter Test condition (in addition to
those in Table 8)(1) Min. Max. Unit
ILI
Input leakage current
(SCL, SDA, E2, E1, E0)
VIN = VSS or VCC
device in Standby mode ± 2 µA
ILO Output leakage current SDA Hi-Z, external voltage
applied on SDA: VSS or VCC
± 2 µA
ICC Supply current (Read) VCC = 1.8 V, fc = 400 kHz 0.8 mA
ICC0 Supply current (Write) During tW, 1.8 V < VCC < 2.5 V 3(2) mA
ICC1 Standby supply current Device not selected(3), VIN = VSS
or VCC, VCC = 1.8 V 1µA
VIL Input low voltage (SDA, SCL, WC)1.8 V ≤ VCC < 2.5 V –0.45 0.25 VCC V
2.5 V ≤ VCC < 5.5 V –0.45 0.3 VCC V
VIH
Input high voltage (SCL, SDA) 0.7VCC 6.5 V
Input high voltage (WC, E0, E1, E2) 0.7VCC VCC+0.6 V
VOL Output low voltage IOL = 1 mA, VCC = 1.8 V 0.2 V
1. If the application uses the M24128-BR at 2.5 V < VCC < 5.5 V and –40 °C < TA < +85 °C, please refer to Table 12: DC
characteristics (M24xxx-W, device grade 6) instead of the above table.
2. Characterized value, not tested in production.
3. The device is not selected after power-up, after a Read command (after the Stop condition) or after the completion of the
internal write cycle tW (tW is triggered by the correct decoding of a Write command).
M24128-BW, M24128-BR, M24128-BF DC and AC parameters
Doc ID 16892 Rev 20 25/38
Table 15. DC characteristics (M24xxx-F)
Symbol Parameter
Test condition
(in addition to those in
Table 9)
Min. Max. Unit
ILI
Input leakage current
(SCL, SDA, E2, E1, E0)
VIN = VSS or VCC
device in Standby mode ± 2 µA
ILO Output leakage current SDA Hi-Z, external voltage
applied on SDA: VSS or VCC ± 2 µA
ICC Supply current (Read) VCC =1.7 V, fc = 400 kHz 0.8 mA
ICC0 Supply current (Write) During tW, 1.7 V < VCC < 2.5
V3(1)
1. Characterized value, not tested in production.
mA
ICC1 Standby supply current Device not selected(2), VIN =
VSS or VCC, VCC = 1.7 V
2. The device is not selected after power-up, after a Read command (after the Stop condition) or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write command).
1µA
VIL
Input low voltage (SDA, SCL,
WC)
1.8 V ≤ VCC < 2.5 V –0.45 0.25 VCC V
2.5 V ≤ VCC < 5.5 V –0.45 0.3 VCC V
VIH
Input high voltage (SCL, SDA) 0.7VCC 6.5 V
Input high voltage (WC, E0, E1,
E2) 0.7VCC VCC+0.6 V
VOL Output low voltage IOL = 0.7 mA, VCC = 1.7 V 0.2 V
DC and AC parameters M24128-BW, M24128-BR, M24128-BF
26/38 Doc ID 16892 Rev 20
Table 16. AC characteristics
Test conditions specified in Tabl e 7, Table 8 and Tabl e 9
Symbol Alt. Parameter Min. Max. Unit
fCfSCL Clock frequency 400 kHz
tCHCL tHIGH Clock pulse width high 600 ns
tCLCH tLOW Clock pulse width low 1300 ns
tQL1QL2(1)
1. Characterized only, not tested in production.
tFSDA (out) fall time 20(2)
2. With CL = 10 pF.
120 ns
tXH1XH2 tRInput signal rise time (3)
3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
fC< 400 kHz.
(3) ns
tXL1XL2 tFInput signal fall time (3) (3) ns
tDXCX tSU:DAT Data in set up time 100 ns
tCLDX tHD:DAT Data in hold time 0 ns
tCLQX tDH Data out hold time 200 ns
tCLQV(4)(5)
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or
0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 5.
tAA Clock low to next data valid (access time) 200 900 ns
tCHDL tSU:STA Start condition setup time 600 ns
tDLCL tHD:STA Start condition hold time 600 ns
tCHDH tSU:STO Stop condition set up time 600 ns
tDHDL tBUF
Time between Stop condition and next Start
condition 1300 ns
tWtWR Write time 5 ms
M24128-BW, M24128-BR, M24128-BF DC and AC parameters
Doc ID 16892 Rev 20 27/38
Figure 13. AC waveforms
3#,
3$!)N
3#,
3$!/UT
3#,
3$!)N
T#(#,
T$,#,
T#($,
3TART
CONDITION
T#,#(
T$8#(T#,$8
3$!
)NPUT
3$!
#HANGE
T#($( T$($,
3TOP
CONDITION
$ATAVALID
T#,16 T#,18
T#($(
3TOP
CONDITION
T#($,
3TART
CONDITION
7RITECYCLE
T7
!)F
3TART
CONDITION
T#(#,
T8(8(
T8(8(
T8,8,
T8,8,
$ATAVALID
T1,1,
Package mechanical data M24128-BW, M24128-BR, M24128-BF
28/38 Doc ID 16892 Rev 20
8 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 14. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package
outline
1. Drawing is not to scale.
Table 17. SO8 narrow – 8 lead plastic small outline, 150 mils body width,
package mechanical data
Symbol
millimeters inches(1)
Typ Min Max Typ Min Max
A 1.75 0.0689
A1 0.10 0.25 0.0039 0.0098
A2 1.25 0.0492
b 0.28 0.48 0.0110 0.0189
c 0.17 0.23 0.0067 0.0091
ccc 0.10 0.0039
D 4.90 4.80 5.00 0.1929 0.1890 0.1969
E 6.00 5.80 6.20 0.2362 0.2283 0.2441
E1 3.90 3.80 4.00 0.1535 0.1496 0.1575
e1.27– –0.0500– –
h 0.25 0.50
k 0°8° 0°8°
SO-A
E1
8
ccc
b
e
A
D
c
1
E
h x 45˚
A2
k
0.25 mm
L
L1
A1
GAUGE PLANE
M24128-BW, M24128-BR, M24128-BF Package mechanical data
Doc ID 16892 Rev 20 29/38
L 0.40 1.27 0.0157 0.0500
L1 1.04 0.0410
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Table 17. SO8 narrow – 8 lead plastic small outline, 150 mils body width,
package mechanical data
Symbol
millimeters inches(1)
Typ Min Max Typ Min Max
Package mechanical data M24128-BW, M24128-BR, M24128-BF
30/38 Doc ID 16892 Rev 20
Figure 15. TSSOP8 – 8 lead thin shrink small outline, package outline
1. Drawing is not to scale.
Table 18. TSSOP8 – 8 lead thin shrink small outline, package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Typ. Min. Max. Typ. Min. Max.
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 1.000 0.800 1.050 0.0394 0.0315 0.0413
b 0.190 0.300 0.0075 0.0118
c 0.090 0.200 0.0035 0.0079
CP 0.100 0.0039
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 – – 0.0256 – –
E 6.400 6.200 6.600 0.2520 0.2441 0.2598
E1 4.400 4.300 4.500 0.1732 0.1693 0.1772
L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 0.0394
α0° 8° 0° 8°
TSSOP8AM
1
8
CP
c
L
EE1
D
A2A
α
eb
4
5
A1
L1
M24128-BW, M24128-BR, M24128-BF Package mechanical data
Doc ID 16892 Rev 20 31/38
Figure 16. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 × 3mm, package outline
1. Drawing is not to scale.
2. The central pad (E2 × D2 area in the above illustration) is internally pulled to VSS. It must not be allowed to
be connected to any other voltage or signal line on the PCB, for example during the soldering process.
3. The circle in the top view of the package indicates the position of pin 1.
Table 19. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to four decimal digits.
Typ Min Max Typ Min Max
A 0.550 0.450 0.600 0.0217 0.0177 0.0236
A1 0.020 0.000 0.050 0.0008 0.0000 0.0020
b 0.250 0.200 0.300 0.0098 0.0079 0.0118
D 2.000 1.900 2.100 0.0787 0.0748 0.0827
D2 (rev MB) 1.600 1.500 1.700 0.0630 0.0591 0.0669
D2 (rev MC) 1.200 1.600 0.0472 0.0630
E 3.000 2.900 3.100 0.1181 0.1142 0.1220
E2 (rev MB) 0.200 0.100 0.300 0.0079 0.0039 0.0118
E2 (rev MC) 1.200 1.600 0.0472 0.0630
e 0.500 0.0197
K 0.300 0.0118
L 0.300 0.500 0.0118 0.0197
L1 0.150 0.0059
L3 0.300 0.0118
eee(2)
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.
0.080 0.0031
$
%
:7?-%E
!
!
EEE
,
EB
$
,
%
, ,
E B
$
,
%
,
0IN
+
+
-" -#
Package mechanical data M24128-BW, M24128-BR, M24128-BF
32/38 Doc ID 16892 Rev 20
Figure 17. WLCSP, 0.5 mm pitch, package outline
1. Drawing is not to scale.
Table 20. WLCSP, 0.5 mm pitch, package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Typ. Min. Max. Typ. Min. Max.
A 0.585 0.535 0.635 0.0230 0.0211 0.0250
A1 0.230 0.205 0.255 0.0091 0.0081 0.0100
A2 0.355 0.330 0.380 0.0140 0.0130 0.0150
B 0.320 0.290 0.350 0.0126 0.0114 0.0138
D 1.805 1.785 1.825 0.0711 0.0703 0.0719
E 1.400 1.380 1.420 0.0551 0.0543 0.0559
e 0.5 0.0197
e1 0.886 0.0349
e2 0.250 0.0098
e3 0.443 0.0174
F 0.257 0.0101
G 0.4025 0.0158
N(2)
2. N is the total number of terminals.
8 8
D
EB
Orientation references
54321
A2
A1
A
e1
FGee2
A
B
C
e3
M24128-BW, M24128-BR, M24128-BF Part numbering
Doc ID 16892 Rev 20 33/38
9 Part numbering
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Table 21. Ordering information scheme
Example: M24128–B W MN 6 T P /P
Device type
M24 = I2C serial access EEPROM
Device function
128–B = 128 Kbit (16384 x 8)
Operating voltage
W = VCC = 2.5 V to 5.5 V
R = VCC = 1.8 V to 5.5 V
F = VCC = 1.7 V to 5.5 V
Package
MN = SO8 (150 mil width)(1)
1. ECOPACK2® (RoHS-compliant and Halogen-free).
DW = TSSOP8 (169 mil width)(1)
MB or MC = UFDFPN8 (MLP8)(1)
CS = WLCSP(1)
Device grade
6 = Industrial: device tested with standard test flow
over –40 to 85 °C
3 = Automotive: device tested with high reliability
certified flow(2) over –40 to 125°C.
2. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.
The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your
nearest ST sales office for a copy.
Option
blank = standard packing
T = Tape and reel packing
Plating technology
P or G = ECOPACK® (RoHS compliant)
Process(3)
3. Used only for device grade 3 and WLCSP packages.
P = F6DP26% Chartered
A = F8L Rousset (only for the WLCSP package)
Revision history M24128-BW, M24128-BR, M24128-BF
34/38 Doc ID 16892 Rev 20
10 Revision history
Table 22. Document revision history
Date Revision Changes
22-Dec-1999 2.3 TSSOP8 package in place of TSSOP14 (pp 1, 2, OrderingInfo,
PackageMechData).
28-Jun-2000 2.4 TSSOP8 package data corrected
31-Oct-2000 2.5
References to Temperature Range 3 removed from Ordering Information
Voltage range -S added, and range -R removed from text and tables
throughout.
20-Apr-2001 2.6
Lead Soldering Temperature in the Absolute Maximum Ratings table
amended
Write Cycle Polling Flow Chart using ACK illustration updated
References to PSDIP changed to PDIP and Package Mechanical data
updated
16-Jan-2002 2.7
Test condition for ILI made more precise, and value of ILI for E2-E0 and
WC added
-R voltage range added
02-Aug-2002 2.8
Document reformatted using new template.
TSSOP8 (3x3mm² body size) package (MSOP8) added.
5ms write time offered for 5V and 2.5V devices
04-Feb-2003 2.9 SO8W package removed. -S voltage range removed
27-May-2003 2.10 TSSOP8 (3x3mm² body size) package (MSOP8) removed
22-Oct-2003 3.0
Table of contents, and Pb-free options added. Minor wording changes in
Summary Description, Power-On Reset, Memory Addressing, Write
Operations, Read Operations. VIL(min) improved to -0.45V.
01-Jun-2004 4.0
Absolute Maximum Ratings for VIO(min) and VCC(min) improved.
Soldering temperature information clarified for RoHS compliant devices.
Device Grade clarified
04-Nov-2004 5.0
Product List summary table added. Device Grade 3 added. 4.5-5.5V
range is Not for New Design. Some minor wording changes. AEC-Q100-
002 compliance. tNS(max) changed. VIL(min) is the same on all input
pins of the device. ZWCL changed.
05-Jan-2005 6.0 UFDFPN8 package added. Small text changes.
M24128-BW, M24128-BR, M24128-BF Revision history
Doc ID 16892 Rev 20 35/38
29-Jun-2006 7
Document converted to new ST template.
M24C32 and M24C64 products (4.5 to 5.5V supply voltage) removed.
M24C64 and M24C32 products (1.7 to 5.5V supply voltage) added.
Section 2.3: Chip Enable (E0, E1, E2) and Section 2.4: Write Control
(WC) modified, Section 2.6: Supply voltage (VCC) added and replaces
Power On Reset: VCC Lock-Out Write Protect section.
TA added, Note 1 updated and TLEAD specified for PDIP packages in
Table 6: Absolute maximum ratings.
ICC0 added, ICC voltage conditions changed and ICC1 specified over the
whole voltage range in Table 12: DC characteristics (M24xxx-W, device
grade 6).
ICC0 added, ICC frequency conditions changed and ICC1 specified over
the whole voltage range in Table 14: DC characteristics (M24xxx-R -
device grade 6).
tW modified in Table 16: AC characteristics.
SO8N package specifications updated (see Figure 14 and Ta bl e 1 7 ).
Device grade 5 added, B and P Process letters added to Ta bl e 21 :
Ordering information scheme. Small text changes.
03-Jul-2006 8
ICC1 modified in Table 12: DC characteristics (M24xxx-W, device grade
6).
Note 1 added to Table 15: DC characteristics (M24xxx-F) and table title
modified.
17-Oct-2006 9
UFDFPN8 package specifications updated (see Ta b le 1 9 ). M24128-BW-
and M24128-BR part numbers added.
Generic part number corrected in Features on page 1.
ICC0 corrected in Ta b le 1 3 and Ta b l e 1 2 .
Packages are ECOPACK® compliant.
27-Apr-2007 10
Available packages and temperature ranges by product specified in
Ta bl e 2 2 , Ta bl e 2 4 and Ta bl e 2 5 .
Notes modified below Table 11: Input parameters.
VIH max modified in DC characteristics tables (see Ta b l e 1 2 , Ta b l e 1 3 ,
Ta bl e 1 4 and Ta b le 1 5 ).
C process code added to Table 21: Ordering information scheme.
For M24xxx-R (1.8 V to 5.5 V range) products assembled from July 2007
on, tW will be 5 ms (see Table 16: AC characteristics.
27-Nov-2007 11
Small text changes. Section 2.5: VSS ground and Section 4.9: ECC
(error correction code) and write cycling added.
VIL and VIH modified in Table 14: DC characteristics (M24xxx-R - device
grade 6).
JEDEC standard reference updated below Table 6: Absolute maximum
ratings.
Package mechanical data inch values calculated from mm and rounded
to 4 decimal digits (see Section 8: Package mechanical data).
Table 22. Document revision history (continued)
Date Revision Changes
Revision history M24128-BW, M24128-BR, M24128-BF
36/38 Doc ID 16892 Rev 20
18-Dec-2007 12
Added Section 2.6.2: Power-up conditions, updated Section 2.6.3:
Device reset, and Section 2.6.4: Power-down conditions in Section 2.6:
Supply voltage (VCC).
Updated Figure 5: Maximum RP value versus bus parasitic capacitance
(C) for an I2C bus.
Replace M24128 and M24C64 by M24128-BFMB6 and M24C64-FMB6,
respectively, in Section 4.9: ECC (error correction code) and write
cycling.
Added temperature grade 6 in Table 9: Operating conditions (M24xxx-
F).
Updated test conditions for ILO and VLO in Table 12: DC characteristics
(M24xxx-W, device grade 6), Table 13: DC characteristics (M24xxx-W,
device grade 3), and Table 14: DC characteristics (M24xxx-R - device
grade 6).
Test condition updated for ILO, and VIH and VIL differentiate for 1.8 V ≤
VCC < 2.5 V and 2.5 V ≤ VCC < 5.5 V in Table 15: DC characteristics
(M24xxx-F).
Updated Table 16: AC characteristics, and Table 17: AC characteristics
(M24xxx-F).
Updated Figure 13: AC waveforms.
Added M24128-BF in Table 25: Available M24C32 products (package,
voltage range, temperature grade).
Process B removed fromTable 21: Ordering information scheme.
30-May-2008 13
Small text changes.
C Process option and Blank Plating technology option removed from
Table 21: Ordering information scheme.
15-Jul-2008 14
WLCSP package added (see Figure 3: WLCSP connections (top view,
marking side, with balls on the underside) and Section 8: Package
mechanical data). Section 4.9: ECC (error correction code) and write
cycling updated.
16-Sep-2008 15
IOL added to Table 6: Absolute maximum ratings.
Table 24: Available M24C32 products (package, voltage range,
temperature grade) and Table 25: Available M24C32 products (package,
voltage range, temperature grade) updated.
05-Jan-2009 16
I2C modes supported specified in Features on page 1.
Note removed from Table 15: DC characteristics (M24xxx-F). Small text
changes.
Table 22. Document revision history (continued)
Date Revision Changes
M24128-BW, M24128-BR, M24128-BF Revision history
Doc ID 16892 Rev 20 37/38
10-Dec-2009 17
32 and 64 Kbit densities removed.
ECOPACK status of packages specified on page 1 and in Ta bl e 2 1 :
Ordering information scheme.
Section 2.6.2: Power-up conditions updated.
Figure 5: Maximum RP value versus bus parasitic capacitance (C) for an
I2C bus updated.
tNS modified in Table 11: Input parameters.
ICC1 and VIH updated in Table 12: DC characteristics (M24xxx-W, device
grade 6), Table 13: DC characteristics (M24xxx-W, device grade 3),
Table 14: DC characteristics (M24xxx-R - device grade 6) and Tabl e 1 5 :
DC characteristics (M24xxx-F). Note added to Table 14: DC
characteristics (M24xxx-R - device grade 6).
Table 16: AC characteristics modified.
Figure 13: AC waveforms modified.
Note added below Figure 16: UFDFPN8 (MLP8) – 8-lead ultra thin fine
pitch dual flat package no lead 2 × 3mm, package outline.
Small text changes.
12-Jan-2010 18 Section 4.9: ECC (error correction code) and write cycling modified.
23-Mar-2010 19 Removed PDIP package.
24-Nov-2011 20
Updated UFDFPN8 silhouette on cover page, Figure 16: UFDFPN8
(MLP8) – 8-lead ultra thin fine pitch dual flat package no lead 2 × 3mm,
package outline and Table 19: UFDFPN8 (MLP8) 8-lead ultra thin fine
pitch dual flat package no lead 2 x 3 mm, mechanical data to add MC
version.
Renamed Figure 2: 8-pin package connections.
Removed “Available M24128 products“ table.
Updated disclaimer on last page.
Table 22. Document revision history (continued)
Date Revision Changes
M24128-BW, M24128-BR, M24128-BF
38/38 Doc ID 16892 Rev 20
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