M24128-BW M24128-BR M24128-BF 128 Kbit serial IC bus EEPROM Features Supports the I2C bus modes: - 400 kHz Fast-mode - 100 kHz Standard-mode Single supply voltages: - 2.5 V to 5.5 V (M24128-BW) - 1.8 V to 5.5 V (M24128-BR) - 1.7 V to 5.5 V (M24128-BF) Write Control input Byte and Page Write Random and Sequential Read modes Self-timed programming cycle Automatic address incrementing Enhanced ESD/latch-up protection More than 1 Million write cycles More than 40-year data retention Packages - ECOPACK2(R) (RoHS-compliant and Halogen-free) SO8 (MN) 150 mil width TSSOP8 (DW) 169 mil width WLCSP (CS) UFDFPN8 (MB, MC) November 2011 Doc ID 16892 Rev 20 1/38 www.st.com 1 Contents M24128-BW, M24128-BR, M24128-BF Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.1 2.6.2 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2/38 4.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.5 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.6 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.7 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.8 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.9 ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . . . 17 4.10 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 18 4.11 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.12 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.13 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.14 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.15 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Doc ID 16892 Rev 20 M24128-BW, M24128-BR, M24128-BF Contents 5 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Doc ID 16892 Rev 20 3/38 List of tables M24128-BW, M24128-BR, M24128-BF List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. 4/38 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Address most significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Address least significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Operating conditions (M24xxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Operating conditions (M24xxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Operating conditions (M24xxx-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DC characteristics (M24xxx-W, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DC characteristics (M24xxx-W, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DC characteristics (M24xxx-R - device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DC characteristics (M24xxx-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SO8 narrow - 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 TSSOP8 - 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 30 UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 WLCSP, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Doc ID 16892 Rev 20 M24128-BW, M24128-BR, M24128-BF List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 WLCSP connections (top view, marking side, with balls on the underside) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Maximum RP value versus bus parasitic capacitance (C) for an I2C bus . . . . . . . . . . . . . . 10 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SO8 narrow - 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . 28 TSSOP8 - 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 30 UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat package no lead 2 x 3mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 WLCSP, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Doc ID 16892 Rev 20 5/38 Description 1 M24128-BW, M24128-BR, M24128-BF Description The M24128-BW, M24128-BR and M24128-BF devices are I2C-compatible electrically erasable programmable memories (EEPROM). They are organized as 16384 x 8 bits. Figure 1. Logic diagram 6## % % 3$! -XXX 3#, 7# 633 !)F I2C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The devices carry a built-in 4-bit device type identifier code (1010) in accordance with the I2C bus definition. The device behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a device select code and Read/Write bit (RW) (as described in Table 2), terminated by an acknowledge bit. When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read. 6/38 Doc ID 16892 Rev 20 M24128-BW, M24128-BR, M24128-BF Table 1. Description Signal names Signal name Function Direction E0, E1, E2 Chip Enable Input SDA Serial Data I/O SCL Serial Clock Input WC Write Control Input VCC Supply voltage VSS Ground Figure 2. 8-pin package connections % % % 633 6## 7# 3#, 3$! !)F 1. See Package mechanical data section for package dimensions, and how to identify pin-1. Figure 3. WLCSP connections (top view, marking side, with balls on the underside) VCC E1 E2 WC SDA E0 SCL VSS ai14799 Doc ID 16892 Rev 20 7/38 Signal description M24128-BW, M24128-BR, M24128-BF 2 Signal description 2.1 Serial Clock (SCL) This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to VCC. (Figure 5 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. 2.2 Serial Data (SDA) This bidirectional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 5 indicates how the value of the pull-up resistor can be calculated). 2.3 Chip Enable (E0, E1, E2) These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code. These inputs must be tied to VCC or VSS, to establish the device select code as shown in Figure 4. When not connected (left floating), these inputs are read as low (0,0,0). Figure 4. Device select code VCC VCC M24xxx M24xxx Ei Ei VSS VSS Ai12806 2.4 Write Control (WC) This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven high. When unconnected, the signal is internally read as VIL, and Write operations are allowed. When Write Control (WC) is driven high, device select and Address bytes are acknowledged, Data bytes are not acknowledged. 8/38 Doc ID 16892 Rev 20 M24128-BW, M24128-BR, M24128-BF 2.5 Signal description VSS ground VSS is the reference for the VCC supply voltage. 2.6 Supply voltage (VCC) 2.6.1 Operating supply voltage VCC Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 7, Table 8 and Table 9). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). 2.6.2 Power-up conditions The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage defined in Table 7, Table 8 and Table 9. The rise time must not vary faster than 1 V/s. 2.6.3 Device reset In order to prevent inadvertent Write operations during power-up, a power on reset (POR) circuit is included. At power-up (continuous rise of VCC), the device does not respond to any instruction until VCC has reached the power on reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Table 8 and Table 9). Until VCC passes over the POR threshold, the device is reset and in Standby Power mode. In a similar way, during power-down (continuous decay of VCC), as soon as VCC drops below the POR threshold voltage, the device is reset and stops responding to any instruction sent to it. 2.6.4 Power-down conditions During power-down (continuous decay of VCC), the device must be in Standby Power mode (mode reached after decoding a Stop condition, assuming that there is no internal Write cycle in progress). Doc ID 16892 Rev 20 9/38 Signal description M24128-BW, M24128-BR, M24128-BF Maximum RP value versus bus parasitic capacitance (C) for an I2C bus Figure 5. Bus line pull-up resistor (k ) 100 10 4 k When tLOW = 1.3 s (min value for fC = 400 kHz), the Rbus x Cbus time constant must be below the 400 ns time constant line represented on the left. R bu s x C bu s = Here Rbus x Cbus = 120 ns 40 VCC Rbus 0n s SCL IC bus master M24xxx SDA 1 30 pF 10 100 Bus line capacitor (pF) Cbus 1000 ai14796b Figure 6. I2C bus protocol SCL SDA SDA Input Start Condition SCL 1 SDA MSB 2 SDA Change Stop Condition 3 7 8 9 ACK Start Condition SCL 1 SDA MSB 2 3 7 8 9 ACK Stop Condition AI00792B 10/38 Doc ID 16892 Rev 20 M24128-BW, M24128-BR, M24128-BF Table 2. Signal description Device select code Device type identifier(1) Device select code Chip Enable address(2) RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 1 0 E2 E1 E0 RW 1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared against the respective external pins on the memory device. Table 3. b15 Table 4. b7 Address most significant byte b14 b13 b12 b11 b10 b9 b8 b3 b2 b1 b0 Address least significant byte b6 b5 b4 Doc ID 16892 Rev 20 11/38 Memory organization 3 M24128-BW, M24128-BR, M24128-BF Memory organization The memory is organized as shown in Figure 7. Figure 7. Block diagram WC E0 E1 High Voltage Generator Control Logic E2 SCL SDA I/O Shift Register Data Register Y Decoder Address Register and Counter 1 Page X Decoder AI06899 12/38 Doc ID 16892 Rev 20 M24128-BW, M24128-BR, M24128-BF 4 Device operation Device operation The device supports the I2C protocol. This is summarized in Figure 6. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The device is always a slave in all communications. 4.1 Start condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given. 4.2 Stop condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Standby mode. A Stop condition at the end of a Write command triggers the internal Write cycle. 4.3 Acknowledge bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to acknowledge the receipt of the eight data bits. 4.4 Data Input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven low. Doc ID 16892 Rev 20 13/38 Device operation 4.5 M24128-BW, M24128-BR, M24128-BF Memory addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 2 (on Serial Data (SDA), most significant bit first). The device select code consists of a 4-bit device type identifier, and a 3-bit Chip Enable "Address" (E2, E1, E0). To address the memory array, the 4-bit device type identifier is 1010b. Up to eight memory devices can be connected on a single I2C bus. Each one is given a unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the device select code is received, the device only responds if the Chip Enable Address is the same as the value on the Chip Enable (E0, E1, E2) inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the device select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the device select code, it deselects itself from the bus, and goes into Standby mode. Table 5. Operating modes Mode Current Address Read RW bit WC(1) 1 X 0 X Bytes 1 Start, device select, RW = 1 Start, device select, RW = 0, Address Random Address Read 1 X Sequential Read 1 X 1 Byte Write 0 VIL 1 Start, device select, RW = 0 Page Write 0 VIL 64 Start, device select, RW = 0 1 reStart, device select, RW = 1 1. X = VIH or VIL. 14/38 Initial sequence Doc ID 16892 Rev 20 Similar to Current or Random Address Read M24128-BW, M24128-BR, M24128-BF Figure 8. Device operation Write mode sequences with WC = 1 (data write inhibited) WC ACK Byte address ACK Byte address NO ACK Data in Stop Dev select Start Byte Write ACK R/W WC ACK Dev select Start Page Write ACK Byte address ACK Byte address NO ACK Data in 1 Data in 2 R/W WC (cont'd) NO ACK Data in N Stop Page Write (cont'd) NO ACK AI01120d Doc ID 16892 Rev 20 15/38 Device operation 4.6 M24128-BW, M24128-BR, M24128-BF Write operations Following a Start condition the bus master sends a device select code with the Read/Write bit (RW) reset to 0. The device acknowledges this, as shown in Figure 9, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data Byte. Writing to the memory may be inhibited if Write Control (WC) is driven high. Any Write instruction with Write Control (WC) driven high (during a period of time from the Start condition until the end of the two address bytes) will not modify the memory contents, and the accompanying data bytes are not acknowledged, as shown in Figure 8. Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant Byte (Table 3) is sent first, followed by the Least Significant Byte (Table 4). Bits b15 to b0 form the address of the byte in memory. When the bus master generates a Stop condition immediately after the Ack bit (in the "10th bit" time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. After the Stop condition, the delay tW, and the successful completion of a Write operation, the device's internal address counter is incremented automatically, to point to the next byte address after the last one that was modified. During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests. 4.7 Byte Write After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven high, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 9. 4.8 Page Write The Page Write mode allows up to 64 bytes to be written in a single Write cycle, provided that they are all located in the same `row' in the memory: that is, the most significant memory address bits (b13-b6) are the same. If more bytes are sent than will fit up to the end of the row, a condition known as `roll-over' occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way. The bus master sends from 1 to 64 bytes of data, each of which is acknowledged by the device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck. After each byte is transferred, the internal byte address counter (inside the page) is incremented. The transfer is terminated by the bus master generating a Stop condition. 16/38 Doc ID 16892 Rev 20 M24128-BW, M24128-BR, M24128-BF Figure 9. Device operation Write mode sequences with WC = 0 (data write enabled) WC ACK Byte address ACK Byte address ACK Data in Stop Dev Select Start Byte Write ACK R/W WC ACK Dev Select Start Page Write ACK Byte address ACK Byte address ACK Data in 1 Data in 2 R/W WC (cont'd) ACK Data in N Stop Page Write (cont'd) ACK 4.9 AI01106d ECC (error correction code) and write cycling The new M24128 devices offer an ECC (error correction code) logic which compares each 4-byte word with its six associated EEPROM ECC bits. As a result, if a single bit out of 4 bytes of data happens to be erroneous during a read operation, the ECC detects it and replaces it by the correct value. The read reliability is therefore much improved by the use of this feature. Note however that even if a single byte has to be written, 4 bytes are internally modified (plus the ECC word), that is, the addressed byte is cycled together with the three other bytes making up the word. It is therefore recommended to write by packets of 4 bytes in order to benefit from the larger amount of write cycles. All M24128 devices are qualified at 1 million (1 000 000) write cycles; the new M24128 devices offering the ECC improvement are qualified using a cycling routine that writes to the device by multiples of 4-byte words. Doc ID 16892 Rev 20 17/38 Device operation M24128-BW, M24128-BR, M24128-BF Figure 10. Write cycle polling flowchart using ACK Write cycle in progress Start condition Device select with RW = 0 NO First byte of instruction with RW = 0 already decoded by the device ACK Returned YES NO Next operation is addressing the memory YES Send address and receive ACK ReStart NO Stop Start condition YES Data for the Write operation Device select with RW = 1 Continue the Write operation Continue the Random Read operation AI01847d 4.10 Minimizing system delays by polling on ACK During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (tw) is shown in Table 16, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 10, is: 18/38 1. Initial condition: a Write cycle is in progress. 2. Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction). 3. Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1). Doc ID 16892 Rev 20 M24128-BW, M24128-BR, M24128-BF Device operation Figure 11. Read mode sequences ACK Data out Stop Start Dev select NO ACK R/W ACK Start Dev select * Byte address Dev select * ACK ACK Data out 1 ACK NO ACK Data out N Byte address ACK Byte address ACK Dev select * Start Start ACK R/W ACK Data out R/W R/W Dev select * NO ACK Stop Start Dev select Sequential Random Read ACK Byte address R/W ACK Sequential Current Read ACK Start Random Address Read ACK Stop Current Address Read ACK Data out 1 R/W NO ACK Stop Data out N AI01105d 1. The seven most significant bits of the device select code of a Random Read (in the 1st and 4th bytes) must be identical. Doc ID 16892 Rev 20 19/38 Device operation 4.11 M24128-BW, M24128-BR, M24128-BF Read operations Read operations are performed independently of the state of the Write Control (WC) signal. After the successful completion of a Read operation, the device's internal address counter is incremented by one, to point to the next byte address. 4.12 Random Address Read A dummy Write is first performed to load the address into this address counter (as shown in Figure 11) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition. 4.13 Current Address Read For the Current Address Read operation, following a Start condition, the bus master only sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 11, without acknowledging the Byte. 4.14 Sequential Read This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 11. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter `rolls-over', and the device continues to output data from memory address 00h. 4.15 Acknowledge in Read mode For all Read commands, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) low during this time, the device terminates the data transfer and switches to its Standby mode. 20/38 Doc ID 16892 Rev 20 M24128-BW, M24128-BR, M24128-BF 5 Initial delivery state Initial delivery state The device is delivered with all bits in the memory array set to 1 (each byte contains FFh). 6 Maximum rating Stressing the device outside the ratings listed in Table 6 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the Operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 6. Absolute maximum ratings Symbol TA TSTG TLEAD Parameter Min. Max. Unit Ambient operating temperature -40 130 C Storage temperature -65 150 C (1) C -0.50 6.5 V - 5 mA -0.50 6.5 V -4000 4000 V Lead temperature during soldering VIO Input or output range IOL DC output current (SDA = 0) VCC Supply voltage VESD Electrostatic discharge voltage (human body see note model)(2) 1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK(R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500 , R2=500 ) Doc ID 16892 Rev 20 21/38 DC and AC parameters 7 M24128-BW, M24128-BR, M24128-BF DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 7. Operating conditions (M24xxx-W) Symbol VCC TA Table 8. Parameter Min. Max. Unit Supply voltage 2.5 5.5 V Ambient operating temperature (device grade 6) -40 85 C Ambient operating temperature (device grade 3) -40 125 C Operating conditions (M24xxx-R) Symbol VCC TA Table 9. Parameter Min. Max. Unit Supply voltage 1.8 5.5 V Ambient operating temperature -40 85 C Operating conditions (M24xxx-F) Symbol VCC TA Table 10. Parameter Min. Max. Unit Supply voltage 1.7 5.5 V Ambient operating temperature (device grade 6) -40 85 C Ambient operating temperature (device grade 5) -20 85 C AC test measurement conditions Symbol CL Parameter Load capacitance Max. 100 Input rise and fall times 22/38 Min. Unit pF 50 ns Input levels 0.2VCC to 0.8VCC V Input and output timing reference levels 0.3VCC to 0.7VCC V Doc ID 16892 Rev 20 M24128-BW, M24128-BR, M24128-BF DC and AC parameters Figure 12. AC test measurement I/O waveform Input Levels Input and Output Timing Reference Levels 0.8VCC 0.7VCC 0.3VCC 0.2VCC AI00825B Table 11. Input parameters Symbol Parameter Test condition Min. Max. Unit CIN Input capacitance (SDA) 8 pF CIN Input capacitance (other pins) 6 pF 200 k ZWCL(1) WC input impedance VIN < 0.3VCC 50 ZWCH(1) WC input impedance VIN > 0.7VCC 500 tNS(1) k Pulse width ignored (Input filter on SCL and SDA) 100 ns 1. Characterized only. Table 12. Symbol DC characteristics (M24xxx-W, device grade 6) Test condition (in addition to those in Table 7) Parameter Min. Max. Unit ILI Input leakage current (SCL, SDA, E2, E1, E0) VIN = VSS or VCC device in Standby mode 2 A ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC 2 A ICC Supply current (Read) 2.5 V < VCC < 5.5 V, fc = 400 kHz 2 mA ICC0 Supply current (Write) During tW, 2.5 V < VCC < 5.5 V 5(1) mA (2) Standby supply current Device not selected , VIN = VSS or VCC, VCC = 5.5 V 5 A Standby supply current Device not selected(2), VIN = VSS or VCC, VCC = 2.5 V 2 A -0.45 0.3VCC V Input high voltage (SCL, SDA) 0.7VCC 6.5 V Input high voltage (WC, E0, E1, E2) 0.7VCC VCC+0.6 ICC1 VIL VIH VOL Input low voltage (SDA, SCL, WC) Output low voltage IOL = 2.1 mA, VCC = 2.5 V or IOL = 3 mA, VCC = 5.5 V 0.4 V V 1. Characterized value, not tested in production. 2. The device is not selected after power-up, after a Read command (after the Stop condition) or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write command). Doc ID 16892 Rev 20 23/38 DC and AC parameters Table 13. Symbol M24128-BW, M24128-BR, M24128-BF DC characteristics (M24xxx-W, device grade 3) Test condition (in addition to those in Table 7) Parameter Min. Max. Unit VIN = VSS or VCC device in Standby mode 2 A ILI Input leakage current (SCL, SDA, E2, E1, E0) ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC 2 A ICC Supply current (Read) 2.5 V < VCC < 5.5 V, fc = 400 kHz 2 mA (1) 5 mA 10 A -0.45 0.3VCC V Input high voltage (SCL, SDA) 0.7VCC 6.5 V Input high voltage (WC, E0, E1, E2) 0.7VCC VCC+0.6 V 0.4 V ICC0 Supply current (Write) During tW, 2.5 V < VCC < 5.5 V (2) ICC1 Standby supply current VIL Input low voltage (SDA, SCL, WC) VIH VOL Output low voltage Device not selected , VIN = VSS or VCC, 2.5 V < VCC < 5.5 V IOL = 2.1 mA, VCC = 2.5 V or IOL = 3 mA, VCC = 5.5 V 1. Characterized value, not tested in production. 2. The device is not selected after power-up, after a Read command (after the Stop condition) or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write command). Table 14. Symbol DC characteristics (M24xxx-R - device grade 6) Parameter Test condition (in addition to those in Table 8)(1) Min. Max. Unit ILI Input leakage current (SCL, SDA, E2, E1, E0) VIN = VSS or VCC device in Standby mode 2 A ILO Output leakage current SDA Hi-Z, external voltage applied on SDA: VSS or VCC 2 A ICC Supply current (Read) VCC = 1.8 V, fc = 400 kHz 0.8 mA During tW, 1.8 V < VCC < 2.5 V 3(2) mA 1 A ICC0 Supply current (Write) (3) ICC1 Standby supply current VIL Input low voltage (SDA, SCL, WC) VIH VOL Device not selected , VIN = VSS or VCC, VCC = 1.8 V 1.8 V VCC < 2.5 V -0.45 0.25 VCC V 2.5 V VCC < 5.5 V -0.45 0.3 VCC V Input high voltage (SCL, SDA) 0.7VCC 6.5 V Input high voltage (WC, E0, E1, E2) 0.7VCC VCC+0.6 V 0.2 V Output low voltage IOL = 1 mA, VCC = 1.8 V 1. If the application uses the M24128-BR at 2.5 V < VCC < 5.5 V and -40 C < TA < +85 C, please refer to Table 12: DC characteristics (M24xxx-W, device grade 6) instead of the above table. 2. Characterized value, not tested in production. 3. The device is not selected after power-up, after a Read command (after the Stop condition) or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write command). 24/38 Doc ID 16892 Rev 20 M24128-BW, M24128-BR, M24128-BF Table 15. Symbol DC and AC parameters DC characteristics (M24xxx-F) Test condition (in addition to those in Table 9) Parameter Min. Max. Unit ILI Input leakage current (SCL, SDA, E2, E1, E0) VIN = VSS or VCC device in Standby mode 2 A ILO Output leakage current SDA Hi-Z, external voltage applied on SDA: VSS or VCC 2 A ICC Supply current (Read) VCC =1.7 V, fc = 400 kHz 0.8 mA ICC0 Supply current (Write) During tW, 1.7 V < VCC < 2.5 V 3(1) mA ICC1 Standby supply current Device not selected(2), VIN = VSS or VCC, VCC = 1.7 V 1 A VIL Input low voltage (SDA, SCL, WC) 1.8 V VCC < 2.5 V -0.45 0.25 VCC V 2.5 V VCC < 5.5 V -0.45 0.3 VCC V Input high voltage (SCL, SDA) 0.7VCC 6.5 V VIH Input high voltage (WC, E0, E1, E2) 0.7VCC VCC+0.6 V VOL Output low voltage 0.2 V IOL = 0.7 mA, VCC = 1.7 V 1. Characterized value, not tested in production. 2. The device is not selected after power-up, after a Read command (after the Stop condition) or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write command). Doc ID 16892 Rev 20 25/38 DC and AC parameters Table 16. M24128-BW, M24128-BR, M24128-BF AC characteristics Test conditions specified in Table 7, Table 8 and Table 9 Symbol Alt. fC fSCL Clock frequency tCHCL tHIGH Clock pulse width high 600 ns tCLCH tLOW Clock pulse width low 1300 ns tQL1QL2(1) tXH1XH2 tF tR Parameter SDA (out) fall time Min. 20 (2) Max. Unit 400 kHz 120 ns Input signal rise time (3) (3) ns (3) ns tXL1XL2 tF Input signal fall time (3) tDXCX tSU:DAT Data in set up time 100 ns tCLDX tHD:DAT Data in hold time 0 ns tCLQX tDH Data out hold time 200 ns tCLQV(4)(5) tAA Clock low to next data valid (access time) 200 tCHDL tSU:STA Start condition setup time 600 ns tDLCL tHD:STA Start condition hold time 600 ns tCHDH tSU:STO Stop condition set up time 600 ns tDHDL tBUF Time between Stop condition and next Start condition 1300 ns tW tWR Write time 900 5 ns ms 1. Characterized only, not tested in production. 2. With CL = 10 pF. 3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the IC specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when fC < 400 kHz. 4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or 0.7VCC, assuming that Rbus x Cbus time constant is within the values specified in Figure 5. 26/38 Doc ID 16892 Rev 20 M24128-BW, M24128-BR, M24128-BF DC and AC parameters Figure 13. AC waveforms T8,8, T8(8( T#(#, T#,#( 3#, T$,#, T8,8, 3$! )N T#($, T#,$8 T8(8( 3TART CONDITION 3$! )NPUT 3$! T$8#( #HANGE T#($( T$($, 3TART 3TOP CONDITION CONDITION 3#, 3$! )N T7 T#($( T#($, 3TOP CONDITION 7RITE CYCLE 3TART CONDITION T#(#, 3#, T#,16 3$! /UT T#,18 $ATA VALID T1,1, $ATA VALID !)F Doc ID 16892 Rev 20 27/38 Package mechanical data 8 M24128-BW, M24128-BR, M24128-BF Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 14. SO8 narrow - 8 lead plastic small outline, 150 mils body width, package outline h x 45 A2 A c ccc b e 0.25 mm GAUGE PLANE D k 8 E1 E 1 L A1 L1 SO-A 1. Drawing is not to scale. Table 17. SO8 narrow - 8 lead plastic small outline, 150 mils body width, package mechanical data inches(1) millimeters Symbol Typ Min A Typ Min 1.75 Max 0.0689 A1 0.10 A2 1.25 b 0.28 0.48 0.0110 0.0189 c 0.17 0.23 0.0067 0.0091 ccc 28/38 Max 0.25 0.0039 0.0098 0.0492 0.10 0.0039 D 4.90 4.80 5.00 0.1929 0.1890 0.1969 E 6.00 5.80 6.20 0.2362 0.2283 0.2441 E1 3.90 3.80 4.00 0.1535 0.1496 0.1575 e 1.27 - - 0.0500 - - h 0.25 0.50 k 0 8 0 8 Doc ID 16892 Rev 20 M24128-BW, M24128-BR, M24128-BF Table 17. Package mechanical data SO8 narrow - 8 lead plastic small outline, 150 mils body width, package mechanical data inches(1) millimeters Symbol Typ L L1 Min Max 0.40 1.27 1.04 Typ Min Max 0.0157 0.0500 0.0410 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 16892 Rev 20 29/38 Package mechanical data M24128-BW, M24128-BR, M24128-BF Figure 15. TSSOP8 - 8 lead thin shrink small outline, package outline D 8 5 c E1 1 E 4 A1 A L A2 L1 CP b e TSSOP8AM 1. Drawing is not to scale. Table 18. TSSOP8 - 8 lead thin shrink small outline, package mechanical data inches(1) millimeters Symbol Typ. Min. A Max. 0.050 0.150 0.800 1.050 b 0.190 c 0.090 1.000 CP Max. 0.0472 0.0020 0.0059 0.0315 0.0413 0.300 0.0075 0.0118 0.200 0.0035 0.0079 0.0394 0.100 0.0039 D 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 - - 0.0256 - - E 6.400 6.200 6.600 0.2520 0.2441 0.2598 E1 4.400 4.300 4.500 0.1732 0.1693 0.1772 L 0.600 0.450 0.750 0.0236 0.0177 0.0295 L1 1.000 0 8 0.0394 0 8 1. Values in inches are converted from mm and rounded to 4 decimal digits. 30/38 Min. 1.200 A1 A2 Typ. Doc ID 16892 Rev 20 M24128-BW, M24128-BR, M24128-BF Package mechanical data Figure 16. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat package no lead 2 x 3mm, package outline -" E $ -# E B , , % B , , % 0IN % + + , , ! $ $ EEE ! :7?-%E 1. Drawing is not to scale. 2. The central pad (E2 x D2 area in the above illustration) is internally pulled to VSS. It must not be allowed to be connected to any other voltage or signal line on the PCB, for example during the soldering process. 3. The circle in the top view of the package indicates the position of pin 1. Table 19. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, mechanical data inches(1) millimeters Symbol Typ Min Max Typ Min Max A 0.550 0.450 0.600 0.0217 0.0177 0.0236 A1 0.020 0.000 0.050 0.0008 0.0000 0.0020 b 0.250 0.200 0.300 0.0098 0.0079 0.0118 D 2.000 1.900 2.100 0.0787 0.0748 0.0827 D2 (rev MB) 1.600 1.500 1.700 0.0630 0.0591 0.0669 1.200 1.600 0.0472 0.0630 D2 (rev MC) E 3.000 2.900 3.100 0.1181 0.1142 0.1220 E2 (rev MB) 0.200 0.100 0.300 0.0079 0.0039 0.0118 1.200 1.600 0.0472 0.0630 E2 (rev MC) e 0.500 0.0197 K 0.300 L 0.300 L1 0.0118 0.500 0.0118 0.150 0.0197 0.0059 L3 0.300 0.0118 eee(2) 0.080 0.0031 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring. Doc ID 16892 Rev 20 31/38 Package mechanical data M24128-BW, M24128-BR, M24128-BF Figure 17. WLCSP, 0.5 mm pitch, package outline Orientation references 5 D 3 4 2 1 A E B e1 B e3 C F G e2 e A A1 A2 1. Drawing is not to scale. Table 20. WLCSP, 0.5 mm pitch, package mechanical data inches(1) millimeters Symbol Typ. Min. Max. Typ. Min. Max. A 0.585 0.535 0.635 0.0230 0.0211 0.0250 A1 0.230 0.205 0.255 0.0091 0.0081 0.0100 A2 0.355 0.330 0.380 0.0140 0.0130 0.0150 B 0.320 0.290 0.350 0.0126 0.0114 0.0138 D 1.805 1.785 1.825 0.0711 0.0703 0.0719 E 1.400 1.380 1.420 0.0551 0.0543 0.0559 e 0.5 0.0197 e1 0.886 0.0349 e2 0.250 0.0098 e3 0.443 0.0174 F 0.257 0.0101 G 0.4025 0.0158 N(2) 8 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. N is the total number of terminals. 32/38 Doc ID 16892 Rev 20 8 M24128-BW, M24128-BR, M24128-BF 9 Part numbering Part numbering Table 21. Ordering information scheme Example: M24128-B W MN 6 T P /P Device type M24 = I2C serial access EEPROM Device function 128-B = 128 Kbit (16384 x 8) Operating voltage W = VCC = 2.5 V to 5.5 V R = VCC = 1.8 V to 5.5 V F = VCC = 1.7 V to 5.5 V Package MN = SO8 (150 mil width)(1) DW = TSSOP8 (169 mil width)(1) MB or MC = UFDFPN8 (MLP8)(1) CS = WLCSP(1) Device grade 6 = Industrial: device tested with standard test flow over -40 to 85 C 3 = Automotive: device tested with high reliability certified flow(2) over -40 to 125C. Option blank = standard packing T = Tape and reel packing Plating technology P or G = ECOPACK(R) (RoHS compliant) Process(3) P = F6DP26% Chartered A = F8L Rousset (only for the WLCSP package) 1. ECOPACK2(R) (RoHS-compliant and Halogen-free). 2. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy. 3. Used only for device grade 3 and WLCSP packages. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. Doc ID 16892 Rev 20 33/38 Revision history 10 M24128-BW, M24128-BR, M24128-BF Revision history Table 22. 34/38 Document revision history Date Revision Changes 22-Dec-1999 2.3 TSSOP8 package in place of TSSOP14 (pp 1, 2, OrderingInfo, PackageMechData). 28-Jun-2000 2.4 TSSOP8 package data corrected 31-Oct-2000 2.5 References to Temperature Range 3 removed from Ordering Information Voltage range -S added, and range -R removed from text and tables throughout. 20-Apr-2001 2.6 Lead Soldering Temperature in the Absolute Maximum Ratings table amended Write Cycle Polling Flow Chart using ACK illustration updated References to PSDIP changed to PDIP and Package Mechanical data updated 16-Jan-2002 2.7 Test condition for ILI made more precise, and value of ILI for E2-E0 and WC added -R voltage range added 02-Aug-2002 2.8 Document reformatted using new template. TSSOP8 (3x3mm body size) package (MSOP8) added. 5ms write time offered for 5V and 2.5V devices 04-Feb-2003 2.9 SO8W package removed. -S voltage range removed 27-May-2003 2.10 TSSOP8 (3x3mm body size) package (MSOP8) removed 22-Oct-2003 3.0 Table of contents, and Pb-free options added. Minor wording changes in Summary Description, Power-On Reset, Memory Addressing, Write Operations, Read Operations. VIL(min) improved to -0.45V. 01-Jun-2004 4.0 Absolute Maximum Ratings for VIO(min) and VCC(min) improved. Soldering temperature information clarified for RoHS compliant devices. Device Grade clarified 04-Nov-2004 5.0 Product List summary table added. Device Grade 3 added. 4.5-5.5V range is Not for New Design. Some minor wording changes. AEC-Q100002 compliance. tNS(max) changed. VIL(min) is the same on all input pins of the device. ZWCL changed. 05-Jan-2005 6.0 UFDFPN8 package added. Small text changes. Doc ID 16892 Rev 20 M24128-BW, M24128-BR, M24128-BF Table 22. Revision history Document revision history (continued) Date 29-Jun-2006 03-Jul-2006 17-Oct-2006 27-Apr-2007 27-Nov-2007 Revision Changes 7 Document converted to new ST template. M24C32 and M24C64 products (4.5 to 5.5V supply voltage) removed. M24C64 and M24C32 products (1.7 to 5.5V supply voltage) added. Section 2.3: Chip Enable (E0, E1, E2) and Section 2.4: Write Control (WC) modified, Section 2.6: Supply voltage (VCC) added and replaces Power On Reset: VCC Lock-Out Write Protect section. TA added, Note 1 updated and TLEAD specified for PDIP packages in Table 6: Absolute maximum ratings. ICC0 added, ICC voltage conditions changed and ICC1 specified over the whole voltage range in Table 12: DC characteristics (M24xxx-W, device grade 6). ICC0 added, ICC frequency conditions changed and ICC1 specified over the whole voltage range in Table 14: DC characteristics (M24xxx-R device grade 6). tW modified in Table 16: AC characteristics. SO8N package specifications updated (see Figure 14 and Table 17). Device grade 5 added, B and P Process letters added to Table 21: Ordering information scheme. Small text changes. 8 ICC1 modified in Table 12: DC characteristics (M24xxx-W, device grade 6). Note 1 added to Table 15: DC characteristics (M24xxx-F) and table title modified. 9 UFDFPN8 package specifications updated (see Table 19). M24128-BWand M24128-BR part numbers added. Generic part number corrected in Features on page 1. ICC0 corrected in Table 13 and Table 12. Packages are ECOPACK(R) compliant. 10 Available packages and temperature ranges by product specified in Table 22, Table 24 and Table 25. Notes modified below Table 11: Input parameters. VIH max modified in DC characteristics tables (see Table 12, Table 13, Table 14 and Table 15). C process code added to Table 21: Ordering information scheme. For M24xxx-R (1.8 V to 5.5 V range) products assembled from July 2007 on, tW will be 5 ms (see Table 16: AC characteristics. 11 Small text changes. Section 2.5: VSS ground and Section 4.9: ECC (error correction code) and write cycling added. VIL and VIH modified in Table 14: DC characteristics (M24xxx-R - device grade 6). JEDEC standard reference updated below Table 6: Absolute maximum ratings. Package mechanical data inch values calculated from mm and rounded to 4 decimal digits (see Section 8: Package mechanical data). Doc ID 16892 Rev 20 35/38 Revision history M24128-BW, M24128-BR, M24128-BF Table 22. Document revision history (continued) Date Revision Changes 18-Dec-2007 12 Added Section 2.6.2: Power-up conditions, updated Section 2.6.3: Device reset, and Section 2.6.4: Power-down conditions in Section 2.6: Supply voltage (VCC). Updated Figure 5: Maximum RP value versus bus parasitic capacitance (C) for an I2C bus. Replace M24128 and M24C64 by M24128-BFMB6 and M24C64-FMB6, respectively, in Section 4.9: ECC (error correction code) and write cycling. Added temperature grade 6 in Table 9: Operating conditions (M24xxxF). Updated test conditions for ILO and VLO in Table 12: DC characteristics (M24xxx-W, device grade 6), Table 13: DC characteristics (M24xxx-W, device grade 3), and Table 14: DC characteristics (M24xxx-R - device grade 6). Test condition updated for ILO, and VIH and VIL differentiate for 1.8 V VCC < 2.5 V and 2.5 V VCC < 5.5 V in Table 15: DC characteristics (M24xxx-F). Updated Table 16: AC characteristics, and Table 17: AC characteristics (M24xxx-F). Updated Figure 13: AC waveforms. Added M24128-BF in Table 25: Available M24C32 products (package, voltage range, temperature grade). Process B removed fromTable 21: Ordering information scheme. 30-May-2008 13 Small text changes. C Process option and Blank Plating technology option removed from Table 21: Ordering information scheme. 14 WLCSP package added (see Figure 3: WLCSP connections (top view, marking side, with balls on the underside) and Section 8: Package mechanical data). Section 4.9: ECC (error correction code) and write cycling updated. 16-Sep-2008 15 IOL added to Table 6: Absolute maximum ratings. Table 24: Available M24C32 products (package, voltage range, temperature grade) and Table 25: Available M24C32 products (package, voltage range, temperature grade) updated. 05-Jan-2009 16 I2C modes supported specified in Features on page 1. Note removed from Table 15: DC characteristics (M24xxx-F). Small text changes. 15-Jul-2008 36/38 Doc ID 16892 Rev 20 M24128-BW, M24128-BR, M24128-BF Table 22. Revision history Document revision history (continued) Date Revision Changes 10-Dec-2009 17 32 and 64 Kbit densities removed. ECOPACK status of packages specified on page 1 and in Table 21: Ordering information scheme. Section 2.6.2: Power-up conditions updated. Figure 5: Maximum RP value versus bus parasitic capacitance (C) for an I2C bus updated. tNS modified in Table 11: Input parameters. ICC1 and VIH updated in Table 12: DC characteristics (M24xxx-W, device grade 6), Table 13: DC characteristics (M24xxx-W, device grade 3), Table 14: DC characteristics (M24xxx-R - device grade 6) and Table 15: DC characteristics (M24xxx-F). Note added to Table 14: DC characteristics (M24xxx-R - device grade 6). Table 16: AC characteristics modified. Figure 13: AC waveforms modified. Note added below Figure 16: UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat package no lead 2 x 3mm, package outline. Small text changes. 12-Jan-2010 18 Section 4.9: ECC (error correction code) and write cycling modified. 23-Mar-2010 19 Removed PDIP package. 20 Updated UFDFPN8 silhouette on cover page, Figure 16: UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat package no lead 2 x 3mm, package outline and Table 19: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, mechanical data to add MC version. Renamed Figure 2: 8-pin package connections. Removed "Available M24128 products" table. Updated disclaimer on last page. 24-Nov-2011 Doc ID 16892 Rev 20 37/38 M24128-BW, M24128-BR, M24128-BF Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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