Standard Products UT54ACS85/UT54ACTS85 4-Bit Comparators Datasheet November 2010 www.aeroflex.com/logic PINOUTS FEATURES 1.2 CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack UT54ACS85 - SMD 5962-96536 UT54ACTS85 - SMD 5962-96537 16-Pin DIP Top View B3 1 16 VDD (A<B)IN 2 15 A3 (A=B)IN 3 14 B2 (A>B)IN (A>B)OUT 4 5 13 12 A2 A1 (A=B)OUT (A<B)OUT 6 7 11 10 B1 A0 VSS 8 9 B0 DESCRIPTION 16-Lead Flatpack Top View The UT54ACS85 and the UT54ACTS85 are 4-bit magnitude comparators that perform comparison of straight binary and straight BCD (8-4-2-1) codes. Three fully decoded decisions about two 4-bit words (A, B) are made and are externally available at three outputs. Devices are fully expandable to any number of bits without external gates. The cascading paths of the devices are implemented with only a two-gate-level delay to reduce overall comparison times for long words. An alternate method of cascading which further reduces the comparison time is shown in the typical application data. The devices are characterized over full military temperature range of -55C to +125C. LOGIC SYMBOL A0 (10) A1 (12) A2 (13) A3 (A<B)IN (A=B)IN (A>B)IN B0 B1 B2 B3 (15) (2) (3) (4) (9) (11) (14) COMP 0 A 3 < < = > = (7) (6) (5) (A<B)OUT (A=B)OUT (A>B)OUT > 0 B (1) 3 Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. 1 B3 1 16 VDD (A<B)IN 2 15 A3 (A=B)IN 3 14 B2 (A>B)IN 13 A2 (A>B)OUT 4 5 12 A1 (A=B)OUT 6 11 B1 (A<B)OUT VSS 7 8 10 9 A0 B0 FUNCTION TABLE COMPARING INPUTS CASCADING INPUTS OUTPUTS A3, B3 A2, B2 A1, B1 A0, B0 A>B A<B A=B A>B A<B A=B A3>B3 X X X X X X H L L A3<B3 X X X X X X L H L A3=B3 A2>B2 X X X X X H L L A3=B3 A2<B2 X X X X X L H L A3=B3 A2=B2 A1>B1 X X X X H L L A3=B3 A2=B2 A1<B1 X X X X L H L A3=B3 A2=B2 A1=B1 A0>B0 X X X H L L A3=B3 A2=B2 A1=B1 A0<B0 X X X L H L A3=B3 A2=B2 A1=B1 A0=B0 H L L H L L A3=B3 A2=B2 A1=B1 A0=B0 L H L L H L A3=B3 A2=B2 A1=B1 A0=B0 X X H L L H A3=B3 A2=B2 A1=B1 A0=B0 H H L L L L A3=B3 A2=B2 A1=B1 A0=B0 L L L H H L LOGIC DIAGRAM (15) A3 (1) B3 (5) A>B A2 (13) B2 (14) A<B (2) (3) A=B (4) A>B (6) A=B (12) A1 B1 (11) (7) A<B (10) A0 (9) B0 2 OPERATIONAL ENVIRONMENT1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C JC Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C 3 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; VSS = 0V 6, -55C < TC < +125C); Unless otherwise noted, Tc is per the temperature range ordered. SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 2.3 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF 4 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum 7. All specifications valid for radiation dose 1E6 rads(Si). 6. Maximum allowable relative shift equals 50mV. 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 5 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; VSS = 0V 1, -55C < TC < +125C); Unless otherwise noted, Tc is per the temperature range ordered. SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL An, Bn to (A<B)OUT 2 22 ns tPLH An, Bn to (A<B)OUT 2 16 ns tPHL An, Bn to (A=B)OUT 2 17 ns tPLH An, Bn to (A=B)OUT 2 16 ns tPHL An, Bn to (A>B)OUT 2 18 ns tPLH An, Bn to (A>B)OUT 2 16 ns tPHL (A<B)IN, (A=B)IN to (A>B)OUT 2 17 ns tPLH (A<B)IN, (A=B)IN to (A>B)OUT 2 15 ns tPHL (A=B)IN to (A=B)OUT 2 13 ns tPLH (A=B)IN to (A=B)OUT 1 15 ns tPHL (A>B)IN, (A=B)IN to (A<B)OUT 2 17 ns tPLH (A>B)IN, (A=B)IN to (A<B)OUT 2 15 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si) 6 PACKAGING Side-Brazed Packages 7 FLATPACK PACKAGES 8 UT54ACS85/UT54ACTS85: SMD 5962 * ***** ** * * * Lead Finish: (Notes 1 & 2) A = Solder C = Gold X = Optional Package Type: X = 16-lead ceramic bottom-brazed dual-in-line Flatpack C = 16-lead ceramic side-brazed dip Class Designator: Q = QML Class Q V = QML Class V Device Type: 01 Drawing Number: 96536 = UT54ACS85 96537 = UT54ACTS85 Total Dose: (Notes 3 & 4) R = 1E5 rads(Si) F = 3E5 rads(Si) G = 5E5 rads(Si) H = 1E6 rads(Si) Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact factory. 4. Device type 02 is only offered with a TID tolerance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test Method 1019 Condition A and section 3.11.2. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5 rads(Si), and is tested in accordance with MIL-STD-883 Test Method 1019 Condition A. 9 Aeroflex Colorado Springs - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced Hi-Rel COLORADO Toll Free: 800-645-8862 Fax: 719-594-8468 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com Aeroflex UTMC Microelectronic Systems Inc. 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