N32D3218LPAF2-60C - Integrated Silicon Solution, Inc.

N32D3218LPAF2

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Ver. A

Description

These N32D3218LPAF2 are low power 33,554,432 bits CMOS Synchronous DRAM organized as 2 banks of 524,288 words x 32 bits.

These products are off ering fully sy nchronou s operation and are referenced to a positive edge of the clock. All inputs and outputs are

synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input

and output voltage levels are compatible with LVCMOS.

Table1: Ordering Information

JEDEC standard 1.8V power supply.

• Auto refresh a nd self refresh.

• All pins are co mp atible w ith LVCMOS interfa c e.

• 4K refresh cycle / 64ms.

• Programmable Burst Length and Burst Type.

- 1, 2, 4, 8 or Full Page for Sequential Burst.

- 4 or 8 for Interleave Burst.

• Programmable CAS Latency : 2,3 clocks.

• Programmable Driver Strength Control

- Full Strength or 1/2, 1/4 of Full Strength

• Deep Power Down Mode.

• All inputs and outputs referenced to the positiv e edge of the

system clo ck.

• Data mask function by DQM.

• Internal dual banks operation.

• Burst Read Single Write operation.

• Special Function Support.

- PASR(Partial Array Self Refresh)

- Auto TCSR(Temper ature Compensated Self R efresh)

• Automatic precharge, includes CONCURRENT Auto Precharge

Mode and controlled Precharge.

Features

133 MHzN32D3218LPAF2-75I

100 MHzN32D3218LPAF2-10I

-25°C to 85°C

Temperature

90-Ball Green

FBGA

LVCMOS1.8V/1.8V

166 MHzN32D3218LPAF2-60I

PackageInterfaceVDD/VDDQClock Freq.Part No.

512K x32Bits x2Banks Low Power Synchronous DRAM

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Ver. A

Figure1: 90Ball FBGA Ball Assignment

DQ26 DQ24 DQ23 DQ21

DQ28 VDDQ VSSQ DQ19

VSSQ DQ27 DQ20 VDDQ

VSSQ DQ29 DQ18 VDDQ

VDDQ DQ31 DQ16 VSSQ

VSS DQM3 DQM2 VDD

A4 A5 A0 A1

A7 A8 NC NC

CLK CKE /CS /RAS

DQM1 NC /WE DQM0

VDDQ DQ8 DQ7 VSSQ

VSSQ DQ10 DQ5 VDDQ

VSSQ DQ12 DQ3 VDDQ

DQ11 VDDQ VSSQ DQ4

DQ13 DQ15 DQ0 DQ2

1 2 3 4 5 6 7 8 9

[Top View]

VDD

VDDQ

DQ22

DQ17

A10

/CAS

VDD

DQ6

DQ1

VDDQ

VDD

VSS

VSSQ

DQ25

DQ30

VSS

DQ9

DQ14

VSSQ

VSS

Note: All Dimensions in millimeters

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Ver. A

Table2: Pin Descriptions

No connection.No ConnectionNC

Power supply for output buffers.Data Output Power/GroundVDDQ/VSSQ

Power supply for internal circuits and input buffers.Power Supply/GroundVDD/VSS

Multiplexed data in put/output pin.Data Input/OutputDQ0~DQ31

Controls output buffers in read mode and masks input data in

write mode.

Data Input/Output MaskDQM0~DQM3

RAS, CAS and WE define the operation.

Refer funct ion truth tabl e for d e tails.

Row Address Strobe,

Column A ddress Strobe ,

Write Enable

/RAS, /CAS, /WE

Row Address : RA0~RA10

Column Address : CA0~CA7

Auto Precharge : A10

AddressA0~A10

Selects bank to be activated during RAS activity.

Selects bank to be read/written during CAS activity.

Bank AddressBA

Enable or disable all inputs except CLK, CKE and DQM.Chip Select/CS

Controls internal clock signal and when deactivated, the SDRAM

will be one of the states among power down, suspend or self

refresh.

Clock EnableCKE

The system clock input. All other inputs are registered to the

SDRAM on the r ising edge CLK.

System ClockCLK

DescriptionsPin NamePin

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Ver. A

TCSR

PASR

Figure2: Functional Block Diagram

CONTROL LOGIC

COMMAND DECODER

COLUMN

ADDRESS

BUFFER &

BURST

COUNTER

CLOCK

GENERATOR

CLK

CKE

ROW

ADDRESS

BUFFER &

REFRESH

COUNTER

/CS

/RAS

/CAS

/WE

MODE

BANK B

ROW DECODER

BANK A

ROW DECODER

SENSE AMPLIFIER

COLUMN DECODER

& LATCH CIRCUIT

DQM

ADDRESS

DATA CONTROL CI R CUIT

LATCH CIRCUIT

INPUT & OUTPUT

BUFFER

EXTENDED

MODE

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Ver. A

CKE ↓

CKE

IDLE

ROW

ACTIVE

SELF

REFRESH

CBR

REFRESH

POWER

DOWN

ACTIVE

POWER

DOWN

READWRITE

READ AWRITE A

PRE-

CHARGE

READ

SUSPEND

READ A

SUSPEND

WRITE

SUSPEND

WRITE A

SUSPEND

POWER

MODE

SET

PRECHARGE

CKE ↓

CKE

CKE ↓

CKE

CKE ↓

CKE

READ

WRITE

CKE ↓

CKE

READ

WRITE

AUTO PRECHARGE

WRITE WITH

AUTO PRECHARGE

WRITE WITH

PRE

BST

ACT

CKE ↓

CKE

REF

SELF

SELF EXIT

MRS

PRE(Precharge termination)

Automatic Sequence

Manual Input

Figure3: Simplified State Diagram

EXTENDED

MODE

SET

EMRS

DEEP

POWER

DOWN

DPD EXIT

DPD

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Ver. A

Burst Type

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is

selec ted via bit M3. The orderin g of accesses within a b urst is determin ed by the burst length, th e burst type and the starting column

address, as shown in Table 3.

Table 3: Burst Definition

Burst Read and Single Write1Burst Read and Burst Write0

Write Burst ModeM9

Interleave1

Sequential0

Burst TypeM3

Reserved001 Reserved101

2010

-100

3110

Reserved011 Reserved111

Reserved000

CAS LatencyM4M5M6

Full Page

Reserved

M3 = 0

Burst Length

Reserved001 Reserved101

4010 2100

8110

Reserved011 Reserved111

1000

M3 = 1

M0M1M2

A0A1A2

7-6-5-4-3-2-1-07-0-1-2-3-4-5-6

0-1-2-3-4-5-6-70-1-2-3-4-5-6-7

1-0-3-2-5-4-7-61-2-3-4-5-6-7-0

2-3-0-1-6-7-4-52-3-4-5-6-7-0-1

4-5-6-7-0-1-2-34-5-6-7-0-1-2-3

5-4-7-6-1-0-3-25-6-7-0-1-2-3-4

1-0-3-2

1-2-3-0

2-3-0-12-3-0-1

3-2-1-03-0-1-2

3-2-1-0-7-6-5-43-4-5-6-7-0-1-2

0-1-2-30-1-2-3

0-10-1

21-01-0

6-7-4-5-2-3-0-16-7-0-1-2-3-4-5

Not Supported

Cn, Cn+1. Cn+2,

Cn+3, Cn+4…

…Cn-1, Cn...

n=A0-7

(Location 0-256)

Full

Page

InterleavedSequential

Order of Access Within a BurstStarting Colum n

Address

Burst

Length Note :

1. For full-page accesses: y = 256

2. For a burst length of two, A1-A7 select the block-

of-two burst; A0 selects the starting column within the

block.

3. For a burst length of four, A2-A7 select the block-

of-four burst; A0-A1 select the starting column within

the block.

4. For a burst length of eight, A3-A7 select the

block-of-eight burst; A0-A2 select the starting column

within the block.

5. For a full-page burst, the full row is selected and A0-A7

select the starting colum n.

6. Whenever a boundary of the block is reached within a

given sequence above, the following access wraps

within the block.

7. For a burst length of one, A0-A7 select the unique

column to be accessed, and mode register bit M3 is

ignored.

0CAS Latency BT Burst Length

Address Bus

01234561098711

A0A1A2A3A4A5A6A7A8A9A10BA

Mode Register (Mx)

Figure4: Mode Register Definition

Note: M11(BA) must be set to “0 ” to select Mod e Register (vs. the E x tended Mode Reg ister)

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Ver. A

1PASR

Figure5: Extended Mode Register

Address Bus

Extended Mode Register (Ex)

01234561098711

A0A1A2A3A4A5A6A7A8A9A10BA

Reserved001

Half of One Bank (BA=0, Row Address MSB=0)101

Reserved110

Quarter of One Bank (BA=0, Row Address 2 MSB=0)011

One Bank (BA=0)100

Reserved010

Reserved111

All Banks000

Self Refresh CoverageE0E1E2

Note: E11( BA) must be set to “1” to select Extend Mode Register ( vs. the bas e Mode Register)

1/2 Strength 10

1/4 Strength 01

Reserved11

Full Strength 00

Driver StrengthE5E6

0000 DS TCSR

70°10

45°01

Auto11

85°00

Maximum Case

Temp.

E3E4

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Ver. A

In general, this 32Mb SDRAM (512K x 32Bits x 2banks) is a dual-bank DRAM that operates at 1.8V and includes a synchronous

interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 16,777,216-bit banks is organized as

2,048 rows by 256 columns by 32-bits

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed

number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed

by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and

row to be accessed (BA select the bank, A0-A10 select the row). The address bits (BA select the bank, A0-A7 select the column)

registered coincident w ith the RE AD or WRITE command are used to selec t the starti ng colu mn location for the burst access.

Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device

initialization, register definition, command descriptions and device operation.

Power up and Initialization

SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in

undefined operation. Once power is applied to VDD and VDDQ(simultaneously) and the clock is stable(stable clock is defined as a

signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100µs delay prior to issuing an y command

other than a COMMAND INHIBIT or NOP. CKE must be held high during the entire initialization period until the RECHARGE command

has been issued. Starting at some point during this 100µs period and continuing at least through the end of this period, COMMAND

INHIBIT or NOP commands should be applied.

Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE

command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is

ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to

applying any operational command. And a extended mode register set command will be issued to program specific mode of self

refresh operation(PASR). The follow i ng these cycles, the Low Power SDRAM is ready for normal operation.

Mode Register

The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst

length, a burst type, a CAS latency, an operating mode and a write burst mode. The mode register is programmed via the LOAD

MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power.

Mode regi ster bits M0-M2 spec ify the burst le ngth, M3 specifie s the type of burst ( sequential or interleaved ), M4-M6 specify the CAS

laten cy, M7 and M8 specify t he op erating mode, M9 spe cifi es the write burst mode, and M10 should be set to zero. M11 should be set

to zero to prevent extended mode register.

The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the

subsequent operation. Violating either of these requirements will result in unspecified operation.

Functional Description

Extended Mode Register

The Extended Mode Register controls the functions beyond those controlled by the Mode Register. These additional functions are

special features of the BATRAM device. They include Temperature Compensated Self Refresh (TCSR) Control, and Partial Array Self

Refresh (PASR ) a nd Driver Strength (DS ).

The Extended Mode Register is programmed via the Mode Register Set command (BA=1) and retains the stored information until it is

programmed again or the device loses power.

The Extended Mode Register must be programmed with M7 through M10 set to “0”. T he Exte nded Mode Reg ister must be loaded whe n

all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent

operation. Violating either of these requirements results in unspecified operation.

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Ver. A

Burst Length

Read and write accesses to t he SDRAM are burst oriented, wit h the burst length being programmable, as shown in Figure 1. The burst

length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst

lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available

for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst

lengths.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE

command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within

this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A7 when

the burst length is set to tw o; by A2-A7 w hen the burst le ngth is s et to four; a nd by A3-A7 wh en the b urst le ngth is s et to eight. The

remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within

the page if the boundary is reached.

Bank(Row) Active

The Bank Active command is used to activate a row in a specified bank of the device. This command is initiated by activating CS, RAS and

deasserting CAS, WE at the positive edge of the clock. The value on the BA selects th e bank, and the v alue o n the A0-A10 selects the row.

This row remains active for column access until a precharge command is issued to that bank. Read and write operations can only be

initiat e d on this act ivated bank after the minimum tRCD time is passed from the activate command.

Read

The READ command is used to initiate the burst read of data. This command is initiated by activating CS, CAS, and deasserting WE, RAS at

the positive edge of the cl ock. BA inpu t select the bank, A0-A7 address inputs select the starting column location. The value on input A10

determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the end of

the READ burst; if A uto Precharge is not selected , the row will r emain active for s u b sequent accesses. The length of burst and the CAS

latency will be determined by the values programmed during the MRS command.

Write

The WRITE command is used to initiate the burst write of data. This command is initiated by activating CS, CAS, WE and deasserting RAS

at the positive edge of the clock. BA input select the bank, A0-A7 address inputs select the starting column location. The valueon input

A10 determines whether or not Auto Precharge is u sed. If Auto Precharge is selected the row being accessed will be precharged at the

end of the WRITE burst; if A uto Precharge i s not selected, the row will remain active for subsequent accesses.

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Ver. A

CAS Latency

The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of

output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is

clocks, the data will be available by clock edge

n +

m. The DQs will start driving as a result of the clock edge one cycle earlier

(n + m

1), and provided that the relevant access times are met, the data will be valid by clock edge

n +

m. For example, assuming that the

clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to

two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 6. Reserved states should not be used

as unknown operation or incompatibility with future versions may result.

Operating Mode

The normal operating mode is sel ected by setting M7 a nd M8 to zero; the other combinations of values for M7 and M8 are rese rved

for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved

states should not be used because unknown operation or incompatibility with future versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed

burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses.

CLK

COMMAND

NOP NOP

Dout

T0 T1 T2

tLZ tOH

tAC

CAS Latency=2

READ

CLK

COMMAND

NOP NOP

Dout

T0 T1 T2

tLZ tOH

tAC

CAS Latency=3

NOP

READ

DON’T CARE

UNDEFINED

Figure6: CAS Latency

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Ver. A

Table4: Command Truth Table

L/H

DQM

XHHHLXHNo Operation ( NOP)

XXXXHXHCommand Inhinit (NOP)

VVVL

HHHL

XXHLDeep Power Down Exit

6XHHLLHDeep Power Down Entry

XXHLClock Suspend Exit

XXXH

LHClock Suspend Entry

XXXH

HLPrecharge Down Exit

XXXH

LHPrecharge Power Down Entry

XXXH

HLSelf Re fresh Ex it

3XHLLLLHSelf Refresh Entry

3XHLLLH

HAuto Refresh

XLHHLHHBurst Stop

LBankLHLLXHPrecharge Selected Bank

HXLHLLXHPrecharge All Banks

5HBank/ColLLHLXHWrite with Autoprecharge

5LBank/ColLLHLXHWrite

5HBank/ColHLHLXHRead with Autoprecharge

5LBank/ColHLHLXHRead

Bank/RowHHLLXH

Active (select bank and

activate row)

4OP CODELLLLXHE x tended Mode Register Set

4OP CODELLLLXHMode Register Set

NoteA10ADDR/WE/CAS/RAS/CSCKEnCKEn-1Function

Note :

1. CKEn is the logic state of CKE at clock edge n; CKEn-1 wa s the stat e of CKE at the previou s clock edge.

H: High Level, L: Low Level, X: Don't Care, V: Valid

2. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high and will put the device in the all banks idle state once

tXSR is met. Com mand Inhibit or NOP comman ds should be issued on any clock ed g e s occuring during the tXSR period. A minimum

of two NOP commands must be provided during tXSR period.

3. During refresh operation, interna l r efresh count er controls r o w addressing; a l l inputs and I/Os are “D on’t Care” except for CKE.

4. A0-A10 define OP CODE written to the mode register, and BA must be issued 0 in the mode register set, and 1 in the extended

mode register set.

5. DQM “L” means the data Write/Ouput Enable and “H” means the Write inhibit/Output High-Z. Wr it e DQM Latency is 0 CLK and Read

DQM Latency is 2 CLK.

6. Standard SDRAM parts assign this command sequence a s Burst Terminate. For Bat Ram parts, the Burst Terminate command is

assigned to the Deep Pow er Do wn function.

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Ver. A

Table5: Function Truth Table

Continue the BurstDevice De selectXXXXXH

Col Add./A10

Terimination Burst :

Start Read(AP)

Read/Read APLHL

8,9

Termination Burst :

Start Write(AP)

Write/WriteAPLHL

Continue the Burst

ILLEGAL

Termination Burst :

Start the Precharge

ILLEGAL

No Operation

Start Read : Optional

AP(A10=H)

Start Write : Optional

AP(A10=H)

ILLEGAL

Activate the Specified

Bank and Row

No Operation

Start Auto or Se lf

Refresh

Set the Mode Register

DescriptionA0-A10BA/WE/CAS/RAS/CS

No OperationHHL

4Bank ActivateRow Add.BAHHLL

PrechargeHLL

13Auto or Self RefreshXXHLLL

13,14Mode Register SetOP CODELLLL

Read

Device De selectXXXXXH

No OperationXXHHHL

6Read/Read APCol Add./A10BAHLHL

6Write/Write APCol Add./A10BALLHL

4Bank ActivateRow Add.BAHHLL

7PrechargePrechargeXBALHLL

13ILLEGALAuto or Self RefreshXXHLLL

13,14ILLEGALMode Register SetOP CODELLLL

Row

Active

No Operation or Power

Down

Device De selectXXXXXH

3No OperationNo OperationXXHHHL

4ILLEGALRead/ReadAPCol Add./ A10BAHLHL

4Write/WriteAPCol Add./ A10BALLHL

Bank ActivateRow Add.BAHHLL

PrechargeXBALHLL

5Auto or Self RefreshXXHLLL

14Mode Register SetOP CODELLLL

Idle

NoteAction

Command

Current

State

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Ver. A

Table5: Function Truth Table

Col Add./A10

Row Add.

13,14ILLEGALMode Register SetOP CODELLLL

Write

with

Auto

Precharge

13ILLEGALAuto or Se lf RefreshXHLLL

4,12ILLEGALPrechargeBALHLL

4,12ILLEGALBank ActivateBAHHLL

12ILLEGALWrite/WriteAPBALLHL

12ILLEGALRead/ReadAPBAHLHL

Continue the BurstNo OperationXHHHL

Continue the BurstDevice De selectXXXXH

Continue the Burst

ILLEGAL

Termination Burst :

Start Write(AP)

ILLEGAL

Termination Burst :

Start the Precharge

ILLEGAL

DescriptionA0-A10BA/WE/CAS/RAS/CS

Device De selectXXXXXH

No OperationXXHHHL

12Read/ReadAPCol Add./A10BAHLHL

12Write/WriteAPCol Add./A10BALLHL

4,12Bank ActivateRow Add.BAHHLL

4,12ILLEGALPrechargeXBALHLL

13ILLEGALAuto or Se lf RefreshXXHLLL

13,14ILLEGALMode Register SetOP CODELLLL

Read

with

Auto

Precharge

Continue the BurstDevice De selectXXXXXH

Continue the BurstNo OperationXXHHHL

8,9

Terimination Burst :

Start READ(AP)

Read/ReadAPCol Add./A10BAHLHL

8Write/WriteAPCol Add./A10BALL

4Bank ActivateRow Add.BAHHLL

10PrechargeXBALHLL

13Auto or Self RefreshXXHLLL

13,14Mode Register SetOP CODELLLL

Write

NoteAction

Command

Current

State

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Ver. A

Table5: Function Truth Table

No Operation : Ro w

Active after tDPL

Device De selectXXXXXH

Col Add./A10

Start Write : Optional

AP(A10=H)

Read/Read APLHL

Start Write : Optional

AP(A10=H)

Write/WriteAPLHL

No Operation : Ro w

Active after tDPL

ILLEGAL

No Operation : ROw

Active after tRCD

No Operation : ROw

Active after tRCD

ILLEGAL

No Operation :

Bank(s) Idle after tRP

ILLEGAL

DescriptionA0-A10BA/WE/CAS/RAS/CS

No OperationHHL

4,12Bank ActivateRow Add.BAHHLL

4,13PrechargeHLL

13Auto or Self Refres hXXHLLL

13,14Mode Register SetOP CODELLLL

Write

Recovering

Device De selectXXXXXH

No OperationXXHHHL

4,12Read/Read APCol Add./A10BAHLHL

4,12Write/Write APCol Add./A10BALLHL

4,11,12Bank ActivateRow Add.BAHHLL

4,12ILLEGALPrechargeXBALHLL

13ILLEGALAuto or Se lf RefreshXXHLLL

13,14ILLEGALMode Register SetOP CODELLLL

Row

Activating

No Operation :

Bank(s) Idle after tRP

Device De selectXXXXXH

No Operation :

Bank(s) Idle after tRP

No OperationXXHHHL

4,12ILLEGALRead/ReadAPCol Add./ A10BAHLHL

4,12Write/WriteAPCol Add./ A10BALLHL

4,12Bank ActivateRow Add.BAHHLL

PrechargeXBALHLL

13Auto or Self Refres hXXHLLL

13,14Mode Register SetOP CODELLLL

Precharging

NoteAction

Command

Current

State

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Ver. A

Table5: Function Truth Table

No Operation : Id le

after 2 Clock Cycle

Device De selectXXXXXH

Col Add./A10

13ILLEGALRead/Read APLHL

13ILLEGALWrite/WriteAPLHL

No Operation : Id le

after 2 Clock Cycle

ILLEGAL

No Operation : Id le

after tRC

No Operation : Id le

after tRC

ILLEGAL

DescriptionA0-A10BA/WE/CAS/RAS/CS

No OperationHHL

13Bank ActivateRow Add.BAHHLL

13PrechargeHLL

13Auto or Self RefreshXXHLLL

13,14Mode Register SetOP CODELLLL

Mode

Accessing

Device De selectXXXXXH

No OperationXXHHHL

13Read/Read APCol Add./A10BAHLHL

13Write/Write APCol Add./A10BALLHL

13Bank ActivateRow Add.BAHHLL

13ILLEGALPrechargeXBALHLL

13ILLEGALAuto or Self RefreshXXHLLL

13,14ILLEGALMode Register SetOP CODELLLL

Refreshing

No Operation :

Precharge after tDPL

Device De selectXXXXXH

No Operation :

Precharge after tDPL

No OperationXXHHHL

4,9,12ILLEGALRead/ReadAPCol Add./ A10BAHLHL

4,12Write/WriteAPCol Add./ A10BALLHL

4,12Bank ActivateRow Add.BAHHLL

4,13PrechargeXBALHLL

13Auto or Self RefreshXXHLLL

13,14Mode Register SetOP CODELLLL

Write

Recovering

with

Auto

Precharge

NoteAction

Command

Current

State

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Ver. A

Note :

1. H: Logic High, L: Logic Low, X: Don't care, BA: Bank Address, AP: Auto Prech arge.

2. All entries assume that CKE was active during the preceding clock cycle.

3. If both banks are idle and CKE is inactive, then in power down cycle

4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address,

depending on the state of that bank.

5. If both banks are idle and CKE is inactive, then Self Refresh mode.

6. Illegal if tRCD is not satisfied.

7. Illegal if tRAS is not satisfied.

8. Must sati sfy burst interrupt condition.

9. Must satisfy bus co ntention, bu s turn arou nd, and/or write recovery req uirement s.

10. Must mask preceding data which don't satisfy tDPL.

11. Illeg al if tRRD is not satisfied

12. Illegal for single bank, but legal for other banks in multi-bank devices.

13. Illegal for all banks.

14. Mode Register Set and Extended Mode Register Set is same co mm a nd truth table exc ept BA.

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Ver. A

Table6: CKE Truth Table

4Refer to the Idl e State

sectio n of the Current State

Truth Table

XXXHHH

All

Banks

Idle

4XXHLHH

4XHLLHH

Auto RefreshXXHLLLHH

5Mode Register SetOP CODELLLLHH

4Refer to the Idl e State

sectio n of the Current State

Truth Table

XXXHLH

4XXHLLH

4XHLLLH

5Entry Self RefreshXXHLLLLH

Mode Register SetOP CODELLLLLH

5Power DownXXXXXXXL

Refer to Operations of the

Current State Truth Table

XXX

XXXHH

Any

State

other

than

listed

above

Begin Clock Suspend next

cycle

XXXXXXLH

Exit Clock Suspend next

cycle

XXXXXXHL

Maintain Clock SuspendXXXXXXLL

XXLXX

XXXLX

XXHHHL

Maintain Deep Power Down

Mode

Deep Power Dow n M od e Set

INVALID

ILLEGAL

Exit Self Refresh with No

Operation

Exit Self Refresh with Device

Deselect

INVALID

A0-A10BA/WE/CAS/RAS/CS

Current

Cycle

XXXXXLL

6XXXXXHL

2XXXXXXH

Deep

Power

Down

Maintain Power Down ModeXXXXXXLL

ILLEGALXXXXL

LHL

Power Down Mode Exit, All

Banks Idle

XXXXXH

2INVALIDXXXXXXXH

Power

Down

Maintain Self RefreshXXXXXXLL

3ILLEGALXXXXLLHL

3ILLEGALXXLHLHL

3XL

HHLHL

3XHHHLHL

3XXXXHHL

2XXXXXXH

Self

Refresh

NoteAction

CommandCKE

Current

State

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Ver. A

Note :

1. H: Logic High, L: Logic Low, X: Don't care

2. For the given current state CKE must be low in the previous cycle.

3. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode,

a NOP (or Device Deselect) command is requ ired on the first positive edge of clock after CKE goes high.

4. The address inputs depend on the command that is issued.

5. The Precharge Power Down mo de, the Self Refresh mode, and the Mode Register Set can only be entered from the all banks idle state.

6. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously.

When exiting deep power down mode, a NOP (or Device Desele ct) comma nd i s required on the first positive edge of clock after CKE goes

high and is maintained for a minimum 100usec.

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Ver. A

Table7: Absolute Maximum Rating

0 ~ 70Ambient Temperature (Commer c ial)

-1.0 ~ 2.6

-55 ~ 150

-25 ~ 85

Rating

WPD

Power Dissipation

mAIOS

Short Circ uit Output Current

VVDD, VDDQVoltage on VDD relative to VSS

VVIN, VOUT

Voltage on Any Pin relative to VSS

°C

TSTG

Storage Temperature

°C

Ambient Temperature (Industrial)

UnitSymbolParameter

Note :

Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress

rating only, and functional operati on of the device at these or any other co nditions abov e those indicat ed in the operation al sections of

this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Table8: Capacitance (TA=25 °C, f=1MHz, VDD=1.8V)

DQ0~DQ31

A0~A10, BA, CKE, /CS, /RAS, /CAS,

/WE, DQM0~DQM3

CLK

Min

Max

pFCIO

Data Input/Output Capa c it ance

pFCI2

pFCI1

Input Capacitance

UnitSymbolParameter

Table9: DC Operating Condition (Voltage referenced to VSS=0V, TA= -25 ~ 85 °C)

-75 / -10-60

MaxTypMin

-1.5

-1

0.9 x VDDQ

-0.3

0.8 x VDDQ

1.65

1.8

1.5

0.2

0.3

VDDQ+0.3

1.95

MaxTypMin

V1.891.81.71VDD

IOL= +0.1mAV0.2--VOL

Output Low Voltage

4uA1--1ILI

Input Leakage Current

2VVDDQ+0.3-0.8 x VDDQVIH

Input High Voltage

3V0.3 0-0.3VIL

Input Low Voltage

IOH= -0.1mAV--0.9 x VDDQVOH

Output High Voltage

Unit

1.8

-1.5

1.71

Speed

1.5

1.89

5ILO

Output Leakage Current

1VDDQ

Power Supply Voltage

NoteSymbolParameter

Note :

1. VDDQ must not ex ceed the level of VDD

2. VIH(max) = VDDQ+1.5V AC. The overshoot voltage duration is ≤3ns.

3. VIL(min) = -1.0V AC. The overshoot voltage duration is ≤3ns.

4. Any input 0V ≤VIN ≤VDDQ.

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.

5. DOUT is disabled, 0V ≤VOUT ≤VDDQ.

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Ver. A

Table10: AC Operating Condition (TA= -25 ~ 85 °C, VDD = 1.8V ±0.15V, VSS=0V)

V0.5 x VDDQVTRIP

Input Timing Meas urement Referen ce Leve l Voltage

ns1 / 1tR/ tF

Input Rise / Fall Time

V0.5 x VDDQVOUTREF

Output Timing Measureme nt Referenc e Level Voltage

pF30CL

Output Load Capacitance for Access Time Measurement

Unit

0.9 x VDDQ / 0.2

Value

VIH / VIL

AC Input High/Low Level Voltage

SymbolParameter

Output

500Ω

VDDQ

30pF

Output

30pF

50Ω

VTT=0.5 x VDDQ

Z0=50Ω

DC Output Load Circuit AC Output Load Circuit

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Ver. A

Table11: DC Characteristic (DC operating conditions unless otherwise noted)

Note :

1. Measur ed with outp uts open.

2. Refresh period is 64ms.

-75

0.5

-10-60

TCSRPASR

CKE ≤0.2V

ICC6

Self

Refresh

Current

120

45~85°C

2 Banks 90

-25~45°C

100

45~85°C

1 Bank 70

-25~45°C

uA10ICC7Deep Power Down Mode Current

2mA40

tRC ≥tRFC(min), All Ban k s Active

ICC5Auto Refresh Current (4K Cycle)

CKE ≥VIH(min), CLK ≤VIL ( m ax ), tCK = ∞

Input signals are stable.

ICC3NS

1mA80

tCK>tCK(m i n), IOL = 0 mA, Page Burst

All Banks Activated, tCCD = 1 clk

ICC4Burst Mode Operating Current

CKE & CLK ≤VIL(max), tCK = ∞

ICC3PS

CKE ≥VIH(min), /CS ≥VIH(min), tCK = 10ns

Input signals are changed one time during 2 cl k s.

ICC3N

Active Standby Current

in Non Power Down Mode

CKE ≤VIL(max), tCK = 10ns

ICC3P

Active Standby Current

in Power Down Mode

CKE & CLK ≤VIL(max), tCK = ∞

ICC2PS

Speed

CKE ≥VIH(min), CLK ≤VIL ( m ax ), tCK = ∞

Input signals are stable.

CKE ≥VIH(min), /CS ≥VIH(min), tCK = 10ns

Input signals are changed one time during 2 cl k s.

CKE ≤VIL(max), tCK = 10ns

Burst Le ngth=1, One Bank Activ e,

tRC ≥tRC(min) IOL = 0 mA

Test Condition

ICC2P

Precharge Standby Current

in Power Down Mode

ICC2N

Precharge Standby Current

in Non Power Down Mode ICC2NS

Note

Unit

ICC1Operating Current

SymbolParameter

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Ver. A

Table12: AC Characteristic (AC operation conditions unless otherwise noted)

1.20.51.20.51.20.5tTTransition time 57067.566tXSRExit SELF REFR ESH to ACTIVE command 5

7067.566tRFCAUTO REFRESH period ms646464tREFRefresh peri od (4,096 rows)

9111tPED

CKE to clock enable or power-down exit

setup mode

CLK

111tCKED

CKE to clock disable or power-down entry

mode

37.5

22.5

67.5

22.5

1.8

2.5

1.0

2.0

1.0

2.0

1.0

2.0

1.0

2.0

2.5

7.5

Min-75

100K

1000

Max

611tBDLLast data- in to burst STOP c ommand 611tCDLLast data-in to new READ/WRITE command

CL = 2

CL = 3 22tROH2

822tMRD

LOAD MODE REGISTER command to ACTI VE

or REFRESH c ommand

600tDQMDQM to data mask during WR I T Es 6

CLK

22tDQZDQM to data high-impedance d uring READs

2012tDPLData-in to PRECHARGE command 730tDALData-in to ACTIVE command

600tDWDWRITE command to input data delay

CLK

11tCCD

READ/WRITE command to READ/WRITE

command

2012tRRDACTIVE bank a to ACTIVE bank b command

2418tRPPRECHARGE command period

2.01.5tDSData-In Setup Time

2.01.5tASAddress Setup Time

2.01.5tCMS/CS, /RAS, /CAS, /WE, DQM Setup Time

2.01.5tCKSCKE Setup Time

1.01.0tCMH/CS, /RAS, /CAS, /WE, DQM Hold Time

1.01.0tCKHCKE Hold Time

32.52.5tCHCLK High-Level Width 32.52.5tCLCLK Low-Level Width

1.8

2.5

1.0

6.0

Min-60

100K

5.5

1000

Max MaxMin

1000

10tCK3CL = 3

CLK Cycle Time 10tCK2CL = 2

20tRCDACTIVE to READ or WRITE delay

3tROH3

Data-out to high-impedanc e from

PRECHARGE command

564tRCACTIVE bank a to ACTIVE bank a command

8CL = 2

CL = 3 4

8tHZ3

Data-Out High-Impedance Time

from CLK (pos.edge) tHZ2 1.0tLZData-Out Low-Impedance Time 2.5tOHData-O ut Hold Time (loa d ) 1.8tOHNData-Out Hold Time ( no load)

1.0tDHData-In Hold Time

100K40tRASACTIVE to PRECHARGE command

1.0tAHAddress Hold Time

8tAC2CL = 2

CL = 3 2

8tAC3

Access time from CLK (pos. edge)

-10 NoteUnitSymbolParameter

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Ver. A

Note :

1. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified forthe

clock pin) during access or precharge states (READ, WRITE, including tDPL, and PRECHARGE commands). CKE may be used to

reduce the data r a te.

2. tAC at CL = 3 with no load is 5.5ns and is guaranteed by design. Access time to be measured with input signals of 1V/ns edge

rate, from 0.8V to 0.2V. If tR > 1n s, then (tR/2-0.5)ns should be added to the parameter.

3. AC characteristic s assu me tT = 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]n s should be added to the parameter.

4. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid

data element will meet tOH before going High-Z.

5. Parameter guaranteed by design.

A. Target values listed with alternative values in parentheses.

B. tRFC must be less than or equal to tRC+1 C LK

tXSR must be less than or equal to tRC+1CLK

6. Required c locks are specif ied by JEDEC funct ionality and are not dependent on any timing parameter.

7. Timing actually specified by tDPL plus tRP; clock(s) specified as a reference only at minimum cycl e rate

8. JEDEC and PC100 specify three clocks.

9. Timing actually specified by tCKs; clock(s) specified as a reference only at minimum cycle rate.

10. A new command can be given tRC after self refresh exit.

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Ver. A

Temperature Compensated Self Refresh

Temperature Compensated Self Refresh allows the controller to program the Refresh interval during SELF REFRESH mode, according to

the case temperature of the Low Power SDRAM devi ce. This allow s great power savings during SELF REFRESH during most operating

temperature ranges. Only during extreme temperatures would the controller have to select a TCSR level that will guarantee data during

SELF REFRESH.

Every cell in the DRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is dependent on

temperature. At higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed

more often. Historically, during Self Refresh, the refresh rate has been set to accommodate the worst case, or highest temperature

range expected.

Thus, during ambient temperatures, the power consumed during refresh was unnecessarily high, because the refresh rate was set to

accom m odate th e h igher temp era ture s. Setti ng M4 a nd M3, all ow th e DRAM to acc o mmod ate m ore sp ecifi c tem peratur e reg ion s dur ing

SELF REFRESH. There are four temperature settings, which will va ry the SELF REFRESH current according to the selected temperature.

This selectable refresh rate will save power when the DRAM is operating at normal temperatures.

Partial Array Self Refr esh

For further power sav ings during SELF REFRESH, the PASR feature a llows the controller to select the amount of memory that will be

refreshed during SELF REFRESH. The refresh options are Two Ba nk;all tw o banks, One Ba nk;bank a. WRITE and READ comm ands can

still occur during standard operation, but only the selected banks will be refreshed during SELF REFRESH. Data in banks that are

disabled will be lost.

Deep Power Down

Deep Power Down is an operating mode to ach ieve ma ximum pow er reduction by eliminating the power of the whole memory array of

the devic es. Data wi ll not be retai ned once th e d e vice enters Deep Power Down Mode.

This mode is entered by having all banks idle then /CS and /WE held low with /RAS and /CAS held high at the rising edge of the clock,

while CKE is low. This mode is exited by asserting CKE high.

Special Operation for Low Power Consumption

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Ver. A

Figure7: Deep Power Down Mode Entry

Figure8: Deep Power Down Mode Exit

CLK

CKE

/CS

/RAS

/CAS

/WE

100 µ s tRP tRFC

Deep Power Down Exit

All Banks Precharge

Auto Refresh Mode Register Set

Extended Mod e Register Se t

New Command

Auto Refresh

CLK

CKE

/CS

/RAS

Precharge if needed Deep Power Down Entry

tRP

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Ver. A

Figure9: 90Ball FBGA Configuration

[Bottom View]

9 8 7 6 5 4 3 2 1

0.80

6.4

13.0±0.1

8.0±0.1

11.2

1.2max 0.35±0.05

0.45±0.05

Unit [mm]

0.80

0.8

Note: All Dimensions in millimeters

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Ver. A

Ordering Information

N 32 D 32 18 LP A X - XX X

Density

32 = 32Mb

Product Type

D = SDRAM

Data I/O Width

32 = 32 I/O

Power Supply

18 = 1.8V

Temperature

Package

F2 = FBGA Green (90Ball)

W = Wafer

Speed

60 = 6.0ns (166MHz)

75 = 7.5ns (133MHz)

10 = 10ns (100MHz)

Features

Generation

A = 1st Generation

LP = Low Pow er SDRAM

Revision History

Initial ReleaseJanuary 5th , 2007A

Change DescriptionDateVersion

Enable Semiconductor Corp.

Enable Semiconductor Corp. (“Enable") reserves the right to change or modify the information contained in this data sheet and the products described therein,

without prior notice. Enable does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data

sheet are provided for illustration purposes only and they vary depending upon specific applications.

Enable makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does Enable assume any liability arising out of the

application or use of any product or circuit described herein. Enable does not authorize use of its products as critical components in any application in which the

failure of the Enable product may be expected to result in significant injury or death, including life support systems and critical medical instrument.

C = Commercial (0°Cto 70°C)

I = Industrial (-25°Cto 85°C)