APA-EVAL-BRD300 - Actel Corporation

ProASICPLUS Evaluation Board

User’s Guide

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ii

Actel Corporation, Sunnyvale, CA 94086

Printed in the United States of America

Part Number: 51700003-0

Release: December 2002

No part of this document may be copied or reproduced in any form or by any means

without prior written consent of Actel.

Actel makes no warranties with respect to this documentation and disclaims any im-

plied warranties of merchantability or fitness for a particular purpose. Information

in this document is subject to change without notice. Actel assumes no responsibil-

ity for any errors that may appear in this document.

This document contains confidential proprietary information that is not to be dis-

closed to any unauthorized person without prior written consent of Actel Corpora-

tion.

Trademarks

Actel and the Actel logotype are registered trademarks of Actel Corporation.

Adobe and Acrobat Reader are registered trademarks of Adobe Systems, Inc.

Liberty is a licensed trademark of Synopsys Inc. This product uses SDC, a Propri-

etary format of Synopsys Inc.

Libero is a trademark of Actel Corporation.

Mentor Graphics, Viewlogic, ViewDraw, MOTIVE, and ModelSim are registered

trademarks of Mentor Graphics, Inc.

Synplify and Synplicity are registered trademarks of Synplicity, Inc.

Verilog is a registered trademark of Open Verilog International.

WaveFormer Lite and SynaptiCAD are trademarks of SynaptiCAD, Inc.

Windows is a registered trademark and Windows NT is a trademark of Microsoft

Corporation in the U.S. and other countries.

All other products or brand names mentioned are trademarks or registered trade-

marks of their respective holders.

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iii

Table of Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Document Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Document Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . .5

1Contents and System Requirements . . . . . . . . . . . . . . . .7

Evaluation Kit Contents . . . . . . . . . . . . . . . . . . . . . . . . . .7

System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2Setup and Self Test . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Software Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Testing the Evaluation Board. . . . . . . . . . . . . . . . . . . . . . . .9

Programming the Test file . . . . . . . . . . . . . . . . . . . . . . . . 10

3Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . 11

Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Programming Headers . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Clock Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

ABoard Connections . . . . . . . . . . . . . . . . . . . . . . . . . 17

BBoard Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

CProduct Support . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Actel U.S. Toll-Free Line . . . . . . . . . . . . . . . . . . . . . . . . . 35

Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Customer Applications Center . . . . . . . . . . . . . . . . . . . . . . 36

Guru Automated Technical Support . . . . . . . . . . . . . . . . . . . 36

Web Site. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

FTP Site . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Contacting the Customer Applications Center . . . . . . . . . . . . . . 36

Worldwide Sales Offices . . . . . . . . . . . . . . . . . . . . . . . . . 38

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5

Introduction

Thank you for purchasing Actel’s ProASICPLUS Evaluation Board.

The purpose of this user’s guide is to provide you with information so you can

easily evaluate the ProASICPLUS devices.

This is the first release of the user’s guide. The most up-to-date version of this

guide is available at:

http://www.actel.com/products/tools/hw.html

Document Contents

Chapter 1 - Contents and System Requirements describes the

contents of the ProASICPLUS Evaluation Kit.

Chapter 2 - Setup and Self Test describes how to setup the ProASICPLUS

Evaluation Board and how to perform a self test.

Chapter 3 - Hardwar e Description describes the components of the

ProASICPLUS Evaluation Board.

Appendix A - Board Connections lists a board connection table.

Appendix B - Board Sc hem atic s show illustrations of the ProASICPLUS

Evaluation Board.

Appendix C - Product Support describes our support services.

Document Assumptions

This user’s guide assumes the following:

• You intend to use Actel’s Libero software.

• You have installed and are familiar with Actel’s Libero software.

• You are familiar with the VHDL or Verilog hardware description language.

• You are familiar with UNIX workstations and operating systems or PCs and

Windows operating systems.

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7

1

Contents and System Requirements

This chapter describes the differences between the three versions of the

ProASICPLUS evaluation board. This chapter also details the contents of the

ProASICPLUS evaluation kit and provides power supply and software system

requirements.

Evaluation Kit Contents

The ProASICPLUS evaluation kit has three board versions.

Note: There is no socket on these boards.

APA-EVAL-BRD1

This board contains all the surrounding circuitry, but no APA device. For this

board, it is assumed that you will acquire a device and solder it to the board

yourself. This allows you to use the board with any device in the APA family.

APA-EVAL-BRD300

Same as BRD1 but with an APA300 device mounted.

APA-EVAL-BRD075

Same as BRD1 but with an APA075 device mounted.

When you purchase any of the above board versions, you also receive the

following:

• Evaluation board - one of the three listed above

• The ProASICPLUS Evaluation Board User’s Guide

•Customer Letter

• CD with design examples

For the CD contents, review the ReadMe.doc file at the top level of the

CD. As more design examples become available, the CD contents will

change. For the latest design examples, refer to the Hardware Tools

section of the Actel website:

http://www.actel.com/products/tools/hw.html

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Chapter 1: Contents and System Requirements

8

Power Supply and Software Requirements

This section describes power supply and software requirements for the

ProASICPLUS evaluation kit.

Power Supply The ProASICPLUS evaluation board requires the following:

• Wall mount power supply

• 9V, 500mA supply with 2.1mm female connector P5 type

• Digikey part number T413-P5P-ND for US

• Digikey part number T408-P5P-ND for Europe

Software Each ProASICPLUS evaluation board requires a different version of the

software.

APA-EVAL-BRD075

This board can use the free evaluation Libero Silver version, which

does not include simulation. To include simulation, use the Libero Gold

version.

APA-EVAL-BRD300

This board requires a full Libero Platinum license.

APA-EVAL-BRD1

With the blank board, you can select any device from the ProASICPLUS family

in a 208 PQFP footprint and solder it to the board yourself.

Use the appropriate software for the device you choose. For software support

details, refer to the Actel Website:

http://www.actel.com/products/tools/support.html

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9

2

Setup and Self Test

Software Installation

Since this package does not include software, this guide does not provide

software installation instructions. For software installation instructions, refer to

the Actel Installation and Licensing Guide at:

http://www.actel.com/products/tools/libero/docs.html

Testing the Evaluation Board

If the evaluation board is shipped directly from Actel, it contains a test program

that determines if the board works properly.

To test the evaluation board:

1. Supply power to the board.

2. T u rn on the ON/OFF sw itch.

3. Perform the actions described in Table 2-1.

Table 2-1. Evaluation Board Test

Action Result Pass/Fail

Press PB1 multiple times, but not

too fast A sequence of LEDs light up Pass

Press and hold SW1 All LEDs are unlit Pass

Press and hold SW2 All LEDs light up except DS1 Pass

Press and hold SW3

A random sequence of LEDs

light up while you hold the

switch

Pass

Press and hold SW4 The LED is lit/unlit in a

01101010 pattern Pass

Any two switches are pressed

together Creates a 00100110 pattern. Pass

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Chapter 2: Setup and Self Test

10

Programming the Test file

If you want to retest the evaluation board, you can reprogram the board using

the test program at any time. Use the STAPL file test.stp or the bitstream file

test.bit. These files are included on the Evaluation Kit CD. Table 2-2 describes

the actions you should perform when retesting your evaluation board.

This design is currently implemented for the APA300 device. If you have a

device of a different size, you can recompile the design into other device sizes.

The design files are available under actelprj/eval in the Evaluation Kit CD.

For instructions on programming the device using Flash Pro, refer to the Flash

Pro User’s Guide at:

http://www.actel.com/techdocs/manuals/docs/flashproUG.pdf

Table 2-2. Retesting the Evaluation Board

Action Result Pass/Fail

Press PB1 multiple

times, but not too fast

Count sequence should be visible on

the LED Pass

Press and hold SW1 All LEDs are unlit Pass

Press and hold SW2 All LEDs are lit Pass

Press and hold SW3 Count sequence runs while you hold

the switch Pass

Press and hold SW4 LED is lit/unlit alternately in a

10101010 pattern Pass

Any two switches are

pressed together Creates a 00110011 pattern Pass

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11

3

Hardware Description

This chapter describes the components of the evaluation board. See Figure 3-1

for a schematic of the evaluation board.

Figure 3-1. ProASICPlus Evaluation Board

The ProASICPlus evaluation board consists of the following:

• Wall mount power supply connector, with switch and LED indicator

• Jumper to select between 2.5V and 3.3V I/O voltages

• 40MHz oscillator and manual clock option

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Chapter 3: Hardware Description

12

• Small program header (compatible with both Flash Pro and Silicon Sculptor)

• Four switches (provides input to the device)

• eight LED (driven by outputs from the device)

• Jumpers (allows disconnection of all external circuitry from the FPGA)

For further information, refer to the following appendices:

Appendix A – Board Connections

Appendix B – Board Schematics

Power Supplies

The evaluation board requires the following power supplies:

• Wall mount power supply

• 9V, 500mA supply with 2.1mm female connector P5 type

Digikey part number T413-P5P-ND for US

Digikey Part Number T408-P5P-ND for Europe

• The power is controlled by an On/Off switch.

• An LED DS9 indicates the presence of a working wall mount supply

JP1 can be used to select either 3.3V or 2.5V for the Device I/O Voltage

JP2 connects AGND to GND for the use of the PLL.

JP3 connects AVDD to VDD for the use of the PLL.

Note: The five pin header next to the power supply connection can also be

used to drive power to the board from a lab supply.

Programming Headers

A small form programming header, which is suitable to use with both the Flash

Pro and Silicon Sculptor II is supplied with the board. The footprint for the

large programming header is on the board, but has not been populated.

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Clock Circuits

13

When using Flash Pro, use the STAPL(.STP) file to program the device.

Silicon Sculptor II requires the ISP programming adapter module SMPA-ISP-

ACTEL-2-KIT, then you can use either the bitstream (.BIT) file or STAPL

(.STP) file.

Clock Circuits

The evaluation board has two clock circuits, the 40MHz oscillator and the

manual clock.

40MHz

Oscillator The 40MHz oscillator on the board is connected to JP4. JP4 connects

the clock to pin 24 of the devices. Pin 24 is a global input pin.

To use pin 24 for a different clock signal, disconnect JP4.

If you want to use a different Clock Frequency, purchase the Crystal from

Epson programmed to a variety of frequencies. The SG-8002JC40.000M-PCC

from Epson is also available through Digikey.

Manual Clock When activated, the manual clock button (PB1) lights DS10 the pulse generated

LED and generates a pulse. This is connected to JP17. JP17 connects to pin

128 of the device. Pin 128 is a global input pin.

If you want to use pin 128 for a different clock signal, disconnect JP17.

LED Device Connections

Eight LED are connected to the device via jumpers. If the jumpers are in place,

the device I/O can drive the LED. The LED changes based on the following

output:

• A 1 on the output of the device lights the LED.

• A 0 on the output of the device switches off the LED.

• An unprogrammed or tristated output may show a faintly lit LED

Table 3-1 lists the LED/device connections.

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Chapter 3: Hardware Description

14

If you want to use the device I/O for other purposes, remove the jumpers.

Switches Device Connections

Four switches are connected to the device via jumpers. If the jumpers are in

place the device I/O can be driven by the following switches:

• Pressing the switch drives a 1 into the device. The 1 continues to drive while

you hold the switch.

• Releasing the switch drives a zero into the device.

Table 3-2 lists the switch/device connections.

If you want to use the device I/O for other purposes, remove the jumpers.

Table 3-1. LED Device Connections

LED Device Connection

DS1 87

DS2 90

DS3 91

DS4 92

DS5 93

DS6 94

DS7 95

DS8 96

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Switches Device Connections

15

Table 3-2. Switch Device Connections

Switch Device

Connection

SW1 55

SW2 63

SW3 69

SW4 79

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Chapter 3: Hardware Description

16

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17

A

Board Connections

This appendix lists a table for board connections.

Table A-1 shows the board connections.

Table A-1. Board Connections

Pin No. APA

075 APA

150 APA

300 APA

450 APA

600 APA

750 APA

1000 Board

Connect

1GND GND GND GND GND GND GND GND

2I/O I/O I/O I/O I/O I/O I/O I/O

3I/O I/O I/O I/O I/O I/O I/O I/O

4I/O I/O I/O I/O I/O I/O I/O I/O

5I/O I/O I/O I/O I/O I/O I/O I/O

6I/O I/O I/O I/O I/O I/O I/O I/O

7I/O I/O I/O I/O I/O I/O I/O I/O

8I/O I/O I/O I/O I/O I/O I/O I/O

9I/O I/O I/O I/O I/O I/O I/O I/O

10 I/O I/O I/O I/O I/O I/O I/O I/O

11 I/O I/O I/O I/O I/O I/O I/O I/O

12 I/O I/O I/O I/O I/O I/O I/O I/O

13 I/O I/O I/O I/O I/O I/O I/O I/O

14 I/O I/O I/O I/O I/O I/O I/O I/O

15 I/O I/O I/O I/O I/O I/O I/O I/O

16 VDD VDD VDD VDD VDD VDD VDD VDD

17 GND GND GND GND GND GND GND GND

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Appendix A: Board Connections

18

18 I/O I/O I/O I/O I/O I/O I/O I/O

19 I/O I/O I/O I/O I/O I/O I/O I/O

20 I/O I/O I/O I/O I/O I/O I/O I/O

21 I/O I/O I/O I/O I/O I/O I/O I/O

22 VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP

23 I/O I/O I/O I/O I/O I/O I/O I/O

24 GL GL GL GL GL GL GL JP4

25 AGND AGND AGND AGND AGND AGND AGND JP2

26 NPECL NPECL NPECL NPECL NPECL NPECL NPECL NPECL

27 AV D D AV DD AV D D AVDD AVDD AV D D AV D D JP3

28 PPECL

(I/P)

PPECL

(I/P)

PPECL

(I/P)

PPECL

(I/P)

PPECL

(I/P)

PPECL

(I/P)

PPECL

(I/P)

PPECL

(I/P)

29 GND GND GND GND GND GND GND GND

30 GL GL GL GL GL GL GL GL

31 I/O I/O I/O I/O I/O I/O I/O I/O

32 I/O I/O I/O I/O I/O I/O I/O I/O

33 I/O I/O I/O I/O I/O I/O I/O I/O

34 I/O I/O I/O I/O I/O I/O I/O I/O

35 I/O I/O I/O I/O I/O I/O I/O I/O

36 VDD VDD VDD VDD VDD VDD VDD VDD

37 I/O I/O I/O I/O I/O I/O I/O I/O

Table A-1. Board Connections

Pin No. APA

075 APA

150 APA

300 APA

450 APA

600 APA

750 APA

1000 Board

Connect

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19

38 I/O I/O I/O I/O I/O I/O I/O I/O

39 I/O I/O I/O I/O I/O I/O I/O I/O

40 VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP

41 GND GND GND GND GND GND GND GND

42 I/O I/O I/O I/O I/O I/O I/O I/O

43 I/O I/O I/O I/O I/O I/O I/O I/O

44 I/O I/O I/O I/O I/O I/O I/O I/O

45 I/O I/O I/O I/O I/O I/O I/O I/O

46 I/O I/O I/O I/O I/O I/O I/O I/O

47 I/O I/O I/O I/O I/O I/O I/O I/O

48 I/O I/O I/O I/O I/O I/O I/O I/O

49 I/O I/O I/O I/O I/O I/O I/O I/O

50 I/O I/O I/O I/O I/O I/O I/O I/O

51 I/O I/O I/O I/O I/O I/O I/O I/O

52 GND GND GND GND GND GND GND GND

53 VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP

54 I/O I/O I/O I/O I/O I/O I/O I/O

55 I/O I/O I/O I/O I/O I/O I/O JP5

56 I/O I/O I/O I/O I/O I/O I/O I/O

57 I/O I/O I/O I/O I/O I/O I/O I/O

58 I/O I/O I/O I/O I/O I/O I/O I/O

Table A-1. Board Connections

Pin No. APA

075 APA

150 APA

300 APA

450 APA

600 APA

750 APA

1000 Board

Connect

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Appendix A: Board Connections

20

59 I/O I/O I/O I/O I/O I/O I/O I/O

60 I/O I/O I/O I/O I/O I/O I/O I/O

61 I/O I/O I/O I/O I/O I/O I/O I/O

62 I/O I/O I/O I/O I/O I/O I/O I/O

63 I/O I/O I/O I/O I/O I/O I/O JP6

64 I/O I/O I/O I/O I/O I/O I/O I/O

65 GND GND GND GND GND GND GND GND

66 I/O I/O I/O I/O I/O I/O I/O I/O

67 I/O I/O I/O I/O I/O I/O I/O I/O

68 I/O I/O I/O I/O I/O I/O I/O I/O

69 I/O I/O I/O I/O I/O I/O I/O JP7

70 I/O I/O I/O I/O I/O I/O I/O I/O

71 VDD VDD VDD VDD VDD VDD VDD VDD

72 VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP

73 I/O I/O I/O I/O I/O I/O I/O I/O

74 I/O I/O I/O I/O I/O I/O I/O I/O

75 I/O I/O I/O I/O I/O I/O I/O I/O

76 I/O I/O I/O I/O I/O I/O I/O I/O

77 I/O I/O I/O I/O I/O I/O I/O I/O

78 I/O I/O I/O I/O I/O I/O I/O I/O

79 I/O I/O I/O I/O I/O I/O I/O JP8

Table A-1. Board Connections

Pin No. APA

075 APA

150 APA

300 APA

450 APA

600 APA

750 APA

1000 Board

Connect

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21

80 I/O I/O I/O I/O I/O I/O I/O I/O

81 GND GND GND GND GND GND GND GND

82 I/O I/O I/O I/O I/O I/O I/O I/O

83 I/O I/O I/O I/O I/O I/O I/O I/O

84 I/O I/O I/O I/O I/O I/O I/O I/O

85 I/O I/O I/O I/O I/O I/O I/O I/O

86 I/O I/O I/O I/O I/O I/O I/O I/O

87 I/O I/O I/O I/O I/O I/O I/O JP9

88 VDD VDD VDD VDD VDD VDD VDD VDD

89 VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP

90 I/O I/O I/O I/O I/O I/O I/O JP10

91 I/O I/O I/O I/O I/O I/O I/O JP11

92 I/O I/O I/O I/O I/O I/O I/O JP12

93 I/O I/O I/O I/O I/O I/O I/O JP13

94 I/O I/O I/O I/O I/O I/O I/O JP14

95 I/O I/O I/O I/O I/O I/O I/O JP15

96 I/O I/O I/O I/O I/O I/O I/O JP16

97 GND GND GND GND GND GND GND GND

98 I/O I/O I/O I/O I/O I/O I/O I/O

99 I/O I/O I/O I/O I/O I/O I/O I/O

100 I/O I/O I/O I/O I/O I/O I/O I/O

Table A-1. Board Connections

Pin No. APA

075 APA

150 APA

300 APA

450 APA

600 APA

750 APA

1000 Board

Connect

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Appendix A: Board Connections

22

101 TCK TCK TCK TCK TCK TCK TCK TCK

102 TDI TDI TDI TDI TDI TDI TDI TDI

103 TMS TMS TMS TMS TMS TMS TMS TMS

104 VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP

105 GND GND GND GND GND GND GND GND

106 VPP VPP VPP VPP VPP VPP VPP VPP

107 VPN VPN VPN VPN VPN VPN VPN VPN

108 TDO TDO TDO TDO TDO TDO TDO TDO

109 TRST TRST TRST TRST TRST TRST TRST TRST

110 RCK RCK RCK RCK RCK RCK RCK RCK

111 I/O I/O I/O I/O I/O I/O I/O I/O

112 I/O I/O I/O I/O I/O I/O I/O I/O

113 I/O I/O I/O I/O I/O I/O I/O I/O

114 I/O I/O I/O I/O I/O I/O I/O I/O

115 I/O I/O I/O I/O I/O I/O I/O I/O

116 I/O I/O I/O I/O I/O I/O I/O I/O

117 I/O I/O I/O I/O I/O I/O I/O I/O

118 I/O I/O I/O I/O I/O I/O I/O I/O

119 I/O I/O I/O I/O I/O I/O I/O I/O

120 I/O I/O I/O I/O I/O I/O I/O I/O

121 I/O I/O I/O I/O I/O I/O I/O I/O

Table A-1. Board Connections

Pin No. APA

075 APA

150 APA

300 APA

450 APA

600 APA

750 APA

1000 Board

Connect

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23

122 GND GND GND GND GND GND GND GND

123 VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP

124 I/O I/O I/O I/O I/O I/O I/O I/O

125 I/O I/O I/O I/O I/O I/O I/O I/O

126 VDD VDD VDD VDD VDD VDD VDD VDD

127 I/O I/O I/O I/O I/O I/O I/O I/O

128 GL GL GL GL GL GL GL JP17

129 PPECL

(I/P)

PPECL

(I/P)

PPECL

(I/P)

PPECL

(I/P)

PPECL

(I/P)

PPECL

(I/P)

PPECL

(I/P)

PPECL

(I/P)

130 GND GND GND GND GND GND GND GND

131 AV D D AV D D AV D D AV DD AVDD AV D D AV D D JP3

132 NPECL NPECL NPECL NPECL NPECL NPECL NPECL NPECL

133 AGND AGND AGND AGND AGND AGND AGND JP2

134 GL GL GL GL GL GL GL GL

135 I/O I/O I/O I/O I/O I/O I/O I/O

136 I/O I/O I/O I/O I/O I/O I/O I/O

137 I/O I/O I/O I/O I/O I/O I/O I/O

138 VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP

139 I/O I/O I/O I/O I/O I/O I/O I/O

140 I/O I/O I/O I/O I/O I/O I/O I/O

141 GND GND GND GND GND GND GND GND

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QS_Tutorial_eval.book Page 23 Monday, January 13, 2003 1:08 PM

Appendix A: Board Connections

24

142 VDD VDD VDD VDD VDD VDD VDD VDD

143 I/O I/O I/O I/O I/O I/O I/O I/O

144 I/O I/O I/O I/O I/O I/O I/O I/O

145 I/O I/O I/O I/O I/O I/O I/O I/O

146 I/O I/O I/O I/O I/O I/O I/O I/O

147 I/O I/O I/O I/O I/O I/O I/O I/O

148 I/O I/O I/O I/O I/O I/O I/O I/O

149 I/O I/O I/O I/O I/O I/O I/O I/O

150 I/O I/O I/O I/O I/O I/O I/O I/O

151 I/O I/O I/O I/O I/O I/O I/O I/O

152 I/O I/O I/O I/O I/O I/O I/O I/O

153 I/O I/O I/O I/O I/O I/O I/O I/O

154 I/O I/O I/O I/O I/O I/O I/O I/O

155 I/O I/O I/O I/O I/O I/O I/O I/O

156 GND GND GND GND GND GND GND GND

157 VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP

158 I/O I/O I/O I/O I/O I/O I/O I/O

159 I/O I/O I/O I/O I/O I/O I/O I/O

160 I/O I/O I/O I/O I/O I/O I/O I/O

161 I/O I/O I/O I/O I/O I/O I/O I/O

162 GND GND GND GND GND GND GND GND

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QS_Tutorial_eval.book Page 24 Monday, January 13, 2003 1:08 PM

25

163 I/O I/O I/O I/O I/O I/O I/O I/O

164 I/O I/O I/O I/O I/O I/O I/O I/O

165 I/O I/O I/O I/O I/O I/O I/O I/O

166 I/O I/O I/O I/O I/O I/O I/O I/O

167 I/O I/O I/O I/O I/O I/O I/O I/O

168 I/O I/O I/O I/O I/O I/O I/O I/O

169 I/O I/O I/O I/O I/O I/O I/O I/O

170 VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP

171 VDD VDD VDD VDD VDD VDD VDD VDD

172 I/O I/O I/O I/O I/O I/O I/O I/O

173 I/O I/O I/O I/O I/O I/O I/O I/O

174 I/O I/O I/O I/O I/O I/O I/O I/O

175 I/O I/O I/O I/O I/O I/O I/O I/O

176 I/O I/O I/O I/O I/O I/O I/O I/O

177 I/O I/O I/O I/O I/O I/O I/O I/O

178 GND GND GND GND GND GND GND GND

179 I/O I/O I/O I/O I/O I/O I/O I/O

180 I/O I/O I/O I/O I/O I/O I/O I/O

181 I/O I/O I/O I/O I/O I/O I/O I/O

182 I/O I/O I/O I/O I/O I/O I/O I/O

183 I/O I/O I/O I/O I/O I/O I/O I/O

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Appendix A: Board Connections

26

184 I/O I/O I/O I/O I/O I/O I/O I/O

185 I/O I/O I/O I/O I/O I/O I/O I/O

186 VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP

187 VDD VDD VDD VDD VDD VDD VDD VDD

188 I/O I/O I/O I/O I/O I/O I/O I/O

189 I/O I/O I/O I/O I/O I/O I/O I/O

190 I/O I/O I/O I/O I/O I/O I/O I/O

191 I/O I/O I/O I/O I/O I/O I/O I/O

192 I/O I/O I/O I/O I/O I/O I/O I/O

193 I/O I/O I/O I/O I/O I/O I/O I/O

194 I/O I/O I/O I/O I/O I/O I/O I/O

195 GND GND GND GND GND GND GND GND

196 I/O I/O I/O I/O I/O I/O I/O I/O

197 I/O I/O I/O I/O I/O I/O I/O I/O

198 I/O I/O I/O I/O I/O I/O I/O I/O

199 I/O I/O I/O I/O I/O I/O I/O I/O

200 I/O I/O I/O I/O I/O I/O I/O I/O

201 I/O I/O I/O I/O I/O I/O I/O I/O

202 I/O I/O I/O I/O I/O I/O I/O I/O

203 I/O I/O I/O I/O I/O I/O I/O I/O

204 I/O I/O I/O I/O I/O I/O I/O I/O

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QS_Tutorial_eval.book Page 26 Monday, January 13, 2003 1:08 PM

27

205 I/O I/O I/O I/O I/O I/O I/O I/O

206 I/O I/O I/O I/O I/O I/O I/O I/O

207 I/O I/O I/O I/O I/O I/O I/O I/O

208 VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP

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QS_Tutorial_eval.book Page 27 Monday, January 13, 2003 1:08 PM

Appendix A: Board Connections

28

QS_Tutorial_eval.book Page 28 Monday, January 13, 2003 1:08 PM

29

B

Board Schematics

This appendix shows illustrations of the ProASIC Evaluation Board.

Figure B-1 shows a board schematic.

QS_Tutorial_eval.book Page 29 Monday, January 13, 2003 1:08 PM

Appendix B: Board Schematics

30

Figure B-1. Board Schematic

C9

1

2

C11

1

2

C15

1

2

C10

1

2

C6

1

2

+3.3v

C7

1

2

C13

1

2

Good

Power

Enable

In

Out

Gnd

TPS77633PWP

VR1

6

7

5

13

14

16

3

C19

1

2

1.0K

R21

1

2

C17

1

2

+3.3v

JP2 12

330

R4

1

2

JP3 12

HDR4

52

C36

1

2

C12

1

2

C5

1

2

Gnd

Out

V+

40.000MHz

Oscillator

Y1 3

4

2

TP2

4

TP2

5

TP2

1

TP2

2

JP4

12

+3.3v

330

R3

1

2

220

R2

1

2

C25

1

2

Global or I/O

VDD(+2.5v)

NPECL1

Analog Gnd

VDDP(2.5/3.3v)

Ground

I/O

Ground

U1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

C23

1

2

+2.5v

Global or I/O

Analog Gnd

NPECL2

Ground

VDDP(2.5/3.3v)

I/O

AVDD

VDD(+2.5v)

Ground

I/O

U1

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

P1

10

C3

1

2

C22

1

2

P2

25

P2

23

P2

21

P2

15

Global or I/O

AVDD(+2.5v)

PPECL1

VDD(+2.5v)

VDDP(2.5/3.3v)

Ground

I/O

Ground

U1

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

Ground

VDDP(2.5/3.3v)

I/O

VDD(+2.5v)

I/O

U1

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

VDD(+2.5v)

VDDP(2.5/3.3v)

I/O

Ground

U1

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

TCK

TDI

TMS

VDD(+2.5v)

VDDP(2.5/3.3v)

Ground

I/O

Ground

U1

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

Global or I/O

TRST

PPECL2

RCK

TDO

VPN

VPP

VDD(+2.5v)

VDDP(2.5/3.3v)

Ground

I/O

Ground

U1

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

Ground

VDDP(2.5/3.3v)

I/O

VDD(+2.5v)

Ground

I/O

U1

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

P1

15

P2

11

P2

10

220

R5

1

2

HDR4

51

HDR4

50

HDR4

49

HDR4

48

HDR4

47

HDR4

46

HDR4

45

HDR4

44

HDR4

43

HDR4

42

HDR4

41

HDR4

40

C8

1

2

C21

1

2

C27

1

2

C28

1

2

P1

9

P1

3

P1

13

P1

5

C16

1

2

HDR4

39

HDR4

38

HDR4

37

C24

1

2

P1

25

P1

23

P1

21

P2

9

P1

17

P1

1

HDR4

36

HDR4

35

HDR4

34

HDR4

33

HDR4

32

HDR4

31

HDR4

30

HDR4

27

HDR4

28

HDR4

29

HDR4

26

HDR4

25

HDR4

24

HDR4

23

HDR4

22

HDR4

21

HDR4

20

HDR4

19

HDR4

18

HDR4

17

HDR4

16

HDR4

15

HDR4

14

HDR4

13

HDR4

12

HDR4

11

HDR4

10

HDR4

9

HDR4

8

HDR4

7

HDR4

6

HDR4

5

HDR4

4

HDR4

1

HDR4

2

HDR4

3

HDR3

52

HDR3

51

HDR3

50

C14

1

2

HDR3

49

HDR3

48

HDR3

47

HDR3

46

HDR3

45

HDR3

44

C18

1

2

Good

Power

Enable

In

Out

Gnd

TPS77625PWP

VR2

6

7

5

13

14

16

3

SW2

1

23

4

C20

1

2

HDR3

43

HDR3

42

HDR3

41

HDR3

40

HDR3

39

HDR3

38

HDR3

37

HDR3

36

HDR3

35

HDR3

34

HDR3

33

HDR3

32

HDR3

31

HDR3

30

HDR3

27

HDR3

28

HDR3

29

HDR3

26

HDR3

25

HDR3

24

HDR3

23

HDR3

22

HDR3

21

HDR3

20

HDR3

19

HDR3

18

HDR3

17

HDR3

16

HDR3

15

HDR3

14

HDR3

13

HDR3

12

HDR3

11

HDR3

10

HDR3

9

HDR3

8

HDR3

7

HDR3

6

HDR3

5

HDR3

4

P1

26

HDR3

1

HDR3

2

HDR3

3

HDR2

52

HDR2

51

HDR2

50

HDR2

49

HDR2

48

P1

24

P1

22

P1

20

P1

18

P1

16

P1

14

P1

12

P1

7

P1

8

P1

6

P1

4

P1

19

P1

2

P1

11

HDR2

47

HDR2

46

C26

1

2

P2

3

P2

13

P2

5

P2

17

P2

1

P2

26

P2

24

P2

22

P2

20

HDR2

45

P2

18

P2

16

HDR2

44

HDR2

43

HDR2

42

P2

14

P2

12

P2

7

P2

8

P2

6

P2

4

HDR2

41

HDR2

40

HDR2

39

P2

19

HDR2

38

HDR2

37

HDR2

36

HDR2

35

HDR2

34

HDR2

33

P2

2

HDR2

32

HDR2

31

HDR2

30

HDR2

27

HDR2

28

HDR2

29

HDR2

26

HDR2

25

HDR2

24

HDR2

23

HDR2

22

HDR2

21

HDR2

20

HDR2

19

HDR2

18

HDR2

17

HDR2

16

HDR2

15

HDR2

14

HDR2

13

HDR2

12

HDR2

11

HDR2

10

HDR2

9

HDR2

8

HDR2

7

HDR2

6

HDR2

5

HDR2

4

HDR2

1

HDR2

2

HDR2

3

HDR1

52

HDR1

51

HDR1

50

HDR1

49

HDR1

48

HDR1

47

HDR1

46

HDR1

45

HDR1

44

HDR1

43

HDR1

42

HDR1

41

HDR1

40

HDR1

39

HDR1

38

HDR1

37

HDR1

36

HDR1

35

HDR1

34

HDR1

33

HDR1

32

HDR1

31

HDR1

30

HDR1

27

HDR1

28

HDR1

29

HDR1

26

HDR1

25

HDR1

24

HDR1

23

HDR1

22

HDR1

21

HDR1

20

HDR1

19

HDR1

18

HDR1

17

HDR1

16

HDR1

15

HDR1

14

HDR1

13

HDR1

12

HDR1

11

HDR1

10

HDR1

9

HDR1

8

HDR1

7

HDR1

6

HDR1

5

HDR1

4

HDR1

1

HDR1

2

HDR1

3

1.0K

R11

1

2

C1

1

2

C2

1

2

On

SW5

123

456

JP1612

JP1512

JP1412

JP1312

JP1212

3

2

1

DC

JP1112

JP1

2

1

3

DS9

1

2

330

R1

1

2

JP9 12

1.0K

R22

1

2

MMBT2222

Q1

3

2

1

2.0KR7

12

2.0K

R8

1

2

150

R10

1

2

+5v

+3.3v

+5v

RC

Q

CLR

74LV123A

U2

5

129

10

11

67

+3.3v

220KR9

12

18KR6

12

C32

12

C35

1

2

1000pF

C30

12

C29

1

2

JP1012

JP5

12

TP2

3

150

R19

1

2

DS1

1

2

DS2

1

2

DS3

1

2

DS4

1

2

DS5

1

2

DS6

1

2

DS7

1

2

DS8

1

2

150

R17

1

2

150

R18

1

2

150

R16

1

2

150

R15

1

2

150

R13

1

2

150

R14

1

2

150

R12

1

2

+3.3v

Ground

74LV123AU2

16

8

+3.3v

JP17

12

C31

1

2

JP8

12

JP6

12

JP7

12

RC

Q

CLR

74LV123A

U2

13

41

2

3

14 15

PB1

1

23

4

1.0K

R20

1

2

330

R26

12

DS10

1

2

C33

1

2

+3.3v

SW4

1

23

4

1.0K

R23

1

2

C4

1

2

C34

1

2

330

R24

12

SW3

1

23

4

SW1

1

23

4

330

R25

12

330

R28

12

330

R27

12

C37

1

2

GL-128

RCK

TRSTB

TDO

VPN

VPP

TMS

TDI

TCK

U1-94

U1-95

U1-92

U1-93

U1-90

U1-91

U1-87

U1-69

U1-63

U1-55

GND

GND GND GND GND GND GNDGNDGND

GNDGND

GND GND

GNDGND

GND

GND GND GND GND

GND

GNDGND GND GND

GND

GND GND GND

GND GND

GND

GND GND

GND

U1-96

U1-79

9V-IN

EXT-IN

AGND

AVDD

VDDP

+2.5V

+3.3V

10-6-02

APAxxx-2 Rev.1.0

Assy.#APAxxx-503 Rev.A

To FPGA Pin 96

To FPGA Pin 94

To FPGA Pin 92

To FPGA Pin 90

To FPGA Pin 87

VDD

VDPP

VDD (+2.5v)VDD

VDD

VDDP

IMPORTANT:

Equal +3.3v OR +2.5v

Install A Jumper At

JP1 To Select VDDP

VDDP

Ground

+2.5v

6-8VDC

To FPGA Pin 79

To FPGA Pin 69

To FPGA Pin 63

To FPGA Pin 55

To FPGA Pin 95

To FPGA Pin 93

To FPGA Pin 91

To FPGA Pin 128

220

Input To Pin 30

Press For Clock

1

Install Jumper To

Manual Clock Input

DC Supply

External

Connect To FPGA I/O

APAxxx-2.Sch

August 9, 2002

stalled at the factory

R5 and R6 are not in-

Note:

To U1 Pin 24 (Global

Input) and HDR1 Pin 24

GL

GND

AGND

GL

GND

GL

TRST

GND

AGND

GND

P1

P2

P1 P1

P2P2

HDR4

HDR3

HDR2

HDR1

Ana.+2.5v

Ana.Gnd

AGND

AVDD

AVDD(+2.5v)

TRSTB

RCK

TMS

TDO

TDI

TCK

VPN

VPP

No Connection

From

Programmer

TRSTB

RCK

TMS

TDO

TDI

TCK

Ground

VPN

VPP

PPECL2

NPECL2

AVDD

RCK

TDO

VPN

VPP

TMS

TDI

TCK

PPECL1

NPECL1

I/O

VDDP(2.5/3.3v)

VDD(+2.5v)

I/O

+2.5v

Demonstration Board

Northridge, CA 91326

Electronics

RASTUR

No Connection

From

Programmer

TRSTB

RCK

TMS

TDO

TDI

TCK

Ground

VPN

VPP

Schematic Diagram-

Drawing Number:

PWB Number:

R.A.Sturla

Drawn By:

Date:

OfSheet # Revised:

I

4

3

2

1

4

3

2

1

HGFEDCBA

11

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31

Figure B-2 shows a schematic of the ProASICPLUS Evaluation Board.

Figure B-2. ProASIC PLUS Evaluation Board

Figure B-3 shows a board schematic.

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Appendix B: Board Schematics

32

Figure B-3. Board Schematic

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33

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Appendix B: Board Schematics

34

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35

C

Product Support

Actel backs its products with various support services including Customer

Service, a Customer Technical Support Center, a web site, an FTP site,

electronic mail, and worldwide sales offices. This appendix contains

information about contacting Actel and using these support services.

Actel U.S. Toll-Free Line

Use the Actel toll-free line to contact Actel for sales information, technical

support, requests for literature, Customer Service, investor information, and

using the Action Facts service.

The Actel toll-free line is (888) 99-ACTEL.

Customer Service

Contact Customer Service for non-technical product support, such as product

pricing, product upgrades, update information, order status, and authorization.

From Northeast and North Central U.S.A., call (408) 522-4480

From Southeast and Southwest U.S.A., call (408) 522-4480

From South Central U.S.A., call (408) 522-4434

From Northwest U.S.A., call (408) 522-4434

From Canada, call (408) 522-4480

From Europe, call (408) 522-4252 or +44 (0) 1276 401500

From Japan, call (408) 522-4743

From the rest of the world, call (408) 522-4743

Fax, from anywhere in the world (408) 522-8044

Actel Customer Technical Support Center

Actel staffs its Customer Technical Support Center with highly skilled

engineers who can help answer your hardware, software, and design questions.

The Customer Technical Support Center spends a great deal of time creating

application notes and answers to FAQs. So, before you contact us, please visit

our online resources. It is very likely we have already answered your questions.

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Appendix C: Product Support

36

Guru Automated Technical Support

Guru is a web-based automated technical support system accessible through the

Actel home page (http://www.actel.com/guru/). Guru provides answers to

technical questions about Actel products. Many answers include diagrams,

illustrations, and links to other resources on the Actel web site.

Website

Actel has a World Wide Web home page where you can browse a variety of

technical and non-technical information. The URL is http://www.actel.com.

Contacting the Customer Technical Support Center

Highly skilled engineers staff the Technical Support Center from 7:00 A.M. to

6:00 P.M., Pacific Time, Monday through Friday. Several ways of contacting the

Center follow:

Electronic Mail You can communicate your technical questions to our e-mail address and

receive answers back by e-mail, fax, or phone. Also, if you have design

problems, you can e-mail your design files to receive assistance. We constantly

monitor the e-mail account throughout the day. When sending your request to

us, please be sure to include your full name, company name, and your contact

information for efficient processing of your request.

The technical support e-mail address is tech@actel.com.

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Contacting the Customer Technical Support Center

37

Telephone Our Technical Support Center answers all calls. The center retrieves

information, such as your name, company name, phone number and your

question, and then issues a case number. The Center then forwards the

information to a queue where the first available application engineer receives

the data and returns your call. The phone hours are from 7:00 A.M. to 6:00 P.M.,

Pacific Time, Monday through Friday. The Technical Support numbers are:

(408) 522-4460

(800) 262-1060

Customers needing assistance outside the US time zones can either contact

technical support via email (tech@actel.com) or contact a local sales office.

Please see our list of Worldwide Sales Offices.

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Appendix C: Product Support

38

Worldwide Sales Offices

Headquarters

Actel Corporation

955 East Arques Avenue

Sunnyvale, California 94086

Toll Free: 888.99.ACTEL

Tel: 408.739.1010

Fax: 408.739.1540

US Sales

Offices

California

Bay Area

Tel: 408.328.2200

Fax: 408.328.2358

Irvine

Tel: 949.727.0470

Fax: 949.727.0476

Newbury Park

Tel: 805.375.5769

Fax: 805.375.5749

Colorado

Tel: 303.420.4335

Fax: 303.420.4336

Florida

Tel: 407.977.6846

Fax: 407.977.6847

Georgia

Tel: 770.277.4980

Fax: 770.277.5896

Illinois

Tel: 847.259.1501

Fax: 847.259.1575

Massachusetts

Tel: 978.244.3800

Fax: 978.244.3820

Minnesota

Tel: 651.917.9116

Fax: 651.917.9114

New Jersey

Tel: 609.517.0304

North Carolina

Tel: 919.654.4529

Fax: 919.674.0055

Pennsylvania

Tel: 215.830.1458

Fax: 215.706.0680

Texas

Tel: 972.235.8944

Fax: 972.235.9659

International Sales

Offices

Canada

235 Stafford Rd. West, Suite

106

Nepean, Ontario K2H9C1,

Canada

Tel: 613.726.7575

Fax: 613.726.8666

France

361 Avenue General de Gaulle

92147 Clamart Cedex

Tel: +33 (0)1.40.83.11.00

Fax: +33 (0)1.40.94.11.04

Germany

Lohweg 27,

D-85375 Neufahrn

Germany

Tel: +49.(0)81.659.584.0

Fax: +49.(0)81.659.584.10

Italy

Via dei Garibaldini 5

20019 Settimo Milanese

Milano, Italy

Tel: +39 (0)2.3809.3259

Fax: +39 (0)2.3809.3260

Japan

EXOS Ebisu Building 4F

1-24-14 Ebisu Shibuya-ku

Tokyo 150

Tel: +81 (0)3.3445.7671

Fax: +81 (0)3.3445.7668

Korea

30th floor, ASEM Tower,

159-1 Samsung-dong,

Kangnam-ku, Seoul, Korea

Tel: +82 (0)2.6001.3382

Fax: +82 (0)2.6001.3030

United Kingdom

Maxfli Court

Riverside Way

Camberley, Surrey

GU15 3YL

United Kingdom

Tel: +44 (0)1276.401450

Fax: +44 (0)1276.401490

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