AM3517, AM3505
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
AM3517/05 Sitara™ ARM Microprocessors
Check for Samples: AM3517,AM3505
1 Device Summary
1.1 Features
123456 – SIDETONE Core Support (McBSP2 and
• AM3517/05 Sitara™ ARM Microprocessor: 3 Only) For Filter, Gain, and Mix
– MPU Subsystem Operations
• 600-MHz Sitara™ ARM®Cortex™-A8 Core – 128-Channel Transmit/Receive Mode
• NEONTM SIMD Coprocessor and Vector – Direct Interface to I2S and PCM Device
floating point (FP) co-processor and TDM Buses
– Memory Interfaces: • HDQ/1-Wire Interface
• 166 MHz 16/32- bit mDDR/DDR2 Interface • 4 UARTs (One with Infrared Data
with 1 GByte total addressable space Association [IrDA] and Consumer Infrared
• Up to 83 MHz General Purpose Memory [CIR] Modes)
Interface supporting 16-bit Wide • 3 Master/Slave High-Speed Inter-
Multiplexed Address/Data bus Integrated Circuit (I2C) Controllers
• 64 K-Byte SRAM • 12 32-bit General Purpose Timers
• 3 Removable Media Interfaces • 1 32-bit Watchdog Timer
[MMC/SD/SDIO] • 1 32-bit 32-kHz Sync Timer
– IO Voltage: • Up to 186 General-Purpose I/O (GPIO)
• mDDR/DDR2 IOs: 1.8V Pins
• Other IOs: 1.8V and 3.3V • Display subsystem
– Core Voltage: 1.2V – Parallel Digital Output
– Commercial and Extended Temperature – Up to 24-Bit RGB
Grade – Supports Up to 2 LCD Panels
(operating restrictions apply) – Support for Remote Frame Buffer Interface
– 16-bit Video Input Port capable of capturing (RFBI) LCD Panels
HD video – Two 10-bit Digital-to-Analog Converters
– HD resolution Display Subsystem (DACs) Supporting
– Serial Communication • Composite NTSC/PAL Video
• High-End CAN Controller • Luma/Chroma Separate Video (S-Video)
• 10/100 Mbit Ethernet MAC – Rotation 90, 180, and 270 degrees
• USB OTG subsystem with standard – Resize Images From 1/4x to 8x
DP/DM interface [HS/FS/LS] – Color Space Converter
• Multiport USB Host Subsystem
[HS/FS/LS] – 8-bit Alpha Blending
– 12-pin ULPI or 6/4/3-pin Serial • Video Processing Front End (VPFE) 16-bit
Interface Video Input Port
• Four Master/Slave Multichannel Serial – RAW Data Interface
Port Interface (McSPI) Ports – 75-MHz Maximum Pixel Clock
• Five Multichannel Buffered Serial Ports – Supports REC656/CCIR656 Standard
– 512-Byte Transmit/Receive Buffer – Supports YCbCr422 Format (8-bit or 16-bit
(McBSP1/3/4/5) With Discrete Horizontal and Vertical Sync
– 5K-Byte Transmit/Receive Buffer Signals)
(McBSP2) – Generates Optical Black Clamping Signals
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerVR SGX is a trademark of Imagination Technologies Ltd.
3Sitara is a trademark of Texas Instruments.
4Cortex, NEON are trademarks of ARM Ltd or its subsidiaries.
5ARM, Jazelle are registered trademarks of ARM Ltd or its subsidiaries.
6All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to Copyright © 2009–2012, Texas Instruments Incorporated
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
AM3517, AM3505
SPRS550D –OCTOBER 2009–REVISED MARCH 2012
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– Built-in Digital Clamping and Black Level 1.1 and 2.0, OpenVG1.0
Compensation – Fine Grained Task Switching, Load
– 10-bit to 8-bit A-law Compression Hardware Balancing, and Power Management
– Supports up to 16K Pixels (Image Size) in – Programmable, High-Quality Image Anti-
Horizontal and Vertical Directions Aliasing
• System Direct Memory Access (sDMA) • Endianess
Controller (32 Logical Channels With – ARM Instructions - Little Endian
Configurable Priority) – ARM Data – Configurable
• Comprehensive Power, Reset and Clock • SDRC Memory Controller
Management – 16/32-bit Memory Controller With 1G-Byte
• ARM Cortex™-A8 Memory Architecture Total Address Space
– ARMv7 Architecture – Double Data Rate (DDR2) SDRAM, mobile
– In-Order, Dual-Issue, Superscalar Double Data Rate (mDDR)SDRAM
Microprocessor Core – SDRAM Memory Scheduler (SMS) and
– ARM NEON™ Multimedia Architecture Rotation Engine
– Over 2x Performance of ARMv6 SIMD • General Purpose Memory Controller (GPMC)
– Supports Both Integer and Floating Point – 16-bit Wide Multiplexed Address/Data Bus
SIMD – Up to 8 Chip Select Pins With 128M-Byte
– Jazelle®RCT Execution Environment Address Space per Chip Select Pin
Architecture – Glueless Interface to NOR Flash, NAND
– Dynamic Branch Prediction with Branch Flash (With ECC Hamming Code
Target Address Cache, Global history buffer Calculation), SRAM and Pseudo-SRAM
and 8 entry return stack – Flexible Asynchronous Protocol Control for
– Embedded Trace Macrocell [ETM] support Interface to Custom Logic (FPGA, CPLD,
for Non_invasive Debug ASICs, etc.)
– 16K-Byte instruction Cache (4-Way set- – Nonmultiplexed Address/Data Mode (Limited
associative) 2K-Byte Address Space)
– 16K-Byte Data Cache (4-Way Set- • Test Interfaces
Associative) – IEEE-1149.1 (JTAG) Boundary-Scan
– 256K-Byte L2 Cache Compatible
• PowerVR SGX™ Graphics Accelerator (AM3517 – Embedded Trace Macro Interface (ETM)
only) • 65-nm CMOS technology
– Tile Based Architecture Delivering up to 10 • Packages:
MPoly/sec – 491-pin BGA (17x17, 0.65mm pitch)
– Universal Scalable Shader Engine: Multi- [ZCN suffix]
threaded Engine Incorporating Pixel and with via channel array technology
Vertex Shader Functionality – 484-pin PBGA (23x23, 1-mm pitch)
– Industry Standard API Support: OpenGLES [ZER suffix]
1.2 Applications
• Single Board Computers • Transportation
• Industrial and Home Automation • Navigation
• Digital Signage • Smart White Goods
• Point of Service • Digital TV
• Portable Media Player • Digital Video Camera
• Portable Industrial • Gaming
2Device Summary Copyright © 2009–2012, Texas Instruments Incorporated
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1.3 Description
AM3517/05 is a high-performance ARM Cortex-A8 microprocessor with speeds up to 600 MHz. The
device offers 3D graphics acceleration while also supporting numerous peripherals, including DDR2, CAN,
EMAC, and USB OTG PHY that are well suited for industrial apllications.
The processor can support other applications, including:
• Single Board Computers
• Home and Industrial automation
• Human Machine Interface
The device supports high-level operating systems (OSs), such as:
• Linux®
• Windows®CE
• Android™
The following subsystems are part of the device:
• Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8 microprocessor.
• PowerVR SGX™ Graphics Accelerator (AM3517 device only) Subsystem for 3D graphics acceleration
to support display and gaming effects.
• Display subsystem with several features for multiple concurrent image manipulation, and a
programmable interface supporting a wide variety of displays. The display subsystem also supports
NTSC/PAL video out.
• High performance interconnects provide high-bandwidth data transfers for multiple initiators to the
internal and external memory controllers and to on-chip peripherals. The device also offers a
comprehensive clock-management scheme.
AM3517/05 devices are available in a 491-pin BGA package and a 484-pin PBGA package.
This AM3517/05 data manual presents the electrical and mechanical specifications for the AM3517/05
Sitara ARM Microprocessor.
Copyright © 2009–2012, Texas Instruments Incorporated Device Summary 3
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64 64
Async
64 64
L2$
256K
MPU
Subsystem
ARM Cortex-
A8TM Core
16K/16K L1$
POWERVR
SGX
Graphics
Accelerator
( only)
TM
AM3517
32
32
32
Channel
System
DMA
3232
Analog
DAC
LCD Panel
CVBS
or
S-Video
Dual Output 3-Layer
Display Processor
(1xGraphics, 2xVideo)
Temporal Dithering
SDTV → QCIF Support
32
HS/FS/
LS
USB
Host
32
L3 Interconnect Network-Hierarchial, Performance, and Power Driven
64K
On-Chip
RAM
32
132K
On-Chip
BOOT
ROM
SMS:
SDRAM
Memory
Scheduler/
Rotation
64
EMIF
Controller
L4 Interconnect
32
System
Controls
PRCM
External
Peripherals
Interfaces
Peripherals:
4xUART, 3xHigh-Speed I2C,
5xMcBSP
(2x with Sidetone/Audio Buffer)
4xMcSPI, 186xGPIO,
3xHigh-Speed MMC/SDIO,
HDQ/1 Wire,
12xGPTimers, 1xWDT,
32K Sync Timer
GPMC:
General
Purpose
Memory
Controller
32
Emulation
Debug: ETM, JTAG
External
DDR2/
mDDR
32
SPRS550-006
Parallel
HECC EMAC VPFE
USB PHY
USB OTG
Controller
DDR PHY
NAND/NOR/
FLASH,
SRAM
USB transceivers /
device ports [3]
AM3517, AM3505
SPRS550D –OCTOBER 2009–REVISED MARCH 2012
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1.4 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the AM3517/05 Sitara ARM Microprocessor.
Figure 1-1. AM3517/05 Functional Block Diagram
4Device Summary Copyright © 2009–2012, Texas Instruments Incorporated
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
1.5 ZCN and ZER Package Differences
Table 1-1 shows the ZER and ZCN package differences on the device.
Table 1-1. ZCN and ZER Package Differences
FEATURE ZCN PACKAGE ZER PACKAGE
Pin Assignments For ZCN package pin assignments, see For ZER package pin assignments, see
Section 2,Terminal Description Section 2,Terminal Description
Video Interfaces TV Out available TV Out not available
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1 Device Summary ........................................ 14.3 Output Clock Specifications ........................ 95
1.1 Features ............................................. 14.4 DPLL Specifications ................................ 97
1.2 Applications .......................................... 25 Video DAC Specifications .......................... 100
1.3 Description ........................................... 35.1 Interface Description .............................. 101
5.2 Electrical Specifications Over Recommended
1.4 Functional Block Diagram ........................... 4Operating Conditions .............................. 102
1.5 ZCN and ZER Package Differences ................. 55.3 Analog Supply (vdda_dac) Noise Requirements .104
Revision History .............................................. 75.4 External Component Value Choice ............... 105
2 Terminal Description ................................... 86 Timing Requirements and Switching
2.1 Pin Assignments ..................................... 8Characteristics ....................................... 106
2.2 Ball Characteristics ................................. 17 6.1 Timing Test Conditions ........................... 106
2.3 Multiplexing Characteristics ........................ 51 6.2 Interface Clock Specifications ..................... 106
2.4 Signal Description .................................. 57 6.3 Timing Parameters ................................ 107
3 Electrical Characteristics ............................ 80 6.4 External Memory Interfaces ....................... 108
3.1 Absolute Maximum Ratings ........................ 80 6.5 Video Interfaces ................................... 150
3.2 Recommended Operating Conditions .............. 82 6.6 Serial Communications Interfaces ................ 155
3.3 DC Electrical Characteristics ....................... 84 6.7 Removable Media Interfaces ...................... 197
3.4 Core Voltage Decoupling ........................... 86 6.8 Test Interfaces .................................... 211
3.5 Power-up and Power-down ......................... 88 7 Package Characteristics ............................ 215
4 Clock Specifications .................................. 91 7.1 Package Thermal Resistance ..................... 215
4.1 Oscillator ........................................... 92 7.2 Device Support .................................... 215
4.2 Input Clock Specifications .......................... 93 7.3 Mechanical Data .................................. 217
6Contents Copyright © 2009–2012, Texas Instruments Incorporated
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data manual revision history table highlights the technical changes made from the previous to the
current revision.
SEE ADDITIONS/MODIFICATIONS/DELETIONS
Section 2.2 Ball Characteristics:
Corrected USB0_VBUS signal voltage to 3.3V in Table 2-1, Ball Characteristics (ZCN Pkg.)
Section 2.4.7 General-Purpose IOs:
Corrected ZCN/ZER ball numbers for GPIO_125, GPIO_126, GPIO_130, GPIO_131 signals in Table 2-25,
General-Purpose IOs Signals Description
Section 4.1 Oscillator:
Deleted paragraph and added notes to Figure 4-3, AM3517/05 Oscillator Connections
Section 6.6.8.1 Management Data Input/Output (MDIO) Electrical Data/Timing:
Modified Parameter 5 MIN value in Table 6-115, Timing Requirements for MDIO Input
Copyright © 2009–2012, Texas Instruments Incorporated Contents 7
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2 Terminal Description
2.1 Pin Assignments
2.1.1 Pin Map (Top View)
The following illustrations show the top views of the 484-pin [ZER] and 491-pin [ZCN] package pin
assignments in four quadrants (A, B, C, and D).
Note: A pin with an "NC" designator indicates No Connection. For proper device operation, these pins
must be left unconnected.
8Terminal Description Copyright © 2009–2012, Texas Instruments Incorporated
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N
P
R
T
U
V
1415162223
N
P
W
Y
2425
AA
AB
T
U
R
21 17181920
NC
VDDS
VSS
VSS
NC
SYS_
CLKOUT1
VDDS_
DPLL_MPU
_USBHOST
VDDSHV
1516
17
181920
2122
23
AC
24
25
AD
AE VSS
V
W
Y
AA
AB
VSS
14
AC
AD
AE
VDDSHV
VDDSHV VDDSHV
VSS VSSVSS VDDS_DPLL_
PER_CORE VDDSHV VSS
VDDSHV VDDSHV VSSVSS VSSVSS VSS
VDD_CORE VDD_CORE VSSVSS VSS
VDD_CORE
VSS
VDD_COREVDD_CORE
VSS
VDD_CORE
VSSVSS
VDD_COREVDD_CORE
VDDSHV
VDDSHVVDDSHV
VDDS
DSS_ACBIAS DSS_PCLK ETK_D15 ETK_D12 ETK_D8 ETK_D5 ETK_CTL MCSPI2_
CS1
MCSPI1_
CS3
MCSPI1_
CS2
MCSPI1_
CLK
DSS_DATA1 DSS_DATA0 DSS_VSYNC DSS_HSYNC ETK_D13 ETK_D9 ETK_D6 ETK_D0 ETK_CLK MCSPI2_
CLK
MCSPI1_
SIMO
MCSPI1_
CS1
DSS_DATA4 DSS_DATA3 DSS_DATA2 ETK_D14 ETK_D10 ETK_D1 MCSPI2_
SIMO
MCSPI1_
SOMI
DSS_DATA6 DSS_DATA5 ETK_D11 ETK_D7 ETK_D2 MCSPI2_
SOMI
MCSPI1_CS0
DSS_DATA9 DSS_DATA8 DSS_DATA7 UART1_TX ETK_D3 MCSPI2_
CS0
DSS_DATA13 DSS_DATA12 DSS_DATA11 DSS_DATA10 UART1_CTS UART1_RTS ETK_D4
DSS_DATA18 DSS_DATA17 DSS_DATA16 DSS_DATA15 DSS_DATA14 UART1_RX
DSS_DATA20 DSS_DATA19
JTAG_TCK JTAG_NTRST DSS_
DATA23
DSS_
DATA22
DSS_
DATA21
JTAG_EMU0 JTAG_TDO JTAG_TDI JTAG_TMS
_TMSC
JTAG_RTCK
MCBSP1_
CLKR
JTAG_
EMU1
MCBSP_
CLKS
MCBSP1_
FSX
MCBSP1_
DR
MCBSP1_
DX
MCBSP1_
FSR
MCBSP1_
CLKX
MM
SYS_
CLKOUT2
VSS VSSVDD_CORE
SYS_
CLKREQ
VSS VSS
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
Figure 2-1. ZCN Pin Map [Quadrant A]
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P
R
Y
AA
AB
AC
AD
U
V
W
T
10 9 8
P
R
T
U
V
W
Y
AA
AB
AC
AD
CCDC_
PCLK
13 12 11 6 5
M
N
43
7
M
N
2 1
CCDC_
FIELD
CCDC_
VD
CCDC_
DATA0
CCDC_
DATA3
RMII_MDIO
_CLK
RMII_TXD0
RMII_TXEN
MMC1_
DAT1
MMC1_
DAT6
MMC2_CLK
MMC2_
DAT2
MMC2_
DAT6
VSS
VSS VSS
VSS
VSS
VSS
VSS
VSS
VDDSHV
VSS
VSS
VSS
VSS
VSS
VSS VSS VSS VSS VSS VDDSHV
VDDSHV
VDDSHV
VDDSHV
VDDSHV GPMC_
NCS5
GPMC_
NCS4
GPMC_
NCS3
GPMC_
NCS2
GPMC_
NCS7
GPMC_
NCS6 GPMC_CLK
UART3_CTS
_RCTX
UART3_RTS
_SD
UART3_RX
_IRRX
UART3_TX
_IRTX
GPMC_NADV
_ALE
GPMC_
NBE1
GPMC_
WAIT3
I2C2_SCL
SYS_NIRQ
SYS_
BOOT1
SYS_
BOOT4
SYS_
BOOT6
SYS_
BOOT7
SYS_
BOOT5
SYS_
BOOT2
SYS
_NRES
PWRON
SYS_
BOOT8
13 12 11 10 9 8 76 5 43
AE
2 1
AE
CCDC_
HD VSS
CCDC_
WEN
CCDC_
DATA1
CCDC_
DATA4
RMII_MDIO
_DATA
RMII_TXD1
RMII_50MHZ
_CLK
MMC1_
DAT2
MMC1_
DAT7
MMC2_
CMD
MMC2_
DAT3
MMC2_
DAT7
MMC2_
DAT1
MMC2_
DAT5
MMC2_
DAT0
MMC2_
DAT4
VDDS_SRAM
_MPU
CAP_VDD_
SRAM_MPU
VDDSHV VDDSHV
VDDSHV
MMC1_
DAT0
MMC1_
DAT5
MMC1_
CMD
MMC1_
DAT4
MMC1_CLK
MMC1_
DAT3
VDDSHV
VDDSHV VDDSHV
VDDS
VDD_CORE VDD_CORE
VDD_CORE VDD_CORE VSS
VSS
VSS
VSS
VDD_CORE VDD_CORE
VDD_CORE VDD_CORE
VSS VSS
VSS VSSVSS VSS
VSS VSS
CCDC_
DATA2
CCDC_
DATA7
CCDC_
DATA6
CCDC_
DATA5
VDDSHV
VDDSHV
VDDSHV
VDDSHV
RMII_RXER
RMII_CRS_
DV
RMII_RXD1
RMII_RXD0
VDDSHV
VDDSHV
VDDSHV
I2C3_SDA
I2C1_SDA
I2C3_SCL
I2C1_SCL
SYS_
BOOT3
SYS
_NRES
WARM
SYS_
BOOT0
I2C2_SDA
HECC1_
TXD
HECC1_
RXD
GPMC_
NWP
GPMC_
WAIT0
GPMC_
WAIT1
GPMC_
WAIT2
VDDS GPMC_NBE0
_CLE GPMC_
NWE
GPMC_
NOE
RESERVED
RESERVED
AM3517, AM3505
SPRS550D –OCTOBER 2009–REVISED MARCH 2012
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Figure 2-2. ZCN Pin Map [Quadrant B]
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L
K
J
H
G
F
E
22
23
15
16
1718
19
2021
22
23
E
DD
CC
24
25
2425
B B
AA
15
16
17
181920
L
K
J
H
G
F
21
14
14
VSS
HDQ_
SIO NC NC
NC
VDDSHV VDD_CORE VSS VSS VSS
NC NC TV_
OUT1
VSS
VSS
VSS
VDD_CORE
VDD_CORE
VDD_CORE
VDD_COREVDD_CORE
VDDSHV
VSS VSS
VDDSHV VDDS
VDDS
VDDS
VDDS VDDS
NC
UART2_RTS
SYS_
XTALIN
SYS_32K
VSSOSC
SYS_
XTALOUT
TV_
OUT2 TV_VFB2 VSSA_DAC VDDA_DAC
TV_VFB1
VSS
VSS
USB0_ID
USB0_DP
USB0_
DRVVBUS
MCBSP2_
FSX
MCBSP2_
CLKX
MCBSP2_DR
VSS MCBSP3_
CLKX
MCBSP3_DX
MCBSP3_
DR
MCBSP2_
DX
UART2
_TX
MCBSP4_
DR
MCBSP4_
CLKX
MCBSP3_
FSX
UART2_RX
VDDA3P3V
_USBPHY
VDDA1P8V
_USBPHY
CAP_
VDDA1P2LDO
_USBPHY
MCBSP4_
FSX
SDRC_
D1
SDRC_
DQS0N
SDRC_
STRBEN0
SDRC_
STRBEN
_DLY0
SDRC_
DQS1N SDRC_
D14
SDRC_
D15
SDRC_
NCS1
SDRC_
NWE
SDRC_
DM1
SDRC_
D13
SDRC_
DQS1P
SDRC_
D8
SDRC_
D7
SDRC_
DQS0P
SDRC_
D0
MCBSP4_
DX
SDRC_DM0 SDRC_D3 SDRC_D6 SDRC_D10 SDRC_D12 SDRC_NRAS
SDRC_CKE0
SDRC_NCAS
VREFSSTL
SDRC_D2 SDRC_D5 SDRC_D9 SDRC_D11
SDRC_D4 VDDS_SRAM
_CORE_BG
CAP_VDD_
SRAM_CORE
USB0_DM UART2_CTS
USB0_
VBUS
VDDSHV
VDDSOSC
NC
NC
TV_VREF
AM3517, AM3505
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Figure 2-3. ZCN Pin Map [Quadrant C]
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L
K
J
H
G
F
E
13 12 11 6 5
13 12 11 10 9 8 76 5
L
K
E
D
D
CC
43
43
BB
10 9 8
H
G
F
J
72 1
2 1
VSS
VSS
VSS
AA VSS
VSS
VSS VSS VDD_CORE VDD_CORE
VDD_CORE
VDD_CORE VDDSHV VDDSHV VDDSHV
VDDSHVVSSVSS
VDDSVSS
VDDS
VDDS
GPMC_
NCS0
GPMC_
NCS1
GPMC_D12 GPMC_D13 GPMC_D14 GPMC_D15
GPMC_D11GPMC_D10
GPMC_D8 GPMC_D9
GPMC_D7
GPMC_D6
GPMC_D5
GPMC_D4
GPMC_D3GPMC_D1 GPMC_D2GPMC_D0
GPMC_A9GPMC_A8
GPMC_A7
GPMC_A6
GPMC_A5
GPMC_A4
GPMC_A3GPMC_A2
GPMC_A1
SDRC_DM3
VSS
VSS
VDD_CORE VDD_CORE
VSS
VSS VDD_CORE VDD_CORE
VDDSVDDS
VDDS VDDS
VDDS
VDDS
SDRC_BA0
SDRC_CLK
SDRC_
NCLK
SDRC_BA1
SDRC_BA2
SDRC_
NCS0
DDR_
PADREF
SDRC_A0
SDRC_A1
SDRC_A2
SDRC_A3
SDRC_
A4
SDRC_
A9
SDRC_A8
SDRC_A7
SDRC_A6
SDRC_A5
SDRC_A11
SDRC_
A10
SDRC_
A12
SDRC_
A13
SDRC_
ODT
SDRC_A14
SDRC_DM2 SDRC_D19
SDRC_D18
SDRC_
D17
SDRC_
D16
GPMC_A10
SDRC_D21
SDRC_D20
SDRC_
DQS2N
SDRC_
DQS2P
SDRC_
STRBEN1
SDRC_D22
SDRC_D23
SDRC_24
SDRC_
STRBEN
_DLY1
SDRC_D25
SDRC_D26
SDRC_D27
SCRC_D29
SDRC_D28
SDRC_
DQS3N
SDRC_
DQS3P
SDRC_D30
SDRC_D31
AM3517, AM3505
SPRS550D –OCTOBER 2009–REVISED MARCH 2012
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Figure 2-4. ZCN Pin Map [Quadrant D]
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12
13
14
15
16
17
18
19
VSS
VSS
MMC2_DAT4
VDDS_DPLL_
MPU_
USBHOST
LK
J
HGF
ED
C
20
B
A
21
22 VSS
VDDS_
SRAM_MPU
VSS VDDS
VSS VDD_CORE VSS VDD_CORE
VSS
VSS
VDD_CORE
VSS
VDD_COREVDD_CORE
VSS
VSSVSS
VSS
VDDSHVVSS
VDDSHV
DSS_PCLK UART1_TX ETK_D8 ETK_D10 ETK_D1 ETK_CLK MCSPI2_
SOMI MCSPI2_CLK MCSPI1_CLK VDDSHV
VDDSHV DSS_HSYNC UART1_RTS ETK_D9 ETK_D7 ETK_D5 ETK_CTL MCSPI2_CS0 MCSPI1_CS3 MMC2_DAT3 MMC2_DAT6
DSS_DATA0 DSS_VSYNC UART1_RX ETK_D11 ETK_D2 MCSPI2_
SIMO MMC2_DAT0 MMC2_DAT5
DSS_DATA1 DSS_ACBIAS ETK_D6 ETK_D3 MCSPI2_CS1 MCSPI1_SIMO MMC2_DAT1
DSS_DATA2 DSS_DATA3 DSS_DATA5 VSS VDDSHV MCSPI1_CS0
DSS_DATA4 DSS_DATA8 DSS_DATA9 DSS_DATA6 VSS VDDSHV VSS
DSS_DATA13 DSS_DATA7 DSS_DATA10 DSS_DATA11 VSS VDDS
DSS_DATA16 DSS_DATA15
DSS_DATA17 DSS_DATA23 DSS_DATA22 DSS_DATA12 JTAG_TCK
DSS_DATA20 DSS_DATA21 DSS_DATA18 JTAG_NTRST JTAG_EMU0
JTAG_TMS_
TMSC JTAG_TDI
LK
J
HGF
ED
C
B
A
12
13
14
15
16
17
18
19
20
21
22
ETK_D13 ETK_D0 MCSPI1_CS1
UART1_CTS ETK_D14 ETK_D4 MCSPI1_CS2
ETK_D15 ETK_D12 VDDSHV MCSPI1_
SOMI
VDDSHV VDDSHV
VSS VDD_CORE
DSS_DATA19 DSS_DATA14 VDDSHV VSS VDDS
VDD_CORE VSS
JTAG_RTCK JTAG_TDO JTAG_EMU1 VDDSHV VDDSHV
AM3517, AM3505
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
Figure 2-5. ZER Pin Map [Quadrant A]
Copyright © 2009–2012, Texas Instruments Incorporated Terminal Description 13
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12
17
18
19
20
21
14
15
16
13
CCDC_FIELD CCDC_
PCLK
CCDC_HDCCDC_WEN
CCDC_
DATA2
RMII_
MDIO_DATA
RMII_
CRS_DV
RMII_
50MHZ_CLK
MMC1_DAT0MMC1_CMDMMC2_CLK
VSS
GPMC_CLK
GPMC_NOE
HECC1_TXD
HECC1_RXD
I2C1_SDA
SYS_NIRQ
SYS_BOOT0
SYS_BOOT1SYS_BOOT7
SYS_BOOT3
SYS_NRES
PWRON
I2C1_SCL
SYS_BOOT8
MN P R TU V WY
22
AA AB
VDDSHV VSS
CCDC_VD
CCDC_
DATA0
CCDC_
DATA4
RMII_
MDIO_CLK
RMII_TXD0
RMII_RXER
MMC1_CLKMMC1_DAT4
VSS
MMC1_DAT3MMC1_DAT1
MMC1_DAT2MMC1_DAT5
MMC1_DAT7
MMC1_DAT6
VSS
VDDSHV VSS
VDDSHV
VDD_CORE VDD_CORE
VSS VDD_CORE VSS
VSS
VDD_CORE
VSS
VDD_CORE VSS
VDD_CORE VDD_CORE
VSS VSS
CCDC_
DATA6
CCDC_
DATA5
CCDC_
DATA7
VSS
VDDSHV
VSS
VSS
VDDSHV
RMII_RXD1
RMII_RXD0
VSS
VDDSHV
VDDS
VDDSHV
VSS
RESERVED
RESERVED
I2C3_SCL
UART3_CTS
_RCTX
SYS_NRE
SWARM
I2C2_SCLI2C3_SDA
GPMC_
WAIT1
GPMC_NWEGPMC_NBE1
GPMC_
NADV_ALE
UART3_RX
_IRRX
UART3_TX
_IRTX
UART3_RTS
_SD
GPMC_
WAIT0
GPMC_NCS3 GPMC_NCS5 GPMC_NCS2 GPMC_NCS6
MN P R TU V WYAA AB
12
17
18
19
20
21
14
15
16
13
22
MMC2_CMD RMII_TXD1 CCDC_
DATA1
MMC2_DAT7 RMII_TXEN CCDC_
DATA3 SYS_BOOT6 SYS_BOOT5
MMC2_DAT2 VDDSHV VDDSHV SYS_BOOT4 SYS_BOOT2
CAP_VDD
_SRAM_MPU VSS VDDSHV
VSS VDDSHV VSS I2C2_SDA
VSS VDDSHV GPMC_
WAIT3 GPMC_NWP GPMC_
WAIT2
VDD_CORE VSS
AM3517, AM3505
SPRS550D –OCTOBER 2009–REVISED MARCH 2012
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Figure 2-6. ZER Pin Map [Quadrant B]
14 Terminal Description Copyright © 2009–2012, Texas Instruments Incorporated
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D
C
5
4
3
B
A
2
1
L
K
J
HGF
11
10
9
8
7
6
E
VSS MCBSP1
_CLKR MCBSP1_FSX MCBSP1_FSR MCBSP_CLKS VSS VSS VSS VDD_CORE VSS
MCBSP1_DX NC SYS_
CLKOUT2
VSS
VDD_CORE
VDD_CORE
VDD_CORE
VSSVDDSHV
VSS VSS
VDD_CORE VSS
VDDS
VDDS
NC
VDDS_SRAM
_CORE_BG
NC
SYS_XTALIN VSSOSC
SYS_
XTALOUT
SYS_32K SYS_CLKREQ MCBSP1
_CLKX NC NC NC
NC
VDDA3P3V
_USBPHY
CAP_VDDA1
P2LDO_
USBPHY
USB0_
DRVVBUS
USB0_DP
UART2_CTS
MCBSP3_FSX
MCBSP4
_CLKX
MCBSP4_DX
VSS VDDSHV
MCBSP4_FSX
MCBSP4_DR
MCBSP3_DR
UART2_RTS
SDRC_D6
SDRC_D3
SDRC_D2
MCBSP2_DR
UART2_RX
VDDA1P8V
_USBPHY
UART2_TX
SDRC_D7 SDRC_DQS0N
SDRC_
STRBEN
_DLY0
SDRC_D13 SDRC_DQS1N SDRC_D15 SDRC_NRAS SDRC_CLK
SDRC_NCLK
SDRC_NWE
SDRC_DM1
SDRC_DQS1P
SDRC_D8
SDRC_
STRBEN0
SDRC_DQS0P
SDRC_D5
SDRC_D0 SDRC_D4 SDRC_D9 SDRC_D14 SDRC_CKE0
SDRC_DM0 SDRC_D11 SDRC_NCS0 SDRC_NCS1
VSS SDRC_BA2 SDRC_BA1
USB0_DM VSS
USB0_ID
VSS
D
C
B
AL
K
J
HGF
E
5
4
3
2
1
11
10
9
8
7
6
VDDS_
DPLL_PER
_CORE
VSS VDD_CORE
HDQ_SIO MCBSP1_DR NC SYS_
CLKOUT1 NC VDDSOSC
VSS
VDDSHV
USB0_VBUS VSS VSS
VSS VSS CAP_VDD_
SRAM_CORE
MCBSP2
_CLKX MCBSP2_FSX VDDS VDDS VREFSSTL
MCBSP3_DX MCBSP3
_CLKX MCBSP2_DX SDRC_D12 SDRC_BA0
SDRC_D1 SDRC_D10 SDRC_NCAS
AM3517, AM3505
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
Figure 2-7. ZER Pin Map [Quadrant C]
Copyright © 2009–2012, Texas Instruments Incorporated Terminal Description 15
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Figure 2-8. ZER Pin Map [Quadrant D]
16 Terminal Description Copyright © 2009–2012, Texas Instruments Incorporated
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
2.2 Ball Characteristics
Table 2-1 and Table 2-2 describe the terminal characteristics and the signals multiplexed on each pin for
the ZCN/ZER packages. The following list describes the table column headers.
1. BALL LOCATION: Ball number(s) on the bottom side associated with each signal(s) on the bottom.
2. PIN NAME: Names of signals multiplexed on each ball (also notice that the name of the pin is the
signal name in mode 0).
Note: The Ball Characteristics table does not take into account subsystem pin multiplexing options.
Subsystem pin multiplexing options are described in Section 2.4,Signal Description.
3. MODE: Multiplexing mode number.
(a) Mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the pin
corresponds to the name of the pin. There is always a function mapped on the primary mode.
Notice that primary mode is not necessarily the default mode.
Note: The default mode is the mode which is automatically configured on release of the internal
GLOBAL_PWRON reset; also see the RESET REL. MODE column.
(b) Modes 1 to 7 are possible modes for alternate functions. On each pin, some modes are effectively
used for alternate functions, while some modes are not used and do not correspond to a functional
configuration.
4. TYPE: Signal direction
– I = Input
– O = Output
– I/O = Input/Output
– D = Open drain
– DS = Differential
– A = Analog
Note: In the safe_mode, the buffer is configured in high-impedance.
5. BALL RESET STATE: The state of the terminal at reset (power up).
– 0: The buffer drives VOL (pulldown/pullup resistor not activated)
0(PD): The buffer drives VOL with an active pulldown resistor.
– 1: The buffer drives VOH (pulldown/pullup resistor not activated)
1(PU): The buffer drives VOH with an active pullup resistor.
– Z: High-impedance
– L: High-impedance with an active pulldown resistor
– H: High-impedance with an active pullup resistor
6. BALL RESET REL. STATE: The state of the terminal at reset release.
– 0: The buffer drives VOL (pulldown/pullup resistor not activated)
0(PD): The buffer drives VOL with an active pulldown resistor.
– 1: The buffer drives VOH (pulldown/pullup resistor not activated)
1(PU): The buffer drives VOH with an active pullup resistor.
– Z: High-impedance
– L: High-impedance with an active pulldown resistor
– H : High-impedance with an active pullup resistor
7. RESET REL. MODE: This mode is automatically configured on release of the internal
GLOBAL_PWRON reset.
8. POWER: The voltage supply that powers the terminal’s I/O buffers.
9. VOLTAGE: Supply voltage for associated pin.
10. HYS: Indicates if the input buffer is with hysteresis.
11. LOAD: Load capacitance of the associated output buffer.
12. PULL U/D - TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and
pulldown resistors can be enabled or disabled via software.
Copyright © 2009–2012, Texas Instruments Incorporated Terminal Description 17
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13. IO CELL: IO cell information.
Note: Configuring two pins to the same input signal is not supported as it can yield unexpected results.
This can be easily prevented with the proper software configuration.
Table 2-1. Ball Characteristics (ZCN Pkg.)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
B21 sdrc_d0 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
A21 sdrc_d1 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
D20 sdrc_d2 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
C20 sdrc_d3 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
E19 sdrc_d4 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
D19 sdrc_d5 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
C19 sdrc_d6 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
B19 sdrc_d7 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
B18 sdrc_d8 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
D17 sdrc_d9 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
C17 sdrc_d10 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
D16 sdrc_d11 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
C16 sdrc_d12 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
B16 sdrc_d13 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
A16 sdrc_d14 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
A15 sdrc_d15 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
A7 sdrc_d16 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
B7 sdrc_d17 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
D7 sdrc_d18 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
E7 sdrc_d19 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
C6 sdrc_d20 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
D6 sdrc_d21 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
B5 sdrc_d22 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
C5 sdrc_d23 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
B4 sdrc_d24 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
A3 sdrc_d25 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
B3 sdrc_d26 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
C3 sdrc_d27 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
C2 sdrc_d28 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
D2 sdrc_d29 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
B1 sdrc_d30 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
C1 sdrc_d31 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
A12 sdrc_ba0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
C13 sdrc_ba1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
D13 sdrc_ba2 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
A11 sdrc_a0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
B11 sdrc_a1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
C11 sdrc_a2 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
D11 sdrc_a3 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
E11 sdrc_a4 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
A10 sdrc_a5 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
B10 sdrc_a6 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
C10 sdrc_a7 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
D10 sdrc_a8 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
E10 sdrc_a9 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
A9 sdrc_a10 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
B9 sdrc_a11 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
A8 sdrc_a12 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
B8 sdrc_a13 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
18 Terminal Description Copyright © 2009–2012, Texas Instruments Incorporated
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
D8 sdrc_a14 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
E13 sdrc_ncs0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
A14 sdrc_ncs1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
A13 sdrc_clk 0 O L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS
B13 sdrc_nclk 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
D14 sdrc_cke0 0 O L PD 7 VDDS 1.8V Yes 8 PU/ PD LVCMOS
sdrc_cke0_s 7 L
afe
C14 sdrc_nras 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
E14 sdrc_ncas 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
B14 sdrc_nwe 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
C21 sdrc_dm0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
B15 sdrc_dm1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
E8 sdrc_dm2 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
D1 sdrc_dm3 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
B20 sdrc_dqs0p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS
B17 sdrc_dqs1p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS
A6 sdrc_dqs2p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS
A2 sdrc_dqs3p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS
A20 sdrc_dqs0n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS
A17 sdrc_dqs1n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS
B6 sdrc_dqs2n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS
B2 sdrc_dqs3n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS
C8 sdrc_odt 0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS
A19 sdrc_strben0 0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS
A18 sdrc_strben_ 0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS
dly0
A5 sdrc_strben1 0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS
A4 sdrc_strben_ 0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS
dly1
B12 ddr_padref 0 A VDDS 1.8V
E3 gpmc_a1 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_34 4 IO
safe_mode 7
E2 gpmc_a2 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_35 4 IO
safe_mode 7
E1 gpmc_a3 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_36 4 IO
safe_mode 7
F7 gpmc_a4 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_37 4 IO
safe_mode 7
F6 gpmc_a5 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_38 4 IO
safe_mode 7
F4 gpmc_a6 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_39 4 IO
safe_mode 7
F3 gpmc_a7 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_40 4 IO
safe_mode 7
F2 gpmc_a8 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_41 4 IO
safe_mode 7
F1 gpmc_a9 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
Copyright © 2009–2012, Texas Instruments Incorporated Terminal Description 19
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Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
sys_ 1 I
ndmareq2
gpio_42 4 IO
safe_mode 7
G6 gpmc_a10 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
sys_ 1 I
ndmareq3
gpio_43 4 IO
safe_mode 7
G5 gpmc_d0 0 IO H PU 0 VDDSHV 1.8V/3.3V 30 PU/ PD LVCMOS
G4 gpmc_d1 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
G3 gpmc_d2 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
G2 gpmc_d3 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
G1 gpmc_d4 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
H2 gpmc_d5 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
H1 gpmc_d6 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
J5 gpmc_d7 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
J4 gpmc_d8 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_44 4 IO
J3 gpmc_d9 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_45 4 IO
J2 gpmc_d10 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_46 4 IO
J1 gpmc_d11 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_47 4 IO
K4 gpmc_d12 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_48 4 IO
K3 gpmc_d13 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_49 4 IO
K2 gpmc_d14 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_50 4 IO
K1 gpmc_d15 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_51 4 IO
L2 gpmc_ncs0 0 O H Z 0 VDDSHV 1.8V/3.3V No 30 NA LVCMOS
L1 gpmc_ncs1 0 O H Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_52 4 IO
M4 gpmc_ncs2 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpt9_pwm_e 2 IO
vt
gpio_53 4 IO
safe_mode 7
M3 gpmc_ncs3 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
sys_ 1 I
ndmareq0
gpt10_pwm_ 2 IO
evt
gpio_54 4 IO
safe_mode 7
M2 gpmc_ncs4 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
sys_ 1 I
ndmareq1
gpt9_pwm_e 3 IO
vt
gpio_55 4 IO
safe_mode 7
20 Terminal Description Copyright © 2009–2012, Texas Instruments Incorporated
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
M1 gpmc_ncs5 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
sys_ 1 I
ndmareq2
gpt10_pwm_ 3 IO
evt
gpio_56 4 IO
safe_mode 7
N5 gpmc_ncs6 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
sys_ 1 I
ndmareq3
gpt11_pwm_ 3 IO
evt
gpio_57 4 IO
safe_mode 7
N4 gpmc_ncs7 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpmc_io_dir 1 O
gpt8_pwm_e 3 IO
vt
gpio_58 4 IO
safe_mode 7
N1 gpmc_clk 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_59 4 IO
R1 gpmc_nadv_ 0 O L Z 0 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS
ale
R2 gpmc_noe 0 O H Z 0 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS
R3 gpmc_nwe 0 O H Z 0 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS
R4 gpmc_nbe0_ 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
cle
gpio_60 4 IO
T1 gpmc_nbe1 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_61 4 IO
safe_mode 7
T2 gpmc_nwp 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_62 4 IO
T3 gpmc_wait0 0 I H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
T4 gpmc_wait1 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
uart4_tx 1 O
gpio_63 4 IO
safe_mode 7
T5 gpmc_wait2 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
uart4_rx 1 I
gpio_64 4 IO
safe_mode 7
U1 gpmc_wait3 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
sys_ 1 I
ndmareq1
uart3_cts_rct 2 I
x
gpio_65 4 IO
safe_mode 7
AE23 dss_pclk 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_66 4 IO
hw_dbg12 5 O
safe_mode 7
AD22 dss_hsync 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_67 4 IO
hw_dbg13 5 O
safe_mode 7
Copyright © 2009–2012, Texas Instruments Incorporated Terminal Description 21
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
www.ti.com
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
AD23 dss_vsync 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_68 4 IO
safe_mode 7
AE24 dss_acbias 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_69 4 IO
safe_mode 7
AD24 dss_data0 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
uart1_cts 2 I
gpio_70 4 IO
safe_mode 7
AD25 dss_data1 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
uart1_rts 2 O
gpio_71 4 IO
safe_mode 7
AC23 dss_data2 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_72 4 IO
safe_mode 7
AC24 dss_data3 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_73 4 IO
safe_mode 7
AC25 dss_data4 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
uart3_rx_ irrx 2 I
gpio_74 4 IO
safe_mode 7
AB24 dss_data5 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
uart3_tx_ irtx 2 O
gpio_75 4 IO
safe_mode 7
AB25 dss_data6 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
uart1_tx 2 O
gpio_76 4 IO
hw_dbg14 5 O
safe_mode 7
AA23 dss_data7 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
uart1_rx 2 I
gpio_77 4 IO
hw_dbg15 5 O
safe_mode 7
AA24 dss_data8 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_78 4 IO
hw_dbg16 5 O
safe_mode 7
AA25 dss_data9 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_79 4 IO
hw_dbg17 5 O
safe_mode 7
Y22 dss_data10 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_80 4 IO
safe_mode 7
Y23 dss_data11 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_81 4 IO
safe_mode 7
Y24 dss_data12 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_82 4 IO
safe_mode 7
22 Terminal Description Copyright © 2009–2012, Texas Instruments Incorporated
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
Y25 dss_data13 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_83 4 IO
safe_mode 7
W21 dss_data14 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_84 4 IO
safe_mode 7
W22 dss_data15 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_85 4 IO
safe_mode 7
W23 dss_data16 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_86 4 IO
safe_mode 7
W24 dss_data17 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_87 4 IO
safe_mode 7
W25 dss_data18 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
mcspi3_clk 2 IO
dss_data4 3 O
gpio_88 4 IO
safe_mode 7
V24 dss_data19 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
mcspi3_ 2 IO
simo
dss_data3 3 O
gpio_89 4 IO
safe_mode 7
V25 dss_data20 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
mcspi3_ 2 IO
somi
dss_data2 3 O
gpio_90 4 IO
safe_mode 7
U21 dss_data21 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
mcspi3_cs0 2 IO
dss_data1 3 O
gpio_91 4 IO
safe_mode 7
U22 dss_data22 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
mcspi3_cs1 2 O
dss_data0 3 O
gpio_92 4 IO
safe_mode 7
U23 dss_data23 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
dss_data5 3 O
gpio_93 4 IO
safe_mode 7
H24 tv_out2 0 O 0 VDDA_DAC 1.8V NA 10-bit DAC
K21 tv_out1 0 O 0 VDDA_DAC 1.8V NA 10-bit DAC
K20 tv_vfb1 0 O Z NA 0 VDDA_DAC 1.8V NA 10-bit DAC
H23 tv_vfb2 0 O Z NA 0 VDDA_DAC 1.8V NA 10-bit DAC
H20 tv_vref 0 I Z NA 0 VDDA_DAC 1.8V NA 10-bit DAC
AD2 ccdc_pclk 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS
gpio_94 4 IO
hw_dbg0 5 O
safe_mode 7
Copyright © 2009–2012, Texas Instruments Incorporated Terminal Description 23
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
www.ti.com
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
AD1 ccdc_field 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS
ccdc_data8 1 I
uart4_tx 2 O
i2c3_scl 3 IOD
gpio_95 4 IO
hw_dbg1 5 O
safe_mode 7
AE2 ccdc_ hd 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS
uart4_rts 2 O
gpio_96 4 IO
safe_mode 7
AD3 ccdc_vd 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS
uart4_cts 2 I
gpio_97 4 IO
hw_dbg2 5 O
safe_mode 7
AE3 ccdc_wen 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS
ccdc_data9 1 I
uart4_rx 2 I
gpio_98 4 IO
hw_dbg3 5 O
safe_mode 7
AD4 ccdc_data0 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS
i2c3_sda 3 IOD
gpio_99 4 I
safe_mode 7
AE4 ccdc_data1 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS
gpio_100 4 I
safe_mode 7
AC5 ccdc_data2 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS
gpio_101 4 IO
hw_dbg4 5 O
safe_mode 7
AD5 ccdc_data3 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS
gpio_102 4 IO
hw_dbg5 5 O
safe_mode 7
AE5 ccdc_data4 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS
gpio_103 4 IO
hw_dbg6 5 O
safe_mode 7
Y6 ccdc_data5 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS
gpio_104 4 IO
hw_dbg7 5 O
safe_mode 7
AB6 ccdc_data6 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS
gpio_105 4 IO
safe_mode 7
AC6 ccdc_data7 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS
gpio_106 4 IO
safe_mode 7
AE6 rmii_mdio_da 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/PD LVCMOS
ta
ccdc_data8 1 I
gpio_107 4 IO
24 Terminal Description Copyright © 2009–2012, Texas Instruments Incorporated
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www.ti.com
SPRS550D –OCTOBER 2009–REVISED MARCH 2012
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
safe_mode 7
AD6 rmii_mdio_cl 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/PD LVCMOS
k
ccdc_data9 1 I
gpio_108 4 IO
safe_mode 7
Y7 rmii_rxd0 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS
ccdc_data10 1 I
gpio_109 4 IO
hw_dbg8 5 O
safe_mode 7
AA7 rmii_rxd1 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS
ccdc_data11 1 I
gpio_110 4 IO
hw_dbg9 5 O
safe_mode 7
AB7 rmii_crs_dv 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS
ccdc_data12 1 I
gpio_111 4 IO
safe_mode 7
AC7 rmii_rxer 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS
ccdc_data13 1 I
gpio_167 4 IO
hw_dbg10 5 O
safe_mode 7
AD7 rmii_txd0 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS
ccdc_ data14 1 I
gpio_126 4 IO
hw_dbg11 5 O
safe_mode 7
AE7 rmii_txd1 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/PD LVCMOS
ccdc_data15 1 I
gpio_112 4 I
safe_mode 7
AD8 rmii_txen 0 O H PU 7 VDDSHV 1.8V/3.3V 25 PU/PD LVCMOS
gpio_113 4 I NA
safe_mode 7
AE8 rmii_50mhz_ 0 I H PU 7 VDDSHV 1.8V/3.3V 25 PU/ PD LVCMOS
clk
gpio_114 4 I NA
safe_mode 7
D25 mcbsp2_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_116 4 IO
safe_mode 7
C25 mcbsp2_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
clkx
gpio_117 4 IO
safe_mode 7
B25 mcbsp2_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_118 4 IO
safe_mode 7
D24 mcbsp2_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_119 4 IO
safe_mode 7
AA9 mmc1_clk 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_120 4 IO
Copyright © 2009–2012, Texas Instruments Incorporated Terminal Description 25
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
www.ti.com
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
safe_mode 7
AB9 mmc1_cmd 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_121 4 IO
safe_mode 7
AC9 mmc1_dat0 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi2_clk 1 IO
gpio_122 4 IO
safe_mode 7
AD9 mmc1_dat1 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi2_simo 1 IO
gpio_123 4 IO
safe_mode 7
AE9 mmc1_dat2 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi2_somi 1 IO
gpio_124 4 IO
safe_mode 7
AA10 mmc1_dat3 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi2_cs0 1 O
gpio_125 4 IO
safe_mode 7
AB10 mmc1_dat4 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS
gpio_126 4 IO
safe_mode 7
AC10 mmc1_dat5 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS
gpio_127 4 IO
safe_mode 7
AD10 mmc1_dat6 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS
gpio_128 4 IO
safe_mode 7
AE10 mmc1_dat7 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS
gpio_129 4 IO
safe_mode 7
AD11 mmc2_clk 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi3_clk 1 IO
uart4_cts 2 I
gpio_130 4 IO
safe_mode 7
AE11 mmc2_ cmd 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi3_ 1 IO
simo
uart4_rts 2 O
gpio_131 4 IO
safe_mode 7
AB12 mmc2_ dat0 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi3_ 1 IO
somi
uart4_tx 2 O
gpio_132 4 IO
safe_mode 7
AC12 mmc2_ dat1 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
uart4_rx 2 I
gpio_133 4 IO
safe_mode 7
AD12 mmc2_ dat2 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi3_cs1 1 O
26 Terminal Description Copyright © 2009–2012, Texas Instruments Incorporated
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Product Folder Link(s): AM3517 AM3505
AM3517, AM3505
www.ti.com
SPRS550D –OCTOBER 2009–REVISED MARCH 2012
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
gpio_134 4 IO
safe_mode 7
AE12 mmc2_ dat3 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi3_cs0 1 IO
gpio_135 4 IO
safe_mode 7
AB13 mmc2_ dat4 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mmc2_dir_da 1 O
t0
mmc3_dat0 3 IO
gpio_136 4 IO
safe_mode 7
AC13 mmc2_ dat5 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mmc2_dir_da 1 O
t1
mmc3_dat1 3 IO
gpio_137 4 IO
mm_fsusb3_r 6 IO
xdp
safe_mode 7
AD13 mmc2_ dat6 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mmc2_dir_ 1 O
cmd
mmc3_dat2 3 IO
gpio_138 4 IO
safe_mode 7
AE13 mmc2_ dat7 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mmc2_ clkin 1 I
mmc3_dat3 3 IO
gpio_139 4 IO
mm_fsusb3_r 6 IO
xdm
safe_mode 7
B24 mcbsp3_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
uart2_cts 1 I
gpio_140 4 IO
safe_mode 7
C24 mcbsp3_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
uart2_rts 1 O
gpio_141 4 IO
safe_mode 7
A24 mcbsp3_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
clkx
uart2_tx 1 O
gpio_142 4 IO
safe_mode 7
C23 mcbsp3_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
uart2_rx 1 I
gpio_143 4 IO
safe_mode 7
F20 uart2_cts 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcbsp3_dx 1 IO
gpt9_pwm_e 2 IO
vt
gpio_144 4 IO
safe_mode 7
F19 uart2_rts 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
Copyright © 2009–2012, Texas Instruments Incorporated Terminal Description 27
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Product Folder Link(s): AM3517 AM3505
AM3517, AM3505
SPRS550D –OCTOBER 2009–REVISED MARCH 2012
www.ti.com
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
mcbsp3_dr 1 I
gpt10_pwm_ 2 IO
evt
gpio_145 4 IO
safe_mode 7
E24 uart2_tx 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcbsp3_ 1 IO
clkx
gpt11_pwm 2 IO
_evt
gpio_146 4 IO
safe_mode 7
E23 uart2_rx 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcbsp3_fsx 1 IO
gpt8_pwm_e 2 IO
vt
gpio_147 4 IO
safe_mode 7
AA19 uart1_tx 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_148 4 IO
safe_mode 7
Y19 uart1_rts 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_149 4 IO
safe_mode 7
Y20 uart1_cts 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_150 4 IO
safe_mode 7
W20 uart1_rx 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcbsp1_ clkr 2 I
mcspi4_clk 3 IO
gpio_151 4 IO
safe_mode 7
B23 mcbsp4_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
clkx
gpio_152 4 IO
mm_fsusb3_t 6 IO
xse0
safe_mode 7
A23 mcbsp4_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_153 4 IO
mm_fsusb3_r 6 IO
xrcv
safe_mode 7
B22 mcbsp4_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_154 4 IO
mm_fsusb3_t 6 IO
xdat
safe_mode 7
A22 mcbsp4_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_155 4 IO
mm_fsusb3_t 6 IO
xen_ n
safe_mode 7
R25 mcbsp1_ clkr 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi4_clk 1 IO
gpio_156 4 IO
safe_mode 7
P21 mcbsp1_fsr 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
28 Terminal Description Copyright © 2009–2012, Texas Instruments Incorporated
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Product Folder Link(s): AM3517 AM3505
AM3517, AM3505
www.ti.com
SPRS550D –OCTOBER 2009–REVISED MARCH 2012
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
gpio_157 4 IO
safe_mode 7
P22 mcbsp1_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi4_ 1 IO
simo
mcbsp3_dx 2 IO
gpio_158 4 IO
safe_mode 7
P23 mcbsp1_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi4_ 1 IO
somi
mcbsp3_dr 2 I
gpio_159 4 IO
safe_mode 7
P25 mcbsp_clks 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_160 4 IO
uart1_cts 5 I
safe_mode 7
P24 mcbsp1_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi4_cs0 1 IO
mcbsp3_fsx 2 IO
gpio_161 4 IO
safe_mode 7
N24 mcbsp1_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
clkx
mcbsp3_ 2 IO
clkx
gpio_162 4 IO
safe_mode 7
N2 uart3_cts_ 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
rctx
gpio_163 4 IO
safe_mode 7
N3 uart3_rts_ sd 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_164 4 IO
safe_mode 7
P1 uart3_rx_ irrx 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_165 4 IO
safe_mode 7
P2 uart3_tx_ irtx 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_166 4 IO
safe_mode 7
F25 usb0_dp 0 IO 5.0V Yes PU/ PD USB_PHY
uart3_tx_ irtx 1 O
F24 usb0_dm 0 IO 5.0V Yes PU/ PD USB_PHY
uart3_rx_ irrx 1 I
G24 usb0_vbus 0 A VDDA3P3V_ 3.3V Yes PU/ PD USB_PHY
USBPHY
G25 usb0_id 0 A VDDA3P3V_ 3.3V Yes PU/ PD USB_PHY
USBPHY
E25 usb0_drvvbu 0 O L PD 7 VDDSHV 1.8V/3.3V 30 LVCMOS
s
uart3_tx_ irtx 2 O
gpio_125 4 IO
safe_mode 7
V2 hecc1_ txd 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 24 PU/ PD LVCMOS
uart3_rx_ irrx 2 I
gpio_130 4 IO
Copyright © 2009–2012, Texas Instruments Incorporated Terminal Description 29
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
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Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
safe_mode 7
V3 hecc1_ rxd 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 24 PU/ PD LVCMOS
uart3_rts_ sd 2 O
gpio_131 4 IO
safe_mode 7
V4 i2c1_scl 0 IOD H PU 0 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain
V5 i2c1_ sda 0 IOD H PU 0 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain
W1 i2c2_scl 0 IOD H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain
gpio_168 4 IO
safe_mode 7
W2 i2c2_sda 0 IOD H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain
gpio_183 4 IO
safe_mode 7
W4 i2c3_scl 0 IOD H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain
gpio_184 4 IO
safe_mode 7
W5 i2c3_sda 0 IOD H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain
gpio_185 4 IO
safe_mode 7
L25 hdq_sio 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD LVCMOS
sys_altclk 1 I
i2c2_sccbe 2 O
i2c3_sccbe 3 O
gpio_170 4 IO
safe_mode 7
AE14 mcspi1_clk 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mmc2_dat4 1 IO
gpio_171 4 IO
safe_mode 7
AD15 mcspi1_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
simo
mmc2_dat5 1 IO
gpio_172 4 IO
safe_mode 7
AC15 mcspi1_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
somi
mmc2_dat6 1 IO
gpio_173 4 IO
safe_mode 7
AB15 mcspi1_cs0 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mmc2_dat7 1 IO
gpio_174 4 IO
safe_mode 7
AD14 mcspi1_cs1 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mmc3_cmd 3 IO
gpio_175 4 IO
safe_mode 7
AE15 mcspi1_cs2 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mmc3_clk 3 O
gpio_176 4 IO
safe_mode 7
AE16 mcspi1_cs3 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
hsusb2_ 3 IO
data2
gpio_177 4 IO
30 Terminal Description Copyright © 2009–2012, Texas Instruments Incorporated
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
mm_fsusb2_t 5 IO
xdat
safe_mode 7
AD16 mcspi2_clk 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
hsusb2_ 3 IO
data7
gpio_178 4 IO
safe_mode 7
AC16 mcspi2_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
simo
gpt9_pwm_e 1 IO
vt
hsusb2_ 3 IO
data4
gpio_179 4 IO
safe_mode 7
AB16 mcspi2_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
somi
gpt10_pwm_ 1 IO
evt
hsusb2_ 3 IO
data5
gpio_180 4 IO
safe_mode 7
AA16 mcspi2_cs0 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpt11_pwm_ 1 IO
evt
hsusb2_ 3 IO
data6
gpio_181 4 IO
safe_mode 7
AE17 mcspi2_cs1 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpt8_pwm_e 1 IO
vt
hsusb2_ 3 IO
data3
gpio_182 4 IO
mm_fsusb2_t 5 IO
xen_ n
safe_mode 7
K24 sys_32k 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
K25 sys_xtalin 0 I Z Z 0 VDDSOSC 1.8V NA PU/ PD LVCMOS
H25 sys_xtalout 0 O Z Z 0 VDDSOSC 1.8V NA PU/ PD LVCMOS
M24 sys_clkreq 0 IO L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_1 4 IO
Y1 sys_nirq 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_0 4 IO
safe_mode 7
Y2 sys_ 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
nrespwron
Y3 sys_ 0 IO L PD 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
nreswarm
gpio_30 4 IO Open Drain
Y4 sys_boot0 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_2 4 IO
AA1 sys_boot1 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_3 4 IO
AA2 sys_boot2 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_4 4 IO
Copyright © 2009–2012, Texas Instruments Incorporated Terminal Description 31
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
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Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
AA3 sys_boot3 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_5 4 IO
AB1 sys_boot4 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mmc2_dir_da 1 O
t2
gpio_6 4 IO
AB2 sys_boot5 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mmc2_dir_da 1 O
t3
gpio_7 4 IO
AC1 sys_boot6 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_8 4 IO
AC2 sys_boot7 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/PD LVCMOS
AC3 sys_boot8 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/PD LVCMOS
N25 sys_clkout1 0 O H PD 0/7(1) VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_10 4 IO
safe_mode 7
M25 sys_clkout2 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 10 PU/ PD LVCMOS
gpio_186 4 IO
safe_mode 7
U24 jtag_ntrst 0 I L PD 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
U25 jtag_tck 0 I L PD 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
T21 jtag_rtck 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
T22 jtag_tms_tms 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
c
T23 jtag_tdi 0 I H PU 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
T24 jtag_tdo 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
T25 jtag_emu0 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_11 4 IO
R24 jtag_emu1 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_31 4 IO
AD17 etk_clk 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mcbsp5_ 1 IO
clkx
mmc3_clk 2 O
hsusb1_stp 3 O
gpio_12 4 IO
AE18 etk_ctl 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mmc3_cmd 2 IO
hsusb1_clk 3 O
gpio_13 4 IO
mm_fsusb1_r 5 IO
xdp
AD18 etk_d0 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mcspi3_ 1 IO
simo
mmc3_dat4 2 IO
hsusb1_ 3 IO
data0
gpio_14 4 IO
mm_fsusb1_r 5 IO
xrcv
AC18 etk_d1 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mcspi3_ 1 IO
somi
hsusb1_ 3 IO
data1
(1) Mux0 if sys_boot6 is pulled down (clock master).
32 Terminal Description Copyright © 2009–2012, Texas Instruments Incorporated
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
gpio_15 4 IO
mm_fsusb1_t 5 IO
xse0
AB18 etk_d2 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mcspi3_cs0 1 IO
hsusb1_ 3 IO
data2
gpio_16 4 IO
mm_fsusb1_t 5 IO
xdat
AA18 etk_d3 0 O L PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mcspi3_clk 1 IO
mmc3_dat3 2 IO
hsusb1_ 3 IO
data7
gpio_17 4 IO
Y18 etk_d4 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mcbsp5_dr 1 I
mmc3_dat0 2 IO
hsusb1_ 3 IO
data4
gpio_18 4 IO
AE19 etk_d5 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mcbsp5_fsx 1 IO
mmc3_dat1 2 IO
hsusb1_ 3 IO
data5
gpio_19 4 IO
AD19 etk_d6 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mcbsp5_dx 1 IO
mmc3_dat2 2 IO
hsusb1_ 3 IO
data6
gpio_20 4 IO
AB19 etk_d7 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mcspi3_cs1 1 O
mmc3_dat7 2 IO
hsusb1_ 3 IO
data3
gpio_21 4 IO
mm_fsusb1_t 5 IO
xen_n
AE20 etk_d8 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mmc3_dat6 2 IO
hsusb1_dir 3 I
gpio_22 4 IO
AD20 etk_d9 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mmc3_dat5 2 IO
hsusb1_nxt 3 I
gpio_23 4 IO
mm_fsusb1_r 5 IO
xdm
AC20 etk_d10 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
uart1_rx 2 I
hsusb2_clk 3 O
gpio_24 4 IO
AB20 etk_d11 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mcspi3_clk 1 IO
Copyright © 2009–2012, Texas Instruments Incorporated Terminal Description 33
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
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Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
hsusb2_stp 3 O
gpio_25 4 IO
mm_fsusb2_r 5 IO
xdp
AE21 etk_d12 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
hsusb2_dir 3 I
gpio_26 4 IO
AD21 etk_d13 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
hsusb2_nxt 3 I
gpio_27 4 IO
mm_fsusb2_r 5 IO
xdm
AC21 etk_d14 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
hsusb2_ 3 IO
data0
gpio_28 4 IO
mm_fsusb2_r 5 IO
xrcv
AE22 etk_d15 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
hsusb2_ 3 IO
data1
gpio_29 4 IO
mm_fsusb2_t 5 IO
xse0
V16, V15, VDD_CORE 0 PWR 1.2V
V11, V10,
U16, U15,
U11, U10,
T18, T17, T9,
T8, R18,
R17, R9, R8,
M18, L18,
L9, L8, K18,
K17, K9, K8,
J16, J15,
J11, J10,
H15, H11,
H10
AA13 VDDS_SRA 0 PWR 1.8V
M_MPU
E17 VDDS_SRA 0 PWR 1.8V
M_CORE_B
G
AA12 CAP_VDD_S 0 PWR 1.2V
RAM_MPU
E16 CAP_VDD_S 0 PWR 1.2V
RAM_CORE
AA15 VDDS_DPLL 0 PWR 1.8V
_MPU_USB
HOST
N20 VDDS_DPLL 0 PWR 1.8V
_PER_CORE
H21 VDDA_DAC 0 PWR 1.8V
F23 VDDA3P3V_ 0 PWR 3.3V
USBPHY
G22 VDDA1P8V_ 0 PWR 1.8V
USBPHY
F22 CAP_VDDA1 0 PWR 1.2V
P2LDO_USB
PHY
34 Terminal Description Copyright © 2009–2012, Texas Instruments Incorporated
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
Y16, Y15, VDDSHV 0 PWR 1.8V/3.3V
Y13, Y12,
Y10, W16,
W15, W13,
W12,W10,
W9, W6, V7,
V6, U19,
T20, T19, T7,
T6, R7, R6,
P20, P19,
N19, N7, N6,
M7, M6, M5,
L19, K19,
K7, K6, K5,
J7, H18, H17
Y9, W18, VDDS 0 PWR 1.8V
U20, R5,
H16, H8,
G17, G16,
G14, G13,
G11, G10,
G8, F16,
F13, F11,
F10, F8
F14 VREFSSTL 0 I
L20 VDDSOSC 0 PWR 1.8V
J25 VSSOSC O GND 1.8V
AE25, AE1, VSS 0 GND
V18, V17,
V14, V13,
V12, V9, V8,
U18, U17,
U14, U13,
U12, U9, U8,
T14, T13,
T12, R16,
R15, R14,
R13, R12,
R11, R10,
P18, P17,
P16, P15,
P14, P13,
P12, P11,
P10, P9, P8,
N18, N17,
N14, N13,
N12, N9, N8,
M17, M16,
M15, M14,
M13,M12,
M11, M10,
M9, M8, L17,
L16, L15,
L14, L13,
L12, L11,
L10, K14,
K13, K12,
J18, J17,
J14, J13,
J12, J9, J8,
H14, H13,
H12, H9,
A25, A1,
N23, G20,
G21
H22 VSSA_DAC 0 GND
L24, L23, NC(2)
L22, L21,
K23, K22,
H19,
N22,N21,F17
U2(3) Reserved
V1(3) Reserved
(2) "NC" indicates "No Connect". For proper device operation, these pins must be left unconnected.
(3) For proper device operation, this pin must be pulled up to VDDSHV via a 10k-Ωresistor.
Copyright © 2009–2012, Texas Instruments Incorporated Terminal Description 35
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
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Table 2-2. Ball Characteristics (ZER Pkg.)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
E3 sdrc_d0 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
D3 sdrc_d1 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
C3 sdrc_d2 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
C2 sdrc_d3 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
F3 sdrc_d4 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
D2 sdrc_d5 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
C1 sdrc_d6 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
D1 sdrc_d7 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
G2 sdrc_d8 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
G3 sdrc_d9 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
H3 sdrc_d10 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
G4 sdrc_d11 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
H4 sdrc_d12 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
G1 sdrc_d13 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
J3 sdrc_d14 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
J1 sdrc_d15 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
T3 sdrc_d16 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
U3 sdrc_d17 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
U4 sdrc_d18 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
V4 sdrc_d19 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
V1 sdrc_d20 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
V2 sdrc_d21 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
V5 sdrc_d22 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
V3 sdrc_d23 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
W3 sdrc_d24 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
W4 sdrc_d25 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
Y3 sdrc_d26 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
Y4 sdrc_d27 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
AA2 sdrc_d28 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
AA3 sdrc_d29 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
AA4 sdrc_d30 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
AB2 sdrc_d31 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
L4 sdrc_ba0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
K5 sdrc_ba1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
J5 sdrc_ba2 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
M3 sdrc_a0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
M4 sdrc_a1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
M5 sdrc_a2 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
N3 sdrc_a3 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
N2 sdrc_a4 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
N4 sdrc_a5 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
P3 sdrc_a6 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
P2 sdrc_a7 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
P1 sdrc_a8 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
P4 sdrc_a9 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
R1 sdrc_a10 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
R2 sdrc_a11 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
R3 sdrc_a12 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
R4 sdrc_a13 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
T2 sdrc_a14 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
J4 sdrc_ncs0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
K4 sdrc_ncs1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
L1 sdrc_clk 0 O L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS
L2 sdrc_nclk 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
36 Terminal Description Copyright © 2009–2012, Texas Instruments Incorporated
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
K3 sdrc_cke0 0 O L PD 7 VDDS 1.8V Yes 8 PU/ PD LVCMOS
sdrc_cke0_s 7 I
afe
K1 sdrc_nras 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
L3 sdrc_ncas 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
K2 sdrc_nwe 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
F4 sdrc_dm0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
J2 sdrc_dm1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
T4 sdrc_dm2 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
AB3 sdrc_dm3 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
E2 sdrc_dqs0p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS
H2 sdrc_dqs1p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS
U1 sdrc_dqs2p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS
Y1 sdrc_dqs3p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS
E1 sdrc_dqs0n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS
H1 sdrc_dqs1n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS
U2 sdrc_dqs2n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS
Y2 sdrc_dqs3n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS
T1 sdrc_odt 0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS
F2 sdrc_strben0 0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS
F1 sdrc_strben_ 0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS
dly0
W1 sdrc_strben1 0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS
W2 sdrc_strben_ 0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS
dly1
W5 gpmc_a1 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_34 4 IO
Y5 gpmc_a2 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_35 4 IO
AB4 gpmc_a3 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_36 4 IO
AA5 gpmc_a4 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_37 4 IO
AB5 gpmc_a5 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_38 4 IO
AB6 gpmc_a6 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_39 4 IO
AA6 gpmc_a7 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_40 4 IO
W6 gpmc_a8 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_41 4 IO
AB7 gpmc_a9 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
sys_ 1 I
ndmareq2
gpio_42 4 IO
Y6 gpmc_a10 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
sys_ 1 I
ndmareq3
gpio_43 4 IO
AA7 gpmc_d0 0 IO H PU 0 VDDSHV 1.8V/3.3V 30 PU/ PD LVCMOS
Y7 gpmc_d1 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
W7 gpmc_d2 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
AA9 gpmc_d3 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
Y8 gpmc_d4 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
AA8 gpmc_d5 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
AB8 gpmc_d6 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
W8 gpmc_d7 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
Copyright © 2009–2012, Texas Instruments Incorporated Terminal Description 37
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
www.ti.com
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
W10 gpmc_d8 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_44 4 IO
AB9 gpmc_d9 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_45 4 IO
AB10 gpmc_d10 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_46 4 IO
W9 gpmc_d11 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_47 4 IO
AA10 gpmc_d12 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_48 4 IO
Y9 gpmc_d13 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_49 4 IO
V10 gpmc_d14 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_50 4 IO
V9 gpmc_d15 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_51 4 IO
Y10 gpmc_ncs0 0 O H Z 0 VDDSHV 1.8V/3.3V No 30 NA LVCMOS
Y11 gpmc_ncs1 0 O H Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_52 4 IO
Y12 gpmc_ncs2 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpt9_pwm_e 2 IO
vt
gpio_53 4 IO
V12 gpmc_ncs3 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
sys_ 1 I
ndmareq0
gpt10_pwm_ 2 IO
evt
gpio_54 4 IO
AA11 gpmc_ncs4 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
sys_ 1 I
ndmareq1
gpt9_pwm_e 3 IO
vt
gpio_55 4 IO
W12 gpmc_ncs5 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
sys_ 1 I
ndmareq2
gpt10_pwm_ 3 IO
evt
gpio_56 4 IO
AA12 gpmc_ncs6 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
sys_ 1 I
ndmareq3
gpt11_pwm_ 3 IO
evt
gpio_57 4 IO
V11 gpmc_ncs7 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpmc_io_dir 1 O
gpt8_pwm_e 3 IO
vt
gpio_58 4 IO
AB13 gpmc_clk 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_59 4 IO
AA14 gpmc_nadv_ 0 O L Z 0 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS
ale
AB14 gpmc_noe 0 O H Z 0 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS
AA15 gpmc_nwe 0 O H Z 0 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS
38 Terminal Description Copyright © 2009–2012, Texas Instruments Incorporated
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Product Folder Link(s): AM3517 AM3505
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www.ti.com
SPRS550D –OCTOBER 2009–REVISED MARCH 2012
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
W11 gpmc_nbe0_ 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
cle
gpio_60 4 IO
Y15 gpmc_nbe1 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_61 4 IO
W14 gpmc_nwp 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_62 4 IO
V13 gpmc_wait0 0 I H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
AA16 gpmc_wait1 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
uart4_tx 1 O
gpio_63 4 IO
Y14 gpmc_wait2 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
uart4_rx 1 I
gpio_64 4 IO
V14 gpmc_wait3 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
sys_ 1 I
ndmareq1
uart3_cts_rct 2 I
x
gpio_65 4 IO
B22 dss_pclk 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_66 4 IO
hw_dbg12 5 O
B21 dss_hsync 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_67 4 IO
hw_dbg13 5 O
B20 dss_vsync 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_68 4 IO
B19 dss_acbias 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_69 4 IO
A20 dss_data0 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
uart1_cts 2 I
gpio_70 4 IO
A19 dss_data1 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
uart1_rts 2 O
gpio_71 4 IO
A18 dss_data2 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_72 4 IO
B18 dss_data3 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_73 4 IO
A17 dss_data4 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
uart3_rx_irrx 2 I
gpio_74 4 IO
C18 dss_data5 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
uart3_tx_irtx 2 O
gpio_75 4 IO
D17 dss_data6 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
uart1_tx 2 O
gpio_76 4 IO
hw_dbg14 5 O
B16 dss_data7 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
uart1_rx 2 I
gpio_77 4 IO
hw_dbg15 5 O
B17 dss_data8 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_78 4 IO
Copyright © 2009–2012, Texas Instruments Incorporated Terminal Description 39
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Product Folder Link(s): AM3517 AM3505
AM3517, AM3505
SPRS550D –OCTOBER 2009–REVISED MARCH 2012
www.ti.com
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
hw_dbg16 5 O
C17 dss_data9 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_79 4 IO
hw_dbg17 5 O
C16 dss_data10 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_80 4 IO
D16 dss_data11 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_81 4 IO
D14 dss_data12 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_82 4 IO
A16 dss_data13 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_83 4 IO
D15 dss_data14 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_84 4 IO
B15 dss_data15 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_85 4 IO
A15 dss_data16 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_86 4 IO
A14 dss_data17 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_87 4 IO
C13 dss_data18 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
mcspi3_clk 2 IO
dss_data4 3 O
gpio_88 4 IO
C15 dss_data19 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
mcspi3_ 2 IO
simo
dss_data3 3 O
gpio_89 4 IO
A13 dss_data20 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
mcspi3_ 2 IO
somi
dss_data2 3 O
gpio_90 4 IO
B13 dss_data21 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
mcspi3_cs0 2 IO
dss_data1 3 O
gpio_91 4 IO
C14 dss_data22 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
mcspi3_cs1 2 O
gpio_92 4 IO
B14 dss_data23 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
dss_data5 3 O
gpio_93 4 IO
AB21 ccdc_pclk 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS
gpio_94 4 IO
hw_dbg0 5 O
AA21 ccdc_field 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS
ccdc_data8 1 I
uart4_tx 2 O
i2c3_scl 3 IO
gpio_95 4 IO
hw_dbg1 5 O
Y21 ccdc_ hd 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS
uart4_rts 2 O
40 Terminal Description Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): AM3517 AM3505
AM3517, AM3505
www.ti.com
SPRS550D –OCTOBER 2009–REVISED MARCH 2012
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
gpio_96 4 IO
Y22 ccdc_vd 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS
uart4_cts 2 I
gpio_97 4 IO
hw_dbg2 5 O
W21 ccdc_wen 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS
ccdc_data9 1 I
uart4_rx 2 I
gpio_98 4 IO
hw_dbg3 5 O
W22 ccdc_data0 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS
i2c3_sda 3 IO
gpio_99 4 I
W20 ccdc_data1 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS
gpio_100 4 I
V21 ccdc_data2 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS
gpio_101 4 IO
hw_dbg4 5 O
V19 ccdc_data3 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS
gpio_102 4 IO
hw_dbg5 5 O
V22 ccdc_data4 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS
gpio_103 4 IO
hw_dbg6 5 O
U20 ccdc_data5 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS
gpio_104 4 IO
hw_dbg7 5 O
V20 ccdc_data6 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS
gpio_105 4 IO
U19 ccdc_data7 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS
gpio_106 4 IO
U21 rmii_mdio_da 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/PD LVCMOS
ta
ccdc_data8 1 I
gpio_107 4 IO 8
U22 rmii_mdio_clk 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/PD LVCMOS
ccdc_data9 1 I 8
gpio_108 4 IO
T19 rmii_rxd0 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS
ccdc_data10 1 I
gpio_109 4 IO
hw_dbg8 5 O
T20 rmii_rxd1 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS
ccdc_data11 1 I
gpio_110 4 IO
hw_dbg9 5 O
T21 rmii_crs_dv 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS
ccdc_data12 1 I
gpio_111 4 IO
R22 rmii_rxer 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS
ccdc_data13 1 I
gpio_167 4 IO
hw_dbg10 5 O
Copyright © 2009–2012, Texas Instruments Incorporated Terminal Description 41
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Product Folder Link(s): AM3517 AM3505
AM3517, AM3505
SPRS550D –OCTOBER 2009–REVISED MARCH 2012
www.ti.com
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
T22 rmii_txd0 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS
ccdc_ data14 1 I
gpio_126 4 IO
hw_dbg11 5 O
R20 rmii_txd1 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/PD LVCMOS
ccdc_data15 1 I
gpio_112 4 I
R19 rmii_txen 0 O H PU 7 VDDSHV 1.8V/3.3V 25 PU/PD LVCMOS
gpio_113 4 I NA
R21 rmii_50mhz_ 0 I H PU 7 VDDSHV 1.8V/3.3V 25 PU/ PD LVCMOS
clk
gpio_114 4 I NA
E5 mcbsp2_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_116 4 IO
D5 mcbsp2_ clkx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_117 4 IO
C5 mcbsp2_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_118 4 IO
E4 mcbsp2_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_119 4 IO
P22 mmc1_clk 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_120 4 IO
N21 mmc1_cmd 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_121 4 IO
P21 mmc1_dat0 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi2_clk 1 IO
gpio_122 4 IO
N20 mmc1_dat1 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi2_simo 1 IO
gpio_123 4 IO
P19 mmc1_dat2 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi2_somi 1 IO
gpio_124 4 IO
P20 mmc1_dat3 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi2_cs0 1 O
gpio_125 4 IO
N22 mmc1_dat4 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS
gpio_126 4 IO
N19 mmc1_dat5 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS
gpio_127 4 IO
N18 mmc1_dat6 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS
gpio_128 4 IO
P18 mmc1_dat7 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS
gpio_129 4 IO
M21 mmc2_clk 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi3_clk 1 IO
uart4_cts 2 I
gpio_130 4 IO
M20 mmc2_ cmd 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi3_ 1 IO
simo
uart4_rts 2 O
gpio_131 4 IO
K20 mmc2_ dat0 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi3_ 1 IO
somi
42 Terminal Description Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): AM3517 AM3505
AM3517, AM3505
www.ti.com
SPRS550D –OCTOBER 2009–REVISED MARCH 2012
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
uart4_tx 2 O
gpio_132 4 IO
L19 mmc2_ dat1 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
uart4_rx 2 I
gpio_133 4 IO
M18 mmc2_ dat2 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi3_cs1 1 O
gpio_134 4 IO
K21 mmc2_ dat3 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi3_cs0 1 IO
gpio_135 4 IO
L18 mmc2_ dat4 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mmc2_dir_da 1 O
t0
mmc3_dat0 3 IO
gpio_136 4 IO
L20 mmc2_ dat5 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mmc2_dir_da 1 O
t1
mmc3_dat1 3 IO
gpio_137 4 IO
mm_fsusb3_r 6 IO
xdp
L21 mmc2_ dat6 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mmc2_dir_c 1 O
md
mmc3_dat2 3 IO
gpio_138 4 IO
M19 mmc2_ dat7 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mmc2_clkin 1 I
mmc3_dat3 3 IO
gpio_139 4 IO
mm_fsusb3_r 6 IO
xdm
C4 mcbsp3_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
uart2_cts 1 I
gpio_140 4 IO
B4 mcbsp3_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
uart2_rts 1 O
gpio_141 4 IO
D4 mcbsp3_ clkx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
uart2_tx 1 O
gpio_142 4 IO
A4 mcbsp3_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
uart2_rx 1 I
gpio_143 4 IO
A5 uart2_cts 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcbsp3_dx 1 IO
gpt9_pwm_e 2 IO
vt
gpio_144 4 IO
B5 uart2_rts 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcbsp3_dr 1 I
gpt10_pwm_ 2 IO
evt
gpio_145 4 IO
D6 uart2_tx 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
Copyright © 2009–2012, Texas Instruments Incorporated Terminal Description 43
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Table 2-2. Ball Characteristics (ZER Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
mcbsp3_clkx 1 IO
gpt11_pwm 2 IO
_evt
gpio_146 4 IO
C6 uart2_rx 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcbsp3_fsx 1 IO
gpt8_pwm_e 2 IO
vt
gpio_147 4 IO
C22 uart1_tx 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_148 4 IO
C21 uart1_rts 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_149 4 IO
C19 uart1_cts 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_150 4 IO
C20 uart1_rx 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcbsp1_ clkr 2 I
mcspi4_clk 3 IO
gpio_151 4 IO
A3 mcbsp4_ clkx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_152 4 IO
mm_fsusb3_t 6 IO
xse0
B3 mcbsp4_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_153 4 IO
mm_fsusb3_r 6 IO
xrcv
A2 mcbsp4_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_154 4 IO
mm_fsusb3_t 6 IO
xdat
B2 mcbsp4_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_155 4 IO
mm_fsusb3_t 6 IO
xen_n
B11 mcbsp1_ clkr 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi4_clk 1 IO
gpio_156 4 IO
D11 mcbsp1_fsr 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_157 4 IO
C10 mcbsp1_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi4_ 1 IO
simo
mcbsp3_dx 2 I
gpio_158 4 IO
C9 mcbsp1_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi4_ 1 IO
somi
mcbsp3_dr 2 I
gpio_159 4 IO
E11 mcbsp_clks 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_160 4 IO
uart1_cts 5 I
C11 mcbsp1_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi4_cs0 1 IO
mcbsp3_fsx 2 IO
gpio_161 4 IO
C8 mcbsp1_ clkx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
44 Terminal Description Copyright © 2009–2012, Texas Instruments Incorporated
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
mcbsp3_clkx 2 IO
gpio_162 4 IO
W15 uart3_cts_rct 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
x
gpio_163 4 IO
W13 uart3_rts_sd 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_164 4 IO
AA13 uart3_rx_irrx 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_165 4 IO
Y13 uart3_tx_irtx 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_166 4 IO
A6 usb0_dp 0 IO 5.0V Yes PU/ PD LVCMOS
B6 usb0_dm 0 IO 5.0V Yes PU/ PD LVCMOS
C7 usb0_vbus 0 A VDDA3P3V_ 3.3V Yes PU/ PD LVCMOS
USBPHY
B7 usb0_id 0 A VDDA3P3V_ 3.3V Yes PU/ PD LVCMOS
USBPHY
A7 usb0_drvvbu 0 O L PD 7 VDDSHV 1.8V/3.3V 30
s
uart3_tx_irtx 2 O
gpio_125 4 IO
AB15 hecc1_ txd 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 24 PU/ PD LVCMOS
uart3_rx_irrx 2 I
gpio_130 4 IO
AB16 hecc1_ rxd 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 24 PU/ PD LVCMOS
uart3_rts_sd 2 O
gpio_131 4 IO
AA17 i2c1_scl 0 IOD H PU 0 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain
AB17 i2c1_ sda 0 IOD H PU 0 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain
Y17 i2c2_scl 0 IOD H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain
gpio_168 4 IO
Y16 i2c2_sda 0 IOD H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain
gpio_183 4 IO
W16 i2c3_scl 0 IOD H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain
gpio_184 4 IO
W17 i2c3_sda 0 IOD H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain
gpio_185 4 IO
B9 hdq_sio 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD LVCMOS
sys_altclk 1 I
i2c2_sccbe 2 O
i2c3_sccbe 3 O
gpio_170 4 IO
K22 mcspi1_clk 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mmc2_dat4 1 IO
gpio_171 4 IO
K19 mcspi1_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
simo
mmc2_dat5 1 IO
gpio_172 4 IO
J18 mcspi1_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
somi
mmc2_dat6 1 IO
gpio_173 4 IO
K18 mcspi1_cs0 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mmc2_dat7 1 IO
gpio_174 4 IO
J20 mcspi1_cs1 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
Copyright © 2009–2012, Texas Instruments Incorporated Terminal Description 45
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
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Table 2-2. Ball Characteristics (ZER Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
mmc3_cmd 3 IO
gpio_175 4 IO
J19 mcspi1_cs2 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mmc3_clk 3 O
gpio_176 4 IO
J21 mcspi1_cs3 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
hsusb2_ 3 IO
data2
gpio_177 4 IO
mm_fsusb2_t 5 IO
xdat
J22 mcspi2_clk 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
hsusb2_ 3 IO
data7
gpio_178 4 IO
H20 mcspi2_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
simo
gpt9_pwm_e 1 IO
vt
hsusb2_ 3 IO
data4
gpio_179 4 IO
H22 mcspi2_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
somi
gpt10_pwm_ 1 IO
evt
hsusb2_ 3 IO
data5
gpio_180 4 IO
H21 mcspi2_cs0 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpt11_pwm_ 1 IO
evt
hsusb2_ 3 IO
data6
gpio_181 4 IO
H19 mcspi2_cs1 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpt8_pwm_e 1 IO
vt
hsusb2_ 3 IO
data3
gpio_182 4 IO
mm_fsusb2_t 5 IO
xen_n
A8 sys_32k 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
A10 sys_xtalin 0 I Z Z 0 VDDSOSC 1.8V NA PU/ PD LVCMOS
A9 sys_xtalout 0 O Z Z 0 VDDSOSC 1.8V NA PU/ PD LVCMOS
B8 sys_clkreq 0 IO L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_1 4 IO
AB18 sys_nirq 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_0 4 IO
AA18 sys_ 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
nrespwron
Y18 sys_ 0 IO L PD 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
nreswarm
gpio_30 4 IO Open Drain
AB19 sys_boot0 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_2 4 IO
AB20 sys_boot1 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_3 4 IO
W18 sys_boot2 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_4 4 IO
46 Terminal Description Copyright © 2009–2012, Texas Instruments Incorporated
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
AA19 sys_boot3 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_5 4 IO
V18 sys_boot4 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mmc2_dir_da 1 O
t2
gpio_6 4 IO
Y19 sys_boot5 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mmc2_dir_da 1 O
t3
gpio_7 4 IO
W19 sys_boot6 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_8 4 IO
AA20 sys_boot7 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/PD LVCMOS
Y20 sys_boot8 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/PD LVCMOS
E9 sys_clkout1 0 O H PD 0/7(1) VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_10 4 IO
E10 sys_clkout2 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 10 PU/ PD LVCMOS
gpio_186 4 IO
D13 jtag_ntrst 0 I L PD 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
E14 jtag_tck 0 I L PD 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
C12 jtag_rtck 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
A12 jtag_tms_tms 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
c
B12 jtag_tdi 0 I H PU 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
D12 jtag_tdo 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
E13 jtag_emu0 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_11 4 IO
E12 jtag_emu1 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_31 4 IO
G22 etk_clk 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mcbsp5_ clkx 1 IO
mmc3_clk 2 O
hsusb1_stp 3 O
gpio_12 4 IO
G21 etk_ctl 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mmc3_cmd 2 IO
hsusb1_clk 3 O
gpio_13 4 IO
mm_fsusb1_r 5 IO
xdp
G20 etk_d0 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mcspi3_ 1 IO
simo
mmc3_dat4 2 IO
hsusb1_ 3 IO
data0
gpio_14 4 IO
mm_fsusb1_r 5 IO
xrcv
F22 etk_d1 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mcspi3_ 1 IO
somi
hsusb1_ 3 IO
data1
gpio_15 4 IO
mm_fsusb1_t 5 IO
xse0
(1) Mux0 if sys_boot6 is pulled down (clock master).
Copyright © 2009–2012, Texas Instruments Incorporated Terminal Description 47
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
www.ti.com
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
F20 etk_d2 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mcspi3_cs0 1 IO
hsusb1_ 3 IO
data2
gpio_16 4 IO
mm_fsusb1_t 5 IO
xdat
G19 etk_d3 0 O L PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mcspi3_clk 1 IO
mmc3_dat3 2 IO
hsusb1_ 3 IO
data7
gpio_17 4 IO
E19 etk_d4 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mcbsp5_dr 1 I
mmc3_dat0 2 IO
hsusb1_ 3 IO
data4
gpio_18 4 IO
F21 etk_d5 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mcbsp5_fsx 1 IO
mmc3_dat1 2 IO
hsusb1_ 3 IO
data5
gpio_19 4 IO
F19 etk_d6 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mcbsp5_dx 1 IO
mmc3_dat2 2 IO
hsusb1_ 3 IO
data6
gpio_20 4 IO
E21 etk_d7 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mcspi3_cs1 1 O
mmc3_dat7 2 IO
hsusb1_ 3 IO
data3
gpio_21 4 IO
mm_fsusb1_t 5 IO
xen_n
D22 etk_d8 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mmc3_dat6 2 IO
hsusb1_dir 3 I
gpio_22 4 IO
D21 etk_d9 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mmc3_dat5 2 IO
hsusb1_nxt 3 I
gpio_23 4 IO
mm_fsusb1_r 5 IO
xdm
E22 etk_d10 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
uart1_rx 2 I
hsusb2_clk 3 O
gpio_24 4 IO
E20 etk_d11 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mcspi3_clk 1 IO
hsusb2_stp 3 O
gpio_25 4 IO
48 Terminal Description Copyright © 2009–2012, Texas Instruments Incorporated
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
mm_fsusb2_r 5 IO
xdp
E18 etk_d12 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
hsusb2_dir 3 I
gpio_26 4 IO
D20 etk_d13 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
hsusb2_nxt 3 I
gpio_27 4 IO
mm_fsusb2_r 5 IO
xdm
D19 etk_d14 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
hsusb2_ 3 IO
data0
gpio_28 4 IO
mm_fsusb2_r 5 IO
xrcv
D18 etk_d15 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
hsusb2_ 3 IO
data1
gpio_29 4 IO
mm_fsusb2_t 5 IO
xse0
M2 ddr_padref 0 A VDDS 1.8V
J8, J10, VDD_CORE 0 PWR 1.2V
J12, J14,
J16, K9,
K11, K13,
K15, L8,
L10, L12,
L14, M7,
M9, M11,
M13, M15,
N8, N10,
N12, N14,
P7, P9,
P11, P13,
P15, R8,
R10, R12,
R14
L17 VDDS_SRA 0 PWR 1.8V
M_MPU
J6 VDDS_SRA 0 PWR 1.8V
M_CORE_B
G
M17 CAP_VDD_S 0 PWR 1.2V
RAM_MPU
K6 CAP_VDD_S 0 PWR 1.2V
RAM_CORE
K17 VDDS_DPLL 0 PWR 1.8V
_MPU_USBH
OST
F11 VDDS_DPLL 0 PWR 1.8V
_PER_CORE
F7 VDDA3P3V_ 0 PWR 3.3V
USBPHY
D7 VDDA1P8V_ 0 PWR 1.8V
USBPHY
E7 CAP_VDDA1 0 PWR 1.2V
P2LDO_USB
PHY
Copyright © 2009–2012, Texas Instruments Incorporated Terminal Description 49
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
www.ti.com
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
A21, B1, VDDSHV 0 PWR 1.8V/3.3V
E15, E17,
F12, F14,
F18, G10,
G12, G13,
G8, G17,
H18, J17,
L22, N16,
P17, R16,
R18, T9,
T11, T13,
T17, U8,
U10, U12,
U14, U16,
U18, V7,
V8, V17,
AA22,
AB11
F5, F16, VDDS 0 PWR 1.8V
G15, H5,
K7, L6,
L16, N1,
N5, N6, P5,
R6, T5, T7,
T15, U6,
AA1
L5 VREFSSTL 0 I .5 * VDDS
G9 VDDSOSC O PWR 1.8V
A1, A11, VSS 0 GND
A22, E6,
E16, F6,
F13, F15,
F17, G5,
G7, G11,
G14, G16,
G18, H6,
H7, H8, H9,
H10, H11,
H12, H13,
H14, H15,
H16, H17,
J9, J11,
J13, J15,
K8, K10,
K12, K14,
K16, L7,
L9, L11,
L13, L15,
M1, M6,
M8, M10,
M12, M14,
M16, M22,
N7, N9,
N11, N13,
N15, N17,
P6, P8,
P10, P12,
P14, P16,
R5, R7, R9,
R11, R13,
R15, R17,
T6, T8,
T10, T12,
T14, T16,
T18, U5,
U7, U9,
U11, U13,
U15, U17,
V6, AB1,
AB12,
AB22
B10 VSSOSC 0 GND
D8, D9, NC(2)
D10, E8,
F8, F9,
F10, J7, G6
V15 Reserved(3)
V16 Reserved(3)
(2) "NC" indicates "No Connect". For proper device operation, these pins must be left unconnected.
(3) For proper device operation, this pin must be pulled up via a 10k-Ωresistor.
50 Terminal Description Copyright © 2009–2012, Texas Instruments Incorporated
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
2.3 Multiplexing Characteristics
Table 2-3 provides descriptions of the AM3517/05 pin multiplexing on the ZCN and ZER packages.
Table 2-3. Multiplexing Characteristics
ZER ZCN MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE 7
BALL NO BALL NO
E3 B21 sdrc_d0
D3 A21 sdrc_d1
C3 D20 sdrc_d2
C2 C20 sdrc_d3
F3 E19 sdrc_d4
D2 D19 sdrc_d5
C1 C19 sdrc_d6
D1 B19 sdrc_d7
G2 B18 sdrc_d8
G3 D17 sdrc_d9
H3 C17 sdrc_d10
G4 D16 sdrc_d11
H4 C16 sdrc_d12
G1 B16 sdrc_d13
J3 A16 sdrc_d14
J1 A15 sdrc_d15
T3 A7 sdrc_d16
U3 B7 sdrc_d17
U4 D7 sdrc_d18
V4 E7 sdrc_d19
V1 C6 sdrc_d20
V2 D6 sdrc_d21
V5 B5 sdrc_d22
V3 C5 sdrc_d23
W3 B4 sdrc_d24
W4 A3 sdrc_d25
Y3 B3 sdrc_d26
Y4 C3 sdrc_d27
AA2 C2 sdrc_d28
AA3 D2 sdrc_d29
AA4 B1 sdrc_d30
AB2 C1 sdrc_d31
L4 A12 sdrc_ba0
K5 C13 sdrc_ba1
J5 D13 sdrc_ba2
M3 A11 sdrc_a0
M4 B11 sdrc_a1
M5 C11 sdrc_a2
N3 D11 sdrc_a3
N2 E11 sdrc_a4
N4 A10 sdrc_a5
P3 B10 sdrc_a6
P2 C10 sdrc_a7
P1 D10 sdrc_a8
P4 E10 sdrc_a9
R1 A9 sdrc_a10
R2 B9 sdrc_a11
R3 A8 sdrc_a12
R4 B8 sdrc_a13
T2 D8 sdrc_a14
J4 E13 sdrc_ncs0
Copyright © 2009–2012, Texas Instruments Incorporated Terminal Description 51
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Table 2-3. Multiplexing Characteristics (continued)
ZER ZCN MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE 7
K4 A14 sdrc_ncs1
L1 A13 sdrc_clk
L2 B13 sdrc_nclk
K3 D14 sdrc_cke0 sdrc_cke0_safe
K1 C14 sdrc_nras
L3 E14 sdrc_ncas
K2 B14 sdrc_nwe
F4 C21 sdrc_dm0
J2 B15 sdrc_dm1
T4 E8 sdrc_dm2
AB3 D1 sdrc_dm3
E2 B20 sdrc_dqs0p
H2 B17 sdrc_dqs1p
U1 A6 sdrc_dqs2p
Y1 A2 sdrc_dqs3p
E1 A20 sdrc_dqs0n
H1 A17 sdrc_dqs1n
U2 B6 sdrc_dqs2n
Y2 B2 sdrc_dqs3n
T1 C8 sdrc_odt
F2 A19 sdrc_strben0
F1 A18 sdrc_strben_dly0
W1 A5 sdrc_strben1
W2 A4 sdrc_strben_dly1
W5 E3 gpmc_a1 gpio_34 safe_mode
Y5 E2 gpmc_a2 gpio_35 safe_mode
AB4 E1 gpmc_a3 gpio_36 safe_mode
AA5 F7 gpmc_a4 gpio_37 safe_mode
AB5 F6 gpmc_a5 gpio_38 safe_mode
AB6 F4 gpmc_a6 gpio_39 safe_mode
AA6 F3 gpmc_a7 gpio_40 safe_mode
W6 F2 gpmc_a8 gpio_41 safe_mode
AB7 F1 gpmc_a9 sys_ndmareq2 gpio_42 safe_mode
Y6 G6 gpmc_a10 sys_ndmareq3 gpio_43 safe_mode
AA7 G5 gpmc_d0
Y7 G4 gpmc_d1
W7 G3 gpmc_d2
AA9 G2 gpmc_d3
Y8 G1 gpmc_d4
AA8 H2 gpmc_d5
AB8 H1 gpmc_d6
W8 J5 gpmc_d7
W10 J4 gpmc_d8 gpio_44
AB9 J3 gpmc_d9 gpio_45
AB10 J2 gpmc_d10 gpio_46
W9 J1 gpmc_d11 gpio_47
AA10 K4 gpmc_d12 gpio_48
Y9 K3 gpmc_d13 gpio_49
V10 K2 gpmc_d14 gpio_50
V9 K1 gpmc_d15 gpio_51
Y10 L2 gpmc_ncs0
Y11 L1 gpmc_ncs1 gpio_52
Y12 M4 gpmc_ncs2 gpt9_pwm_evt gpio_53 safe_mode
V12 M3 gpmc_ncs3 sys_ndmareq0 gpt10_pwm_evt gpio_54 safe_mode
AA11 M2 gpmc_ncs4 sys_ndmareq1 gpt9_pwm_evt gpio_55 safe_mode
W12 M1 gpmc_ncs5 sys_ndmareq2 gpt10_pwm_evt gpio_56 safe_mode
52 Terminal Description Copyright © 2009–2012, Texas Instruments Incorporated
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
Table 2-3. Multiplexing Characteristics (continued)
ZER ZCN MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE 7
AA12 N5 gpmc_ncs6 sys_ndmareq3 gpt11_pwm_evt gpio_57 safe_mode
V11 N4 gpmc_ncs7 gpmc_io_dir gpt8_pwm_evt gpio_58 safe_mode
AB13 N1 gpmc_clk gpio_59
AA14 R1 gpmc_nadv_ale
AB14 R2 gpmc_noe
AA15 R3 gpmc_nwe
W11 R4 gpmc_nbe0_cle gpio_60
Y15 T1 gpmc_nbe1 gpio_61 safe_mode
W14 T2 gpmc_nwp gpio_62
V13 T3 gpmc_wait0
AA16 T4 gpmc_wait1 uart4_tx gpio_63 safe_mode
Y14 T5 gpmc_wait2 uart4_rx gpio_64 safe_mode
V14 U1 gpmc_wait3 sys_ndmareq1 uart3_cts_rctx gpio_65 safe_mode
B22 AE23 dss_pclk gpio_66 hw_dbg12 safe_mode
B21 AD22 dss_hsync gpio_67 hw_dbg13 safe_mode
B20 AD23 dss_vsync gpio_68 safe_mode
B19 AE24 dss_acbias gpio_69 safe_mode
A20 AD24 dss_data0 uart1_cts gpio_70 safe_mode
A19 AD25 dss_data1 uart1_rts gpio_71 safe_mode
A18 AC23 dss_data2 gpio_72 safe_mode
B18 AC24 dss_data3 gpio_73 safe_mode
A17 AC25 dss_data4 uart3_rx_irrx gpio_74 safe_mode
C18 AB24 dss_data5 uart3_tx_irtx gpio_75 safe_mode
D17 AB25 dss_data6 uart1_tx gpio_76 hw_dbg14 safe_mode
B16 AA23 dss_data7 uart1_rx gpio_77 hw_dbg15 safe_mode
B17 AA24 dss_data8 gpio_78 hw_dbg16 safe_mode
C17 AA25 dss_data9 gpio_79 hw_dbg17 safe_mode
C16 Y22 dss_data10 gpio_80 safe_mode
D16 Y23 dss_data11 gpio_81 safe_mode
D14 Y24 dss_data12 gpio_82 safe_mode
A16 Y25 dss_data13 gpio_83 safe_mode
D15 W21 dss_data14 gpio_84 safe_mode
B15 W22 dss_data15 gpio_85 safe_mode
A15 W23 dss_data16 gpio_86 safe_mode
A14 W24 dss_data17 gpio_87 safe_mode
C13 W25 dss_data18 mcspi3_clk dss_data4 gpio_88 safe_mode
C15 V24 dss_data19 mcspi3_simo dss_data3 gpio_89 safe_mode
A13 V25 dss_data20 mcspi3_somi dss_data2 gpio_90 safe_mode
B13 U21 dss_data21 mcspi3_cs0 dss_data1 gpio_91 safe_mode
C14 U22 dss_data22 mcspi3_cs1 dss_data0 gpio_92 safe_mode
B14 U23 dss_data23 dss_data5 gpio_93 safe_mode
NA K20 tv_vfb1
NA K21 tv_out1
NA H23 tv_vfb2
NA H24 tv_out2
NA H20 tv_vref
AB21 AD2 ccdc_pclk gpio_94 hw_dbg0 safe_mode
AA21 AD1 ccdc_field ccdc_data8 uart4_tx i2c3_scl gpio_95 hw_dbg1 safe_mode
Y21 AE2 ccdc_hd uart4_rts gpio_96 safe_mode
Y22 AD3 ccdc_vd uart4_cts gpio_97 hw_dbg2 safe_mode
W21 AE3 ccdc_wen ccdc_data9 uart4_rx gpio_98 hw_dbg3 safe_mode
W22 AD4 ccdc_data0 i2c3_sda gpio_99 safe_mode
W20 AE4 ccdc_data1 gpio_100 safe_mode
V21 AC5 ccdc_data2 gpio_101 hw_dbg4 safe_mode
V19 AD5 ccdc_data3 gpio_102 hw_dbg5 safe_mode
V22 AE5 ccdc_data4 gpio_103 hw_dbg6 safe_mode
Copyright © 2009–2012, Texas Instruments Incorporated Terminal Description 53
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Table 2-3. Multiplexing Characteristics (continued)
ZER ZCN MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE 7
U20 Y6 ccdc_data5 gpio_104 hw_dbg7 safe_mode
V20 AB6 ccdc_data6 gpio_105 safe_mode
U19 AC6 ccdc_data7 gpio_106 safe_mode
U21 AE6 rmii_mdio_data ccdc_data8 gpio_107 safe_mode
U22 AD6 rmii_mdio_clk ccdc_data9 gpio_108 safe_mode
T19 Y7 rmii_rxd0 ccdc_data10 gpio_109 hw_dbg8 safe_mode
T20 AA7 rmii_rxd1 ccdc_data11 gpio_110 hw_dbg9 safe_mode
T21 AB7 rmii_crs_dv ccdc_data12 gpio_111 safe_mode
R22 AC7 rmii_rxer ccdc_data13 gpio_167 hw_dbg10 safe_mode
T22 AD7 rmii_txd0 ccdc_data14 gpio_126 hw_dbg11 safe_mode
R20 AE7 rmii_txd1 ccdc_data15 gpio_112 safe_mode
R19 AD8 rmii_txen gpio_113 safe_mode
R21 AE8 rmii_50mhz_clk gpio_114 safe_mode
E5 D25 mcbsp2_fsx gpio_116 safe_mode
D5 C25 mcbsp2_clkx gpio_117 safe_mode
C5 B25 mcbsp2_dr gpio_118 safe_mode
E4 D24 mcbsp2_dx gpio_119 safe_mode
P22 AA9 mmc1_clk gpio_120 safe_mode
N21 AB9 mmc1_cmd gpio_121 safe_mode
P21 AC9 mmc1_dat0 mcspi2_clk gpio_122 safe_mode
N20 AD9 mmc1_dat1 mcspi2_simo gpio_123 safe_mode
P19 AE9 mmc1_dat2 mcspi2_somi gpio_124 safe_mode
P20 AA10 mmc1_dat3 mcspi2_cs0 gpio_125 safe_mode
N22 AB10 mmc1_dat4 gpio_126 safe_mode
N19 AC10 mmc1_dat5 gpio_127 safe_mode
N18 AD10 mmc1_dat6 gpio_128 safe_mode
P18 AE10 mmc1_dat7 gpio_129 safe_mode
M21 AD11 mmc2_clk mcspi3_clk uart4_cts gpio_130 safe_mode
M20 AE11 mmc2_cmd mcspi3_simo uart4_rts gpio_131 safe_mode
K20 AB12 mmc2_dat0 mcspi3_somi uart4_tx gpio_132 safe_mode
L19 AC12 mmc2_dat1 uart4_rx gpio_133 safe_mode
M18 AD12 mmc2_dat2 mcspi3_cs1 gpio_134 safe_mode
K21 AE12 mmc2_dat3 mcspi3_cs0 gpio_135 safe_mode
L18 AB13 mmc2_dat4 mmc2_dir_dat0 mmc3_dat0 gpio_136 safe_mode
L20 AC13 mmc2_dat5 mmc2_dir_dat1 mmc3_dat1 gpio_137 mm_fsusb3_rxdp safe_mode
L21 AD13 mmc2_dat6 mmc2_dir_cmd mmc3_dat2 gpio_138 safe_mode
M19 AE13 mmc2_dat7 mmc2_clkin mmc3_dat3 gpio_139 mm_fsusb3_rxdm safe_mode
C4 B24 mcbsp3_dx uart2_cts gpio_140 safe_mode
B4 C24 mcbsp3_dr uart2_rts gpio_141 safe_mode
D4 A24 mcbsp3_clkx uart2_tx gpio_142 safe_mode
A4 C23 mcbsp3_fsx uart2_rx gpio_143 safe_mode
A5 F20 uart2_cts mcbsp3_dx gpt9_pwm_evt gpio_144 safe_mode
B5 F19 uart2_rts mcbsp3_dr gpt10_pwm_evt gpio_145 safe_mode
D6 E24 uart2_tx mcbsp3_clkx gpt11_pwm_evt gpio_146 safe_mode
C6 E23 uart2_rx mcbsp3_fsx gpt8_pwm_evt gpio_147 safe_mode
C22 AA19 uart1_tx gpio_148 safe_mode
C21 Y19 uart1_rts gpio_149 safe_mode
C19 Y20 uart1_cts gpio_150 safe_mode
C20 W20 uart1_rx mcbsp1_clkr mcspi4_clk gpio_151 safe_mode
A3 B23 mcbsp4_clkx gpio_152 mm_fsusb3_txse safe_mode
0
B3 A23 mcbsp4_dr gpio_153 mm_fsusb3_rxrcv safe_mode
A2 B22 mcbsp4_dx gpio_154 mm_fsusb3_txdat safe_mode
B2 A22 mcbsp4_fsx gpio_155 mm_fsusb3_txen safe_mode
_n
B11 R25 mcbsp1_clkr mcspi4_clk gpio_156 safe_mode
D11 P21 mcbsp1_fsr gpio_157 safe_mode
54 Terminal Description Copyright © 2009–2012, Texas Instruments Incorporated
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
Table 2-3. Multiplexing Characteristics (continued)
ZER ZCN MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE 7
C10 P22 mcbsp1_dx mcspi4_simo mcbsp3_dx gpio_158 safe_mode
C9 P23 mcbsp1_dr mcspi4_somi mcbsp3_dr gpio_159 safe_mode
E11 P25 mcbsp_clks gpio_160 uart1_cts safe_mode
C11 P24 mcbsp1_fsx mcspi4_cs0 mcbsp3_fsx gpio_161 safe_mode
C8 N24 mcbsp1_clkx mcbsp3_clkx gpio_162 safe_mode
W15 N2 uart3_cts_rctx gpio_163 safe_mode
W13 N3 uart3_rts_sd gpio_164 safe_mode
AA13 P1 uart3_rx_irrx gpio_165 safe_mode
Y13 P2 uart3_tx_irtx gpio_166
A6 F25 usb0_dp(1) uart3_tx_irtx
B6 F24 usb0_dm(1) uart3_rx_irrx
C7 G24 usb0_vbus
B7 G25 usb0_id
A7 E25 usb0_drvvbus uart3_tx_irtx gpio_125 safe_mode
AB15 V2 hecc1_txd uart3_rx_irrx gpio_130 safe_mode
AB16 V3 hecc1_rxd uart3_rts_sd gpio_131 safe_mode
AA17 V4 i2c1_scl
AB17 V5 i2c1_sda
Y17 W1 i2c2_scl gpio_168 safe_mode
Y16 W2 i2c2_sda gpio_183 safe_mode
W16 W4 i2c3_scl gpio_184 safe_mode
W17 W5 i2c3_sda gpio_185 safe_mode
B9 L25 hdq_sio sys_altclk i2c2_sccbe i2c3_sccbe gpio_170 safe_mode
K22 AE14 mcspi1_clk mmc2_dat4 gpio_171 safe_mode
K19 AD15 mcspi1_simo mmc2_dat5 gpio_172 safe_mode
J18 AC15 mcspi1_somi mmc2_dat6 gpio_173 safe_mode
K18 AB15 mcspi1_cs0 mmc2_dat7 gpio_174 safe_mode
J20 AD14 mcspi1_cs1 mmc3_cmd gpio_175 safe_mode
J19 AE15 mcspi1_cs2 mmc3_clk gpio_176 safe_mode
J21 AE16 mcspi1_cs3 hsusb2_data2 gpio_177 mm_fsusb2_txdat safe_mode
J22 AD16 mcspi2_clk hsusb2_data7 gpio_178 safe_mode
H20 AC16 mcspi2_simo gpt9_pwm_evt hsusb2_data4 gpio_179 safe_mode
H22 AB16 mcspi2_somi gpt10_pwm_evt hsusb2_data5 gpio_180 safe_mode
H21 AA16 mcspi2_cs0 gpt11_pwm_evt hsusb2_data6 gpio_181 safe_mode
H19 AE17 mcspi2_cs1 gpt8_pwm_evt hsusb2_data3 gpio_182 mm_fsusb2_txen safe_mode
_n
AB18 Y1 sys_nirq gpio_0 safe_mode
E10 M25 sys_clkout2 gpio_186 safe_mode
G22 AD17 etk_clk mcbsp5_clkx mmc3_clk hsusb1_stp gpio_12 hw_dbg0
G21 AE18 etk_ctl mmc3_cmd hsusb1_clk gpio_13 mm_fsusb1_rxdp hw_dbg1
G20 AD18 etk_d0 mcspi3_simo mmc3_dat4 hsusb1_data0 gpio_14 mm_fsusb1_rxrcv hw_dbg2
F22 AC18 etk_d1 mcspi3_somi hsusb1_data1 gpio_15 mm_fsusb1_txse hw_dbg3
0
F20 AB18 etk_d2 mcspi3_cs0 hsusb1_data2 gpio_16 mm_fsusb1_txdat hw_dbg4
G19 AA18 etk_d3 mcspi3_clk mmc3_dat3 hsusb1_data7 gpio_17 hw_dbg5
E19 Y18 etk_d4 mcbsp5_dr mmc3_dat0 hsusb1_data4 gpio_18 hw_dbg6
F21 AE19 etk_d5 mcbsp5_fsx mmc3_dat1 hsusb1_data5 gpio_19 hw_dbg7
F19 AD19 etk_d6 mcbsp5_dx mmc3_dat2 hsusb1_data6 gpio_20 hw_dbg8
E21 AB19 etk_d7 mcspi3_cs1 mmc3_dat7 hsusb1_data3 gpio_21 mm_fsusb1_txen hw_dbg9
_n
D22 AE20 etk_d8 mmc3_dat6 hsusb1_dir gpio_22 hw_dbg10
D21 AD20 etk_d9 mmc3_dat5 hsusb1_nxt gpio_23 mm_fsusb1_rxdm hw_dbg11
E22 AC20 etk_d10 uart1_rx hsusb2_clk gpio_24 hw_dbg12
E20 AB20 etk_d11 mcspi3_clk hsusb2_stp gpio_25 mm_fsusb2_rxdp hw_dbg13
E18 AE21 etk_d12 hsusb2_dir gpio_26 hw_dbg14
D20 AD21 etk_d13 hsusb2_nxt gpio_27 mm_fsusb2_rxdm hw_dbg15
(1) This mux selection is controlled by CONTROL_DEVCONF2 register.
Copyright © 2009–2012, Texas Instruments Incorporated Terminal Description 55
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Table 2-3. Multiplexing Characteristics (continued)
ZER ZCN MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE 7
D19 AC21 etk_d14 hsusb2_data0 gpio_28 mm_fsusb2_rxrcv hw_dbg16
D18 AE22 etk_d15 hsusb2_data1 gpio_29 mm_fsusb2_txse hw_dbg17
0
A8 K24 sys_32k
A10 K25 sys_xtalin
A9 H25 sys_xtalout
B8 M24 sys_clkreq gpio_1
AA18 Y2 sys_nrespwron
Y18 Y3 sys_nreswarm gpio_30
AB19 Y4 sys_boot0 gpio_2
AB20 AA1 sys_boot1 gpio_3
W18 AA2 sys_boot2 gpio_4
AA19 AA3 sys_boot3 gpio_5
V18 AB1 sys_boot4 mmc2_dir_dat2 gpio_6
Y19 AB2 sys_boot5 mmc2_dir_dat3 gpio_7
W19 AC1 sys_boot6 gpio_8
AA20 AC2 sys_boot7
Y20 AC3 sys_boot8
E9 N25 sys_clkout1 gpio_10 safe_mode
D13 U24 jtag_ntrst
E14 U25 jtag_tck
C12 T21 jtag_rtck
A12 T22 jtag_tms_tmsc
B12 T23 jtag_tdi
D12 T24 jtag_tdo
E13 T25 jtag_emu0 gpio_11
E12 R24 jtag_emu1 gpio_31
M2 B12 ddr_padref
56 Terminal Description Copyright © 2009–2012, Texas Instruments Incorporated
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
2.4 Signal Description
Many signals are available on multiple pins according to the software configuration of the pin multiplexing
options.
1. SIGNAL NAME: The signal name
2. DESCRIPTION: Description of the signal
3. TYPE: Type = Ball type for this specific function:
– I = Input
– O = Output
– Z = High-impedance
– D = Open Drain
– DS = Differential
– A = Analog
4. BALL: Associated ball location
5. SUBSYSTEM PIN MULTIPLEXING: Contains a list of the pin multiplexing options at the
module/subsystem level. The pin function is selected at the module/system level.
Note: The Subsystem Multiplexing Signals are not described in Table 2-1 through Table 2-2.
2.4.1 External Memory Interfaces
Table 2-4. External Memory Interfaces - GPMC Signals Description
SIGNAL NAME[1] DESCRIPTION[2] TYPE[3] ZCN BALL[4] ZER BALL[4] SUBSYSTEM PIN
MULTIPLEXING [5]
gpmc_a1 GPMC Address bit 1 O E3/G5 W5/AA7 gpmc_a17
gpmc_a2 GPMC Address bit 2 O E2/G4 Y5/Y7 gpmc_a18
gpmc_a3 GPMC Address bit 3 O E1/G3 AB4/W7 gpmc_a19
gpmc_a4 GPMC Address bit 4 O F7/G2 AA5/AA9 gpmc_a20
gpmc_a5 GPMC Address bit 5 O F6/G1 AB5/Y8 gpmc_a21
gpmc_a6 GPMC Address bit 6 O F4/H2 AB6/AA8 gpmc_a22
gpmc_a7 GPMC Address bit 7 O F3/H1 AA6/AB8 gpmc_a23
gpmc_a8 GPMC Address bit 8 O F2/J5 W6/W8 gpmc_a24
gpmc_a9 GPMC Address bit 9 O F1/J4 AB7/W10 gpmc_a25
gpmc_a10 GPMC Address bit 10 O G6/J3 Y6/AB9 gpmc_a26
gpmc_a11 GPMC Address bit 11 O J2 AB10
multiplexed on
gpmc_d10
gpmc_a12 GPMC Address bit12 O J1 W9
multiplexed on
gpmc_d11
gpmc_a13 GPMC Address bit13 O K4 AA10
multiplexed on
gpmc_d12
gpmc_a14 GPMC Address bit O K3 Y9
14multiplexed on
gpmc_d13
gpmc_a15 GPMC Address bit15 O K2 V10
multiplexed on
gpmc_d14
gpmc_a16 GPMC Address bit16 O K1 V9
multiplexed on
gpmc_d15
gpmc_a17 GPMC Address bit17 O E3 W5
multiplexed on
gpmc_a1
Copyright © 2009–2012, Texas Instruments Incorporated Terminal Description 57
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Table 2-4. External Memory Interfaces - GPMC Signals Description (continued)
SIGNAL NAME[1] DESCRIPTION[2] TYPE[3] ZCN BALL[4] ZER BALL[4] SUBSYSTEM PIN
MULTIPLEXING [5]
gpmc_a18 GPMC Address bit18 O E2 Y5
multiplexed on
gpmc_a2
gpmc_a19 GPMC Address bit19 O E1 AB4
multiplexed on
gpmc_a3
gpmc_a20 GPMC Address bit20 O F7 AA5
multiplexed on
gpmc_a4
gpmc_a21 GPMC Address bit21 O F6 AB5
multiplexed on
gpmc_a5
gpmc_a22 GPMC Address bit22 O F4 AB6
multiplexed on
gpmc_a6
gpmc_a23 GPMC Address bit23 O F3 AA6
multiplexed on
gpmc_a7
gpmc_a24 GPMC Address bit24 O F2 W6
multiplexed on
gpmc_a8
gpmc_a25 GPMC Address bit25 O F1 AB7
multiplexed on
gpmc_a9
gpmc_a26 GPMC Address bit26 O G6 Y6
multiplexed on
gpmc_a10
gpmc_d0 GPMC Data bit 0 IO G5 AA7 gpmc_a1/gpmc_d0
gpmc_d1 GPMC Data bit 1 IO G4 Y7 gpmc_a2/gpmc_d1
gpmc_d2 GPMC Data bit 2 IO G3 W7 gpmc_a3/gpmc_d2
gpmc_d3 GPMC Data bit 3 IO G2 AA9 gpmc_a4/gpmc_d3
gpmc_d4 GPMC Data bit 4 IO G1 Y8 gpmc_a5/gpmc_d4
gpmc_d5 GPMC Data bit 5 IO H2 AA8 gpmc_a6/gpmc_d5
gpmc_d6 GPMC Data bit 6 IO H1 AB8 gpmc_a7/gpmc_d6
gpmc_d7 GPMC Data bit 7 IO J5 W8 gpmc_a8/gpmc_d7
gpmc_d8 GPMC Data bit 8 IO J4 W10 gpmc_a9/gpmc_d8
gpmc_d9 GPMC Data bit 9 IO J3 AB9 gpmc_a10/gpmc_d9
gpmc_d10 GPMC Data bit 10 IO J2 AB10 gpmc_a11/gpmc_d10
gpmc_d11 GPMC Data bit 11 IO J1 W9 gpmc_a12/gpmc_d11
gpmc_d12 GPMC Data bit 12 IO K4 AA10 gpmc_a13/gpmc_d12
gpmc_d13 GPMC Data bit 13 IO K3 Y9 gpmc_a14/gpmc_d13
gpmc_d14 GPMC Data bit 14 IO K2 V10 gpmc_a15/gpmc_d14
gpmc_d15 GPMC Data bit 15 IO K1 V9 gpmc_a16/gpmc_d15
gpmc_ncs0 GPMC Chip Select 0 O L2 Y10
gpmc_ncs1 GPMC Chip Select 1 O L1 Y11
gpmc_ncs2 GPMC Chip Select 2 O M4 Y12
gpmc_ncs3 GPMC Chip Select 3 O M3 V12
gpmc_ncs4 GPMC Chip Select 4 O M2 AA11
gpmc_ncs5 GPMC Chip Select 5 O M1 W12
gpmc_ncs6 GPMC Chip Select 6 O N5 AA12
gpmc_ncs7 GPMC Chip Select 7 O N4 V11
gpmc_clk GPMC clock O N1 AB13
58 Terminal Description Copyright © 2009–2012, Texas Instruments Incorporated
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
Table 2-4. External Memory Interfaces - GPMC Signals Description (continued)
SIGNAL NAME[1] DESCRIPTION[2] TYPE[3] ZCN BALL[4] ZER BALL[4] SUBSYSTEM PIN
MULTIPLEXING [5]
gpmc_nadv_ale Address Valid or O R1 AA14
Address Latch
Enable
gpmc_noe Output Enable O R2 AB14
gpmc_nwe Write Enable O R3 AA15
gpmc_nbe0_cle Lower Byte Enable. O R4 W11
Also used for
Command Latch
Enable
gpmc_nbe1 Upper Byte Enable O T1 Y15
gpmc_nwp Flash Write Protect O T2 W14
gpmc_wait0 External indication of I T3 V13
wait
gpmc_wait1 External indication of I T4 AA16
wait
gpmc_wait2 External indication of I T5 Y14
wait
gpmc_wait3 External indication of I U1 V14
wait
Table 2-5. External Memory Interfaces - SDRC Signals Description
SIGNAL NAME[1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
sdrc_d0 SDRAM data bit 0 IO B21 E3
sdrc_d1 SDRAM data bit 1 IO A21 D3
sdrc_d2 SDRAM data bit2 IO D20 C3
sdrc_d3 SDRAM data bit 3 IO C20 C2
sdrc_d4 SDRAM data bit 4 IO E19 F3
sdrc_d5 SDRAM data bit 5 IO D19 D2
sdrc_d6 SDRAM data bit 6 IO C19 C1
sdrc_d7 SDRAM data bit 7 IO B19 D1
sdrc_d8 SDRAM data bit 8 IO B18 G2
sdrc_d9 SDRAM data bit 9 IO D17 G3
sdrc_d10 SDRAM data bit 10 IO C17 H3
sdrc_d11 SDRAM data bit 11 IO D16 G4
sdrc_d12 SDRAM data bit 12 IO C16 H4
sdrc_d13 SDRAM data bit 13 IO B16 G1
sdrc_d14 SDRAM data bit 14 IO A16 J3
sdrc_d15 SDRAM data bit 15 IO A15 J1
sdrc_d16 SDRAM data bit 16 IO A7 T3
sdrc_d17 SDRAM data bit 17 IO B7 U3
sdrc_d18 SDRAM data bit 18 IO D7 U4
sdrc_d19 SDRAM data bit 19 IO E7 V4
sdrc_d20 SDRAM data bit 20 IO C6 V1
sdrc_d21 SDRAM data bit 21 IO D6 V2
sdrc_d22 SDRAM data bit 22 IO B5 V5
sdrc_d23 SDRAM data bit 23 IO C5 V3
sdrc_d24 SDRAM data bit 24 IO B4 W3
sdrc_d25 SDRAM data bit 25 IO A3 W4
sdrc_d26 SDRAM data bit 26 IO B3 Y3
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Table 2-5. External Memory Interfaces - SDRC Signals Description (continued)
SIGNAL NAME[1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
sdrc_d27 SDRAM data bit 27 IO C3 Y4
sdrc_d28 SDRAM data bit 28 IO C2 AA2
sdrc_d29 SDRAM data bit 29 IO D2 AA3
sdrc_d30 SDRAM data bit 30 IO B1 AA4
sdrc_d31 SDRAM data bit 31 IO C1 AB2
sdrc_ba0 SDRAM bank select 0 O A12 L4
sdrc_ba1 SDRAM bank select 1 O C13 K5
sdrc_ba2 SDRAM bank select 2 O D13 J5
sdrc_a0 SDRAM address bit 0 O A11 M3
sdrc_a1 SDRAM address bit 1 O B11 M4
sdrc_a2 SDRAM address bit 2 O C11 M5
sdrc_a3 SDRAM address bit 3 O D11 N3
sdrc_a4 SDRAM address bit 4 O E11 N2
sdrc_a5 SDRAM address bit 5 O A10 N4
sdrc_a6 SDRAM address bit 6 O B10 P3
sdrc_a7 SDRAM address bit 7 O C10 P2
sdrc_a8 SDRAM address bit 8 O D10 P1
sdrc_a9 SDRAM address bit 9 O E10 P4
sdrc_a10 SDRAM address bit 10 O A9 R1
sdrc_a11 SDRAM address bit 11 O B9 R2
sdrc_a12 SDRAM address bit 12 O A8 R3
sdrc_a13 SDRAM address bit 13 O B8 R4
sdrc_a14 SDRAM address bit 14 O D8 T2
sdrc_ncs0 Chip select 0 O E13 J4
sdrc_ncs1 Chip select 1 O A14 K4
sdrc_clk Clock O A13 L1
sdrc_nclk Clock Invert O B13 L2
sdrc_cke0 Clock Enable 0 O D14 K3
sdrc_nras SDRAM Row Access O C14 K1
sdrc_ncas SDRAM column address O E14 L3
strobe
sdrc_nwe SDRAM write enable O B14 K2
sdrc_dm0 Data Mask 0 O C21 F4
sdrc_dm1 Data Mask 1 O B15 J2
sdrc_dm2 Data Mask 2 O E8 T4
sdrc_dm3 Data Mask 3 O D1 AB3
sdrc_strben0 PCB layout trace loop 0 A A19 F2
pin 0
sdrc_strben_dly0 PCB layout trace loop 0 A A18 F1
pin 1
sdrc_strben1 PCB layout trace loop 1 A A5 W1
pin 0
sdrc_strben_dly1 PCB layout trace loop 1 A A4 W2
pin 1
sdrc_odt On-die termination output O C8 T1
for sdrc_ncs0 only
sdrc_dqs0p Data Strobe 0 IO B20 E2
sdrc_dqs0n Data Strobe 0 IO A20 E1
sdrc_dqs1p Data Strobe 1 IO B17 H2
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Table 2-5. External Memory Interfaces - SDRC Signals Description (continued)
SIGNAL NAME[1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
sdrc_dqs1n Data Strobe 1 IO A17 H1
sdrc_dqs2p Data Strobe 2 IO A6 U1
sdrc_dqs2n Data Strobe 2 IO B6 U2
sdrc_dqs3p Data Strobe 3 IO A2 Y1
sdrc_dqs3n Data Strobe 3 IO B2 Y2
ddr_padref Impedance control for A B12 M2
DDR2 output. This pin
must be connected to
ground via a 50-ohm (±
2%) resistor.
VREFSSTL VREFSSTL is .5 * VDDS IO F14 L5
= 0.9V for DDR data
PHY0 reference voltage
input
2.4.2 Video Interfaces
Table 2-6. Video Interfaces - CCDC Signals Description
SIGNAL NAME[1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4] SYSTEM MUX
MODE(1)
ccdc_pclk CCDC pixel clock IO AD2 AB21 mode0
ccdc_field CCDC field ID signal IO AD1 AA21 mode0
ccdc_hd CCDC horizontal IO AE2 Y21 mode0
sync
ccdc_vd CCDC vertical sync IO AD3 Y22 mode0
ccdc_wen CCDC write enable I AE3 W21 mode0
ccdc_data0 CCDC data bit 0 I AD4 W22 mode0
ccdc_data1 CCDC data bit 1 I AE4 W20 mode0
ccdc_data2 CCDC data bit 2 I AC5 V21 mode0
ccdc_data3 CCDC data bit 3 I AD5 V19 mode0
ccdc_data4 CCDC data bit 4 I AE5 V22 mode0
ccdc_data5 CCDC data bit 5 I Y6 U20 mode0
ccdc_data6 CCDC data bit 6 I AB6 V20 mode0
ccdc_data7 CCDC data bit 7 I AC6 U19 mode0
ccdc_data8 CCDC data bit 8 I AE6 U21 mode1
ccdc_data9 CCDC data bit 9 I AD6 U22 mode1
ccdc_data10 CCDC data bit 10 I Y7 T19 mode1
ccdc_data11 CCDC data bit 11 I AA7 T20 mode1
ccdc_data12 CCDC data bit 12 I AB7 T21 mode1
ccdc_data13 CCDC data bit 13 I AC7 R22 mode1
ccdc_data14 CCDC data bit 14 I AD7 T22 mode1
ccdc_data15 CCDC data bit 15 I AE7 R20 mode1
(1) See Multiplexing Characteristics table for more information.
Table 2-7. Video Interfaces - DSS Signals Description
SIGNAL NAME[1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
dss_pclk LCD Pixel Clock O AE23 B22
dss_hsync LCD Horizontal O AD22 B21
Synchronization
dss_vsync LCD Vertical O AD23 B20
Synchronization
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Table 2-7. Video Interfaces - DSS Signals Description (continued)
SIGNAL NAME[1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
dss_acbias AC bias control (STN) or O AE24 B19
pixel data enable (TFT)
output
dss_data0 LCD Pixel Data bit 0 IO AD24 A20
dss_data1 LCD Pixel Data bit 1 IO AD25 A19
dss_data2 LCD Pixel Data bit 2 IO AC23 A18
dss_data3 LCD Pixel Data bit 3 IO AC24 B18
dss_data4 LCD Pixel Data bit 4 IO AC25 A17
dss_data5 LCD Pixel Data bit 5 IO AB24 C18
dss_data6 LCD Pixel Data bit 6 IO AB25 D17
dss_data7 LCD Pixel Data bit 7 IO AA23 B16
dss_data8 LCD Pixel Data bit 8 IO AA24 B17
dss_data9 LCD Pixel Data bit 9 IO AA25 C17
dss_data10 LCD Pixel Data bit 10 IO Y22 C16
dss_data11 LCD Pixel Data bit 11 IO Y23 D16
dss_data12 LCD Pixel Data bit 12 IO Y24 D14
dss_data13 LCD Pixel Data bit 13 IO Y25 A16
dss_data14 LCD Pixel Data bit 14 IO W21 D15
dss_data15 LCD Pixel Data bit 15 IO W22 B15
dss_data16 LCD Pixel Data bit 16 IO W23 A15
dss_data17 LCD Pixel Data bit 17 IO W24 A14
dss_data18 LCD Pixel Data bit 18 IO W25 C13
dss_data19 LCD Pixel Data bit 19 IO V24 C15
dss_data20 LCD Pixel Data bit 20 O V25 A13
dss_data21 LCD Pixel Data bit 21 O U21 B13
dss_data22 LCD Pixel Data bit 22 O U22 C14
dss_data23 LCD Pixel Data bit 23 O U23 B14
Table 2-8. Video Interfaces – RFBI Signals Description
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4] SUBSYSTEM PIN
MULTIPLEXING [5]
rfbi_a0 RFBI command/data O AE24 B19 dss_acbias
control
rfbi_cs0 1st LCD chip select O AD22 B21 dss_hsync
rfbi_da0 RFBI data bus 0 IO AD24 A20 dss_data0
rfbi_da1 RFBI data bus 1 IO AD25 A19 dss_data1
rfbi_da2 RFBI data bus 2 IO AC23 A18 dss_data2
rfbi_da3 RFBI data bus 3 IO AC24 B18 dss_data3
rfbi_da4 RFBI data bus 4 IO AC25 A17 dss_data4
rfbi_da5 RFBI data bus 5 IO AB24 C18 dss_data5
rfbi_da6 RFBI data bus 6 IO AB25 D17 dss_data6
rfbi_da7 RFBI data bus 7 IO AA23 B16 dss_data7
rfbi_da8 RFBI data bus 8 IO AA24 B17 dss_data8
rfbi_da9 RFBI data bus 9 IO AA25 C17 dss_data9
rfbi_da10 RFBI data bus 10 IO Y22 C16 dss_data10
rfbi_da11 RFBI data bus 11 IO Y23 D16 dss_data11
rfbi_da12 RFBI data bus 12 IO Y24 D14 dss_data12
rfbi_da13 RFBI data bus 13 IO Y25 A16 dss_data13
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Table 2-8. Video Interfaces – RFBI Signals Description (continued)
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4] SUBSYSTEM PIN
MULTIPLEXING [5]
rfbi_da14 RFBI data bus 14 IO W21 D15 dss_data14
rfbi_da15 RFBI data bus 15 IO W22 B15 dss_data15
rfbi_rd Read enable for RFBI O AE23 B22 dss_pclk
rfbi_wr Write Enable for O AD23 B20 dss_vsync
RFBI
rfbi_te_vsync0 tearing effect removal I W23 A15 dss_data16
and Vsync input from
1st LCD
rfbi_hsync0 Hsync for 1st LCD I W24 A14 dss_data17
rfbi_te_vsync1 tearing effect removal I W25 C13 dss_data18
and Vsync input from
2nd LCD
rfbi_hsync1 Hsync for 2nd LCD I V24 C15 dss_data19
rfbi_cs1 2nd LCD chip select O V25 A13 dss_data20
Table 2-9. Video Interfaces – TV Signals Description
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
tv_out1 TV analog output O K21 NA
Composite: tv_out1
tv_out2 TV analog output S- O H24 NA
VIDEO: tv_out2
tv_vfb1 tv_vfb1: Feedback O K20 NA
through external resistor
to composite
tv_vfb2 tv_vfb2: Feedback O H23 NA
through external resistor
to S-VIDEO
tv_vref External capacitor I H20 NA
2.4.3 Serial Communication Interfaces
Table 2-10. HDQ Signals Description
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
hdq_sio Bidirectional HDQ 1-Wire IO L25 B9
control and data Interface.
Output is open drain.
Table 2-11. Serial Communication Interfaces – I2C Signals Description (I2C1)
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
i2c1_scl I2C Master Serial clock. IOD V4 AA17
Output is open drain.
i2c1_sda I2C Serial Bidirectional IOD V5 AB17
Data. Output is open
drain.
Table 2-12. Serial Communication Interfaces - I2C Signals Description (I2C2)
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
i2c2_scl I2C Master Serial clock. IOD W1 Y17
Output is open drain.
i2c2_sda I2C Serial Bidirectional IOD W2 Y16
Data. Output is open
drain.
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Table 2-13. Serial Communication Interfaces - I2C Signals Description (I2C3)
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
i2c3_scl I2C Master Serial clock. IOD W4 W16
Output is open drain.
i2c3_sda I2C Serial Bidirectional IOD W5 W17
Data. Output is open
drain.
Table 2-14. Serial Communication Interfaces – McBSP LP Signals Description
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 1)
mcbsp1_dr Received serial data I P23 C9
mcbsp1_clkr Receive Clock IO R25 B11
mcbsp1_fsr Receive frame IO P21 D11
synchronization
mcbsp1_dx Transmitted serial data IO P22 C10
mcbsp1_clkx Transmit clock IO N24 C8
mcbsp1_fsx Transmit frame IO P24 C11
synchronization
mcbsp_clks External clock input I P25 E11
(shared by McBSP1, 2, 3,
4, and 5)
MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 2)
mcbsp2_dr Received serial data I B25 C5
mcbsp2_dx Transmitted serial data IO D24 E4
mcbsp2_clkx Combined serial clock IO C25 D5
mcbsp2_fsx Combined frame IO D25 E5
synchronization
MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 3)
mcbsp3_dr Received serial data I C24 B4
mcbsp3_dx Transmitted serial data IO B24 C4
mcbsp3_clkx Combined serial clock IO A24 D4
mcbsp3_fsx Combined frame IO C23 A4
synchronization
MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 4)
mcbsp4_dr Received serial data I A23 B3
mcbsp4_dx Transmitted serial data IO B22 A2
mcbsp4_clkx Combined serial clock IO B23 A3
mcbsp4_fsx Combined frame IO A22 B2
synchronization
MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 5)
mcbsp5_dr Received serial data I Y18 E19
mcbsp5_dx Transmitted serial data IO AD19 F19
mcbsp5_clkx Combined serial clock IO AD17 G22
mcbsp5_fsx Combined frame IO AE19 F21
synchronization
Table 2-15. Serial Communication Interfaces – McSPI Signals Description
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
MULTICHANNEL SERIAL PORT INTERFACE (McSPI1)
mcspi1_clk SPI Clock IO AE14 K22
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Table 2-15. Serial Communication Interfaces – McSPI Signals Description (continued)
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
mcspi1_simo Slave data in, master data IO AD15 K19
out
mcspi1_somi Slave data out, master IO AC15 J18
data in
mcspi1_cs0 SPI Enable 0, polarity IO AB15 K18
configured by software
mcspi1_cs1 SPI Enable 1, polarity O AD14 J20
configured by software
mcspi1_cs2 SPI Enable 2, polarity O AE15 J19
configured by software
mcspi1_cs3 SPI Enable 3, polarity O AE16 J21
configured by software
MULTICHANNEL SERIAL PORT INTERFACE (McSPI2)
mcspi2_clk SPI Clock IO AD16,AC9 J22
mcspi2_simo Slave data in, master data IO AC16,AD9 H20
out
mcspi2_somi Slave data out, master IO AB16,AE9 H22
data in
mcspi2_cs0 SPI Enable 0, polarity IO AA16,AA10 H21
configured by software
mcspi2_cs1 SPI Enable 1, polarity O AE17 H19
configured by software
MULTICHANNEL SERIAL PORT INTERFACE (McSPI3)
mcspi3_clk SPI Clock IO W25,AD11,AA18 C13, M21, G19, E20
mcspi3_simo Slave data in, master data IO V24,AE11,AD18 C15, M20, G20
out
mcspi3_somi Slave data out, master IO V25, AB12, AC18 A13, K20, F22
data in
mcspi3_cs0 SPI Enable 0, polarity IO U21,AE12,AB18 B13, K21, F20
configured by software
mcspi3_cs1 SPI Enable 1, polarity O U22, AD12, AB19 C14, M18, E21
configured by software
MULTICHANNEL SERIAL PORT INTERFACE (McSPI4)
mcspi4_clk SPI Clock IO W20, R25 C20, B11
mcspi4_simo Slave data in, master data IO P22 C10
out
mcspi4_somi Slave data out, master IO P23 C9
data in
mcspi4_cs0 SPI Enable 0, polarity IO P24 C11
configured by software
Table 2-16. Serial Communication Interfaces – HECC Signals Description
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
hecc1_txd Transmit serial data pin O V2 AB15
hecc1_rxd Receive serial data pin I V3 AB16
Table 2-17. Serial Communication Interfaces – EMAC (RMII) Signals Description
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
rmii_mdio_data Management data I/O IO AE6 U21
rmii_mdio_clk Management data clock O AD6 U22
rmii_rxd0 EMAC receive data pin 0 I Y7 T19
rmii_rxd1 EMAC receive data pin 1 I AA7 T20
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Table 2-17. Serial Communication Interfaces – EMAC (RMII) Signals Description (continued)
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
rmii_crs_dv EMAC carrier I AB7 T21
sense/receive data valid
rmii_rxer EMAC receive error I AC7 R22
rmii_txd0 EMAC transmit data pin 0 O AD7 T22
rmii_txd1 EMAC transmit data pin 1 O AE7 R20
rmii_txen EMAC transmit enable O AD8 R19
rmii_50mhz_clk EMAC RMII 50 MHz clock I AE8 R21
Table 2-18. Serial Communication Interfaces – UARTs Signals Description
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART1)
uart1_cts UART1 Clear To Send I AD24,Y20,P25 C19,A20,E11
uart1_rts UART1 Request To Send O AD25,Y19 C21,A19
uart1_rx UART1 Receive data I AA23,W20,AC20 C20,B16,E22
uart1_tx UART1 Transmit data O AB25,AA19 C22,D17
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART2)
uart2_cts UART2 Clear To Send I B24,F20 A5,C4
uart2_rts UART2 Request To Send O C24,F19 B5,B4
uart2_rx UART2 Receive data I C23,E23 C6,A4
uart2_tx UART2 Transmit data O A24,E24 D6,D4
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART3) / IrDA
uart3_cts_rctx UART3 Clear To Send IO U1,N2 W15,V14
(input), Remote TX
(output)
uart3_rts_sd UART3 Request To O N3,V3 W13AB16
Send , IR enable
uart3_rx_irrx UART3 Receive data , IR I AC25,P1,F25,V2 AA13,A17,A6,AB15
and Remote RX
uart3_tx_irtx UART3 Transmit data , IR O AB24,P2,F24,E25 Y13,C18,B6,A7
TX
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART4)
uart4_cts UART4 Clear To Send I AD3,AD11 Y22,M21
uart4_rts UART4 Request To Send O AE2,AE11 Y21,M20
uart4_rx UART4 Receive data I T5,AE3,AC12 Y14,W21,L19
uart4_tx UART4 Transmit data O T4,AD1,AB12 AA16,AA21,K20
Table 2-19. Serial Communication Interfaces – USB Signals Description
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
UNIVERSAL SERIAL BUS INTERFACE (USB0)
usb0_dp USB D+ (differential signal A F25 A6
pair)
usb0_dm USB D- (differential signal A F24 B6
pair)
usb0_drvvbus Digital output to control O E25 A7
external supply
usb0_id USB operating mode A G25 B7
identification pin
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Table 2-19. Serial Communication Interfaces – USB Signals Description (continued)
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
usb0_vbus For host or device mode A G24 C7
operation, tie the
VBUS/USB power signal
to the USB connector.
When used in OTG mode
operation, tie VBUS to the
external charge pump and
to the VBUS signal on the
USB connector.
MM_FSUSB3
mm_fsusb3_rxdm Vminus receive data (not IO AE13 M19
used in 3- or 4-pin
configurations)
mm_fsusb3_rxdp Vplus receive data (not IO AC13 L20
used in 3- or 4-pin
configurations)
mm_fsusb3_rxrcv Differential receiver signal IO A23 B3
input (not used in 3-pin
mode)
mm_fsusb3_txse0 Single-ended zero. Used IO B23 A3
as VM in 4-pin VP_VM
mode.
mm_fsusb3_txdat USB data. Used as VP in IO B22 A2
4-pin VP_VM mode.
mm_fsusb3_txen_n Transmit enable IO A22 B2
MM_FSUSB2
mm_fsusb2_rxdm Vminus receive data (not IO AD21 D20
used in 3- or 4-pin
configurations)
mm_fsusb2_rxdp Vplus receive data (not IO AB20 E20
used in 3- or 4-pin
configurations)
mm_fsusb2_rxrcv Differential receiver signal IO AC21 D19
input (not used in 3-pin
mode)
mm_fsusb2_txse0 Single-ended zero. Used IO AE22 D18
as VM in 4-pin VP_VM
mode.
mm_fsusb2_txdat USB data. Used as VP in IO AE16 J21
4-pin VP_VM mode.
mm_fsusb2_txen_n Transmit enable IO AE17 H19
MM_FSUSB1
mm_fsusb1_rxdm Vminus receive data (not IO AD20 D21
used in 3- or 4-pin
configurations)
mm_fsusb1_rxdp Vplus receive data (not IO AE18 G21
used in 3- or 4-pin
configurations)
mm_fsusb1_rxrcv Differential receiver signal IO AD18 G20
input (not used in 3-pin
mode)
mm_fsusb1_txse0 Single-ended zero. Used IO AC18 F22
as VM in 4-pin VP_VM
mode.
mm_fsusb1_txdat USB data. Used as VP in IO AB18 F20
4-pin VP_VM mode.
mm_fsusb1_txen_n Transmit enable IO AB19 E21
HSUSB2
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Table 2-19. Serial Communication Interfaces – USB Signals Description (continued)
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
hsusb2_clk Dedicated for external O AC20 E22
transceiver 60-MHz clock
input from PHY
hsusb2_stp Dedicated for external O AB20 E20
transceiver Stop signal
hsusb2_dir Dedicated for external I AE21 E18
transceiver Data direction
control from PHY
hsusb2_nxt Dedicated for external I AD21 D20
transceiver Next signal
from PHY
hsusb2_data0 Dedicated for external IO AC21 D19
transceiver Bidirectional
data bus
hsusb2_data1 Dedicated for external IO AE22 D18
transceiver Bidirectional
data bus
hsusb2_data2 Dedicated for external IO AE16 J21
transceiver Bidirectional
data bus
hsusb2_data3 Dedicated for external IO AE17 H19
transceiver Bidirectional
data bus
hsusb2_data4 Dedicated for external IO AC16 H20
transceiver Bidirectional
data bus additional signals
for 12-pin ULPI operation.
hsusb2_data5 Dedicated for external IO AB16 H22
transceiver Bidirectional
data bus additional signals
for 12-pin ULPI operation.
hsusb2_data6 Dedicated for external IO AA16 H21
transceiver Bidirectional
data bus additional signals
for 12-pin ULPI operation.
hsusb2_data7 Dedicated for external IO AD16 J22
transceiver Bidirectional
data bus
HSUSB1
hsusb1_clk Dedicated for external O AE18 G21
transceiver 60-MHz clock
input from PHY
hsusb1_stp Dedicated for external O AD17 G22
transceiver Stop signal
hsusb1_dir Dedicated for external I AE20 D22
transceiver Data direction
control from PHY
hsusb1_nxt Dedicated for external I AD20 D21
transceiver Next signal
from PHY
hsusb1_data0 Dedicated for external IO AD18 G20
transceiver Bidirectional
data bus
hsusb1_data1 Dedicated for external IO AC18 F22
transceiver Bidirectional
data bus
hsusb1_data2 Dedicated for external IO AB18 F20
transceiver Bidirectional
data bus
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Table 2-19. Serial Communication Interfaces – USB Signals Description (continued)
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
hsusb1_data3 Dedicated for external IO AB19 E21
transceiver Bidirectional
data bus
hsusb1_data4 Dedicated for external IO Y18 E19
transceiver Bidirectional
data bus additional signals
for 12-pin ULPI operation
hsusb1_data5 Dedicated for external IO AE19 F21
transceiver Bidirectional
data bus additional signals
for 12-pin ULPI operation
hsusb1_data6 Dedicated for external IO AD19 F19
transceiver Bidirectional
data bus additional signals
for 12-pin ULPI operation
hsusb1_data7 Dedicated for external IO AA18 G19
transceiver Bidirectional
data bus additional signals
for 12-pin ULPI operation
2.4.4 Removable Media Interfaces
Table 2-20. Removable Media Interfaces – MMC/SDIO Signals Description
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
MULTIMEDIA MEMORY CARD (MMC1) / SECURE DIGITAL IO (SDIO1)
mmc1_clk MMC/SD Output Clock O AA9 P22
mmc1_cmd MMC/SD command signal IO AB9 N21
mmc1_dat0 MMC/SD Card Data bit 0 / IO AC9 P21
SPI Serial Input
mmc1_dat1 MMC/SD Card Data bit 1 IO AD9 N20
mmc1_dat2 MMC/SD Card Data bit 2 IO AE9 P19
mmc1_dat3 MMC/SD Card Data bit 3 IO AA10 P20
mmc1_dat4 MMC/SD Card Data bit 4 IO AB10 N22
mmc1_dat5 MMC/SD Card Data bit 5 IO AC10 N19
mmc1_dat6 MMC/SD Card Data bit 6 IO AD10 N18
mmc1_dat7 MMC/SD Card Data bit 7 IO AE10 P18
MULTIMEDIA MEMORY CARD (MMC2) / SECURE DIGITAL IO (SDIO2)
mmc2_clk MMC/SD Output Clock O AD11 M21
mmc2_dir_dat0 Direction control for DAT0 O AB13 L18
signal case an external
transceiver used
mmc2_dir_dat1 Direction control for DAT1 O AC13 L20
and DAT3 signals case an
external transceiver used
mmc2_dir_dat2 Direction control for DAT2 O AB1 V18
signal case an external
transceiver used
mmc2_dir_dat3 Direction control for DAT4, O AB2 Y19
DAT5, DAT6, and DAT7
signals case an external
transceiver used
mmc2_clkin MMC/SD input clock I AE13 NA
mmc2_dat0 MMC/SD Card Data bit 0 IO AB12 K20
mmc2_dat1 MMC/SD Card Data bit 1 IO AC12 L19
mmc2_dat2 MMC/SD Card Data bit 2 IO AD12 M18
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Table 2-20. Removable Media Interfaces – MMC/SDIO Signals Description (continued)
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
mmc2_dat3 MMC/SD Card Data bit 3 IO AE12 K21
mmc2_dat4 MMC/SD Card Data bit 4 IO AB13 L18
mmc2_dat5 MMC/SD Card Data bit 5 IO AC13 L20
mmc2_dat6 MMC/SD Card Data bit 6 IO AD13 L21
mmc2_dat7 MMC/SD Card Data bit 7 IO AE13 M19
mmc2_dir_cmd Direction control for CMD O AD13 NA
signal case an external
transceiver is used
mmc2_cmd MMC/SD command signal IO AE11 M20
MULTIMEDIA MEMORY CARD (MMC3) / SECURE DIGITAL IO (SDIO3)
mmc3_clk MMC/SD Output Clock O AE15,AD17 J19,G22
mmc3_cmd MMC/SD command signal IO AD14,AE18 J20,G21
mmc3_dat0 MMC/SD Card Data bit 0 / IO AB13,Y18 E19,L18
SPI Serial Input
mmc3_dat1 MMC/SD Card Data bit 1 IO AC13,AE19 L20,F21
mmc3_dat2 MMC/SD Card Data bit 2 IO AD13,AD19 L21,F19
mmc3_dat3 MMC/SD Card Data bit 3 IO AE13,AA18 M19,G19
mmc3_dat4 MMC/SD Card Data bit 4 IO AD18 G20
mmc3_dat5 MMC/SD Card Data bit 5 IO AD20 D21
mmc3_dat6 MMC/SD Card Data bit 6 IO AE20 D22
mmc3_dat7 MMC/SD Card Data bit 7 IO AB19 E21
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2.4.5 Test Interfaces
Table 2-21. Test Interfaces – ETK Signals Description
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
etk_ctl ETK trace ctl O AE18 G21
etk_clk ETK trace clock O AD17 G22
etk_d0 ETK data 0 O AD18 G20
etk_d1 ETK data 1 O AC18 F22
etk_d2 ETK data 2 O AB18 F20
etk_d3 ETK data 3 O AA18 G19
etk_d4 ETK data 4 O Y18 E19
etk_d5 ETK data 5 O AE19 F21
etk_d6 ETK data 6 O AD19 F19
etk_d7 ETK data 7 O AB19 E21
etk_d8 ETK data 8 O AE20 D22
etk_d9 ETK data 9 O AD20 D21
etk_d10 ETK data 10 O AC20 E22
etk_d11 ETK data 11 O AB20 E20
etk_d12 ETK data 12 O AE21 E18
etk_d13 ETK data 13 O AD21 D20
etk_d14 ETK data 14 O AC21 D19
etk_d15 ETK data 15 O AE22 D18
Table 2-22. Test Interfaces – JTAG Signals Description
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
jtag_ntrst Test Reset I U24 D13
jtag_tck Test Clock I U25 E14
jtag_rtck ARM Clock Emulation O T21 C12
jtag_tms_tmsc Test Mode Select IO T22 A12
jtag_tdi Test Data Input I T23 B12
jtag_tdo Test Data Output O T24 D12
jtag_emu0 Test emulation 0 IO T25 E13
jtag_emu1 Test emulation 1 IO R24 E12
Table 2-23. Test Interfaces – HWDBG Signals Description
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
hw_dbg0 Debug signal 0 O AD2,AD17 G22
hw_dbg1 Debug signal 1 O AD1,AE18 G21
hw_dbg2 Debug signal 2 O AD3,AD18 G20
hw_dbg3 Debug signal 3 O AE3,AC18 F22
hw_dbg4 Debug signal 4 O AC5,AB18 F20
hw_dbg5 Debug signal 5 O AD5,AA18 G19
hw_dbg6 Debug signal 6 O Y18,AE5 E19
hw_dbg7 Debug signal 7 O Y6,AE19 F21
hw_dbg8 Debug signal 8 O Y7,AD19 F19
hw_dbg9 Debug signal 9 O AA7,AB19 E21
hw_dbg10 Debug signal 10 O AC7,AE20 D22
hw_dbg11 Debug signal 11 O AD7,AD20 D21
hw_dbg12 Debug signal 12 O AE23,AC20 E22
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Table 2-23. Test Interfaces – HWDBG Signals Description (continued)
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
hw_dbg13 Debug signal 13 O AD22,AB20 E20
hw_dbg14 Debug signal 14 O AB25,AE21 E18
hw_dbg15 Debug signal 15 O AA23,AD21 D20
hw_dbg16 Debug signal 16 O AA24,AC21 D19
hw_dbg17 Debug signal 17 O AA25,AE22 D18
2.4.6 Miscellaneous
Table 2-24. Miscellaneous – GP Timer Signals Description
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
gpt8_pwm_evt PWM or event for GP IO N4,E23,AE17 V11,C6,H19
timer 8
gpt9_pwm_evt PWM or event for GP IO M4,M2,F20,AC16 Y12,AA11,A5,H20
timer 9
gpt10_pwm_evt PWM or event for GP IO M3,M1,F19,AB16 V12,W12,B5,H22
timer 10
gpt11_pwm_evt PWM or event for GP IO N5,E24,AA16 AA12,D6,H21
timer 11
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2.4.7 General-Purpose IOs
Table 2-25. General-Purpose IOs Signals Description
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
gpio_0 General-purpose IO 0 IO Y1 AB18
gpio_1 General-purpose IO 1 IO M24 B8
gpio_2 General-purpose IO 2 IO Y4 AB19
gpio_3 General-purpose IO 3 IO AA1 AB20
gpio_4 General-purpose IO 4 IO AA2 W18
gpio_5 General-purpose IO 5 IO AA3 AA19
gpio_6 General-purpose IO 6 IO AB1 V18
gpio_7 General-purpose IO 7 IO AB2 Y19
gpio_8 General-purpose IO 8 IO AC1 W19
gpio_10 General-purpose IO 10 IO N25 E9
gpio_11 General-purpose IO 11 IO T25 E13
gpio_12 General-purpose IO 12 IO AD17 G22
gpio_13 General-purpose IO 13 IO AE18 G21
gpio_14 General-purpose IO 14 IO AD18 G20
gpio_15 General-purpose IO 15 IO AC18 F22
gpio_16 General-purpose IO 16 IO AB18 F20
gpio_17 General-purpose IO 17 IO AA18 G19
gpio_18 General-purpose IO 18 IO Y18 E19
gpio_19 General-purpose IO 19 IO AE19 F21
gpio_20 General-purpose IO 20 IO AD19 F19
gpio_21 General-purpose IO 21 IO AB19 E21
gpio_22 General-purpose IO 22 IO AE20 D22
gpio_23 General-purpose IO 23 IO AD20 D21
gpio_24 General-purpose IO 24 IO AC20 E22
gpio_25 General-purpose IO 25 IO AB20 E20
gpio_26 General-purpose IO 26 IO AE21 E18
gpio_27 General-purpose IO 27 IO AD21 D20
gpio_28 General-purpose IO 28 IO AC21 D19
gpio_29 General-purpose IO 29 IO AE22 D18
gpio_30 General-purpose IO 30 IO Y3 Y18
gpio_31 General-purpose IO 31 IO R24 E12
gpio_34 General-purpose IO 34 IO E3 W5
gpio_35 General-purpose IO 35 IO E2 Y5
gpio_36 General-purpose IO 36 IO E1 AB4
gpio_37 General-purpose IO 37 IO F7 AA5
gpio_38 General-purpose IO 38 IO F6 AB5
gpio_39 General-purpose IO 39 IO F4 AB6
gpio_40 General-purpose IO 40 IO F3 AA6
gpio_41 General-purpose IO 41 IO F2 W6
gpio_42 General-purpose IO 42 IO F1 AB7
gpio_43 General-purpose IO 43 IO G6 Y6
gpio_44 General-purpose IO 44 IO J4 W10
gpio_45 General-purpose IO 45 IO J3 AB9
gpio_46 General-purpose IO 46 IO J2 AB10
gpio_47 General-purpose IO 47 IO J1 W9
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Table 2-25. General-Purpose IOs Signals Description (continued)
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
gpio_48 General-purpose IO 48 IO K4 AA10
gpio_49 General-purpose IO 49 IO K3 Y9
gpio_50 General-purpose IO 50 IO K2 V10
gpio_51 General-purpose IO 51 IO K1 V9
gpio_52 General-purpose IO 52 IO L1 Y11
gpio_53 General-purpose IO 53 IO M4 Y12
gpio_54 General-purpose IO 54 IO M3 V12
gpio_55 General-purpose IO 55 IO M2 AA11
gpio_56 General-purpose IO 56 IO M1 W12
gpio_57 General-purpose IO 57 IO N5 AA12
gpio_58 General-purpose IO 58 IO N4 V11
gpio_59 General-purpose IO 59 IO N1 AB13
gpio_60 General-purpose IO 60 IO R4 W11
gpio_61 General-purpose IO 61 IO T1 Y15
gpio_62 General-purpose IO 62 IO T2 W14
gpio_63 General-purpose IO 63 IO T4 AA16
gpio_64 General-purpose IO 64 IO T5 Y14
gpio_65 General-purpose IO 65 IO U1 V14
gpio_66 General-purpose IO 66 IO AE23 B22
gpio_67 General-purpose IO 67 IO AD22 B21
gpio_68 General-purpose IO 68 IO AD23 B20
gpio_69 General-purpose IO 69 IO AE24 B19
gpio_70 General-purpose IO 70 IO AD24 A20
gpio_71 General-purpose IO 71 IO AD25 A19
gpio_72 General-purpose IO 72 IO AC23 A18
gpio_73 General-purpose IO 73 IO AC24 B18
gpio_74 General-purpose IO 74 IO AC25 A17
gpio_75 General-purpose IO 75 IO AB24 C18
gpio_76 General-purpose IO 76 IO AB25 D17
gpio_77 General-purpose IO 77 IO AA23 B16
gpio_78 General-purpose IO 78 IO AA24 B17
gpio_79 General-purpose IO 79 IO AA25 C17
gpio_80 General-purpose IO 80 IO Y22 C16
gpio_81 General-purpose IO 81 IO Y23 D16
gpio_82 General-purpose IO 82 IO Y24 D14
gpio_83 General-purpose IO 83 IO Y25 A16
gpio_84 General-purpose IO 84 IO W21 D15
gpio_85 General-purpose IO 85 IO W22 B15
gpio_86 General-purpose IO 86 IO W23 A15
gpio_87 General-purpose IO 87 IO W24 A14
gpio_88 General-purpose IO 88 IO W25 C13
gpio_89 General-purpose IO 89 IO V24 C15
gpio_90 General-purpose IO 90 IO V25 A13
gpio_91 General-purpose IO 91 IO U21 B13
gpio_92 General-purpose IO 92 IO U22 C14
gpio_93 General-purpose IO 93 IO U23 B14
gpio_94 General-purpose IO 94 IO AD2 AB21
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Table 2-25. General-Purpose IOs Signals Description (continued)
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
gpio_95 General-purpose IO 95 IO AD1 AA21
gpio_96 General-purpose IO 96 IO AE2 Y21
gpio_97 General-purpose IO 97 IO AD3 Y22
gpio_98 General-purpose IO 98 IO AE3 W21
gpio_99 General-purpose IO 99 I AD4 W22
gpio_100 General-purpose IO 100 I AE4 W20
gpio_101 General-purpose IO 101 IO AC5 V21
gpio_102 General-purpose IO 102 IO AD5 V19
gpio_103 General-purpose IO 103 IO AE5 V22
gpio_104 General-purpose IO 104 IO Y6 U20
gpio_105 General-purpose IO 105 IO AB6 V20
gpio_106 General-purpose IO 106 IO AC6 U19
gpio_107 General-purpose IO 107 IO AE6 U21
gpio_108 General-purpose IO 108 IO AD6 U22
gpio_109 General-purpose IO 109 IO Y7 T19
gpio_110 General-purpose IO 110 IO AA7 T20
gpio_111 General-purpose IO 111 IO AB7 T21
gpio_112 General-purpose IO 112 I AE7 R20
gpio_113 General-purpose IO 113 I AD8 R19
gpio_114 General-purpose IO 114 I AE8 R21
gpio_116 General-purpose IO 116 IO D25 E5
gpio_117 General-purpose IO 117 IO C25 D5
gpio_118 General-purpose IO 118 IO B25 C5
gpio_119 General-purpose IO 119 IO D24 E4
gpio_120 General-purpose IO 120 IO AA9 P22
gpio_121 General-purpose IO 121 IO AB9 N21
gpio_122 General-purpose IO 122 IO AC9 P21
gpio_123 General-purpose IO 123 IO AD9 N20
gpio_124 General-purpose IO 124 IO AE9 P19
gpio_125 General-purpose IO 125 IO E25, AA10 A7, P20
gpio_126 General-purpose IO 126 IO AB10, AD7 N22, T22
gpio_127 General-purpose IO 127 IO AC10 N19
gpio_128 General-purpose IO 128 IO AD10 N18
gpio_129 General-purpose IO 129 IO AE10 P18
gpio_130 General-purpose IO 130 IO V2, AD11 M21, AB15
gpio_131 General-purpose IO 131 IO V3, AE11 M20, AB16
gpio_132 General-purpose IO 132 IO AB12 K20
gpio_133 General-purpose IO 133 IO AC12 L19
gpio_134 General-purpose IO 134 IO AD12 M18
gpio_135 General-purpose IO 135 IO AE12 K21
gpio_136 General-purpose IO 136 IO AB13 L18
gpio_137 General-purpose IO 137 IO AC13 L20
gpio_138 General-purpose IO 138 IO AD13 L21
gpio_139 General-purpose IO 139 IO AE13 M19
gpio_140 General-purpose IO 140 IO B24 C4
gpio_141 General-purpose IO 141 IO C24 B4
gpio_142 General-purpose IO 142 IO A24 D4
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Table 2-25. General-Purpose IOs Signals Description (continued)
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
gpio_143 General-purpose IO 143 IO C23 A4
gpio_144 General-purpose IO 144 IO F20 A5
gpio_145 General-purpose IO 145 IO F19 B5
gpio_146 General-purpose IO 146 IO E24 D6
gpio_147 General-purpose IO 147 IO E23 C6
gpio_148 General-purpose IO 148 IO AA19 C22
gpio_149 General-purpose IO 149 IO Y19 C21
gpio_150 General-purpose IO 150 IO Y20 C19
gpio_151 General-purpose IO 151 IO W20 C20
gpio_152 General-purpose IO 152 IO B23 A3
gpio_153 General-purpose IO 153 IO A23 B3
gpio_154 General-purpose IO 154 IO B22 A2
gpio_155 General-purpose IO 155 IO A22 B2
gpio_156 General-purpose IO 156 IO R25 B11
gpio_157 General-purpose IO 157 IO P21 D11
gpio_158 General-purpose IO 158 IO P22 C10
gpio_159 General-purpose IO 159 IO P23 C9
gpio_160 General-purpose IO 160 IO P25 E11
gpio_161 General-purpose IO 161 IO P24 C11
gpio_162 General-purpose IO 162 IO N24 C8
gpio_163 General-purpose IO 163 IO N2 W15
gpio_164 General-purpose IO 164 IO N3 W13
gpio_165 General-purpose IO 165 IO P1 AA13
gpio_166 General-purpose IO 166 IO P2 Y13
gpio_167 General-purpose IO 167 IO AC7 R22
gpio_168 General-purpose IO 168 IO W1 Y17
gpio_170 General-purpose IO 170 IO L25 B9
gpio_171 General-purpose IO 171 IO AE14 K22
gpio_172 General-purpose IO 172 IO AD15 K19
gpio_173 General-purpose IO 173 IO AC15 J18
gpio_174 General-purpose IO 174 IO AB15 K18
gpio_175 General-purpose IO 175 IO AD14 J20
gpio_176 General-purpose IO 176 IO AE15 J19
gpio_177 General-purpose IO 177 IO AE16 J21
gpio_178 General-purpose IO 178 IO AD16 J22
gpio_179 General-purpose IO 179 IO AC16 H20
gpio_180 General-purpose IO 180 IO AB16 H22
gpio_181 General-purpose IO 181 IO AA16 H21
gpio_182 General-purpose IO 182 IO AE17 H19
gpio_183 General-purpose IO 183 IO W2 Y16
gpio_184 General-purpose IO 184 IO W4 W16
gpio_185 General-purpose IO 185 IO W5 W17
gpio_186 General-purpose IO 186 IO M25 E10
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2.4.8 System and Miscellaneous Terminals
Table 2-26. System and Miscellaneous Signals Description
SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
sys_32k 32-kHz clock input I K24 A8
sys_xtalin Main input clock. Oscillator input I K25 A10
sys_xtalout Output of oscillator O H25 A9
sys_altclk Alternate clock source selectable for I L25 B9
GPTIMERs (maximum 54 MHz), USB (48
MHz) , or NTSC/PAL (54 MHz)
sys_clkreq Request from device for system clock (open IO M24 B8
source type)
sys_clkout1 Configurable output clock1 O N25 E9
sys_clkout2 Configurable output clock2 O M25 E10
sys_boot0 Boot configuration mode bit 0 I Y4 AB19
sys_boot1 Boot configuration mode bit 1 I AA1 AB20
sys_boot2 Boot configuration mode bit 2 I AA2 W18
sys_boot3 Boot configuration mode bit 3 I AA3 AA19
sys_boot4 Boot configuration mode bit 4 I AB1 V18
sys_boot5 Boot configuration mode bit 5 I AB2 Y19
sys_boot6 Boot configuration mode bit 6 I AC1 W19
sys_boot7 Boot configuration mode bit 7 I AC2 AA20
sys_boot8 Boot configuration mode bit 8 I AC3 Y20
sys_nrespwron Power On Reset I Y2 AA18
sys_nreswarm Warm Boot Reset (open drain output) IOD Y3 Y18
sys_nirq External FIQ input I Y1 AB18
sys_ndmareq0 External DMA request 0 (system I M3 V12
expansion). Level (active low) or edge
(falling) selectable.
sys_ndmareq1 External DMA request 1 (system I M2,U1 AA11,V14
expansion). Level (active low) or edge
(falling) selectable.
sys_ndmareq2 External DMA request 2 (system I F1,M1 W12,AB7
expansion). Level (active low) or edge
(falling) selectable.
sys_ndmareq3 External DMA request 3 (system I G6,N5 AA12,V6
expansion). Level (active low) or edge
(falling) selectable.
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2.4.9 Power Supplies
Table 2-27. Power Supplies Description
BALL BALL
SIGNAL NAME[1] DESCRIPTION[2] (ZCN Pkg.) [4] (ZER Pkg.) [4]
V16, V15, V11,
V10, U16, U15,
U11, U10, T18,
T17, T9, T8, J8,J10, J12, J14, J16, K9, K11, K13,
R18, R17, R9, K15, L8, L10, L12, L14, M7, M9,
VDD_CORE 1.2-V core and oscillator macros power supply. R8, M18, L18, M11, M13, M15, N8, N10, N12, N14,
L9, L8, K18, P7, P9, P11, P13, P15, R8, R10,
K17, K9, K8, R12, R14
J16, J15, J11,
J10, H15, H11,
H10
AE25, AE1,
V18, V17, V14,
V13, V12, V9,
V8, U18, U17,
U14, U13, U12,
U9, U8, T14,
T13, T12, R16,
R15, R14, R13, A1, A11,A22, E6, E16, F6, F13, F15,
R12, R11, R10, F17, G5, G7, G11, G14, G16, G18,
P18, P17, P16, H6, H7, H8, H9, H10, H11, H12, H13,
P15, P14, P13, H14, H15, H16, H17, J9, J11, J13,
P12, P11, P10, J15, K8, K10, K12, K14, K16, L7, L9,
P9, P8, N18, L11, L13, L15, M1, M6, M8, M10,
VSS Core and I/O common ground. N17, N14, N13, M12, M14, M16, M22, N7, N9, N11,
N12, N9, N8, N13, N15, N17, P6, P8, P10, P12,
M17, M16, M15, P14, P16, R5, R7, R9, R11, R13,
M14, M13,M12, R15, R17, T6, T8, T10, T12, T14,
M11, M10, M9, T16, T18, U5, U7, U9, U11, U13,
M8, L17, L16, U15, U17, V6, AB1, AB12, AB22
L15, L14, L13,
L12, L11, L10,
K14, K13, K12,
J18, J17, J14,
J13, J12, J9, J8,
H14, H13, H12,
H9, A25, A1,
N23, G20, G21
VDDS_SRAM_MPU 1.8-V MPU SLDO analog power supply. AA13 L17
1.8-V Core SLDO and VDDA of BandGap analog
VDDS_SRAM_CORE_BG E17 J6
power supply.
1.2-V SRAMOUT for MPU SLDO.
CAP_VDD_SRAM_MPU For proper device operation, connect to a 1μF AA12 M17
decoupling capacitor.
1.2-V SRAMOUT for Core SLDO.
CAP_VDD_SRAM_CORE For proper device operation, connect to a 1μF E16 K6
decoupling capacitor.
VDDS_DPLL_MPU_USBH 1.8-V MPUSS DPLL and USBHOST DPLL analog AA15 K17
OST power supply.
1.8-V DPLL and HSDIVIDER/ CORE and
VDDS_DPLL_PER_CORE N20 F11
HSDIVIDER analog power supply.
VDDA_DAC 1.8-V DAC analog power supply. H21 NA
VSSA_DAC DAC analog ground. H22 NA
VDDA3P3V_USBPHY 3.3-V USB transceiver analog power supply. F23 F7
VDDA1P8V_USBPHY 1.8-V USB transceiver power supply. G22 D7
Output of the 1.2-V internal LDO.
CAP_VDDA1P2LDO_USB For proper device operation, connect a 0.22uF F22 E7
PHY capacitor between this pin and VSSA.
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Table 2-27. Power Supplies Description (continued)
BALL BALL
SIGNAL NAME[1] DESCRIPTION[2] (ZCN Pkg.) [4] (ZER Pkg.) [4]
Y16, Y15, Y13,
Y12, Y10, W16,
W15, W13,
W12,W10, W9, A21, B1,E15, E17, F12, F14, F18,
W6, V7, V6, G10, G12, G13, G8, G17, H18, J17,
U19, T20, T19,
VDDSHV 1.8/3.3-V power supply. L22, N16, P17, R16, R18, T9, T11,
T7, T6, R7, R6, T13, T17, U8, U10, U12, U14, U16,
P20, P19, N19, U18, V7, V8, V17, AA22, AB11
N7, N6, M7, M6,
M5, L19, K19,
K7, K6, K5, J7,
H18, H17
Y9, W18, U20,
R5, H16, H8, F5, F16, G9, G15, H5, K7, L6, L16,
G17, G16, G14,
VDDS 1.8-V power supply. N1, N5, N6, P5, R6, T5, T7, T15, U6,
G13, G11, G10, AA1
G8, F16, F13,
F11, F10, F8
VDDSOSC 1.8-V oscillator power supply. L20 G9
VSSOSC Oscillator ground. J25 B10
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3 Electrical Characteristics
3.1 Absolute Maximum Ratings
The following table specifies the absolute maximum ratings over the operating junction temperature range
of commercial and extended temperature devices. Stresses beyond those listed under absolute maximum
ratings may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under recommended
operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods
may affect device reliability.
Notes:
• Logic functions and parameter values are not assured out of the range specified in the recommended
operating conditions.
Table 3-1. Absolute Maximum Ratings Over Operating Junction Temperature Range
PARAMETER MIN MAX UNIT
VDD_CORE Supply voltage range for core macros -0.5 1.6 V
VDDS Second supply voltage range for 1.8-V I/O macros -0.5 2.25 V
VDDSHV Supply voltage range for 1.8/3.3V I/O macros -0.5 3.8 V
VDDS_SRAM_MPU Analog Supply voltage range for 1.8-V MPU SLDO -0.5 2.25 V
VDDS_SRAM_CORE_BG Analog Supply voltage range for 1.8-V Core SLDO and -0.5 2.25 V
VDDA of BandGap
VDDS_DPLL_MPU_USBHOST Analog power supply for 1.8-V MPUSS DPLL and -0.5 2.1 V
USBHOST DPLL
VDDS_DPLL_PER_CORE Analog power supply for 1.8-V DPLL and HSDIVIDER/ -0.5 2.1 V
CORE and HSDIVIDER
VDDA_DAC Analog Power Supply for 1.8-V DAC -0.5 2.43 V
VDDA3P3V_USBPHY Analog power supply for 3.3-V USB transceiver -0.5 3.6 V
VDDA1P8V_USBPHY Power Supply for 1.8-V USB transceiver -0.5 2.0 V
VDDSOSC Power Supply for 1.8-V oscillator -0.5 2.1 V
Oscillator input (sys_xtalin) -0.3 VDDSOSC + 0.3
VDDS 1.8-V I/O macros -0.3 VDDS + 0.3
Dual-voltage LVCMOS inputs, VDDSHV -0.3 VDDSHV + 0.3
= 1.8 V
Voltage range at
VPAD V
Dual-voltage LVCMOS inputs, VDDSHV -0.3 3.8
PAD = 3.3 V
USB VBUS pin (usb0_vbus) 5.5
USB 5V Tolerant IOs (usb0_dp, 5.25
usb0_dm, usb0_id)
HBM (human body model)(2) >1000
ESD stress
VESD V
voltage(1) CDM (charged device model)(3) >500
IIOI Current-pulse injection on each I/O pin(4) 200 mA
Iclamp Clamp current for an input or output -20 20 mA
Tstg Storage temperature range -65 150 °C
(1) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.
(2) The level listed above is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP155 states that 500V HBM
allows safe manufacturing with a standard ESD control process, and manufacturing with less than 500V HBM is possible if necessary
precautions are taken. Actual performance of the device may exceed the value listed above.
(3) The level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250V CDM allows
safe manufacturing with a standard ESD control process. Actual performance of the device may exceed the value listed above.
(4) Each device is tested with I/O pin injection of 200 mA with a stress voltage of 1.5 times maximum vdd at room temperature.
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The supply voltages and power consumption estimates are detailed in Table 3-2.
Table 3-2. Estimated Power Consumption at Ball Level
MAX
SIGNAL NAME DESCRIPTION CURRENT
(mA)
VDD_CORE 1.2-V core and oscillator macros power supply AM3517 1500 mA
AM3505 1400 mA
VDDS_SRAM_MPU 1.8-V MPU SLDO analog power supply 40 mA
VDDS_SRAM_CORE_BG 1.8-V Core SLDO and VDDA of BandGap analog power supply 40 mA
VDDS_DPLL_MPU_USBHOST 1.8-V MPUSS DPLL and USBHOST DPLL analog power supply 25 mA
VDDS_DPLL_PER_CORE 1.8-V DPLL and HSDIVIDER/ CORE and HSDIVIDER analog power supply 25 mA
VDDA_DAC 1.8-V DAC analog power supply 65 mA
VDDA3P3V_USBPHY 3.3-V USB transceiver analog power supply 10 mA
VDDA1P8V_USBPHY 1.8-V USB transceiver power supply 50 mA
VDDSHV 3.3-/1.8-V power supply 300 mA
VDDS 1.8-V power supply 200 mA
VDDSOSC 1.8-V oscillator power supply 20 mA
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3.2 Recommended Operating Conditions
All AM3517/05 modules are used under the operating conditions contained in Table 3-3.
Note: Logic functions and parameter values are not assured if the device is operated out of the range
specified in the recommended operating conditions.
Table 3-3. Recommended Operating Conditions
PARAMETER DESCRIPTION MIN NOM MAX UNIT
VDD_CORE Core and oscillator macros power supply 1.152 1.20 1.248 V
Noise (peak-peak) 24.00 mVpp
VDDS_SRAM_ MPU SRAM LDO analog power supply 1.71 1.80 1.89 V
MPU Noise (peak-peak) 50.00 mVpp
VDDS_SRAM_ Core SRAM LDO and BandGap analog power 1.71 1.80 1.89 V
CORE_BG supply
Noise (peak-peak) 50.00 mVpp
VDDS_DPLL_ MPU and USBHOST DPLL analog power supply 1.71 1.80 1.89 V
MPU_ Noise (peak-peak) 35.00 mVpp
USBHOST
VDDS_DPLL_ Peripherals and Core DPLLs analog power supply 1.71 1.80 1.89 V
PER_CORE Noise (peak-peak) 35.00 mVpp
VDDA_DAC DAC analog power supply 1.71 1.80 1.89 V
Noise (peak-peak) 30.00 mVpp
VSSA_DAC DAC analog ground 0.00 V
VDDA3P3V_ Analog power supply for 3.3-V USB transceiver 3.14 3.30 3.47 V
USBPHY Noise (peak-peak) 70.00 mVpp
VDDA1P8V_ Power Supply for 1.8-V USB transceiver 1.71 1.80 1.89 V
USBPHY Noise (peak-peak) 50.00 mVpp
VDDSHV 3.3-/1.8-V power supply 1.8 V Mode 1.71 1.80 1.89 V
3.3 V Mode 3.14 3.30 3.47 V
VDDS 1.8-V power supply 1.71 1.80 1.89 V
Tj Operating junction temperature Commercial 0 90 °C
range Temperature
Extended -40 105 °C
Temperature
Device 500 MHz ARM Clock Freq. < 90°C TJ100K hrs.
Operating Life 90 - 105 °C TJ100K
Power-On 600 MHz ARM Clock Freq. < 90°C TJ100K
Hours (POH)(1)
90 - 105 °C TJ50K(2)
(1) The POH information is provided solely for your convenience and does not extend or modify the warranty provided under TI’s standard
terms and conditions for TI semiconductor products.
(2) Maximum lifetime will be 100k Power On Hours as long as no more than 50k is greater than 90°C.
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MPU
Core
Periph1
vdd_core domain
DPLL_MPU
LDO
in 1.8 V
out 1.2 V
Dual Video DAC
SRAM2
ARRAY
SRAM 2 LDO
0 V/1.0 V/1.2 V
SRAM1
ARRAY
SRAM 1 LDO
0 V/1.0 V/1.2 V
DPLL_CORE
LDO
in 1.8 V
out 1.2 V
DPLL4
LDO
in 1.8 V
out 1.2 V
LDO3
1.0 V/1.2 V
vdds
Periph2
DPLL5
LDO
in 1.8 V
out 1.2 V
BandGap
BCK
MEM
vss
DLL/DCDL
HSDIVIDER
LDO
HSDIVIDER
LDO
cap_vdd_sram_core
tv_ref
(for capacitor)
vssa_dac
vdds_dpll_mpu_usbhost
vddshv
Device
vdd_core
vdds_dpll_per_core
vdda_dac
030-003
VDDSHV
VDDS
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The following diagram illustrates the power domains:
Figure 3-1. AM3517/05 Voltage Domains
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3.3 DC Electrical Characteristics
Table 3-4 summarizes the dc electrical characteristics.
Table 3-4. DC Electrical Characteristics
PARAMETER MIN NOM MAX UNIT
LVCMOS Pin Buffers
VIH High-level input voltage 0.65 x V
VDDSHV = 1.8 V(1) VDDSHV.
2
VDDSHV = 3.3 V(1)
sys_xtalin 0.8 x
VDDSOSC
VIL Low-level input voltage 0.35 x V
VDDSHV = 1.8 V(1) VDDSHV
0.8
VDDSHV = 3.3 V(1)
sys_xtalin 0.2 x
VDDSOSC
VOH High-level output voltage VDDSHV - V
VDDSHV = 1.8 V(1) 0.45
IOH = -2 mA
2.4
VDDSHV = 3.3 V(1)
IOH = -2 mA
VOL Low-level output voltage 0.45 V
VDDSHV = 1.8 V(1)
IOL = 2 mA
0.4
VDDSHV = 3.3 V(1)
IOL = 2 mA
IIInput current for dual voltage IO pins VI= Vss to Input pins with -9 9 µA
VDDSHV pull disabled
VI= Vss to Input pins with -310 -70
VDDSHV 100 µA pull-up
enabled
VI= Vss to Input pins with 75 270
VDDSHV 100 µA pull-down
enabled
Input current for DDR2/mDDR 1.8V IO VI= Vss to Input pins with 77 286
pins VDDSHV 100 µA pull-down
enabled
IOZ Off-state output current VO= VDDSHV Pull disabled -20 20 µA
or 0V
IOH High-level output current (dual-voltage -2 mA
LVCMOS IOs)
IOL Low-level output current (dual-voltage 2 mA
LVCMOS IOs)
tTInput transition time (rise time, tR or fall VDDSHV = 1.8 Normal mode 10 ns
time, tF evaluated between 10% and V(1) High-speed mode 3
90% at PAD) VDDSHV = 3.3 Normal mode 10
V(1) High-speed mode 3
Capacitan Input capacitance 3 pF
ce (dual-voltage LVCMOS I/Os)
Output capacitance 3 pF
(dual-voltage LVCMOS I/Os)
Complex IO Dedicated to USB : USB0_DM and USB0_DP
VIH High-level input voltage Low/Full speed 2.0 V
High speed
(2)VIL Low-level input voltage Low/Full speed 0.8 V
High speed (2)
VOH High-level output voltage Low/Full speed 2.8 VDDA3P3V_ V
USBPHY
High speed 360 440 mV
(1) These IO specifications apply to the dual-voltage IOs only and do not apply to the DDR2/mDDR interfaces. DDR2/mDDR IOs are 1.8V
IOs and adhere to the JESD79-2A standard.
(2) These parameters must adhere to the requirements defined in section 7.1.7.2 of Universal Serial Bus Specifications revision 2.0.
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Table 3-4. DC Electrical Characteristics (continued)
PARAMETER MIN NOM MAX UNIT
VOL Low-level output voltage Low/Full speed 0.0 0.3 V
High speed -10 10 mV
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3.4 Core Voltage Decoupling
For module performance, decoupling capacitors are required to suppress the switching noise generated
by high frequency and to stabilize the supply voltage. A decoupling capacitor is most effective when it is
close to the device because this minimizes the inductance of the circuit board wiring and interconnects.
Table 3-5 summarizes the power supplies decoupling characteristics.
Table 3-5. Core Voltage Decoupling Characteristics
PARAMETER MIN TYP MAX UNIT
Cvdd_core(1) 50 100 120 nF
Ccap_vdd_sram_core 100 nF
Cvdds_dpll_mpu_usbhost 100 nF
Cvdds_dpll_per_core 100 nF
Cvdda_dac 100 nF
Cvdd_sram_core 100 nF
Cvdd_sram_core_bg 100 nF
Cvdds_sram_mpu 100 nF
Cvddshv 100 nF
Cvdda3p3v_usbphy 100 nF
Cvdda1p8v_usbphy 100 nF
(1) 1 capacitor per 2 to 4 balls
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SRAM_LDO1
SRAM_LDO2
WKUP_LDO
DPLL_MPU
DPLL_CORE
vdds_dpll_mpu
_usbhost
vdds_sram_mpu
DPLL5
DPLL4
vdds_dpll_per_core
Video DAC
vdda_dac
Device
VSS
vssa_dac
Cvdds_sram_mpu
vdds_sram_core_bg
Ccap_vdd_sram_core
Cvdds_dpll_mpu_usbhost
Cvdds_dpll_per_core
Cvdda_dac
vdda_dac
vdds_dpll_per_core
vdds_dpll_mpu_usbhost
Core vdd_core
Cvdd_core
Vdd_core
030-004
MPU
BG
Cvdds_sram_core_bg
Cvdd_sram_core
cap_vdd_sram_mpu
Ccap_vdd_sram_mpu
vdd_sram_core
cap_vdd_sram
_core
vdds_sram_mpu
vdd_sram_core
vdds_sram_core_bg
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The following illustrates an example of power supply decoupling.
(1) Decoupling capacitors must be placed as closed as possible to the power ball. Choose the ground located closest to the power pin
for each decoupling capacitor. Place the decoupling capacitor Ci in a group of 1, 2, or 3 balls; the total must be equal to the
decoupling requirement. In case you interconnect powers, first insert the decoupling capacitor and then interconnect the powers.
(2) The decoupling capacitor value depends on the board characteristics.
Figure 3-2. Power Supply Decoupling
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3.5 Power-up and Power-down
This section provides the timing requirements for the AM3517/05 hardware signals.
3.5.1 Power-up Sequence
The following steps give an example of power-up sequence supported by the AM3517/05.
1. IO 1.8V supply (VDDS), Band-gap and LDO supplies (VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU)
and oscillator supply (VDDSOSC) should come up first to a stable state.
2. IO 3.3V (VDDSHV) supply should be ramped up next to a stable state.
3. Core (VDD_CORE) supply follows next to a stable state.
4. All the PLL supplies (VDDS_DPLL_PER_CORE, VDDS_DPLL_MPU_USBHOST) and 1.8 V complex
IO supplies (VDDA_DAC, VDDA1P8V_USBPHY) should be ramped up next to a stable state.
5. Finally, 3.3 V complex IO (VDDA_3P3V_USBPHY) should be ramped up.
6. sys_nrespwron must be held low at the time the power supplies are ramped up till the time the
sys_32k and sys_xtalin clocks are stable.
Note: In VDDSHV 1.8 V operation mode, VDDSHV can be grouped and powered up together with VDDS,
VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU and VDDSOSC.
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VDDS, VDDS_SRAM_CORE_BG
VDDS_SRAM_MPU
VDDSOSC
,
1.8V
VDDSHV 3.3V
1.2V
VDD_CORE
VDDS_DPLL_PER_CORE
VDDS_DPLL_MPU_USBHOST,
VDDA_DAC,
VDDA1P8V_USBPHY
1.8V
VDDA3P3V_USBPHY 3.3V
sys_nrespwron
sys_32k
sys_xtalin
,
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Figure 3-3 shows the power-up sequence.
Figure 3-3. Power-up Sequence
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3.5.2 Power-down Sequence
The AM3517/05 device proceeds with the power-down sequence shown below.
The following steps give an example of the power-down sequence supported by the AM3517/05
device.
1. Reset AM3517/05 device.
2. Stop all signals driven to AM3517/05.
3. Option 1: Power down all domains simutaneously.
4. Option 2: If all domains cannot be powered down simultaneously, follow the below sequence:
(a) Power off all complex I/O domains
(b) Power off core domain (VDD_CORE)
(c) Power off all PLL domains (VDDS_DPLL_MPU_USBHOST and VDDS_DPLL_PER_CORE)
(d) Power off all SRAM LDOs
(e) Power off all standard I/O domains (VDDS and VDDSHV)
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Microprocessor
Power IC
sys_32k
sys_altclk
sys_clkout1
Alternate Clock Source Selectable (54, 48 MHz or other [up
to 59 MHz])
To Quartz (Oscillator output) or Unconnected
From Quartz (Oscillator input), Square Clock, or Crystal
Clock Request. To Square Clock Source or from Peripherals
Oscillator
is Used
Oscillator
is Bypassed
Unconnected
Square
Clock
Source
To Peripherals (From OSC_CLK: 26 MHz, core_clk
[DPLL, up to 166 MHz], DPLL-96 MHZ or DPLL-54 MHz
outputs with a divider of 1, 2, 4, 8, or 16)
GPin
To Peripherals (From OSC_CLK: 26 MHz)
sys_clkout2
sys_xtalout
sys_xtalin
sys_clkreq
sys_xtalout
sys_xtalin
sys_clkreq
sys_xtalout
sys_xtalin
sys_clkreq
Ethernet input 50-MHz clock
rmii_50mhz_clk
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4 Clock Specifications
The AM3517/05 device has three external input clocks, a low frequency (sys_32k), a high frequency
(sys_xtalin), and an optional (sys_altclk). The AM3517/05 device has two configurable output clocks,
sys_clkout1 and sys_clkout2.
Figure 4-1 shows the interface to the external clock sources and clock outputs.
Figure 4-1. Clock Interface
The AM3517/05 device operation requires the following three input clocks:
• The 32-kHz clock can be generated using one of the following options and can be selected via the
sys_boot7 pin. See Figure 4-2.
– External: Supplied by an oscillator on the sys_32k pin.
– Internal: 32-kHz clock generation using a fixed divider on the HS system clock (26MHz).
• The system alternative clock can be used (through the sys_altclk pin) to provide alternative 48 or 54
MHz or other clock source (up to 54 MHz).
• The system clock input (26 MHz) is used to generate the main source clock of the AM3517/05 device.
It supplies the DPLLs as well as several AM3517/05 modules. The system clock input can be
connected to either:
– A crystal oscillator clock managed by sys_xtalin and sys_xtalout. In this case, the sys_clkreq is
used as an input (GPIN).
– A CMOS digital clock through the sys_xtalin pin. In this case, the sys_clkreq is used as an output to
request the external system clock.
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0
1
Sys_32k_in
32.5 kHz Fixed
Divider
/800
0
1
Latch
Sys_clk=
26 MHz
JTAG Overrides
for DFT
1
Sys_clk
PowerOn Reset
Sys_32k
Sys_xtalin
Sys_xtalout
Sys_boot7
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Figure 4-2. 32-kHz Clock Generation
The AM3517/05 outputs externally two clocks:
• sys_clkout1 can output the oscillator clock (26 MHz) at any time.
• sys_clkout2 can output the oscillator clock, core_clk, 96 MHz or 54 MHz. It can be divided by 2, 4, 8,
or 16 and its off state polarity is programmable.
4.1 Oscillator
The sys_xtalin (26 MHz) oscillator provides the primary reference clock for the device. The on-chip
oscillator requires an external crystal connected across the sys_xtalin and sys_xtalout pins, along with two
load capacitors, as shown in Figure 4-3. The external crystal load capacitors must be connected only to
the oscillator ground pin (VSSOSC). Do not connect to board ground (VSS).
Note: If an external oscillator is to be used, the external oscillator clock signal should be connected to the
sys_xtalin pin with a 1.8V amplitude. The sys_xtalout should be left unconnected and the VSSOSC signal
should be connected to board ground (VSS).
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sys_xtalin sys_xtalout VSSOSC
Crystal
26 MHz
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A. Oscillator components (Crystal, C1, C2) must be located close to the AM35x package. Parasitic capacitance to the
printed circuit board (PCB) ground and other signals should be minimized to reduce noise coupled into the oscillator.
The VSSOSC terminal provides a Kelvin ground reference for the external crystal components. External crystal
component grounds should only be connected to the VSSOSC terminal and should not be connected to the PCB
ground plane.
B. C1and C2represent the total capacitance of the respective PCB trace, load capacitor, and other components
(excluding the crystal) connected to each crystal terminal. The value of capacitors C1and C2should be selected to
provide the total load capacitance, CL, specified by the crystal manufacturer. The total load capacitance is CL=
[(C1*C2)/(C1+C2)] + Cshunt, where Cshunt is the crystal shunt capacitance (C0) specified by the crystal manufacturer
plus any mutual capacitance (Cpkg + CPCB) seen across the AM3517/05 sys_xtalin and sys_xtalout signals. For
recommended values of crystal circuit components, see Table 4-1.
Figure 4-3. AM3517/05 Oscillator Connections
Table 4-1. Crystal Electrical Characteristics
PARAMETER MIN TYP MAX UNIT
Oscillation frequency 26 MHz
Crystal ESR 50 Ω
Frequency stability +/- 50 ppm
Parallel Load Capacitance 20 pF
(C1 and C2)
Shunt Capacitance 5 pF
4.2 Input Clock Specifications
The clock system accepts three input clock sources:
• 32-kHz digital CMOS clock
• Crystal oscillator clock or CMOS digital clock (26 MHz)
• Alternate clock (48 or 54 MHz, or other up to 54 MHz)
Table 4-2. 26-MHz SYS_CLK Input Clock Timing Requirements
PARAMETER DESCRIPTION MIN TYP MAX UNIT
f(xtalin) Frequency, sys_xtalin 26 MHz
tw(xtalin) Duty Cycle, 45 55 %
sys_xtalin
tj(xtalin) Jitter, sys_xtalin -1 1 %
tt(xtalin) Transition time, 5 ns
sys_xtalin
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Table 4-3. 32-kHz Input Clock Source Electrical Characteristics
PARAMET DESCRIPTION MIN TYP MAX UNIT
ER
f Frequency, sys_32k 32.768 kHz
CiInput capacitance 0.45 pF
RiInput resistance 0.25 106GΩ
Table 4-4 details the input requirements of the 32-kHz input clock.
Table 4-4. 32-kHz Input Clock Source Timing Requirements(1)
PARAMETE DESCRIPTION MIN TYP MAX UNIT
R
1 / tc(32k) Frequency, sys_32k 32 kHz
tR(32k) Rise transition time, sys_32k 20 ns
tF(32k) Fall transition time, sys_32k 20 ns
tJ(32k) Frequency stability, sys_32k +/-200 ppm
(1) See Electrical Characteristics for Standard LVCMOS IOs part for sys_32k VIH/VIL parameters.
Table 4-5. 48-MHz, 54-MHz, or up to 59-MHz Input Clock Source Electrical Characteristics
NAME DESCRIPTION MIN MAX UNIT
f Frequency , sys_altclk 48, 54, or up to 59 MHz
CiInput capacitance 0.74 pF
RiInput resistance 0.25 106GΩ
Table 4-6 details the input requirements of the 48- or 54-MHz input clock.
Table 4-6. 48-MHz, 54-MHz, or up to 59-MHz Input Clock Source Timing Requirements(1) (2)
PARAMETER DESCRIPTION MIN MAX UNIT
1 / tc(sys_altclk) Frequency, sys_altclk 48, 54, or up to 59 MHz
tw(sys_altclk) Duty cycle 45 60 %
tj(sys_altclk) Jitter -1 1 %
tr(sys_altclk) Rise transition time 10 ns
tf(sys_altclk) Fall transition time 10 ns
ft(sys_altclk) Frequency tolerance -50 50 ppm
(1) Peak-to-peak jitter is defined as the difference between the maximum and the minimum output periods on a statistical population of 300
period samples. The sinusoidal noise is added on top of the vdds supply voltage.
(2) See Section 3,Electrical Characteristics, for sys_altclk VIH/VIL parameters.
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4.3 Output Clock Specifications
Two output clocks (pin sys_clkout1 and pin sys_clkout2) are available:
• sys_clkout1 can output the oscillator clock (26 MHz) at any time. It can be controlled by software or
externally using sys_clkreq control. When the device is in the off state, the sys_clkreq can be asserted
to enable the oscillator and activate the sys_clkout1 without waking up the device. The off state polarity
of sys_clkout1 is programmable.
• sys_clkout2 can output sys_clk (26 MHz), core_clk (core DPLL output), APLL-96 MHz, or APLL-54
MHz. It can be divided by 2, 4, 8, or 16 and its off state polarity is programmable. This output is active
only when the core domain is active.
Table 4-7 summarizes the sys_clkout1 output clock electrical characteristics.
Table 4-7. SYS_CLKOUT1 Output Clock Electrical Characteristics
NAME DESCRIPTION MIN TYP MAX UNIT
f Frequency 26 MHz
CILoad capacitance(1) f(max) = 38.4 MHz 70 pF
f(max) = 26 MHz 125
(1) The load capacitance is adapted to a frequency.
Table 4-8 details the sys_clkout1 output clock timing characteristics.
Table 4-8. SYS_CLKOUT1 Output Clock Switching Characteristics
NAME DESCRIPTION MIN TYP MAX UNIT
f 1 / CO0 Frequency 26 MHz
CO1 tw(CLKOUT1) Pulse duration, sys_clkout1 low or high 0.40 * 0.60 * ns
tc(CLKOUT1) tc(CLKOUT1)
CO2 tR(CLKOUT1) Rise time, sys_clkout1(1) 3.31 ns
CO3 tF(CLKOUT1) Fall time, sys_clkout1(1) 3.31 ns
(1) With a load capacitance of 25 pF.
Figure 4-4. SYS_CLKOUT1 System Output Clock
Table 4-9 summarizes the sys_clkout2 output clock electrical characteristics.
Table 4-9. SYS_CLKOUT2 Output Clock Electrical Characteristics
NAME DESCRIPTION MIN TYP MAX UNIT
f Frequency, sys_clkout2(1) 166 MHz
CLLoad capacitance(2) f(max) = 166 MHz 2 8 12 pF
(1) The maximum frequency supported is core_clk/2 MHz.
(2) The load capacitance is adapted to a frequency.
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Table 4-10 details the sys_clkout2 output clock timing characteristics.
Table 4-10. SYS_CLKOUT2 Output Clock Switching Characteristics
NAME DESCRIPTION MIN TYP MAX UNIT
f 1 / CO0 Frequency 166 MHz
CO1 tw(CLKOUT2) Pulse duration, sys_clkout2 low or high 0.40 * tc(CLKOUT2) 0.60 * tc(CLKOUT2) ns
CO2 tR(CLKOUT2) Rise time, sys_clkout2(1) 3.7 ns
CO3 tF(CLKOUT2) Fall time, sys_clkout2(1) 4.3 ns
(1) With a load capacitance of 25 pF.
Figure 4-5. SYS_CLKOUT2 System Output Clock
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VDDS_DPLL_MPU_USBHOST Power Rail
DPLL4
DPLL1
DPLL3
VDDS_DPLL_PER_CORE
DPLL5
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4.4 DPLL Specifications
The AM3517/05 integrates four DPLLs. The PRM and CM drive them.
The four main DPLLs are:
• DPLL1 (MPU)
• DPLL3 (Core)
• DPLL4 (Peripherals)
• DPLL5 (Second Peripherals DPLL)
Figure 4-6 illustrates the DPLL implementation.
Figure 4-6. DPLL Implementation
4.4.1 Digital Phase-Locked Loop (DPLL)
The DPLL provides all interface clocks and some functional clocks (such as the processor clocks) of the
AM3517/05 device.
DPLL1 gets an always-on clock used to produce the synthesized clock. They get a high-speed bypass
clock used to switch the DPLL output clock on this high-speed clock during bypass mode.
The high-speed bypass clock is an L3 divided clock (programmable by 1 or 2) that saves DPLL processor
power consumption when the processor does not need to run faster than the L3 clock speed, or optimizes
performance during frequency scaling.
Each DPLL synthesized frequency is set by programming M (multiplier) and N (divider) factors. In addition,
all DPLL outputs can be controlled by an independent divider (M2 to M6).
The clock generating DPLLs of the AM3517/05 device have following features:
• Independent power domain per DPLL
• Controlled by clock-manager (CM)
• Fed with always-on system clock with independent gating control per DPLL
• Analog part supplied through dedicated power supply (1.8 V) and an embedded LDO to get rid of 1-
MHz noise
• Up to four independent output dividers for simultaneous generation of multiple clock frequencies
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4.4.1.1 DPLL1 (MPU)
DPLL1 is located in the MPU subsystem and supplies all clocks of the subsystem. All MPU subsystem
clocks are internally generated in the subsystem. When the core domain is on, it can use the DPLL3
(CORE DPLL) output as a high-frequency bypass input clock.
4.4.1.2 DPLL3 (CORE)
DPLL3 supplies all interface clocks and also a few module functional clocks. It can be also source of the
emulation trace clock. It is located in the core domain area. All interface clocks and a few module
functional clocks are generated in the CM. When the core domain is on, it can be used as a bypass input
to DPLL1.
4.4.1.3 DPLL4 (Peripherals)
DPLL4 generates clocks for the peripherals. It supplies five clock sources: 96-MHz functional clocks to
subsystems and peripherals, 54 MHz to TV DAC, display functional clock, camera sensor clock, and
emulation trace clock. It is located in the core domain area. All interface clocks and few module functional
clocks are generated in the CM. Its outputs to the DSS, PER, and EMU domains are propagated with
always-on clock trees.
4.4.1.4 DPLL5 (Second peripherals DPLL)
DPLL5 supplies the 120-MHz functional clock to the CM.
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C
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4.4.2 DPLL Noise Isolation
The DPLL requires dedicated power supply pins to isolate the core analog circuit from the switching noise
generated by the core logic that can cause jitter on the clock output signal. Guard rings are added to the
cell to isolate it from substrate noise injection.
The vdd supplies are the most sensitive to noise; decoupling capacitance is recommended below the
supply rails. The maximum input noise level allowed is 30 mVPP for frequencies below 1 MHz.
Figure 4-7 illustrates an example of a noise filter.
Figure 4-7. DPLL Noise Filter
Table 4-11 specifies the noise filter requirements.
Table 4-11. DPLL Noise Filter Requirements
NAME MIN TYP MAX UNIT
Filtering capacitor 100 nF
(1) The capacitors must be inserted between power and ground as close as possible.
(2) This circuit is provided only as an example.
(3) The filter must be located as close as possible to the device.
(4) No filtering required if noise is below 10 mVPP.
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Device
DSS
tv_vref
DIN1[9:0]
vssa_dacvdda_dac
Video DAC 1
TV DCT
Video DAC 2 TVOUT
BUFFER
DIN2[9:0]
TVOUT
BUFFER
TVOUT
BUFFER
tv_vfb1
tv_out1
CBG
tv_out2
tv_vfb2
V_ref
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ROUT2
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5 Video DAC Specifications
A dual-display interface equips the AM3517/05 processor. This display subsystem provides the necessary
control signals to interface the memory frame buffer directly to the external displays (TV-set). Two (one
per channel) 10-bit current steering DACs are inserted between the DSS and the TV set to generate the
video analog signal. One of the video DACs also includes TV detection and power-down mode. Figure 5-1
illustrates the AM3517/05 DAC architecture.
Figure 5-1. Video DAC Architecture
The following paragraphs detail the 10-bit DAC interface pinout, static and dynamic specifications, and
noise requirements. The operating conditions and absolute maximum ratings are detailed in Table 5-2 and
Table 5-4.
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5.1 Interface Description
Table 5-1 summarizes the external pins of the video DAC.
Table 5-1. External Pins of 10-bit Video DAC
PIN NAME I/O DESCRIPTION
tv_out1 O TV analog output composite DAC1 video output. An external resistor is connected between this
node and tv_vfb1. The nominal value of ROUT1 is 1650 . Finally, note
that this is the output node that drives the load (75 ).
tv_out2 O TV analog output S-VIDEO DAC2 video output. An external resistor is connected between this
node and tv_vfb2. The nominal value of ROUT2 is 1650 . Finally, note
that this is the output node that drives the load (75 ).
tv_vref I Reference output voltage from internal A decoupling capacitor (CBG) needs to be connected for optimum
bandgap performance.
tv_vfb1 O Amplifier feedback node Amplifier feedback node. An external resistor is connected between
this node and tv_out1. The nominal value of ROUT1 is 1650 (1%).
tv_vfb2 O Amplifier feedback node Amplifier feedback node. An external resistor is connected between
this node and tv_out2. The nominal value of ROUT2 is 1650 (1%).
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5.2 Electrical Specifications Over Recommended Operating Conditions
(TMIN to TMAX, vdda_dac = 1.8 V, ROUT1/2 = 1650Ω, RLOAD = 75Ω, unless otherwise noted)
Table 5-2. DAC Static Electrical Specification
PARAMETER CONDITIONS/ASSUMPTIONS MIN TYP MAX UNIT
R Resolution 10 Bits
DC ACCURACY
INL(1) Integral nonlinearity 1 1 LSB
DNL(2) Differential nonlinearity 1 1 LSB
ANALOG OUTPUT
- Full-scale output voltage RLOAD = 75Ω0,7 0.88 1 V
- Output offset voltage 50 mV
- Output offset voltage drift 20 mV/C
- Gain error 17 19 % FS
RVOUT Output impedance 67.5 75 82.5
REFERENCE
VREF Reference voltage range 0.525 0.55 0.575 V
- Reference noise density 100-kHz reference noise 129
bandwidth
RSET Full-scale current adjust resistor 3700 4000 4200
PSRR Reference PSRR(3) (Up to 6 MHz) 40 dB
POWER CONSUMPTION
Ivdda-up Analog Supply Current(4) 2 channels, no load 8 mA
- Analog supply driving a 75- load 2 channels 50 mA
(RMS)
Ivdda-up (peak) Peak analog supply current: Lasts less than 1 ns 60 mA
Ivdd-up Digital supply current(5) Measured at fCLK = 54 MHz, fOUT 2 mA
= 2 MHz sine wave, vdd = 1.3 V
Ivdd-up (peak) Peak digital supply current(6) Lasts less than 1 ns 2.5 mA
Ivdda-down Analog power at power-down T = 30C, vdda = 1.8 V 1.5 mA
Ivdd-down Digital power at power-down T = 30C, vdd = 1.3 V 1 mA
(1) The INL is measured at the output of the DAC (accessible at an external pin during bypass mode).
(2) The DNL is measured at the output of the DAC (accessible at an external pin during bypass mode).
(3) Assuming a capacitor of 0.1 F at the tv_ref node.
(4) The analog supply current Ivdda is directly proportional to the full-scale output current IFS and is insensitive to fCLK
(5) The digital supply current IVDD is dependent on the digital input waveform, the DAC update rate fCLK, and the digital supply VDD.
(6) The peak digital supply current occurs at full-scale transition for duration less than 1 ns.
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(TMIN to TMAX, vdda_dac = 1.8 V, ROUT1/2 = 1650 , RLOAD = 75 , unless otherwise noted)
Table 5-3. Video DAC Dynamic Electrical Specification
PARAMETER CONDITIONS/ASSUMPTIONS MIN TYP MAX UNIT
fCLK (1) Output update rate Equal to input clock frequency 54 MHz
Clock jitter rms clock jitter required in order to assure 10- 40 ps
bit accuracy
Attenuation at 5.1 MHz Corner frequency for signal 0.1 0.5 1.5 dB
Attenuation at 54 MHz(1) Image frequency 25 30 33 dB
tST Output settling time Time from the start of the output transition to 85 ns
output within 1 LSB of final value.
tRout Output rise time Measured from 10% to 90% of full-scale 25 ns
transition
tFout Output fall time Measured from 10% to 90% of full-scale 25 ns
transition
BW Signal bandwidth 6 MHz
Differential gain(2) 1.5%
Differential phase(2) 1 deg.
SFDR Within bandwidth fCLK = 54 MHz, fOUT = 1 MHz 45 dB
SNR Signal-to-noise ratio fCLK = 54 MHz, fOUT = 1 MHz 55(3) dB
1 kHz to 6 MHz bandwidth
PSRR Power supply rejection ratio Up to 6 MHz 20(4) dB
Crosstalk Between the two video 50 40 dB
channels
(1) For internal input clock information, For more information, see the Device Display Interface Subsystem Reference Guide [literature
number SPRUFV2].
(2) The differential gain and phase value is for dc coupling. Note that there is degradation for the ac coupling.
(3) The SNR value is for dc coupling. Note that there is a 6-dB degradation for ac coupling.
(4) The PSSR value is for dc coupling. Note that there is a 10-dB degradation for ac coupling.
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OUTFS
OUT
DAC V
I
I
PSRR
D
×
=
100
%FSR
V
1
100kHz 1MHz
10
PSRR(%FSR/V)
f
Firstpoleof
DACoutputload
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5.3 Analog Supply (vdda_dac) Noise Requirements
In order to assure 10-bit accuracy of the DAC analog output, the analog supply vdda_dac has to meet the
noise requirements stated in this section.
The DAC Power Supply Rejection Ratio is defined as the relative variation of the full-scale output current
divided by the supply variation. Thus, it is expressed in percentage of Full-Scale Range (FSR) per volt of
supply variation as shown in the following equation:
Depending on frequency, the PSRR is defined in Table 5-4.
Table 5-4. Video DAC Power Supply Rejection Ratio
Supply Noise Frequency PSRR % FSR/V
0 to 100 kHz 1
> 100 kHz The rejection decreases 20 dB/dec.
Example: at 1 MHz the PSRR is 10% of FSR/V
A graphic representation is shown in Figure 5-2.
Figure 5-2. Video DAC Power Supply Rejection Ratio
To ensure that the DAC SFDR specification is met, the PSRR values and the clock jitter requirements
translate to the following limits on vdda_dac (for the Video DAC).
The maximum peak-to-peak noise on vdda (ripple) is defined in Table 5-5:
Table 5-5. Video DAC Maximum Peak-to-Peak Noise on vdda_dac
Tone Frequency Maximum Peak-to-Peak Noise on vdda_dac
0 to 100 kHz < 30 mVpp
> 100 kHz Decreases 20 dB/dec.
Example: at 1 MHz the maximum is 3 mVpp
The maximum noise spectral density (white noise) is defined in Table 5-6:
Table 5-6. Video DAC Maximum Noise Spectral Density
Supply Noise Bandwidth Maximum Supply Noise Density
0 to 100 kHz < 20 V / Hz
> 100 kHz Decreases 20 dB/dec.
Example: at 1 MHz the maximum noise density is 2 / Hz
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Because the DAC PSRR deteriorates at a rate of 20 dB/dec after 100 kHz, it is highly recommended to
have vdda_dac low pass filtered (proper decoupling) (see the illustrated application: Section 5.4,External
Component Value Choice).
5.4 External Component Value Choice
The full-scale output voltage VOUTMAX is regulated by the reference amplifier, and is set by an internal
resistor RSET. IOUTMAX can be expressed as:
IOUTMAX = IREF /8 * (63 + 15/16) (1)
Where:
VREF = 0.5V (2)
IREF = VREF/RSET (3)
The output current IOUT appearing at DAC output is a function of both the input code and IOUTMAX and can
be expressed as:
IOUT = (DAC_CODE/1023) * IOUTMAX (4)
Where:
DAC_CODE = 0 to 1023 is the DAC input code in decimal. (5)
The output voltage is:
VOUT = IOUT *N* RCABLE (6)
Where:
(N = amplifier gain = 21) (7)
RCABLEΩ(cable typical impedance) (8)
The TV-out buffer requires a per channel external resistors: ROUT1/2. The equation below can be used to
select different resistor values (if necessary):
ROUT = (N+1) RCABLE = 1650Ω(9)
Recommended parameter values are:
Table 5-7. Video DAC Recommended External Components Values
Recommended Value UNIT
CBG 100 nF
ROUT1/2 1650 Ω
In order to limit the reference noise bandwidth and to suppress transients on VREF, it is necessary to
connect a large decoupling capacitor ©BG) between the tv_vref and vssa_dac pins.
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Cycle(orPeriod)Jitter
Tn-1 TnTn+1
Max.CycleJitter=Max(T )
i
Min.CycleJitter=Min(T )
i
JitterStandardDeviation(orrmsJitter)=StandardDeviation(T )
i
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6 Timing Requirements and Switching Characteristics
Note: The timing data shown is preliminary data and is subject to change in future revisions.
6.1 Timing Test Conditions
All timing requirements and switching characteristics are valid over the recommended operating conditions
of Table 3-3, unless otherwise specified.
6.2 Interface Clock Specifications
6.2.1 Interface Clock Terminology
The Interface clock is used at the system level to sequence the data and/or control transfers accordingly
with the interface protocol.
6.2.2 Interface Clock Frequency
The two interface clock characteristics are:
• The maximum clock frequency
• The maximum operating frequency
The interface clock frequency documented in this document is the maximum clock frequency, which
corresponds to the maximum frequency programmable on this output clock. This frequency defines the
maximum limit supported by the AM3517/05 IC and doesn't take into account any system consideration
(PCB, peripherals).
The system designer will have to consider these system considerations and AM3517/05 IC timings
characteristics as well, to define properly the maximum operating frequency, which corresponds to the
maximum frequency supported to transfer the data on this interface.
6.2.3 Clock Jitter Specifications
Jitter is a phase noise, which may alter different characteristics of a clock signal. The jitter specified in this
document is the time difference between the typical cycle period and the actual cycle period affected by
noise sources on the clock. The cycle (or period) jitter terminology identifies this type of jitter.
Figure 6-1. Cycle (or Period) Jitter
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6.2.4 Clock Duty Cycle Error
The maximum duty cycle error is the difference between the absolute value of the maximum high-level
pulse duration or the maximum low-level pulse duration and the typical pulse duration value:
• Maximum pulse duration = typical pulse duration + maximum duty cycle error
• Minimum pulse duration = typical pulse duration - maximum duty cycle error
6.3 Timing Parameters
The timing parameter symbols used in the timing requirement and switching characteristic tables are
created in accordance with JEDEC Standard 100. To shorten the symbols, some pin names and other
related terminologies have been abbreviated as follows:
Table 6-1. Timing Parameters
LOWERCASE SUBSCRIPTS
Symbols Parameter
c Cycle time (period)
d Delay time
dis Disable time
en Enable time
h Hold time
su Setup time
START Start bit
t Transition time
v Valid time
w Pulse duration (width)
X Unknown, changing, or dont care level
H High
L Low
V Valid
IV Invalid
AE Active Edge
FE First Edge
LE Last Edge
Z High impedance
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6.4 External Memory Interfaces
The AM3517/05 processor includes the following external memory interfaces:
• General-purpose memory controller (GPMC)
• SDRAM controller (SDRC)
6.4.1 General-Purpose Memory Controller (GPMC)
The GPMC is the AM3517/05 unified memory controller used to interface external memory devices such
as:
• Asynchronous SRAM-like memories and ASIC devices
• Asynchronous page mode and synchronous burst NOR flash
• NAND flash
6.4.1.1 GPMC/NOR Flash Interface Synchronous Timing
The following tables assume testing over the recommended operating conditions and electrical
characteristic conditions.
Table 6-2. GPMC/NOR Flash Synchronous Mode Timing Conditions
TIMING CONDITION PARAMETER 1.8V, 3.3V UNIT
MIN MAX
Input Conditions
tRInput signal rise time 0.3 1.8 ns
tFInput signal fall time 0.3 1.8 ns
Output Conditions
CLOAD Output load capacitance 30 pF
Table 6-3. GPMC/NOR Flash Interface Timing Requirements Synchronous Mode
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
F12 tsu(DV-CLKH) Setup time, read gpmc_d[15:0] valid before 2.021 ns
gpmc_clk high
F13 th(CLKH-DV) Hold time, gpmc_d[15:0] valid after gpmc_clk high 3.403 ns
F21 tsu(WAITV-CLKH) Setup time, gpmc_waitx(1) valid before gpmc_clk 3.782 ns
high
F22 th(CLKH-WAITV) Hold Time, gpmc_waitx(1) valid after gpmc_clk 3.343 ns
high
(1) Wait monitoring support is limited to a WaitMonitoringTime value > 0.
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Table 6-4. GPMC/NOR Flash Interface Switching Characteristics Synchronous Mode
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
F0 tc(CLK) Cycle time(1), output clock gpmc_clk 10 ns
period
F1 tw(CLKH) Typical pulse duration, output clock 0.5 P(2) 0.5 P(2) ns
gpmc_clk high
F1 tw(CLKL) Typical pulse duration, output clock 0.5 P(2) 0.5 P(2) ns
gpmc_clk low
tdc(CLK) Duty cycle error, output clk gpmc_clk -500 500 ps
tj(CLK) Jitter standard deviation(3), output clock 33.30 ps
gpmc_clk
tR(CLK) Rise time, output clock gpmc_clk 1.6 ns
tF(CLK) Fall time, output clock gpmc_clk 1.6 ns
tR(DO) Rise time, output data 2 ns
tF(DO) Fall time, output data 2 ns
F2 td(CLKH-nCSV) Delay time, gpmc_clk rising edge to F(5) - 1.9 F(5) + 3.3 ns
gpmc_ncsx(4) transition
F3 td(CLKH-nCSIV) Delay time, gpmc_clk rising edge to E(6) - 1.9 E(6) + 3.3 ns
gpmc_ncsx(4) invalid
F4 td(ADDV-CLK) Delay time, address bus valid to B(7) - 4.1 B(7) + 2.1 ns
gpmc_clk first edge
F5 td(CLKH-ADDIV) Delay time, gpmc_clk rising edge to -2.103 ns
gpmc_a[16:1] invalid
F6 td(nBEV-CLK) Delay time, gpmc_nbe0_cle, gpmc_nbe1 B(7) - 1.37 B(7) + 2.1 ns
valid to gpmc_clk first edge
F7 td(CLKH-nBEIV) Delay time, gpmc_clk rising edge to D(8) - 2.1 D(8) + 1.1 ns
gpmc_nbe0_cle, gpmc_nbe1 invalid
(1) Related to the gpmc_clk output clock maximum and minimum frequencies programmable in the I/F module by setting the
GPMC_CONFIG1_CSx configuration register bit field GpmcFCLKDivider.
(2) P = gpmc_clk period
(3) The jitter probability density can be approximated by a Gaussian function.
(4) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
(5) For nCS falling edge (CS activated):
•Case GpmcFCLKDivider = 0:
• F = 0.5 * CSExtraDelay * GPMC_FCLK
•Case GpmcFCLKDivider = 1:
• F = 0.5 * CSExtraDelay * GPMC_FCLK if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are
even)
• F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK otherwise
•Case GpmcFCLKDivider = 2:
• F = 0.5 * CSExtraDelay * GPMC_FCLK if ((CSOnTime - ClkActivationTime) is a multiple of 3)
• F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)
• F = (2 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)
(6) For single read: E = (CSRdOffTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: E = (CSRdOffTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: E = (CSWrOffTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(7) B = ClkActivationTime * GPMC_FCLK
(8) For single read: D = (RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: D = (RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: D = (WrCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
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Table 6-4. GPMC/NOR Flash Interface Switching Characteristics Synchronous Mode (continued)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
F8 td(CLKH-nADV) Delay time, gpmc_clk rising edge to G(9) - 1.9 G(9) + 4.1 ns
gpmc_nadv_ale transition
F9 td(CLKH-nADVIV) Delay time, gpmc_clk rising edge to D(8) - 1.9 D(8) + 4.1 ns
gpmc_nadv_ale invalid
F10 td(CLKH-nOE) Delay time, gpmc_clk rising edge to H(10) - 2.1 H(10) + 2.1 ns
gpmc_noe transition
F11 td(CLKH-nOEIV) Delay time, gpcm rising edge to E(6) - 2.1 E(6) + 2.1 ns
gpmc_noe invalid
(9) For ADV falling edge (ADV activated):
•Case GpmcFCLKDivider = 0:
• G = 0.5 * ADVExtraDelay * GPMC_FCLK
•Case GpmcFCLKDivider = 1:
• G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime
are even)
• G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise
•Case GpmcFCLKDivider = 2:
• G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVOnTime - ClkActivationTime) is a multiple of 3)
• G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)
• G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime --ClkActivationTime - 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Reading mode:
•Case GpmcFCLKDivider = 0:
• G = 0.5 * ADVExtraDelay * GPMC_FCLK
•Case GpmcFCLKDivider = 1:
• G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and
ADVRdOffTime are even)
• G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise
• Case GpmcFCLKDivider = 2:
• G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)
• G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime --ClkActivationTime --1) is a multiple of 3)
• G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime --ClkActivationTime - 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Writing mode:
•Case GpmcFCLKDivider = 0:
• G = 0.5 * ADVExtraDelay * GPMC_FCLK
•Case GpmcFCLKDivider = 1:
• G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and
ADVWrOffTime are even)
• G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise
•Case GpmcFCLKDivider = 2:
• G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)
• G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)
• G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)
(10) For OE falling edge (OE activated) / IO DIR rising edge (Data Bus input direction):
•Case GpmcFCLKDivider = 0:
• H = 0.5 * OEExtraDelay * GPMC_FCLK
•Case GpmcFCLKDivider = 1:
• H = 0.5 * OEExtraDelay * GPMC_FCLK if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are
even)
• H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise
•Case GpmcFCLKDivider = 2:
• H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOnTime - ClkActivationTime) is a multiple of 3)
• H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)
• H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)
For OE rising edge (OE deactivated):
•GpmcFCLKDivider = 0:
• H = 0.5 * OEExtraDelay * GPMC_FCLK
•Case GpmcFCLKDivider = 1:
• H = 0.5 * OEExtraDelay * GPMC_FC if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are
even)
• H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise
•Case GpmcFCLKDivider = 2:
• H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOffTime - ClkActivationTime) is a multiple of 3)
• H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)
• H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)
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Table 6-4. GPMC/NOR Flash Interface Switching Characteristics Synchronous Mode (continued)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
F14 td(CLKH-nWE) Delay time, gpmc_clk rising edge to I(11) - 1.9 I(11) + 4.1 ns
gpmc_nwe transition
F15 td(CLKH-Data) Delay time, gpmc_clk rising edge to data J(12) - 2.1 J(12) + 1.1 ns
bus transition
F17 td(CLKH-nBE) Delay time, gpmc_clk rising edge to J(12) - 2.1 J(12) + 1.1 ns
gpmc_nbex_cle transition
F18 tW(nCSV) Pulse duration, Read A(13) ns
gpmc_ncsx(4) low Write A(13) ns
F19 tW(nBEV) Pulse duration, Read C(14) ns
gpmc_nbe0_cle, Write C(14) ns
gpmc_nbe1 low
F20 tW(nADVV) Pulse duration, Read K(15) ns
gpmc_nadv_ale low Write K(15) ns
F23 td(CLKH-IODIR) Delay time, gpmc_clk rising edge to H(10) - 2.1 H(10) + 4.1 ns
gpmc_io_dir high (IN direction)
F24 td(CLKH-IODIRIV) Delay time, gpmc_clk rising edge to M(16) - 2.1 M(16) + 4.1 ns
gpmc_io_dir low (OUT direction)
(11) For WE falling edge (WE activated):
•Case GpmcFCLKDivider = 0:
• I = 0.5 * WEExtraDelay * GPMC_FCLK
•Case GpmcFCLKDivider = 1:
• I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are
even)
• I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise
•Case GpmcFCLKDivider = 2:
• I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOnTime - ClkActivationTime) is a multiple of 3)
• I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime --ClkActivationTime - 1) is a multiple of 3)
• I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)
For WE rising edge (WE deactivated):
•Case GpmcFCLKDivider = 0:
• I = 0.5 * WEExtraDelay * GPMC_FCLK
•Case GpmcFCLKDivider = 1:
• I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are
even)
• I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise
•Case GpmcFCLKDivider = 2:
• I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOffTime - ClkActivationTime) is a multiple of 3)
• I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)
• I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)
(12) J = GPMC_FCLK period
(13) For single read: A = (CSRdOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK period
For burst read: A = (CSRdOffTime - CSOnTime + (n 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period
For burst write: A = (CSWrOffTime - CSOnTime + (n 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period
with n being the page burst access number.
(14) For single read: C = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: C = (RdCycleTime + (n 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: C = (WrCycleTime + (n 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK with n being the page
burst access number.
(15) For read: K = (ADVRdOffTime - ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For write: K = (ADVWrOffTime - ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(16) M = (RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
Above M parameter expression is given as one example of GPMC programming. IO DIR signal will go from IN to OUT after both
RdCycleTime and BusTurnAround completion. Behavior of IO direction signal does depend on kind of successive Read/Write accesses
performed to Memory and multiplexed or non-multiplexed memory addressing scheme, bus keeping feature enabled or not. IO DIR
behavior is automatically handled by GPMC controller.
Copyright © 2009–2012, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 111
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gpmc_clk
gpmc_ncsx
gpmc_a[10:1]
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nadv_ale
gpmc_noe
gpmc_d[15:0]
gpmc_waitx
gpmc_io_dir
Valid Address
D0
OUTOUT IN OUT
F0
F12
F13
F4
F6
F2
F8
F3
F7
F9
F11
F1
F1
F8
F19
F18
F20
F10
F6
F19
030-021
F23 F24
AM3517, AM3505
SPRS550D –OCTOBER 2009–REVISED MARCH 2012
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In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
Figure 6-2. GPMC/NOR Flash Synchronous Single Read (GpmcFCLKDivider = 0)
112 Timing Requirements and Switching Characteristics Copyright © 2009–2012, Texas Instruments Incorporated
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gpmc_clk
gpmc_ncsx
gpmc_a[10:1]
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nadv_ale
gpmc_noe
gpmc_d[15:0]
gpmc_waitx
gpmc_io_dir
Valid Address
D0 D1 D2 D3
OUTOUT IN OUT
F0
F12
F13 F13
F12
F4
F1
F1
F2
F6
F3
F7
F8 F8 F9
F10 F11
F21 F22
F6
F7
030-022
F23 F24
AM3517, AM3505
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
Figure 6-3. GPMC/NOR Flash Synchronous Burst Read 4x16-bit (GpmcFCLKDivider = 0)
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gpmc_clk
gpmc_ncsx
gpmc_a[10:1]
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nadv_ale
gpmc_nwe
gpmc_d[15:0]
gpmc_waitx
gpmc_io_dir
Valid Address
D0 D1 D2 D3
OUT
F4
F15 F15 F15
F1
F1
F2
F6
F8F8
F0
F14F14
F3
F17
F17
F17
F9F6
F17
F17
F17
030-023
AM3517, AM3505
SPRS550D –OCTOBER 2009–REVISED MARCH 2012
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In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
Figure 6-4. GPMC/NOR Flash Synchronous Burst Write (GpmcFCLKDivider = 0)
114 Timing Requirements and Switching Characteristics Copyright © 2009–2012, Texas Instruments Incorporated
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gpmc_clk
gpmc_ncsx
gpmc_nbe0_cle
gpmc_nbe1
gpmc_a[26:17]
gpmc_a[16:1]_d[15:0]
gpmc_nadv_ale
gpmc_noe
gpmc_waitx
gpmc_io_dir
Valid
Valid
Address(MSB)
Address(LSB) D0 D1 D2 D3
OUTOUT IN OUT
F4
F6
F4
F2
F8 F8
F10
F13
F12
F12
F11
F9
F7
F3
F0 F1
F1
F5
F6 F7
030-024
F23 F24
AM3517, AM3505
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
Figure 6-5. GPMC/Multiplexed NOR Flash Synchronous Burst Read
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gpmc_clk
gpmc_ncsx
gpmc_a[26:17]
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nadv_ale
gpmc_nwe
gpmc_d[15:0]
gpmc_waitx
gpmc_io_dir
Address(MSB)
Address(LSB) D0 D1 D2 D3
OUT
F4
F15 F15 F15
F1
F1
F2
F6
F8F8
F0
F3
F17
F17
F17
F9F6
F17
F17
F17
F14F14
030-025
AM3517, AM3505
SPRS550D –OCTOBER 2009–REVISED MARCH 2012
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In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
Figure 6-6. GPMC/Multiplexed NOR Flash Synchronous Burst Write
6.4.1.2 GPMC/NOR Flash Interface Asynchronous Timing
The following tables assume testing over the recommended operating conditions and electrical
characteristic conditions.
Table 6-5. GPMC/NOR Flash Asynchronous Mode Timing Conditions
TIMING CONDITION PARAMETER VALUE UNIT
Input Conditions
tRInput signal rise time 1.8 ns
tFInput signal fall time 1.8 ns
Output Conditions
CLOAD Output load capacitance 30 pF
Table 6-6. GPMC/NOR Flash Interface Asynchronous Timing – Internal Parameters(1) (2)
NO. PARAMETER 1.8V,3.3V UNIT
MIN MAX
FI1 Maximum output data generation delay from internal functional clock 6.5 ns
FI2 Maximum input data capture delay by internal functional clock 4 ns
FI3 Maximum device select generation delay from internal functional clock 6.5 ns
FI4 Maximum address generation delay from internal functional clock 6.5 ns
FI5 Maximum address valid generation delay from internal functional clock 6.5 ns
FI6 Maximum byte enable generation delay from internal functional clock 6.5 ns
(1) The internal parameters table must be used to calculate Data Access Time stored in the corresponding CS register bit field.
(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.
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Table 6-6. GPMC/NOR Flash Interface Asynchronous Timing – Internal Parameters(1) (2) (continued)
NO. PARAMETER 1.8V,3.3V UNIT
MIN MAX
FI7 Maximum output enable generation delay from internal functional clock 6.5 ns
FI8 Maximum write enable generation delay from internal functional clock 6.5 ns
FI9 Maximum functional clock skew 100 ps
Table 6-7. GPMC/NOR Flash Interface Timing Requirements – Asynchronous Mode
NO. PARAMETER 1.8V,3.3V UNIT
MIN MAX
FA5(1) tacc(DAT) Data maximum access time H(2) GPMC_FCLK cycles
FA20(3) tacc1-pgmode(DAT) Page mode successive data maximum P(4) GPMC_FCLK cycles
access time
FA21(5) tacc2-pgmode(DAT) Page mode first data maximum access H(2) GPMC_FCLK cycles
time
(1) The FA5 parameter illustrates the amount of time required to internally sample input Data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after FA5 functional clock cycles, input Data is internally sampled by active functional clock
edge. FA5 value must be stored inside the AccessTime register bit field.
(2) H = AccessTime * (TimeParaGranularity + 1)
(3) The FA20 parameter illustrates amount of time required to internally sample successive input Page Data. It is expressed in number of
GPMC functional clock cycles. After each access to input Page Data, next input Page Data is internally sampled by active functional
clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.
(4) P = PageBurstAccessTime * (TimeParaGranularity + 1)
(5) The FA21 parameter illustrates amount of time required to internally sample first input Page Data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, First input Page Data is internally sampled by
active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.
Table 6-8. GPMC/NOR Flash Interface Switching Characteristics – Asynchronous Mode
NO. PARAMETER 1.8V/ 3.3V UNIT
MIN MAX
tR(DO) Rise time, output data 2.0 ns
tF(DO) Fall time, output data 2.0 ns
FA0 tW(nBEV) Pulse duration, Read N(12) ns
gpmc_nbe0_cle, Write N(12) ns
gpmc_nbe1 valid time
FA1 tW(nCSV) Pulse duration, Read A(1) ns
gpmc_ncsx(13) v low Write A(1) ns
FA3 td(nCSV-nADVIV) Delay time, Read B(2) – 0.2 B(2) + 2.0 ns
gpmc_ncsx(13) valid to Write B(2) – 0.2 B(2) + 2.0 ns
gpmc_nadv_ale invalid
FA4 td(nCSV-nOEIV) Delay time, gpmc_ncsx(13) valid to C(3) – 0.2 C(3) + 2.0 ns
gpmc_noe invalid (Single read)
FA9 td(AV-nCSV) Delay time, address bus valid to J(9) – 0.2 J(9) + 2.0 ns
gpmc_ncsx(13) valid
FA10 td(nBEV-nCSV) Delay time, gpmc_nbe0_cle, J(9) – 0.2 J(9) + 2.0 ns
gpmc_nbe1 valid to gpmc_ncsx(13)
valid
FA12 td(nCSV-nADVV) Delay time, gpmc_ncsx(13) valid to K(10) – 0.2 K(10) + 2.0 ns
gpmc_nadv_ale valid
FA13 td(nCSV-nOEV) Delay time, gpmc_ncsx(13) valid to L(11) – 0.2 L(11) + 2.0 ns
gpmc_noe valid
FA14 td(nCSV-IODIR) Delay time, gpmc_ncsx(13) valid to L(11) – 0.2 L(11) + 2.0 ns
gpmc_io_dir high
FA15 td(nCSV-IODIR) Delay time, gpmc_ncsx(13) valid to M(14) – 0.2 M(14) + 2.0 ns
gpmc_io_dir low
FA16 tw(AIV) Address invalid duration between 2 G(7) ns
successive R/W accesses
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Table 6-8. GPMC/NOR Flash Interface Switching Characteristics – Asynchronous Mode (continued)
NO. PARAMETER 1.8V/ 3.3V UNIT
MIN MAX
FA18 td(nCSV-nOEIV) Delay time, gpmc_ncsx(13) valid to I(8) – 0.2 I(8) + 2.0 ns
gpmc_noe invalid (Burst read)
FA20 tw(AV) Pulse duration, address valid – 2nd, 3rd, D(4) ns
and 4th accesses
FA25 td(nCSV-nWEV) Delay time, gpmc_ncsx(13) valid to E(5) – 0.2 E(5) + 2.0 ns
gpmc_nwe valid
FA27 td(nCSV-nWEIV) Delay time, gpmc_ncsx(13) valid to F(6) – 0.2 F(6) + 2.0 ns
gpmc_nwe invalid
FA28 td(nWEV-DV) Delay time, gpmc_ new valid to data bus 2.0 ns
valid
FA29 td(DV-nCSV) Delay time, data bus valid to J(9) – 0.2 J(9) + 2.0 ns
gpmc_ncsx(13) valid
FA37 td(nOEV-AIV) Delay time, gpmc_noe valid to 2.0 ns
gpmc_a[16:1]_d[15:0] address phase
end
(1) For single read: A = (CSRdOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For single write: A = (CSWrOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: A = (CSRdOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: A = (CSWrOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK with n
being the page burst access number
(2) For reading: B = ((ADVRdOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK
For writing: B = ((ADVWrOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK
(3) C = ((OEOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK
(4) D = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK
(5) E = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK
(6) F = ((WEOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK
(7) G = Cycle2CycleDelay * GPMC_FCLK
(8) I = ((OEOffTime + (n – 1) * PageBurstAccessTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) *
GPMC_FCLK
(9) J = (CSOnTime * (TimeParaGranularity + 1) + 0.5 * CSExtraDelay) * GPMC_FCLK
(10) K = ((ADVOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK
(11) L = ((OEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK
(12) For single read: N = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
For single write: N = WrCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: N = (RdCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: N = (WrCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(13) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.
(14) M = ((RdCycleTime - CSOnTime) * (TimeParaGranularity + 1) - 0.5 * CSExtraDelay) * GPMC_FCLK
Above M parameter expression is given as one example of GPMC programming. IO DIR signal will go from IN to OUT after both
RdCycleTime and BusTurnAround completion. Behavior of IO direction signal does depend on kind of successive Read/Write accesses
performed to Memory and multiplexed or non-multiplexed memory addressing scheme, bus keeping feature enabled or not. IO DIR
behavior is automatically handled by GPMC controller.
118 Timing Requirements and Switching Characteristics Copyright © 2009–2012, Texas Instruments Incorporated
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GPMC_FCLK
gpmc_clk
gpmc_ncsx
gpmc_a[10:1]
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nadv_ale
gpmc_noe
gpmc_d[15:0]
gpmc_waitx
gpmc_io_dir
Valid Address
Valid
Valid
DataIN0 DataIN0
OUTOUT IN OUT
FA0
FA9
FA10
FA3
FA1
FA4
FA12
FA13
FA0
FA10
FA5
030-026
FA15
FA14
AM3517, AM3505
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
Figure 6-7. GPMC/NOR Flash – Asynchronous Read – Single Word Timing(1) (2) (3)
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge.
FA5 value must be stored inside AccessTime register bit field.
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Copyright © 2009–2012, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 119
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GPMC_FCLK
gpmc_clk
gpmc_ncsx
gpmc_a[10:1]
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nadv_ale
gpmc_noe
gpmc_d[15:0]
gpmc_waitx
gpmc_io_dir
Address0 Address1
Valid Valid
Valid Valid
DataUpper
OUTOUT IN OUT IN
FA9
FA10
FA3
FA9
FA3
FA13 FA13
FA1 FA1
FA4 FA4
FA12 FA12
FA10
FA0 FA0
FA16
FA0 FA0
FA10 FA10
FA5 FA5
030-027
FA15 FA15
FA14
FA14
AM3517, AM3505
SPRS550D –OCTOBER 2009–REVISED MARCH 2012
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Figure 6-8. GPMC/NOR Flash – Asynchronous Read – 32-bit Timing(1) (2) (3)
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge.
FA5 value must be stored inside AccessTime register bit field.
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
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GPMC_FCLK
gpmc_clk
gpmc_ncsx
gpmc_a[10:1]
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nadv_ale
gpmc_noe
gpmc_d[15:0]
gpmc_waitx
gpmc_io_dir
Add0 Add1 Add2 Add3 Add4
D0 D1 D2 D3 D3
OUT IN OUT
FA1
FA0
FA18
FA13
FA12
FA0
FA9
FA10
FA10
FA21 FA20 FA20 FA20
030-028
FA15
FA14
AM3517, AM3505
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Figure 6-9. GPMC/NOR Flash – Asynchronous Read – Page Mode 4x16-bit Timing(1) (2) (3) (4)
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
(2) FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by
active functional clock edge. FA21 value must be stored inside AccessTime register bit field.
(3) FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC
functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock edge
after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first input
page data). FA20 value must be stored in PageBurstAccessTime register bit field.
(4) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Copyright © 2009–2012, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 121
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gpmc_fclk
gpmc_clk
gpmc_ncsx
gpmc_a[10:1]
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nadv_ale
gpmc_nwe
gpmc_d[15:0]
gpmc_waitx
gpmc_io_dir
Valid Address
DataOUT
OUT
FA0
FA1
FA10
FA3
FA25
FA29
FA9
FA12
FA27
FA0
FA10
030-029
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In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
Figure 6-10. GPMC/NOR Flash – Asynchronous Write – Single Word Timing
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GPMC_FCLK
gpmc_clk
gpmc_ncsx
gpmc_a[26:17]
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nadv_ale
gpmc_noe
gpmc_a[16:1]_d[15:0]
gpmc_io_dir
gpmc_waitx
Address(MSB)
Valid
Valid
Address(LSB) DataIN DataIN
OUT IN OUT
FA0
FA9
FA10
FA3
FA13
FA29
FA1
FA37
FA12
FA4
FA10
FA0
FA5
030-030
FA15
FA14
AM3517, AM3505
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
Figure 6-11. GPMC/Multiplexed NOR Flash – Asynchronous Read – Single Word Timing(1) (2) (3)
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge.
FA5 value must be stored inside AccessTime register bit field.
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Copyright © 2009–2012, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 123
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gpmc_fclk
gpmc_clk
gpmc_ncsx
gpmc_a[26:17]
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nadv_ale
gpmc_nwe
gpmc_a[16:1]_d[15:0]
gpmc_waitx
gpmc_io_dir
Address(MSB)
Valid Address(LSB) DataOUT
OUT
FA0
FA1
FA9
FA10
FA3
FA25
FA29
FA12
FA27
FA28
FA0
FA10
030-031
AM3517, AM3505
SPRS550D –OCTOBER 2009–REVISED MARCH 2012
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In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
Figure 6-12. GPMC/Multiplexed NOR Flash – Asynchronous Write – Single Word Timing
6.4.1.3 GPMC/NAND Flash Interface Timing
The following tables assume testing over the recommended operating conditions and electrical
characteristic conditions.
Table 6-9. GPMC/NAND Flash Asynchronous Mode Timing Conditions
TIMING CONDITION PARAMETER 1.8V, 3.3V UNIT
MIN MAX
Input Conditions
tRInput signal rise time 1.8 ns
tFInput signal fall time 1.8 ns
CLOAD Output load capacitance 30 pF
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Table 6-10. GPMC/NAND Flash Interface Asynchronous Timing Internal Parameters(1) (2)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
GNFI1 Maximum output data generation delay from internal functional clock 6.5 ns
GNFI2 Maximum input data capture delay by internal functional clock 4 ns
GNFI3 Maximum device select generation delay from internal functional clock 6.5 ns
GNFI4 Maximum address latch enable generation delay from internal functional 6.5 ns
clock
GNFI5 Maximum command latch enable generation delay from internal 6.5 ns
functional clock
GNFI6 Maximum output enable generation delay from internal functional clock 6.5 ns
GNFI7 Maximum write enable generation delay from internal functional clock 6.5 ns
GNFI8 Maximum functional clock skew 100 ps
(1) Internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.
(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.
Table 6-11. GPMC/NAND Flash Interface Timing Requirements
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
GNF12(1) tacc(DAT) Data maximum access time J(2) GPMC_FCLK cycles
(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the
active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.
(2) J = AccessTime * (TimeParaGranularity + 1)
Table 6-12. GPMC/NAND Flash Interface Switching Characteristics
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
tR(DO) Rise time, output data 2.0 ns
tF(DO) Fall time, output data 2.0 ns
GNF0 tw(nWEV) Pulse duration, gpmc_nwe A(1) ns
valid time
GNF1 td(nCSV-nWEV) Delay time, gpmc_ncsx(13) B(2) - 0.2 B(2) + 2.0 ns
valid to gpmc_nwe valid
GNF2 tw(CLEH-nWEV) Delay time, gpmc_nbe0_cle C(3) - 0.2 C(3) + 2.0 ns
high to gpmc_nwe valid
GNF3 tw(nWEV-DV) Delay time, gpmc_d[15:0] D(4) - 0.2 D(4) + 2.0 ns
valid to gpmc_nwe valid
GNF4 tw(nWEIV-DIV) Delay time, gpmc_nwe invalid E(5) - 0.2 E(5) + 2.0 ns
to gpmc_d[15:0] invalid
GNF5 tw(nWEIV-CLEIV) Delay time, gpmc_nwe invalid F(6) - 0.2 F(6) + 2.0 ns
to gpmc_nbe0_cle invalid
GNF6 tw(nWEIV-nCSIV) Delay time, gpmc_nwe invalid G(7) - 0.2 G(7) + 2.0 ns
to gpmc_ncsx(13) invalid
GNF7 tw(ALEH-nWEV) Delay time, gpmc_nadv_ale C(3) - 0.2 C(3) + 2.0 ns
High to gpmc_nwe valid
GNF8 tw(nWEIV-ALEIV) Delay time, gpmc_nwe invalid F(6) - 0.2 F(6) + 2.0 ns
to gpmc_nadv_ale invalid
GNF9 tc(nWE) Cycle time, Write cycle time H(8) ns
GNF10 td(nCSV-nOEV) Delay time, gpmc_ncsx(13) I(9) - 0.2 I(9) + 2.0 ns
valid to gpmc_noe valid
GNF13 tw(nOEV) Pulse duration, gpmc_noe K(10) ns
valid time
GN F14 tc(nOE) Cycle time, Read cycle time L(11) ns
Copyright © 2009–2012, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 125
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GPMC_FCLK
gpmc_ncsx
gpmc_nbe0_cle
gpmc_nadv_ale
gpmc_noe
gpmc_nwe
gpmc_a[16:1]_d[15:0] Command
GNF0
GNF1
GNF2
GNF3 GNF4
GNF5
GNF6
030-032
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Table 6-12. GPMC/NAND Flash Interface Switching Characteristics (continued)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
GNF15 tw(nOEIV-nCSIV) Delay time, gpmc_noe invalid M(12) - 0.2 M(12) + 2.0 ns
to gpmc_ncsx(13) invalid
(1) A = (WEOffTime – WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(2) B = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK
(3) C = ((WEOnTime – ADVOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – ADVExtraDelay)) * GPMC_FCLK
(4) D = (WEOnTime * (TimeParaGranularity + 1) + 0.5 * WEExtraDelay ) * GPMC_FCLK
(5) E = (WrCycleTime – WEOffTime * (TimeParaGranularity + 1) – 0.5 * WEExtraDelay ) * GPMC_FCLK
(6) F = (ADVWrOffTime – WEOffTime * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – WEExtraDelay ) * GPMC_FCLK
(7) G = (CSWrOffTime – WEOffTime * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – WEExtraDelay ) * GPMC_FCLK
(8) H = WrCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK
(9) I = ((OEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK
(10) K = (OEOffTime – OEOnTime) * (1 + TimeParaGranularity) * GPMC_FCLK
(11) L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK
(12) M = (CSRdOffTime – OEOffTime * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – OEExtraDelay ) * GPMC_FCLK
(13) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.
Figure 6-13. GPMC/NAND Flash – Command Latch Cycle Timing
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GPMC_FCLK
gpmc_ncsx
gpmc_nbe0_cle
gpmc_nadv_ale
gpmc_noe
gpmc_nwe
gpmc_a[16:1]_d[15:0] Address
GNF0
GNF1
GNF7
GNF3 GNF4
GNF6
GNF8
GNF9
030-033
GPMC_FCLK
gpmc_ncsx
gpmc_nbe0_cle
gpmc_nadv_ale
gpmc_noe
gpmc_a[16:1]_d[15:0]
gpmc_waitx
DATA
GNF10
GNF13
GNF14
GNF15
GNF12
030-034
AM3517, AM3505
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.
Figure 6-14. GPMC/NAND Flash – Address Latch Cycle Timing
Figure 6-15. GPMC/NAND Flash – Data Read Cycle Timing(1) (2) (3)
(1) The GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data is internally sampled by active functional clock
edge. The GNF12 value must be stored inside AccessTime register bit field.
(2) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
(3) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0 ,1, 2, or 3.
Copyright © 2009–2012, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 127
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GPMC_FCLK
gpmc_ncsx
gpmc_nbe0_cle
gpmc_nadv_ale
gpmc_noe
gpmc_nwe
gpmc_a[16:1]_d[15:0] DATA
GNF0
GNF1
GNF4
GNF6
GNF9
GNF3
030-035
AM3517, AM3505
SPRS550D –OCTOBER 2009–REVISED MARCH 2012
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In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0 or 1.
Figure 6-16. GPMC/NAND Flash – Data Write Cycle Timing
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6.4.2 SDRAM Controller (SDRC)
The SDRC is a dedicated interface to DDR2/LPDDR1 SDRAM that performs the following functions:
• Buffering of input image data from sensors or video sources
• Intermediate buffering for processing/resizing of image data in the VPFE
• Numerous OSD display buffers
• Intermediate buffering for large raw Bayer data image files while performing image processing
functions
• Buffering for intermediate data while performing video encode and decode functions
• Storage of executable code for the ARM
The main features of the controller are:
• Open Core Protocol 2.2 (OCP) compliant [7].
• Supports JEDEC standard compliant DDR2 [2] and LPDDR1 [4] devices.
– SDRAM address range over 2 chip selects.
– Supports following data bus widths:
OCP Data Bus Width SDRAM Data Bus Width
64 and 128-Bit 16, 32, and 64-Bit
– Supports following CAS latencies:
SDRAM Type CAS Latencies
DDR2 2, 3, 4, 5, and 6
LPDDR1 2 and 3
– Supports following number of internal banks:
SDRAM Type Internal Banks
DDR2 1, 2, 4, and 8
LPDDR1 1, 2, and 4
– Supports 256, 512, 1024, and 2048-word page sizes.
– Supports following burst lengths:
SDRAM Type Burst Length
DDR2 8 (4 not supported)
LPDDR1 8 (2 and 4 not supported)
– Supports sequential burst type.
– SDRAM auto initialization from reset or configuration change.
– Supports Bank Interleaving across both the chip selects.
– Supports Clock Stop mode for LPDDR1 for low power.
– Supports Self Refresh and Precharge Power-Down modes for low power.
– Supports Partial Array Self Refresh and Temperature Controlled Self Refresh modes for low power
in LPDDR1.
– Temperature Controlled Self Refresh is only supported for mobile SDRAM having on-chip
temperature sensor.
– Supports ODT on DDR2.
– Supports prioritized refresh.
– Programmable SDRAM refresh rate and backlog counter.
– Programmable SDRAM timing parameters.
– Supports only little endian.
Copyright © 2009–2012, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 129
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sdrc_d0
sdrc_d7
sdrc_dm0
sdrc_dqs0p
sdrc_d8
sdrc_d15
sdrc_dm1
sdrc_dqs1p
sdrc_d16
sdrc_d23
sdrc_dm2
sdrc_dqs2p
sdrc_d24
sdrc_d31
sdrc_dm3
sdrc_dqs3p
sdrc_ba0
sdrc_ba1
sdrc_a0
sdrc_a14
sdrc_ncs0
sdrc_ncas
sdrc_nras
sdrc_nwe
sdrc_cke0
sdrc_clk
sdrc_nclk
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
DQ0
DQ7
LDM
LDQS
DQ8
DQ15
UDM
UDQS
BA0
BA1
A0
A14
CS
CAS
RAS
WE
CKE
CK
CK
BA0
BA1
A0
A14
CS
CAS
RAS
WE
CKE
CK
CK
T
T
T
T
T
T
T
T
LPDDR
Microprocessor
DQ0
DQ7
LDM
LDQS
DQ8
DQ15
UDM
UDQS
LPDDR
AM3517, AM3505
SPRS550D –OCTOBER 2009–REVISED MARCH 2012
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6.4.2.1 LPDDR Interface
This section provides the timing specification for the LPDDR interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. These rules, when followed, result in a reliable LPDDR memory system without the
need for a complex timing closure process. For more information regarding guidelines for using this
LPDDR specification, see the Understanding TI's PCB Routing Rule-Based DDR Timing Specification
Application Report (literature number SPRAAV0).
6.4.2.1.1 LPDDR Interface Schematic
Figure 6-17 and Figure 6-18 show the LPDDR interface schematics for a LPDDR memory system. The 1
x16 LPDDR system schematic is identical to Figure 6-17 except that the high word LPDDR device is
deleted.
Figure 6-17. AM3517/05 LPDDR High Level Schematic (x16 memories)
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sdrc_d0
sdrc_d7
sdrc_dm0
sdrc_dqs0
sdrc_d8
sdrc_d15
sdrc_dm1
sdrc_dqs1
sdrc_d16
sdrc_d23
sdrc_dm2
sdrc_dqs2
sdrc_d24
sdrc_d31
sdrc_dm3
sdrc_dqs3
sdrc_ba0
sdrc_ba1
sdrc_a0
sdrc_a14
sdrc_ncs0
sdrc_ncas
sdrc_nras
sdrc_nwe
sdrc_cke0
sdrc_clk
sdrc_nclk
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
BA0
BA1
A0
A14
CS
CAS
RAS
WE
CKE
CK
CK
T
T
T
T
T
T
T
T
Microprocessor
DQ0
DQ7
DM0
DQS0
DQ8
DQ15
DM1
DQS1
LPDDR
DQ16
DQ23
DM2
DQS2
DQ24
DQ31
DM3
DQS3
N/C
N/C
sdrc_ncs1
sdrc_cke1
AM3517, AM3505
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
Figure 6-18. AM3517/05 LPDDR High Level Schematic (x32 memory)
6.4.2.1.2 Compatible JEDEC LPDDR Devices
Table 6-13 shows the parameters of the JEDEC LPDDR devices that are compatible with this interface.
Generally, the LPDDR interface is compatible with x16 and x32 LPDDR333 speed grade LPDDR devices.
Table 6-13. Compatible JEDEC LPDDR Devices
NO. PARAMETER MIN MAX UNIT NOTES
JEDEC LPDDR Device Speed
1 LPDDR333 See Note (1)
Grade
2 JEDEC LPDDR Device Bit Width 16 32 Bits
3 JEDEC LPDDR Device Count 1 2 Devices See Note (2)
JEDEC LPDDR Device Ball
4 60 90 Balls
Count
(1) Higher LPDDR speed grades operating at the specified speeds are supported due to inherent JEDEC LPDDR backwards compatibility.
(2) 1 x16 LPDDR device is used for 16 bit LPDDR memory system. 1x32 or 2x16 LPDDR devices are used for a 32-bit LPDDR memory
system.
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6.4.2.1.3 PCB Stackup
The minimum stackup required for routing the microprocessor is a six layer stack as shown in Table 6-14.
Additional layers may be added to the PCB stack up to accommodate other circuity or to reduce the size
of the PCB footprint.
Table 6-14. Minimum PCB Stack Up
LAYER TYPE DESCRIPTION
1 Signal Top Routing Mostly Horizontal
2 Plane Ground
3 Plane Power
4 Signal Internal Routing
5 Plane Ground
6 Signal Bottom Routing Mostly Vertical
Table 6-15. PCB Stack Up Specifications
NO. PARAMETER MIN TYP MAX UNIT NOTES
1 PCB Routing/Plane Layers 6
2 Signal Routing Layers 3
3 Full ground layers under LPDDR routing region 2
4 Number of ground plane cuts allowed within LPDDR routing region 0
Number of ground reference planes required for each LPDDR routing 1
5 1
layer
Number of layers between LPDDR routing layer and reference ground 0
6 0
plane
7 PCB Routing Feature Size 4 Mils
8 PCB Trace Width w 4 Mils
9 PCB BGA escape via pad size 18 Mils
10 PCB BGA escape via hole size 8 Mils
11 Device BGA Pad Size See Note(1)
12 LPDDR Device BGA Pad Size See Note(2)
13 Single Ended Impedance, ZO 50 75 Ω
14 Impedance Control Z-5 Z Z + 5 ΩSee Note(3)
(1) Please see the Flip Chip Ball Grid Array Package Reference Guide (literature number SPRU811) for device BGA pad size.
(2) Please see the LPDDR device manufacturer documentation for the LPDDR device BGA pad size.
(3) Z is the nominal singled ended impedance selected for the PCB specified by item 12.
6.4.2.1.4 Placement
Figure 6-19 shows the required placement for the microprocessor as well as the LPDDR devices. The
dimensions for Figure 6-19 are defined in Table 6-16. The placement does not restrict the side of the PCB
that the devices are mounted on. The ultimate purpose of the placement is to limit the maximum trace
lengths and allow for proper routing space. For 1x16 and 1x32 LPDDR memory systems, the second
LPDDR device is omitted from the placement.
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Y
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Figure 6-19. AM3517/05 and LPDDR Device Placement
Table 6-16. Placement Specifications
NO. PARAMETER MIN MAX UNIT NOTES
1 X 1440 Mils See Notes(1),(2)
2 Y 1030 Mils See Notes(1),(2)
3 Y Offset 525 Mils See Notes(1),(2),(3)
4 LPDDR Keepout Region See Note(4)
Clearance from non-LPDDR signal to LPDDR
5 4 w See Note(5)
Keepout Region
(1) See Figure 6-19 for dimension definitions.
(2) Measurements from center of device to center of LPDDR device.
(3) For 16 bit memory systems it is recommended that Y Offset be as small as possible.
(4) LPDDR keepout region to encompass entire LPDDR routing area.
(5) Non-LPDDR signals allowed within LPDDR keepout region provided they are separated from LPDDR routing layers by a ground plane.
6.4.2.1.5 LPDDR Keep Out Region
The region of the PCB used for the LPDDR circuitry must be isolated from other signals. The LPDDR
keep out region is defined for this purpose and is shown in Figure 6-20. The size of this region varies with
the placement and LPDDR routing. Additional clearances required for the keep out region are shown in
Table 6-16.
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A1
LPDDRController
LPDDRDevice
RegionshouldencompassallLPDDRcircuitryandvariesdepending
onplacement.Non-LPDDRsignalsshouldnotberoutedonthe
LPDDRsignallayerswithintheLPDDRkeepoutregion.Non-LPDDR
signalsmayberoutedintheregionprovidedtheyareroutedon
layersseparatedfromLPDDRsignallayersbyagroundlayer.No
breaksshouldbeallowedinthereferencegroundlayersinthis
region.Inaddition,the1.8Vpowerplaneshouldcovertheentirekeep
outregion.
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Figure 6-20. LPDDR Keepout Region
6.4.2.1.6 Net Classes
Table 6-17 lists the clock net classes for the LPDDR interface. Table 6-18 lists the signal net classes, and
associated clock net classes, for the signals in the LPDDR interface. These net classes are used for the
termination and routing rules that follow.
Table 6-17. Clock Net Class Definitions
CLOCK NET CLASS PIN NAMES
CK sdrc_clk/sdrc_nclk
DQS0 sdrc_dqs0
DQS1 sdrc_dqs1
DQS2 sdrc_dqs2
DQS3 sdrc_dqs3
Table 6-18. Signal Net Class Definitions
CLOCK NET CLASS ASSOCIATED CLOCK NET CLASS PIN NAMES
sdrc_ba, sdrc_a, sdrc_ncs0, sdrc_ncas,
ADDR_CTRL CK sdrc_nras, sdrc_nwe, sdrc_cke0
DQ0 DQS0 sdrc_d, sdrc_dm0
DQ1 DQS1 sdrc_d, sdrc_dm1
DQ2 DQS2 sdrc_d, sdrc_dm2
DQ3 DQS3 sdrc_d, sdrc_dm3
6.4.2.1.7 LPDDR Signal Termination
No terminations of any kind are required in order to meet signal integrity and overshoot requirements.
Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only
type permitted. Table 6-19 shows the specifications for the series terminators.
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A
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Table 6-19. LPDDR Signal Terminations
NO. PARAMETER MIN TYP MAX UNIT NOTES
1 CK Net Class 0 10 ΩSee Note(1)
2 ADDR_CTRL Net Class 0 22 Zo ΩSee Notes(1),(2),(3)
Data Byte Net Classes
3 0 22 Zo ΩSee Notes(1),(2),(3)
(DQS0-DQS3, DQ0-DQ3)
(1) Only series termination is permitted, parallel or SST specifically disallowed.
(2) Terminator values larger than typical only recommended to address EMI issues.
(3) Termination value should be uniform across net class.
6.4.2.1.8 LPDDR CK and ADDR_CTRL Routing
Figure 6-21 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a
balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A
should be maximized.
Figure 6-21. CK and ADDR_CTRL Routing and Topology
Table 6-20. CK and ADDR_CTRL Routing Specification
NO. PARAMETER MIN TYP MAX UNIT NOTES
1 Center to Center CK-CK spacing 2w
2 CK A to B/A to C Skew Length Mismatch 25 Mils See Note(1)
3 CK B to C Skew Length Mismatch 25 Mils
Center to Center CK to other
4 4w See Note(2)
LPDDR trace spacing
5 CK/ADDR_CTRL nominal trace length CACLM-50 CACLM CACLM+50 Mils See Note(3)
6 ADDR_CTRL to CK Skew Length Mismatch 100 Mils
ADDR_CTRL to ADDR_CTRL
7 100 Mils
Skew Length Mismatch
Center to Center ADDR_CTRL to other
8 4w See Note(2)
LPDDR trace 4w spacing
Center to Center ADDR_CTRL to other
9 3w See Note(2)
ADDR_CTRL 3w trace spacing
ADDR_CTRL A to B/A to C Skew Length
10 100 Mils See Note(1)
Mismatch
11 ADDR_CTRL B to C Skew Length Mismatch 100 Mils
(1) Series terminator, if used, should be located closest to device.
(2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(3) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.
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E0
T
E1
T
E2
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E3
T
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T
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Figure 6-22 shows the topology and routing for the DQS and DQ net classes; the routes are point to point.
Skew matching across bytes is not needed nor recommended.
Figure 6-22. DQS and DQ Routing and Topology
Table 6-21. DQS and DQ Routing Specification(1)
NO. PARAMETER MIN TYP MAX UNIT NOTES
2 DQS E Skew Length Mismatch 25 Mils
Center to Center DQS to other LPDDR
3 4w See Note(2)
trace spacing
4 DQS/DQ nominal trace length DQLM - 50 DQLM DQLM + 50 Mils See Note(3)
5 DQ to DQS Skew Length Mismatch 100 Mils
6 DQ to DQ Skew Length Mismatch 100 Mils
Center to Center DQ to other LPDDR
7 4w See Note(2)
trace spacing
Center to Center DQ to other DQ trace
8 3w See Note(2),(4)
spacing
9 DQ E Skew Length Mismatch 100 Mils
(1) Series terminator, if used, should be located closest to LPDDR.
(2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(3) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(4) DQLM is the longest Manhattan distance of the DQS and DQ net classes.
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6.4.2.2 DDR2 Interface
This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need
for a complex timing closure process. For more information regarding guidelines for using this DDR2
specification, Understanding TI's PCB Routing Rule-Based DDR2 Timing Specification (SPRAAV0).
6.4.2.2.1 DDR2 Interface Schematic
Figure 6-23 shows the DDR2 interface schematic for a dual-memory DDR2 system. The single-memory
system is shown in Figure 6-24. Pin numbers for the AM3517/05 can be obtained from the pin description
section.
6.4.2.2.2 Compatible JEDEC DDR2 Devices
Table 6-22 shows the parameters of the JEDEC DDR2 devices that are compatible with this interface.
Generally, the DDR2 interface is compatible with x16 or x32 DDR2 speed grade DDR2-333 devices.
Table 6-22. Compatible JEDEC DDR2 Devices
No. Parameter Min Max Unit Notes
1 JEDEC DDR2 Device Speed Grade DDR2-333 MHz See Note (1)
2 JEDEC DDR2 Device Bit Width x16 x32 Bits
3 JEDEC DDR2 Device Count 1 2 Devices See Note (2)
4 JEDEC DDR2 Device Ball Count 84 92 Balls See Note (3)
(1) Higher DDR2 speed grades operating at the specified speeds are supported due to inherent JEDEC DDR2 backwards compatibility.
(2) Device count indicates number of dies. If a package contains 2 dies, that is the maximum number of devices that can be connected.
(3) 92 ball devices retained for legacy support. New designs should use 84 ball DDR2 devices. Electrically, the 92 and 84 ball DDR2
devices are the same.
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6.4.2.2.3 PCB Stackup
The minimum stackup required for routing the AM3517/05 is a six-layer stack as shown in Table 6-23.
Additional layers may be added to the PCB stack up to accommodate other circuitry or to reduce the size
of the PCB footprint.
Table 6-23. Minimum PCB Stack Up
Layer Type Description
1 Signal Top Routing Mostly Horizontal
2 Plane Ground
3 Plane Power
4 Signal Internal Routing
5 Plane Ground
6 Signal Bottom Routing Mostly Vertical
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1%
1%
Vio1.8
0.1
0.1
0.1
0.10.1µF(A)
Microprocessor
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
50 1%
T
x16 DDR2
SDRC_D0
SDRC_D7
SDRC_DM0
SDRC_DQS0P
SDRC_DQS0N
SDRC_D8
SDRC_D15
SDRC_DM1
SDRC_DQS1P
SDRC_DQS1N
SDRC_STRBEN0
SDRC_STRBEN_DLY0
SDRC_D16
SDRC_D23
SDRC_DM2
SDRC_DQS2P
SDRC_DQS2N
SDRC_D24
SDRC_D31
SDRC_DM3
SDRC_DQS3P
SDRC_DQS3N
SDRC_STRBEN1
SDRC_STRBEN_DLY1
SDRC_BA0
SDRC_BA1
SDRC_BA2
SDRC_A0
SDRC_A14
SDRC_nCS0
SDRC_nCS1
SDRC_nCAS
SDRC_nRAS
SDRC_nWE
SDRC_nCKE0
SDRC_CLK
SDRC_nCLK
SDRC_ODT
VREFSSTL
DDR_PADREF µF(A)
µF(A)
µF
µF
1K Ω
1K Ω
DQ0
Length = avg DQS0-1 length+CLK
Length = avg DQS2-3 length+CLK
DQ7
LDM
LDQS
LDQS#
LQ8
LQ15
UDM
UDQS
UDQS#
DQ0
DQ7
LDM
LDQS
LDQS#
DQ8
DQ15
UDM
UDQS
UDQS#
BA0
BA1
BA2*
A0
A14*
BA0
BA1
BA2*
A0
A14*
CS1
CS2*
CAS#
RAS#
WE#
CLK
CLK#
ODT*
VREF
CS1
CS2*
CAS#
RAS#
WE#
CLK
CLK#
ODT*
VREF
A. See VREF Routing and Topology figure for information on capacitor placement.
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Complete stack up specifications are provided in Table 6-24.
Figure 6-23. DDR2 Dual-Memory High Level Schematic
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SDRC_D0
SDRC_D7
SDRC_DM0
SDRC_DQS0P
SDRC_D8
SDRC_D15
SDRC_DQS1P
SDRC_DQS1N
DQ0
DQ7
DM0
DQS0
DQS0#
DQ8
DQ15
DM1
DQS1
DQS1#
BA0
BA2*
A0
A14*
CS1
CAS#
RAS#
WE#
CKE
CLK
CLK#
VREF
SDRC_BA0
SDRC_BA2
SDRC_A0
SDRC_A14
SDRC_nCS0
SDRC_nCAS
SDRC_nRAS
SDRC_nWE
SDRC_nCKE0
SDRC_CLK
SDRC_nCLK
ODT*
1K 1%Ω
1K 1%Ω
Vio1.8
0.1 Fµ
0.1 Fµ
0.1 Fµ(A)
0.1 Fµ(A)
0.1 Fµ(A)
Microprocessor DDR2
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
SDRC_DQS0N
T
T
T
T
SDRC_DM1
SDRC_D16
SDRC_D23
SDRC_DM2
SDRC_DQS2P
DQ16
DQ23
DM2
DQS2
DQS2#
T
SDRC_DQS2N T
T
SDRC_D24
SDRC_D31
SDRC_DM3
SDRC_DQS3P
DQ24
DQ31
DM3
DQS3
DQS3#
T
SDRC_DQS3N
T
T
SDRC_BA1 BA1
T
SDRC_nCS1 CS2*
SDRC_ODT0 T
VREFSSTL
SDRC_STRBEN0
SDRC_STRBEN_DLY0
T
T
T
T
T
T
T
SDRC_STRBEN1
SDRC_STRBEN_DLY1
T
T
Length = avg D0-D15 length+CLK
Length = avg D16-D31 length+CLK
DDR_PADREF
50 1%
A. See VREF Routing and Topology figure for information on capacitor placement.
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Figure 6-24. DDR2 Single-Memory High Level Schematic
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X
Y
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Device Orientation
Y
Y
OFFSET
DDR2
Device
DDR2
Controller
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Table 6-24. PCB Stack Up Specifications
No. Parameter Min Typ Max Unit Notes
1 PCB Routing/Plane Layers 6
2 Signal Routing Layers 3
3 Full ground layers under DDR2 routing Region 2
4 Number of ground plane cuts allowed within DDR routing region 0
5 Number of ground reference planes required for each DDR2 routing layer 1
6 Number of layers between DDR2 routing layer and ground plane 0
7 PCB Routing Feature Size 4 Mils
8 PCB Trace Width w 4 Mils
9 PCB BGA escape via pad size 20 Mils
10 PCB BGA escape via hole size 10 Mils
11 AM3517/05 BGA pad size 12 See Note (1)
12 DDR2 Device BGA pad size See Note (2)
13 Single Ended Impedance, Zo 50 75 Ω
14 Impedance Control Z-5 Z Z+5 ΩSee Note (3)
(1) The recommended pad size is 0.3 mm per IPC-7351 specification.
(2) Please refer to IPC standard IPC-7351 or manufacturer's recommendations for correct BGA pad size.
(3) Z is the nominal singled ended impedance selected for the PCB specified by item 12.
6.4.2.2.4 Placement
Figure 6-24 shows the required placement for the DDR2 devices. The dimensions for Figure 6-25 are
defined in Table 6-25. The placement does not restrict the side of the PCB that the devices are mounted
on. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper
routing space. For single-memory DDR2 systems, the second DDR2 device is omitted from the
placement.
Figure 6-25. DDR2 Device Placement
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A1
DDR2
Controller
DDR2
Device
Region should encompass all DDR2 circuitry and varies depending
on placement. Non-DDR2 signals should not be routed on the DDR
signal layers within the DDR2 keep out region. Non-DDR2 signals may
be routed in the region provided they are routed on layers separated
from DDR2 signal layers by a ground layer. No breaks should be
allowed in the reference ground layers in this region. In addition, the
1.8 V power plane should cover the entire keep out region.
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Table 6-25. Placement Specifications
No. Parameter Min Max Unit Notes
1 X 1750 Mils See Notes (1),(2)
2 Y 1280 Mils See Notes (1),(2)
3 Y Offset 650 Mils See Notes (1).(2),
(3)
4 DDR2 Keepout Region See Note (4)
5 Clearance from non-DDR2 signal to DDR2 Keepout Region 4 w See Note (5)
(1) See Figure 6-23 for dimension definitions.
(2) Measurements from center of AM3517/05 device to center of DDR2 device.
(3) For single memory systems it is recommended that Y Offset be as small as possible.
(4) DDR2 Keepout region to encompass entire DDR2 routing area
(5) Non-DDR2 signals allowed within DDR2 keepout region provided they are separated from DDR2 routing layers by a ground plane.
6.4.2.2.5 DDR2 Keep Out Region
The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2 keep
out region is defined for this purpose and is shown in Figure 6-26. The size of this region varies with the
placement and DDR routing. Additional clearances required for the keep out region are shown in Table 6-
25.
Figure 6-26. DDR2 Keepout Region
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6.4.2.2.6 Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry.
Table 6-26 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note
that this table only covers the bypass needs of the AM3517/05and DDR2 interfaces. Additional bulk
bypass capacitance may be needed for other circuitry.
Table 6-26. Bulk Bypass Capacitors
No. Parameter Min Max Unit Notes
1 VDDS Bulk Bypass Capacitor Count 3 Devices See Note
(1)
2 VDDS Bulk Bypass Total Capacitance 30 uF
3 DDR#1 Bulk Bypass Capacitor Count 1 Devices See Note
(1)
4 DDR#1 Bulk Bypass Total Capacitance 22 uF
5 DDR#2 Bulk Bypass Capacitor Count 1 Devices See Notes
(1),(2)
6 DDR#2 Bulk Bypass Total Capacitance 22 uF See Note
(2)
(1) These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed
(HS) bypass caps.
(2) Only used on dual-memory systems
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6.4.2.2.7 High-Speed Bypass Capacitors
High-speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass cap, AM3517/05 DDR2 power, and
AM3517/05 DDR2 ground connections. Table 6-27 contains the specification for the HS bypass capacitors
as well as for the power connections on the PCB.
6.4.2.2.8 Net Classes
Table 6-28 lists the clock net classes for the DDR2 interface. Table 6-29 lists the signal net classes, and
associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the
termination and routing rules that follow.
Table 6-27. High-Speed Bypass Capacitors
No. Parameter Min Max Unit Notes
1 HS Bypass Capacitor Package Size 0402 10 Mils See Note (1)
2 Distance from HS bypass capacitor to device being bypassed 250 Mils
3 Number of connection vias for each HS bypass capacitor 2 Vias See Note (2)
4 Trace length from bypass capacitor contact to connection via 1 30 Mils
5 Number of connection vias for each DDR2 device power or ground balls 1 Vias
6 Trace length from DDR2 device power ball to connection via 35 Mils
7 VDDS HS Bypass Capacitor Count 20 Devices See Note (3)
8 VDDS HS Bypass Capacitor Total Capacitance 1.2 μF
9 DDR#1 HS Bypass Capacitor Count 8 Devices See Note (3)
10 DDR#1 HS Bypass Capacitor Total Capacitance 0.4 μF
11 DDR#2 HS Bypass Capacitor Count 8 Devices See Notes
(3),(4)
12 DDR#2 HS Bypass Capacitor Total Capacitance 0.4 μF See Note (4)
(1) LxW, 10 mil units, i.e., a 0402 is a 40x20 mil surface mount capacitor
(2) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.
(3) These devices should be placed as close as possible to the device being bypassed.
(4) Only used on dual-memory systems
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Table 6-28. Clock Net Class Definitions
Clock Net Class AM3517/05 Device Pin Names
CK sdrc_clk/sdrc_nclk
DQS0 sdrc_dqs0p /sdrc_dqs0n
DQS1 sdrc_dqs1p /sdrc_dqs1n
DQS2 sdrc_dqs2p/sdrc_dqs2n
DQS3 sdrc_dqs3p/sdrc_dqs3n
Table 6-29. Signal Net Class Definitions
Associated Clock Net
Clock Net Class Class AM3517/05 Device Pin Names
ADDR_CTRL CK sdrc_ba[2:0], sdrc_ncs1, sdrc_a[14:0], sdrc_ncs0 , sdrc_ncas, sdrc_nras,
sdrc_nwe, sdrc_cke0
DQ0 DQS0 sdrc_d[7:0], sdrc_dm0
DQ1 DQS1 sdrc_d[15:8], sdrc_dm1
DQ2 DQS2 sdrc_d[23:16],sdrc_dm2
DQ3 DQS3 sdrc_d[31:24],sdrc_dm3
SDRC_STRBEN0 CK,DQS0,DQS1 sdrc_strben0, sdrc_strben_dly0
SDRC_STRBEN1 CK,DQS2,DQS3 sdrc_strben1, sdrc_strben_dly1
6.4.2.2.9 DDR2 Signal Termination
No terminations of any kind are required in order to meet signal integrity and overshoot requirements.
Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only
type permitted. Table 6-30 shows the specifications for the series terminators.
Table 6-30. DDR2 Signal Terminations
No. Parameter Min Typ Max Unit Notes
1 CLK Net Class 0 10 ΩSee Note (1)
2 ADDR_CTRL Net Class 0 22 Zo ΩSee Notes (1),
(2),(3)
3 Data Byte Net Classes (DQS0-DQS1, D0-D31) 0 22 Zo ΩSee Notes (1),
(2),(3)
4 SDRC_STRBENx Net Class (SDRC_STRBENx) 0 10 Zo ΩSee Notes (1),
(2),(3)
(1) Only series termination is permitted, parallel or SST specifically disallowed.
(2) Terminator values larger than typical only recommended to address EMI issues.
(3) Termination value should be uniform across net class.
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Microprocessor
A1
A1
DDR2 Device
VREF Nominal Minimum
Trace Width is 20 Mils
VREF Bypass Capacitor
Neck down to minimum in BGA escape
regions is acceptable. Narrowing to
accomodate via congestion for short
distances is also acceptable. Best
performance is obtained if the width
of VREF is maximized.
A1
A1
C B
A
T
DDR2
Controller
Microprocessor
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6.4.2.2.10 VREF Routing
VREF is used as a reference by the input buffers of the DDR2 memories as well as the AM3517/05. VREF
is intended to be half of the DDR2 power supply voltage and should be created using a resistive divider as
shown in Figure 6-23. Other methods of creating VREF are not recommended. Figure 6-27 shows the
layout guidelines for VREF.
Figure 6-27. VREF Routing and Topology
6.4.2.2.11 DDR2 CLK and ADDR_CTRL Routing
Figure 6-28 shows the topology of the routing for the CLK and ADDR_CTRL net classes. The route is a
balanced Tas it is intended that the length of segments B and C be equal. In addition, the length of A
should be maximized.
Figure 6-28. CLK and ADDR_CTRL Routing and Topology
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A1
E0
T
E1
T
E2
Microprocessor
E3
T
DDR2
Controller
T
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Table 6-31. CLK and ADDR_CTRL Routing Specification (1)
No Parameter Min Typ Max Unit Notes
1 Center to center DQS-DQSN spacing 2w
2 CK differential pair Skew Length Mismatch(2) 25 Mils See Note (1)
3 CLKB to CLKC Skew Length Mismatch 25 Mils
4 Center to center CLK to other DDR2 trace spacing 4w See Note (3)
5 CK/ADDR_CTRL nominal trace length CACLM-50 CACLM CACLM+50 Mils See Note (4)
6 ADDR_CTRL to CLK Skew Length Mismatch 100 Mils
7 ADDR_CTRL to ADDR_CTRL Skew Length Mismatch 100 Mils
8 Center to center ADDR_CTRL to other DDR2 trace 4w See Note (3)
spacing
9 Center to center ADDR_CTRL to other ADDR_CTRL 3w See Note (3)
trace spacing
10 ADDR_CTRL A to B, ADDR_CTRL A to C, Skew Length 100 Mils See Note (1)
Mismatch
11 ADDR_CTRL B to C Skew Length Mismatch 100 Mils
(1) Series terminator, if used, should be located closest to AM3517/05.
(2) Differential impedance should be 100-ohms.
(3) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(4) CACLM is the longest Manhattan distance of the CLK and ADDR_CTRL net classes.
Figure 6-29 shows the topology and routing for the DQS and Dx net classes; the routes are point to point.
Skew matching across bytes is not needed nor recommended.
Figure 6-29. DQS and Dx Routing and Topology
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A1
T
T
FL
FH
DDR2
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Table 6-32. DQS and Dx Routing Specification(1) (2)
No. Parameter Min Typ Max Unit Notes
1 Center to center DQS-DQSN spacing 2w
2 DQS E differential pair Skew Length Mismatch(3) 25 Mils
3 Center to center DQS to other DDR2 trace spacing 4w See Note (4)
4 DQS/Dx nominal trace length DQLM-50 DQLM DQLM+ Mils See Notes (2),
50 (5)
5 Dx to DQS Skew Length Mismatch 100 Mils See Note (5)
6 Dx to Dx Skew Length Mismatch 100 Mils See Note (5)
7 Center to center Dx to other DDR2 trace spacing 4w See Notes (4),
(6)
8 Center to Center Dx to other Dx trace spacing 3w See Notes (7),
(4)
(1) "Dx" indicates a data line. E indicates length of DQS differential pair or Dx signal.
(2) Series terminator, if used, should be located closest to DDR.
(3) Differential impedance should be 100-ohms.
(4) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(5) There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and data byte
1.
(6) Dx's from other DQS domains are considered other DDR2 trace.
(7) DQLM is the longest Manhattan distance of each of the DQS and Dx net classes.
Figure 6-30 shows the routing for the SDRC_STRBENx net classes. Table 6-33 contains the routing
specification. SDRC_STRBENx net classes should be shielded from or routed on different layers than the
DQx net classes.
Figure 6-30. SDRC_STRBENx Routing
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DDR2
vo DDR2 on One Chip Select
sdrc_cs0 CS#
CS#
ODT
ODT
sdrc_odt
DDR2
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Table 6-33. SDRC_STRBENx Routing Specification(1)(2)
No. Parameter Min Typ Max Unit Notes
1 SDRC_STRBEN0 Length F CKB0B1 See Note (3)
SDRC_STRBEN1 Length F CKB0B2 See Note (4)
3 Center to center SDRC_STRBENx to any other trace spacing 4w
4 DQS/Dx nominal trace length DQLM-50 DQLM DQLM+50 Mils
5 SDRC_STRBENx Skew 100 Mils See Note (5)
(1) STRBENx termination resistors should be placed close to AM3517/05 STRBENx signal (not close to STRBEN_DLYx signal).
(2) Ensure signal velocities across different layers are taken into account when calculating STRBENx length. For example, if DQS0 and
DSQ1 are 1inch each, and DQS0 is on a layer that is 10% faster, use 1.1inch as the length for DQS0.
(3) CKB0B1 is the sum of the length of the CLK (the portion that goes to the memory associated with DQS0 and DQS1) plus the average
length of the DQS0 and DQS1 differential pairs.
(4) CKB0B2 is the sum of the length of the CLK (the portion that goes to the memory associated with DQS2 and DQS3) plus the average
length of the DQS2 and DQS3 differential pairs.
(5) Skew from CKB0B1 or CKB0B2.
6.4.2.2.12 On Die Termination (ODT)
ODT should only be used with 1 chip select as shown in Figure 6-31. If using sdrc_cs0 and sdrc_cs1,
sdrc_odt should not be used. ODT signals should be tied off at the memory.
Figure 6-31. ODT Connection Using One Chip select (sdrc_cs0)
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6.5 Video Interfaces
6.5.1 Video Processing Subsystem (VPSS)
The Video Processing Sub-System (VPSS) provides a Video Processing Front End (VPFE) input interface
for external imaging peripherals (i.e., image sensors, video decoders, etc.).
6.5.1.1 Video Processing Front End (VPFE)
The Video Processing Front-End (VPFE) controller receives input video/image data from external capture
devices and stores it to external memory which is transferred into the external memory via a built in DMA
engine. An internal buffer block provides a high bandwidth path between the VPSS module and the
external memory. The Cortex-A8 will process the image data based on application requirements.
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VF1
VDIN_CLK
(Falling Edge)
VF2 VF7 VF7
VF10
VF8, VF9, VF11
VF3, VF4, VF6
VF5
VDIN_CLK
(Rising Edge)
VDIN_D[xx]
VDIN_HD,
VDIN_VD,
VDIN_FIELD
VDIN_WEN
SPRS550-001
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6.5.1.1.1 Video Processing Front End (VPFE) Timing
The following tables assume testing over recommended operating conditions.
Table 6-34. VPFE Timing Requirements
1.8V, 3.3V
NO. PARAMETER MIN MAX UNIT
VF1 tc(VDIN_CLK) Cycle time, pixel clock input, VDIN_CLK 13.33 100 ns
VF2 tsu(VDIN_D-VDIN_CLK) Setup time, VDIN_D to VDIN_CLK rising edge 3.5 ns
VF3 tsu(VDIN_HD-VDIN_CLK) Setup time, VDIN_HD to VDIN_CLK rising edge 3.5 ns
VF4 tsu(VDIN_VD-VDIN_CLK) Setup time, VDIN_VD to VDIN_CLK rising edge 3.5 ns
VF5 tsu(VDIN_WEN-VDIN_CLK) Setup time, VDIN_WEN to VDIN_CLK rising edge 3.5 ns
VF6 tsu(C_FLD-VDIN_CLK) Setup time, VDIN_FIELD to VDIN_CLK rising edge 3.5 ns
VF7 th(VDIN_CLK-VDIN_D) Hold time, VDIN_D valid after VDIN_CLK rising edge 2.5 ns
VF8 th(VDIN-HD-VDIN_CLK) Hold time, VDIN_HD to VDIN_CLK rising edge 2.5 ns
VF9 th(VDIN_VD-VDIN_CLK) Hold time, VDIN_VD to VDIN_CLK rising edge 2.5 ns
VF10 th(VDIN_WEN-VDIN_CLK) Hold time, VDIN_WEN to VDIN_CLK rising edge 2.5 ns
VF11 th(C_FLD-VDIN_CLK) Hold time, VDIN_FIELD to VDIN_CLK rising edge 2.5 ns
Table 6-35. VPFE Output Switching Characteristics
1.8V, 3.3V
NO. PARAMETER MIN MAX UNIT
VF12 td(VDIN_HD-VDIN_CLK) Output delay time, VDIN_HD to CLK rising edge 10 ns
VF13 td(VDIN_VD-VDIN_CLK) Output delay time, VDIN_VD to CLK rising edge 10 ns
VF14 td(VDIN_WEN-VDIN_CLK) Output delay time, VDIN_WEN to CLK rising edge 10 ns
VF15 toh(VDIN_HD-VDIN_CLK) Output hold time, VDIN_HD to CLK rising edge 0.5 ns
VF16 toh(VDIN_VD-VDIN_CLK) Output hold time, VDIN_VD to CLK rising edge 0.5 ns
VF17 toh(C_FLD-VDIN_CLK) Output hold time, VDIN_FLD to CLK rising edge 0.5 ns
Figure 6-32. VPFE0 Input Timings
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VDIN_CLK
(Falling Edge)
VF12,
VF13, VF14
VDIN_CLK
(Rising Edge)
VDIN_HD,
VDIN_VD,
VDIN_FIELD
VF15, VF16,
VF17 VF12, VF13, VF14
VF15, VF16,
VF17
SPRS550-002
VDIN_D[xx]
VDIN_HD
(Falling Edge)
VDIN_HD
(Rising Edge)
VF19 VF20
VF18
SPRS550-003
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Figure 6-33. VPFE Output Timings
Figure 6-34. VPFE Input Timings With VDIN0_HD as Pixel Clock
6.5.2 Display Subsystem (DSS)
The display subsystem (DSS) provides the logic to display the video frame from external (SDRAM) or
internal (SRAM) memory on an LCD panel or a TV set. The DSS integrates a display controller. It can be
used in two configurations:
• LCD display support in:
– Bypass mode (RFBI module bypassed)
– RFBI mode (through RFBI module)
• TV display support (not discussed in this document because of its analog IO signals)
The two display supports can be active at the same time.
6.5.2.1 LCD Display Support in Bypass Mode
Two types of LCD panel are supported:
• Thin film transistor (TFT) or active matrix technology
• Supertwisted nematic (STN) or passive matrix technology
Both configurations are discussed in the following paragraphs.
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dss_pclk
dss_vsync
dss_hsync
dss_acbias
dss_data[23:0]
DL4
DL5
DL3
DL0
DL2
DL1
030-061
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6.5.2.1.1 LCD Display in TFT Mode
Table 6-36 assumes testing over the recommended operating conditions (see Figure 6-35).
Table 6-36. LCD Display Interface Switching Characteristics in TFT Mode(1)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
DL0 td(PCLKA-HSYNCT) Delay time, dss_pclk active edge to dss_hsync transition -4.215 4.215 ns
DL1 td(PCLKA-VSYNCT) Delay time, dss_pclk active edge to dss_vsync transition -4.215 4.215 ns
DL2 td(PCLKA-ACBIASA) Delay time, dss_pclk active edge to dss_acbias active level -4.215 4.215 ns
DL3 td(PCLKA-DATAV) Delay time, dss_pclk active edge to dss_data bus valid -4.215 4.215 ns
DL4 tc(PCLK) Cycle time(2), dss_pclk 13.468 ns
DL5 tw(PCLK) Pulse duration, dss_pclk low or high 6.06 7.46 ns
cload Load capacitance 25 pF
(1) The capacitive load is equivalent to 25 pF.
(2) The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the
DISPC_DIVISOR register.
Figure 6-35. LCD Display in TFT Mode(1) (2) (3) (4)
(1) The pixel data bus depends on the use of 8-, 9-, 12-, 16-, 18-, or 24-bit per pixel data output pins.
(2) The pixel clock frequency is programmable.
(3) All timings not illustrated in the waveform are programmable by software, control signal polarity, and driven edge of dss_pclk.
(4) For more information, see the AM35x ARM Microprocessor Technical Reference Manual (literature number SPRUGR0).
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dss_vsync
dss_hsync
dss_acbias
dss_data[23:0]
DL4
DL5
DL3
030-062
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6.5.2.1.2 LCD Display in STN Mode
Table 6-37 assumes testing over the recommended operating conditions (see Figure 6-36).
Table 6-37. LCD Display Interface Switching Characteristics in STN Mode(1) (2) (3)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
DL3 td(PCLKA-DATAV) Delay time, dss_pclk active edge to dss_data bus valid -4.21 6.9 ns
DL4 tc(PCLK) Cycle time(4), dss_pclk 22.73 ns
DL5 tw(PCLK) Pulse duration, dss_pclk low or high 10.23 12.5 ns
cload Load capacitance 40 pF
(1) The DSS in STN mode is used with 4 or 8 pins only; unused pixel data bits always remain low.
(2) The capacitive load is equivalent to 40 pF.
(3) For more information, see the AM35x ARM Microprocessor Technical Reference Manual (literature number SPRUGR0).
(4) The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the
DISPC_DIVISOR register.
Figure 6-36. LCD Display in STN Mode(1) (2) (3) (4) (5)
(1) The pixel data bus depends on the use 4-, 8-, 12-, 16-, 18-, or 24-bit per pixel data output pins.
(2) All timings not illustrated in the waveform are programmable by software, control signal polarity, and driven edge of dss_pclk.
(3) dss_vsync width must be programmed to be as small as possible.
(4) The pixel clock frequency is programmable.
(5) For more information, see the AM35x ARM Microprocessor Technical Reference Manual (literature number SPRUGR0).
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6.6 Serial Communications Interfaces
6.6.1 Multichannel Buffered Serial Port (McBSP) Timing
There are five McBSP modules called McBSP1 through McBSP5. McBSP provides a full-duplex, direct
serial interface between the AM3517/05 device and other devices in a system such as other application
devices or codecs. It can accommodate a wide range of peripherals and clocked frame-oriented protocols
(I2S, PCM, and TDM) due to its high level of versatility.
The McBSP1-5 modules may support two types of data transfer at the system level:
• The full-cycle mode, for which one clock period is used to transfer the data, generated on one edge
and captured on the same edge (one clock period later).
• The half-cycle mode, for which one half clock period is used to transfer the data, generated on one
edge and captured on the opposite edge (one half clock period later). Note that a new data is
generated only every clock period, which secures the required hold time.
The interface clock (CLKX/CLKR) activation edge (data/frame sync capture and generation) has to be
configured accordingly with the external peripheral (activation edge capability) and the type of data
transfer required at the system level.
The AM3517/05 McBSP1-5 timing characteristics are described for both rising and falling activation edges.
McBSP1 supports:
• 6-pin mode: dx and dr as data pins; clkx, clkr, fsx, and fsr as control pins.
• 4-pin mode: dx and dr as data pins; clkx and fsx pins as control pins. The clkx and fsx pins are
internally looped back via software configuration, respectively, to the clkr and fsr internal signals for
data receive.
McBSP2, 3, 4, and 5 support only the 4-pin mode.
The following sections describe the timing characteristics for applications in normal mode (that is,
AM3517/05 McBSPx connected to one peripheral) and TDM applications in multipoint mode.
6.6.1.1 McBSP in Normal Mode
The following tables assume=testing over the recommended operating conditions.
Table 6-38. McBSP Timing Conditions
TIMING CONDITION PARAMETER 1.8V, 3.3 V UNIT
Input Conditions VALUE
tRInput signal rise time 2(1) ns
tFInput signal fall time 2 ns
Output Conditions
CLOAD Output load 10 pF
capacitance
(1) Maximum value.
Table 6-39. McBSP1,2,4,5 Output Clock Pulse Duration
PARAMETER VDDSHV = 1.8V, 3.3V UNIT
MIN MAX
tC(CLK) Cycle Time, 20.83 ns
mcbsp1_clkr/mcbspx_clkx
(1)
tW(CLKH) Typical pulse duration, 0.5*P(2) 0.5*P(2) ns
mcbsp1_clkr /
mcbspx_clkx high(1)
(1) In mcbspx, x identifies the McBSP number; 1, 2, 4, or 5.
(2) P = mcbsp1_clkr / mcbspx_clkx clock period.
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Table 6-39. McBSP1,2,4,5 Output Clock Pulse Duration (continued)
PARAMETER VDDSHV = 1.8V, 3.3V UNIT
tW(CLKL) Typical pulse duration, 0.5*P(2) 0.5*P(2) ns
mcbsp1_clkr /
mcbspx_clkx low(1)
tdc(CLK) Duty cycle error, -0.75 0.75 ns
mcbsp1_clkr /
mcbspx_clkx(1)
Table 6-40. McBSP3 Output Clock Pulse Duration
PARAMETER VDDSHV = 1.8V, 3.3V UNIT
MIN MAX
tC(CLK) Cycle time, mcbsp3_clkx 31.25 ns
tW(CLKH) Typical pulse duration, 0.5*P(1) 0.5*P(1) ns
mcbsp3_clkx high
tW(CLKL) Typical pulse duration, 0.5*P(1) 0.5*P(1) ns
mcbsp3_clkx low
tdc(CLK) Duty cycle error, -0.75 0.75 ns
mcbsp3_clkx
(1) P = mcbsp3_clkx clock period
6.6.1.1.1 McBSP1
The following tables show the timing requirements and switching characteristics for McBSP1.
Table 6-41. McBSP1 Timing Requirements - Rising Edge and Receive Mode
No. PARAMETER VDDSHV=3.3V VDDSHV=1.8V UNIT
MIN MAX MIN MAX
B3 tsu(DRV- Setup time, Half Cycle 5.0 5.0 ns
CLKAE) mcbsp1_dr Master
valid before Half Cycle 5.2 5.2 ns
mcbsp1_clkr / Slave
mcbsp1_clkx
active edge Full Cycle 4.0 4.0 ns
Master
Full Cycle 4.2 4.2 ns
Slave
B4 th(CLKAE- Hold time, Half Cycle 5.8 5.8 ns
DRV) mcbsp1_dr Master
valid after Half Cycle 5.2 5.2 ns
mcbsp1_clkr / Slave
mcbsp1_clkx
active edge Full Cycle 1.5 1.5 ns
Master
Full Cycle 0.9 0.9 ns
Slave
B5 tsu(FSV- Setup time, Half Cycle 5.2 5.2 ns
CLKAE) mcbsp1_fsr / Slave
mcbsp1_fsx Full Cycle 4.2 4.2 ns
valid before Slave
mcbsp1_clkr /
mcbsp1_clkx
active edge
B6 th(CLKAE-FSV) Hold time, Half Cycle 0.5 0.5 ns
mcbsp1_fsr / Slave
mcbsp1_fsx Full Cycle 1.0 1.0 ns
valid after Slave
mcbsp1_clkr /
mcbsp1_clkx
active edge
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Table 6-42. McBSP1 Switching Characteristics - Rising Edge and Receive Mode
No. PARAMETER VDDSHV=3.3V VDDSHV=1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKAE-FSV) Delay time, 0.2 14.8 0.2 14.8 ns
mcbsp1_clkr
active edge to
mcbsp1_fsr /
mcbsp1_fsx
valid
Table 6-43. McBSP1 Timing Requirements - Rising Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B5 tsu(FSXV- Setup time, Full Cycle 5.2 4.7 ns
CLKXAE) mcbsp1_fsx Slave
valid before Half Cycle 4.2 3.7 ns
mcbsp1_clkx Slave
active edge
B6 th(CLKXAE- Hold time, Full Cycle 5.2 4.7 ns
FSXV) mcbsp1_fsx Slave
valid after Half Cycle 1.0 0.5 ns
mcbsp1_clkx Slave
active edge
Table 6-44. McBSP1 Switching Characteristics - Rising Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, 0.2 14.8 0.7 14.8 ns
FSXV) mcbsp1_clkx
active edge to
mcbsp1_fsx
valid
B8 td(CLKXAE- Delay time, Master 0.6 14.8 0.6 14.8 ns
DXV) mcbsp1_clkx Slave 0.6 14.8 0.6 14.8 ns
active edge to
mcbsp1_dx
valid
Table 6-45. McBSP1 Timing Requirements - Falling Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B3 tsu(DRV- Setup time, Half Cycle 5.0 5.0 ns
CLKAE) mcbsp1_dr Master
valid before Half Cycle 5.2 5.2 ns
mcbsp1_clkr / Slave
mcbsp1_clkx
active edge Full Cycle 4.0 4.0 ns
Master
Full Cycle 4.2 4.2 ns
Slave
B4 th(CLKAE- Hold time, Half Cycle 5.8 5.8 ns
DRV) mcbsp1_dr Master
valid after Half Cycle 5.2 5.2 ns
mcbsp1_clkr / Slave
mcbsp1_clkx
active edge Full Cycle 1.5 1.5 ns
Master
Full Cycle 0.9 0.9 ns
Slave
B5 tsu(FSV- Setup time, Half Cycle 5.2 5.2 ns
CLKAE) mcbsp1_fsr / Slave
mcbsp1_fsx Full Cycle 4.2 4.2 ns
valid before Slave
mcbsp1_clkr /
mcbsp1_clkx
active edge
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Table 6-45. McBSP1 Timing Requirements - Falling Edge and Receive Mode (continued)
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
B6 th(CLKAE-FSV) Hold time, Half Cycle 0.5 0.5 ns
mcbsp1_fsr / Slave
mcbsp1_fsx Full Cycle 1.0 1.0 ns
valid after Slave
mcbsp1_clkr /
mcbsp1_clkx
active edge
Table 6-46. McBSP1 Switching Characteristics - Falling Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKAE-FSV) Delay time, mcbsp1_clkr / 0.2 14.8 0.7 14.8 ns
mcbsp1_clkx active edge to
mcbsp1_fsr / mcbsp1_fsx valid
Table 6-47. McBSP1 Timing Requirements - Falling Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B5 tsu(FSXV- Setup time, Half Cycle 5.2 5.2 ns
CLKXAE) mcbsp1_fsx Slave
valid before Full Cycle 4.2 4.2 ns
mcbsp1_clkx Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 5.2 5.2 ns
FSXV) mcbsp1_fsx Slave
valid after Full Cycle 1.0 1.0 ns
mcbsp1_clkx Slave
active edge
Table 6-48. McBSP1 Switching Characteristics - Falling Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, 0.2 14.8 0.2 14.8 ns
FSXV) mcbsp1_clkx
active edge to
mcbsp1_fsx
valid
B8 td(CLKXAE- Delay time, Master 0.6 14.8 0.6 14.8 ns
DXV) mcbsp1_clkx Slave 0.6 14.8 0.6 14.8 ns
active edge to
mcbsp1_dx
valid
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6.6.1.1.2 McBSP2
The following tables show the timing requirements and switching characteristics for McBSP2.
Table 6-49. McBSP2 Timing Requirements - Rising Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B3 tsu(DRV- Setup time, Half Cycle 5.0 5.0 ns
CLKXAE) mcbsp2_dr Master
valid before Half Cycle 5.2 5.2 ns
mcbsp2_clkx Slave
active edge Full Cycle 4.2 4.2 ns
Master
Full Cycle 4.2 4.2 ns
Slave
B4 th(CLKXAE- Hold time, Half Cycle 5.8 5.8 ns
DRV) mcbsp2_dr Master
valid after Half Cycle 5.2 5.2 ns
mcbsp2_clkx Slave
active edge Full Cycle 1.5 1.5 ns
Master
Full Cycle 0.9 0.9 ns
Slave
B5 tsu(FSV- Setup time, Half Cycle 5.2 5.2 ns
CLKXAE) mcbsp2_fsx Slave
valid before Full Cycle 4.2 4.2 ns
mcbsp2_clkx Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 5.2 5.2 ns
FSV) mcbsp2_fsx Slave
valid after Full Cycle 1.0 1.0 ns
mcbsp2_clkx Slave
active edge
Table 6-50. McBSP2 Switching Characteristics - Rising Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, 0.2 14.8 0.2 14.8 ns
FSXV) mcbsp2_clkx
active edge to
mcbsp2_fsx
valid
Table 6-51. McBSP2 Timing Requirements - Rising Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B5 tsu(FSXV- Setup time, Half Cycle 5.2 4.7 ns
CLKXAE) mcbsp2_fsx Slave
valid before Full Cycle 4.2 3.7 ns
mcbsp2_clkx Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 5.2 4.7 ns
FSXV) mcbsp2_fsx Slave
valid after Full Cycle 1.0 0.5 ns
mcbsp2_clkx Slave
active edge
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Table 6-52. McBSP2 Switching Characteristics - Rising Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, 0.2 14.8 0.2 14.8 ns
FSXV) mcbsp2_clkx
active edge to
mcbsp2_fsx
valid
B8 td(CLKXAE- Delay time, Master 0.6 14.8 0.6 14.8 ns
DXV) mcbsp2_clkx Slave 0.6 14.8 0.6 14.8 ns
active edge to
mcbsp2_dx
valid
Table 6-53. McBSP2 Timing Requirements - Falling Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B3 tsu(DRV- Setup time, Half Cycle 5.0 5.0 ns
CLKXAE) mcbsp2_dr Master
valid before Half Cycle 5.2 5.2 ns
mcbsp2_clkx Slave
active edge Full Cycle 4.2 4.2 ns
Master
Full Cycle 4.2 4.2 ns
Slave
B4 th(CLKXAE- Hold time, Half Cycle 5.8 5.8 ns
DRV) mcbsp2_dr Master
valid after Half Cycle 5.2 5.2 ns
mcbsp2_clkx Slave
active edge Full Cycle 1.5 1.5 ns
Master
Full Cycle 0.9 0.9 ns
Slave
B5 tsu(FSXV- Setup time, Half Cycle 5.2 5.2 ns
CLKXAE) mcbsp2_fsx Slave
valid before Full Cycle 4.2 4.2 ns
mcbsp2_clkx Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 5.2 5.2 ns
FSXV) mcbsp2_fsx Slave
valid after Full Cycle 1.0 1.0 ns
mcbsp2_clkx Slave
active edge
Table 6-54. McBSP2 Switching Characteristics - Falling Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, mcbsp2_clkx active 0.2 14.8 0.2 14.8 ns
FSXV) edge to mcbsp2_fsx valid
Table 6-55. McBSP2 Timing Requirements - Falling Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B5 tsu(FSXV- Setup time, Half Cycle 5.2 5.2 ns
CLKXAE) mcbsp2_fsx Slave
valid before Full Cycle 4.2 4.2 ns
mcbsp2_clkx Slave
active edge
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Table 6-55. McBSP2 Timing Requirements - Falling Edge and Transmit Mode (continued)
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
B6 th(CLKXAE- Hold time, Half Cycle 5.2 5.2 ns
FSXV) mcbsp2_fsx Slave
valid after Full Cycle 1.0 1.0 ns
mcbsp2_clkx Slave
active edge
Table 6-56. McBSP2 Switching Characteristics - Falling Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, mcbsp2_clkx active 0.2 14.8 0.2 14.8 ns
FSXV) edge to mcbsp2_fsx valid
B8 td(CLKXAE- Delay time, Master 0.6 14.8 0.6 14.8 ns
DXV) mcbsp2_clkx Slave 0.6 14.8 0.6 14.8 ns
active edge to
mcbsp2_dx
valid
6.6.1.1.3 McBSP3
6.6.1.1.3.1 McBSP3 Multiplexed on McBSP3 Pins
The following tables show the timing conditions and switching characteristics for McBSP3 multiplexed on
McBSP3 pins.
Note: All timings apply only to Set #1- multiplexing on mcbsp3 pins.
Table 6-57. McBSP3 (Set #1) Timing Requirements - Rising Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B3 tsu(DRV- Setup time, Half Cycle 7.5 7.5 ns
CLKXAE) mcbsp3_dr Master
valid before Half Cycle 7.7 7.7 ns
mcbsp3_clkx Slave
active edge Full Cycle 5.6 5.6 ns
Master
Full Cycle 5.8 5.8 ns
Slave
B4 th(CLKXAE- Hold time, Half Cycle 8.3 8.3 ns
DRV) mcbsp3_dr Master
valid after Half Cycle 7.7 7.7 ns
mcbsp3_clkx Slave
active edge Full Cycle 1.5 1.5 ns
Master
Full Cycle 0.9 0.9 ns
Slave
B5 tsu(FSV- Setup time, Half Cycle 7.7 7.7 ns
CLKXAE) mcbsp3_fsx Slave
valid before Full Cycle 5.8 5.8 ns
mcbsp3_clkx Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 7.7 7.7 ns
FSV) mcbsp3_fsx Slave
valid after Full Cycle 1.0 1.0 ns
mcbsp3_clkx Slave
active edge
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Table 6-58. McBSP3 (Set #1) Switching Characteristics - Rising Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, mcbsp3_clkx active 0.2 22.2 0.2 22.2 ns
FSXV) edge to mcbsp3_fsx valid
Table 6-59. McBSP3 (Set #1) Timing Requirements - Rising Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B5 tsu(FSXV- Setup time, Half Cycle 7.7 7.7 ns
CLKXAE) mcbsp3_fsx Slave
valid before Full Cycle 5.8 5.8 ns
mcbsp3_clkx Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 7.7 7.7 ns
FSXV) mcbsp3_fsx Slave
valid after Full Cycle 1 1 ns
mcbsp3_clkx Slave
active edge
Table 6-60. McBSP3 (Set #1) Switching Characteristics - Rising Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, mcbsp3_clkx active 0.2 22.2 0.2 22.2 ns
FSXV) edge to mcbsp3_fsx valid
B8 td(CLKXAE- Delay time, Master 0.6 22.2 0.6 22.2 ns
DXV) mcbsp3_clkx Slave 0.6 22.2 0.6 22.2 ns
active edge to
mcbsp3_dx
valid
Table 6-61. McBSP3 (Set #1) Timing Requirements - Falling Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
tsu(DRV- Setup time, Half Cycle 7.5 7.5 ns
CLKXAE) mcbsp3_dr Master
valid before Half Cycle 7.7 7.7 ns
mcbsp3_clkx Slave
active edge Full Cycle 5.6 5.6 ns
Master
Full Cycle 5.8 5.8 ns
Slave
th(CLKXAE- Hold time, Half Cycle 8.3 8.3 ns
DRV) mcbsp3_dr Master
valid after Half Cycle 7.7 7.7 ns
mcbsp3_clkx Slave
active edge Full Cycle 1.5 1.5 ns
Master
Full Cycle 0.9 0.9 ns
Slave
B5 tsu(FXSV- Setup time, Half Cycle 7.7 7.7 ns
CLKXAE) mcbsp3_fsx Slave
valid before Full Cycle 5.8 5.8 ns
mcbsp3_clkx Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 7.7 7.7 ns
FSXV) mcbsp3_fsx Slave
valid after Full Cycle 1.0 1.0 ns
mcbsp3_clkx Slave
active edge
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Table 6-62. McBSP3 (Set #1) Switching Characteristics - Falling Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, mcbsp3_clkx active 0.2 22.2 0.2 22.2 ns
FSXV) edge to mcbsp3_fsx valid
Table 6-63. McBSP3 (Set #1) Timing Requirements - Falling Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B5 tsu(FSXV- Setup time, Half Cycle 5.2 5.2 ns
CLKXAE) mcbsp3_fsx Slave
valid before Full Cycle 4.2 4.2 ns
mcbsp3_clkx Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 5.2 5.2 ns
FSXV) mcbsp3_fsx Slave
valid after Full Cycle 1.0 1.0 ns
mcbsp3_clkx Slave
active edge
Table 6-64. McBSP3 (Set #1) Switching Characteristics - Falling Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, mcbsp3_clkx active 0.2 22.2 0.2 22.2 ns
FSXV) edge to mcbsp3_fsx valid
B8 td(CLKXAE- Delay time, Master 0.6 22.2 0.6 22.2 ns
DXV) mcbsp3_clkx Slave 0.6 22.2 0.6 22.2 ns
active edge to
mcbsp3_dx
valid
6.6.1.1.3.2 McBSP3 Multiplexed on UART2 or McBSP1 Pins
The following tables show the timing conditions and switching characteristics for McBSP3 multiplexed on
UART2 or McBSP1 pins.
Note: These timings only apply to Set #2 (multiplexing mode on uart2 pins) and Set #3 (multiplexing on
mcbsp1 pins).
Table 6-65. McBSP3 (Sets #2 and #3) Timing Requirements - Rising Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B3 tsu(DRV- Setup time, Half Cycle 5.0 5.0 ns
CLKXAE) mcbsp3_dr Master
valid before Half Cycle 5.2 5.2 ns
mcbsp3_clkx Slave
active edge Full Cycle 4.2 4.2 ns
Master
Full Cycle 4.2 4.2 ns
Slave
B4 th(CLKXAE- Hold time, Half Cycle 5.8 5.8 ns
DRV) mcbsp3_dr Master
valid after Half Cycle 5.2 5.2 ns
mcbsp3_clkx Slave
active edge Full Cycle 1.5 1.5 ns
Master
Full Cycle 0.9 0.9 ns
Slave
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Table 6-65. McBSP3 (Sets #2 and #3) Timing Requirements - Rising Edge and Receive Mode (continued)
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
B5 tsu(FSV- Setup time, Half Cycle 5.2 5.2 ns
CLKXAE) mcbsp3_fsx Slave
valid before Full Cycle 4.2 4.2 ns
mcbsp3_clkx Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 5.2 5.2 ns
FSV) mcbsp3_fsx Slave
valid after Full Cycle 1.0 1.0 ns
mcbsp3_clkx Slave
active edge
Table 6-66. McBSP3 (Sets #2 and #3) Switching Characteristics - Rising Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, 0.2 14.8 0.2 14.8 ns
FSXV) mcbsp3_clkx
active edge to
mcbsp3_fsx
valid
Table 6-67. McBSP3 (Sets #2 and #3) Timing Requirements - Rising Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B5 tsu(FSXV- Setup time, Half Cycle 5.2 5.2 ns
CLKXAE) mcbsp3_fsx Slave
valid before Full Cycle 4.2 4.2 ns
mcbsp3_clkx Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 5.2 5.2 ns
FSXV) mcbsp3_fsx Slave
valid after Full Cycle 1.0 1.0 ns
mcbsp3_clkx Slave
active edge
Table 6-68. McBSP3 (Sets #2 and #3) Switching Characteristics - Rising Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, mcbsp3_clkx active 0.2 14.8 0.2 14.8 ns
FSXV) edge to mcbsp3_fsx valid
B8 td(CLKXAE- Delay time, Master 0.6 14.8 0.6 14.8 ns
DXV) mcbsp3_clkx Slave 0.6 14.8 0.6 14.8 ns
active edge to
mcbsp3_dx
valid
Table 6-69. McBSP3 (Sets #2 and #3) Timing Requirements - Falling Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B3 tsu(DRV- Setup time, Half Cycle 5.0 5.0 ns
CLKXAE) mcbsp3_dr Master
valid before Half Cycle 5.2 5.2 ns
mcbsp3_clkx Slave
active edge Full Cycle 4.2 4.2 ns
Master
Full Cycle 4.2 4.2 ns
Slave
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Table 6-69. McBSP3 (Sets #2 and #3) Timing Requirements - Falling Edge and Receive Mode (continued)
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
B4 th(CLKXAE- Hold time, Half Cycle 5.8 5.8 ns
DRV) mcbsp3_dr Master
valid after Half Cycle 5.2 5.2 ns
mcbsp3_clkx Slave
active edge Full Cycle 1.5 1.5 ns
Master
Full Cycle 0.9 0.9 ns
Slave
B5 tsu(FXSV- Setup time, Half Cycle 5.2 5.2 ns
CLKXAE) mcbsp3_fsx Slave
valid before Full Cycle 4.2 4.2 ns
mcbsp3_clkx Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 5.2 5.2 ns
FSXV) mcbsp3_fsx Slave
valid after Full Cycle 1.0 1.0 ns
mcbsp3_clkx Slave
active edge
Table 6-70. McBSP3 (Sets #2 and #3) Switching Characteristics - Falling Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, mcbsp3_clkx active 0.2 14.8 0.2 14.8 ns
FSXV) edge to mcbsp3_fsx valid
Table 6-71. McBSP3 (Sets #2 and #3) Timing Requirements - Falling Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B5 tsu(FSXV- Setup time, Half Cycle 5.2 5.2 ns
CLKXAE) mcbsp3_fsx Slave
valid before Full Cycle 4.2 4.2 ns
mcbsp3_clkx Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 5.2 5.2 ns
FSXV) mcbsp3_fsx Slave
valid after Full Cycle 1.0 1.0 ns
mcbsp3_clkx Slave
active edge
Table 6-72. McBSP3 (Sets #2 and #3) Switching Characteristics - Falling Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1 .8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, mcbsp3_clkx active 0.2 14.8 0.2 14.8 ns
FSXV) edge to mcbsp3_fsx valid
B8 td(CLKXAE- Delay time, Master 0.6 14.8 0.6 14.8 ns
DXV) mcbsp3_clkx
active edge to
mcbsp3_dx
valid
Slave 0.6 14.8 0.6 14.8 ns
6.6.1.1.4 McBSP4
The following tables show the timing requirements and switching characteristics for McBSP4.
Table 6-73. McBSP4 Timing Requirements - Rising Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
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Table 6-73. McBSP4 Timing Requirements - Rising Edge and Receive Mode (continued)
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
B3 tsu(DRV- Setup time, Half Cycle 7.5 7.5 ns
CLKXAE) mcbsp4_dr Master
valid before Half Cycle 7.7 7.7 ns
mcbsp4_clkx Slave
active edge Full Cycle 3.2 3.2 ns
Master
Full Cycle 4.2 4.2 ns
Slave
B4 th(CLKXAE- Hold time, Half Cycle 7.7 7.7 ns
DRV) mcbsp4_dr Master
valid after Half Cycle 5.2 5.2 ns
mcbsp4_clkx Slave
active edge Full Cycle 1.5 1.5 ns
Master
Full Cycle 0.9 0.9 ns
Slave
B5 tsu(FSV- Setup time, Half Cycle 7.7 7.7 ns
CLKXAE) mcbsp4_fsx Slave
valid before Full Cycle 4.2 4.2 ns
mcbsp4_clkx Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 5.2 5.2 ns
FSV) mcbsp4_fsx Slave
valid after Full Cycle 1.0 1.0 ns
mcbsp4_clkx Slave
active edge
Table 6-74. McBSP4 Switching Characteristics - Rising Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, 0.2 16.6 0.2 16.6 ns
FSXV) mcbsp4_clkx
active edge to
mcbsp4_fsx
valid
Table 6-75. McBSP4 Timing Requirements - Rising Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B5 tsu(FSXV- Setup time, Half Cycle 7.7 7.7 ns
CLKXAE) mcbsp4_fsx Slave
valid before Full Cycle 3.7 3.7 ns
mcbsp4_clkx Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 1.0 1.0 ns
FSXV) mcbsp4_fsx Slave
valid after Full Cycle 1.0 1.0 ns
mcbsp4_clkx Slave
active edge
Table 6-76. McBSP4 Switching Characteristics - Rising Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, 0.2 16.6 0.2 16.6 ns
FSXV) mcbsp4_clkx
active edge to
mcbsp4_fsx
valid
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Table 6-76. McBSP4 Switching Characteristics - Rising Edge and Transmit Mode (continued)
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
B8 td(CLKXAE- Delay time, Master 0.6 16.6 0.6 16.6 ns
DXV) mcbsp4_clkx Slave 0.6 17.3 0.6 17.3 ns
active edge to
mcbsp4_dx
valid
Table 6-77. McBSP4 Timing Requirements - Falling Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B3 tsu(DRV- Setup time, Half Cycle 7.5 7.5 ns
CLKXAE) mcbsp4_dr Master
valid before Half Cycle 7.7 7.7 ns
mcbsp4_clkx Slave
active edge Full Cycle 5.6 5.6 ns
Master
Full Cycle 5.8 5.8 ns
Slave
B4 th(CLKXAE- Hold time, Half Cycle 7.7 7.7 ns
DRV) mcbsp4_dr Master
valid after Half Cycle 5.2 5.2 ns
mcbsp4_clkx Slave
active edge Full Cycle 1.5 1.5 ns
Master
Full Cycle 0.9 0.9 ns
Slave
B5 tsu(FXSV- Setup time, Half Cycle 7.7 7.7 ns
CLKXAE) mcbsp4_fsx Slave
valid before Full Cycle 5.8 5.8 ns
mcbsp4_clkx Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 5.2 5.2 ns
FSXV) mcbsp4_fsx Slave
valid after
mcbsp4_clkx
active edge
Full Cycle 1.0 1.0 ns
Slave
Table 6-78. McBSP4 Switching Characteristics - Falling Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, mcbsp4_clkx active 0.2 16.6 0.2 16.6 ns
FSXV) edge to mcbsp4_fsx valid
Table 6-79. McBSP4 Timing Requirements - Falling Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B5 tsu(FSXV- Setup time, Half Cycle 7.7 7.7 ns
CLKXAE) mcbsp4_fsx Slave
valid before Full Cycle 3.7 3.7 ns
mcbsp4_clkx Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 5.2 5.2 ns
FSXV) mcbsp4_fsx Slave
valid after Full Cycle 1.0 1.0 ns
mcbsp4_clkx Slave
active edge
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Table 6-80. McBSP4 Switching Characteristics - Falling Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, mcbsp4_clkx active 0.2 16.6 0.2 16.6 ns
FSXV) edge to mcbsp4_fsx valid
B8 td(CLKXAE- Delay time, Master 0.6 16.6 0.6 16.6 ns
DXV) mcbsp4_clkx
active edge to Slave 0.6 17.3 0.6 17.3 ns
mcbsp4_dx
valid
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6.6.1.1.5 McBSP5
The following tables show the timing conditions and switching characteristics for McBSP5.
Table 6-81. McBSP5 Timing Requirements - Rising Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B3 tsu(DRV- Setup time, Half Cycle 7.5 7.5 ns
CLKXAE) mcbsp5_dr Master
valid before Half Cycle 7.7 7.7 ns
mcbsp5_clkx Slave
active edge Full Cycle 5.6 5.6 ns
Master
Full Cycle 5.8 5.8 ns
Slave
B4 th(CLKXAE- Hold time, Half Cycle 7.5 7.5 ns
DRV) mcbsp5_dr Master
valid after Half Cycle 7.7 7.7 ns
mcbsp5_clkx Slave
active edge Full Cycle 1.5 1.5 ns
Master
Full Cycle 0.9 0.9 ns
Slave
B5 tsu(FSV- Setup time, Half Cycle 7.7 7.7 ns
CLKXAE) mcbsp5_fsx Slave
valid before Full Cycle 5.8 5.8 ns
mcbsp5_clkx Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 7.7 7.7 ns
FSV) mcbsp5_fsx Slave
valid after Full Cycle 1.0 1.0 ns
mcbsp5_clkx Slave
active edge
Table 6-82. McBSP5 Switching Characteristics - Rising Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, mcbsp5_clkx active 0.2 14.8 0.7 14.8 ns
FSXV) edge to mcbsp5_fsx valid
Table 6-83. McBSP5 Timing Requirements - Rising Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B5 tsu(FSXV- Setup time, Half Cycle 7.7 7.7 ns
CLKXAE) mcbsp5_fsx Slave
valid before Full Cycle 5.8 5.8 ns
mcbsp5_clkx Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 7.7 7.7 ns
FSXV) mcbsp5_fsx Slave
valid after Full Cycle 1.0 1.0 ns
mcbsp5_clkx Slave
active edge
Table 6-84. McBSP5 Switching Characteristics - Rising Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, 0.2 14.8 0.2 14.8 ns
FSXV) mcbsp5_clkx
active edge to
mcbsp5_fsx
valid
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Table 6-84. McBSP5 Switching Characteristics - Rising Edge and Transmit Mode (continued)
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
B8 td(CLKXAE- Delay time, Master 0.6 14.8 0.6 14.8 ns
DXV) mcbsp5_clkx Slave 0.6 14.8 0.6 14.8 ns
active edge to
mcbsp5_dx
valid
Table 6-85. McBSP5 Timing Requirements - Falling Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B3 tsu(DRV- Setup time, Half Cycle 7.5 7.5 ns
CLKXAE) mcbsp5_dr Master
valid before Half Cycle 7.7 7.7 ns
mcbsp5_clkx Slave
active edge Full Cycle 5.6 5.6 ns
Master
Full Cycle 5.8 5.8 ns
Slave
B4 th(CLKXAE- Hold time, Half Cycle 8.3 8.3 ns
DRV) mcbsp5_dr Master
valid after Half Cycle 7.7 7.7 ns
mcbsp5_clkx Slave
active edge Full Cycle 1.5 1.5 ns
Master
Full Cycle 0.9 0.9 ns
Slave
B5 tsu(FXSV- Setup time, Half Cycle 7.7 7.7 ns
CLKXAE) mcbsp5_fsx Slave
valid before Full Cycle 5.8 5.8 ns
mcbsp5_clkx Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 7.7 7.7 ns
FSXV) mcbsp5_fsx Slave
valid after Full Cycle 1.0 1.0 ns
mcbsp5_clkx Slave
active edge
Table 6-86. McBSP5 Switching Characteristics - Falling Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, mcbsp5_clkx active 0.2 22.2 0.2 22.2 ns
FSXV) edge to mcbsp5_fsx valid
Table 6-87. McBSP5 Timing Requirements - Falling Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B5 tsu(FSXV- Setup time, Half Cycle 7.7 7.7 ns
CLKXAE) mcbsp5_fsx Slave
valid before Full Cycle 5.8 5.8 ns
mcbsp5_clkx Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 7.7 7.7 ns
FSXV) mcbsp5_fsx Slave
valid after Full Cycle 1.0 1.0 ns
mcbsp5_clkx Slave
active edge
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Table 6-88. McBSP5 Switching Characteristics - Falling Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, 0.2 22.2 0.2 22.2 ns
FSXV) mcbsp5_clkx
active edge to
mcbsp5_fsx
valid
B8 td(CLKXAE- Delay time, Master 0.6 22.2 0.6 22.2 ns
DXV) mcbsp5_clkx Slave 0.6 22.2 0.6 22.2 ns
active edge to
mcbsp5_dx
valid
6.6.1.1.6 McBSP in TDM Mode
The following tables assume=testing over the recommended operating conditions.
Table 6-89. McBSP Timing Conditions – TDM in Multipoint Mode
PARAMETER DESCRIPTION VDDSHV = 1.8V or 3.3V UNIT
MIN MAX
tr Input signal rise time 1 8.5 ns
tf Input signal fall time 1 8.5 ns
Cload Output load capacitance 40 pf
Table 6-90. McBSP Timing Requirements — TDM in Multipoint Mode
INDEX PARAMETER DESCRIPTION VDDSHV = 1.8V or 3.3V UNIT
MIN MAX
tw(CLKH) Cycle Time, mcbspx_clkx 162.8 ns
tw(CLKH) Typical Pulse duration, mcbspx_clkx high 81.4 ns
tw(CLKL) Typical Pulse duration, mcbspx_clkx low 81.4 ns
tdc(CLK) Duty cycle error, mcbspx_clkx -8.14 8.14 ns
B3 tsu(DRV-CLKAE) Setup time, mcbspx_dr valid before 9 ns
mcbspx_clkx active edge
B4 th(CLKAE-DRV) Hold time, mcbspx_dr valid after mcbspx_clkx 2.4 ns
active edge
B5 tsu(FSV-CLKAE) Setup time, mcbspx_fsx valid before 9 ns
mcbspx_clkx active edge
B6 th(CLKAE-FSV) Hold time, mcbspx_fsx valid after mcbspx_clkx 2.4 ns
active edge
Table 6-91. McBSP Switching Characteristics — TDM in Multipoint Mode
INDEX PARAMETER DESCRIPTION VDDSHV = 1.8V or 3.3V UNIT
MIN MAX
B8 td(CLKXAE-DXV) Delay time, mcbspx_clkx active edge to 0.6 16.8 ns
mcbspx_dx valid
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mcbspx_clkr
mcbspx_fsr
mcbspx_dr D7 D6 D5
B2 B2
B3 B4
030-068
mcbspx_clkr
mcbspx_fsr
mcbspx_dr D7 D6 D5
B3 B4
B5 B6
030-069
mcbspx_clkx
mcbspx_fsx
mcbspx_dx D7 D6 D5
B2 B2
B8
030-070
mcbspx_clkx
mcbspx_fsx
mcbspx_dx D7 D6 D5
B8
B5 B6
030-071
mcbspx_clkr
mcbspx_fsr
mcbspx_dr D7 D6 D5
B2 B2
B3 B4
030-072
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6.6.1.1.7 McBSP Timing Diagrams
Figure 6-37. McBSP Rising Edge Receive Timing in Master Mode
Figure 6-38. McBSP Rising Edge Receive Timing in Slave Mode
Figure 6-39. McBSP Rising Edge Transmit Timing in Master Mode
Figure 6-40. McBSP Rising Edge Transmit Timing in Slave Mode
Figure 6-41. McBSP Falling Edge Receive Timing in Master Mode
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mcbspx_clkr
mcbspx_fsr
mcbspx_dr D7 D6 D5
B3 B4
B5 B6
030-073
mcbspx_clkx
mcbspx_fsx
mcbspx_dx D7 D6 D5
B2 B2
B8
030-074
mcbspx_clkx
mcbspx_fsx
mcbspx_dx D7 D6 D5
B8
B5 B6
030-075
AM3517, AM3505
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012
Figure 6-42. McBSP Falling Edge Receive Timing in Slave Mode
Figure 6-43. McBSP Falling Edge Transmit Timing in Master Mode
Figure 6-44. McBSP Falling Edge Transmit Timing in Slave Mode
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6.6.2 Multichannel Serial Port Interface (McSPI) Timing
The multichannel SPI is a master/slave synchronous serial bus. The McSPI1 module supports up to four
peripherals and the others (McSPI2, McSPI3, and McSPI4) support up to two peripherals. The following
timings are applicable to the different configurations of McSPI in master/slave mode for any McSPI and
any channel (n).
6.6.2.1 McSPI in Slave Mode
The following tables assume testing over the recommended operating conditions.
Table 6-92. McSPI Interface Timing Requirements – Slave Mode
NO. PARAMETER 1.8 V 3.3 V UNIT
MIN MAX MIN MAX
SS0 tc(CLK) Cycle time, mcspix_clk 41.67 41.67 ns
SS1 tw(CLK) Pulse duration, mcspix_clk high or low 18.75 22.92 11.25 ns
SS2 tsu(SIMOV-CLKAE) Setup time, mcspix_simo valid before mcspix_clk 4.2 4 ns
active edge
SS3 th(SIMOV-CLKAE) Hold time, mcspix_simo valid after mcspix_clk active 4.6 3 ns
edge
SS4 tsu(CS0V-CLKFE) Setup time, mcspix_cs0 valid before mcspix_clk first 13.8 7 ns
edge
SS5 th(CS0I-CLKLE) Hold time, mcspix_cs0 invalid after mcspix_clk last 13.8 9.17 ns
edge
Table 6-93. McSPI Interface Switching Characteristics(1) (2) (3) (4)
NO. PARAMETER 1.8 V 3.3 V UNIT
MIN MAX MIN MAX
SS6 td(CLKAE-SOMIV) Delay time, mcspix_clk active edge to mcspix_somi 1.8 15.9 2 16.5 ns
shifted
SS7 td(CS0AE-SOMIV) Delay time, mcspix_cs0 active edge to Modes 0 and 2 16.38 15.9 ns
mcspix_somi shifted
(1) The capacitive load is equivalent to 20 pF.
(2) In mcspix, x is equal to 1, 2, 3, or 4.
(3) The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all
software configurable.
(4) This timing applies to all configurations regardless of mcspix_clk polarity and which clock edges are used to drive output data and
capture input data.
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mcspix_cs0(EPOL=1)
mcspix_clk(POL=0)
mcspix_clk(POL=1)
mcspix_simo
mcspix_somi
mcspix_cs0(EPOL=1)
mcspix_clk(POL=0)
mcspix_clk(POL=1)
mcspix_simo
mcspix_somi
Bitn-1 Bitn-2 Bitn-3 Bitn-4 Bit0
Bitn-1 Bitn-2 Bitn-3 Bitn-4 Bit0
Bitn-1 Bitn-2 Bitn-3 Bit1 Bit0
Bitn-1 Bitn-2 Bitn-3 Bit1 Bit0
SS4 SS5
SS6
SS3
SS1
SS0
SS2
SS1
SS0
SS4 SS5
SS3
SS1
SS0
SS1
SS0
SS2
SS6
SS7
Mode0&2
Mode1&3
030-076
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Figure 6-45. McSPI Interface Transmit and Receive in Slave Mode(1) (2)
(1) The active clock edge (rising or falling) on which mcspi_somi is driven and mcspi_simo data is latched is software configurable with the
bit MSPI_CHCONFx[0] = PHA and the bit MSPI_CHCONFx[1] = POL.
(2) The polarity of mcspix_csi is software configurable with the bit MSPI_CHCONFx[6] = EPOL In mcspix, x is equal to 1, 2, 3, or 4.
6.6.2.2 McSPI in Master Mode
The following tables assume testing over the recommended operating conditions.
Table 6-94. McSPI1, 2, and 4 Interface Timing Requirements – Master Mode(1) (2)
NO. PARAMETER 1.8 V 3.3 V UNIT
MIN MAX MIN MAX
SM2 tsu(SOMIV-CLKAE) Setup time, mcspix_somi valid before mcspix_clk 2.56 4 ns
active edge
SM3 th(SOMIV-CLKAE) Hold time, mcspix_somi valid after mcspix_clk active 2.93 4 ns
edge
(1) The input timing requirements are given by considering a rise time and a fall time of 4 ns.
(2) In mcspix, x is equal to 1, 2, 3, or 4. In mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 3.
n is equal to 0 for x equal to 4.
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Table 6-95. McSPI1, 2, and 4 Interface Switching Characteristics – Master Mode(1) (2) (3)
NO. PARAMETER 1.8 V 3.3 V UNIT
MIN MAX MIN MAX
SM0 tc(CLK) Cycle time, mcspix_clk 20.83 20.83 ns
tj(CLK) Cycle jitter(4), mcspix_clk -200 200 -200 200 ps
SM1 tw(CLK) Pulse duration, mcspix_clk high or low 0.45P(5) 0.55P(5) 0.45P(5) 0.55P(5) ns
SM4 td(CLKAE-SIMOV) Delay time, mcspix_clk active edge to -2.1 5 -3 6 ns
mcspix_simo shifted
SM5 td(CSnA-CLKFE) Delay time, mcspix_csi active to Modes 1 A(6) - 3.2 A(6) - 3.0 6 ns
mcspix_clk first edge and 3
Modes 0 B(7) - 3.2 B(7) -3.0 6 ns
and 2
SM6 td(CLKLE-CSnI) Delay time, mcspix_clk last edge to Modes 1 B(7) - 3.2 B(7) - 3.0 ns
mcspix_csi inactive and 3
Modes 0 A(6) - 3.2 A(6) - 3.0 ns
and 2
SM7 td(CSnAE-SIMOV) Delay time, mcspix_csi active edge Modes 0 5 5 ns
to mcspix_simo shifted and 2
(1) Timings are given for a maximum load capacitance of 20 pF for spix_csn signals, 30 pF for spix_clk and spix_simo signals with x = 1 or
2, and 20 pF for spi4_clk and spi4_simo signals.
(2) In mcspix, x is equal to 1, 2, 3, or 4. In mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 3.
n is equal to 0 for x equal to 4.
(3) The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all
software configurable.
(4) Maximum cycle jitter supported by mcspix_clk input clock.
(5) P = mcspix_clk clock period
(6) Case P = 20.8 ns, A = (TCS+0.5)*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). Case P > 20.8 ns, A = TCS*P (TCS is a
bitfield of MSPI_CHCONFx[26:25] register). For more information, see the Device Multichannel Serial Port Interface (McSPI) Reference
Guide [literature number SPRUFV6].
(7) B = TCS*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). For more information, see the Device Multichannel Serial Port
Interface (McSPI) Reference Guide [literature number SPRUFV6].
The following tables assume testing over the recommended operating conditions.
Table 6-96. McSPI 3 Interface Timing Requirements – Master Mode(1) (2)
NO. PARAMETER 1.8 V 3.3 V UNIT
MIN MAX MIN MAX
SM2 tsu(SOMIV-CLKAE) Setup time, mcspi3_somi valid before 2.5 4 ns
mcspi3_clk active edge
SM3 th(SOMIV-CLKAE) Hold time, mcspi3_somi valid after mcspi3_clk 2.89 4 ns
active edge
(1) The input timing requirements are given by considering a rise time and a fall time of 4 ns.
(2) In mcspi3_csn, n is equal to 0 or 1. The polarity of mcspi3_clk and the active edge (rising or falling) on which mcspi3_simo is driven and
mcspi3_somi is latched is all software configurable.
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Table 6-97. McSPI3 Interface Switching Characteristics – Master Mode(1) (2) (3)
NO. PARAMETER 1.8 V 3.3 V UNIT
MIN MAX MIN MAX
SM0 tc(CLK) Cycle time, mcspix_clk 41.67 41.67 ns
tj(CLK) Cycle jitter(4) -200 200 -200 200 ps
SM1 tw(CLK) Pulse duration, mcspix_clk high or low 0.45P(5) 0.55P(5) 0.45P(5) 0.55P(5) ns
SM4 td(CLKAE-SIMOV) Delay time, mcspix_clk active edge to -2.1 11.3 -3 ns
mcspix_simo shifted
SM5 td(CSnA-CLKFE) Delay time, mcspix_csi active Modes 1 A(6) - 4.4 A(6) - 3.0 6 ns
to mcspix_clk first edge and 3
Modes 0 B(7) - 4.4 B(7) - 3.0 6 ns
and 2
SM6 td(CLKLE-CSnI) Delay time, mcspix_clk last Modes 1 B(7) - 4.4 B(7) - 3.0 ns
edge to mcspix_csi inactive and 3
Modes 0 A(6) - 4.4 A(6) - 3.0 ns
and 2
SM7 td(CSnAE-SIMOV) Delay time, mcspix_csi active Modes 0 11.3 5 ns
edge to mcspix_simo shifted and 2
(1) The capacitive load is equivalent to 20 pF.
(2) In mcspi3_csn, n is equal to 0 or 1. The polarity of mcspi3_clk and the active edge (rising or falling) on which mcspi3_simo is driven and
mcspi3_somi is latched are all software configurable.
(3) This timing applies to all configurations regardless of McSPI3_CLK polarity and which clock edges are used to drive output data and
capture input data.
(4) Maximum cycle jitter supported by mcspix_clk input clock.
(5) P = mcspix_clk clock period.
(6) Case P = 20.8 ns, A = (TCS + 0.5)*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). Case P > 20.8 ns, A = TCS*P (TCS is a bit
field of MSPI_CHCONFx[26:25] register). For more information, see the Device Multichannel Serial Port Interface (McSPI) Reference
Guide [literature number SPRUFV6].
(7) B = TCS*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). For more information, see the Device Multichannel Serial Port
Interface (McSPI) Reference Guide [literature number SPRUFV6].
Copyright © 2009–2012, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 177
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mcspix_csn(EPOL=1)
mcspix_clk(POL=0)
mcspix_clk(POL=1)
mcspix_simo
mcspix_somi
mcspix_csn(EPOL=1)
mcspix_clk(POL=0)
mcspix_clk(POL=1)
mcspix_simo
mcspix_somi
Bitn-1 Bitn-2 Bitn-3 Bitn-4 Bit0
Bitn-1 Bitn-2 Bitn-3 Bitn-4 Bit0
Bitn-1 Bitn-2 Bitn-3 Bit1 Bit0
Bitn-1 Bitn-2 Bitn-3 Bit1 Bit0
SM5 SM6
SM4
SM3
SM1
SM0
SM2
SM1
SM0
SM5 SM6
SM3
SM1
SM0
SM1
SM0
SM2
SM4
SM7
Mode0&2
Mode1&3
030-077
AM3517, AM3505
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Figure 6-46. McSPI Interface Transmit and Receive in Master Mode(1) (2) (3)
(1) The active clock edge (rising or falling) on which mcspix_simo is driven and mcspi_somi data is latched is software configurable with the
bit MSPI_CHCONFx[0] = PHA and the bit MSPI_CHCONFx[1] = POL.
(2) The polarity of mcspix_csi is software configurable with the bit MSPI_CHCONFx[6] = EPOL.
(3) In mcspix, x is equal to 1. In mcspix_csn, n is equal to 0, 1, 2, or 3.
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6.6.3 Multiport Full-Speed Universal Serial Bus (USB) Interface
The AM3517/05 microprocessor provides three USB ports working in full- and low-speed data transactions
(up to 12Mbit/s).
Connected to either a serial link controller or a serial PHY (PHY interface modes) it supports:
• 6-pin (Tx: Dat/Se0 or Tx: Dp/Dm) unidirectional mode
• 4-pin bidirectional mode
• 3-pin bidirectional mode
6.6.3.1 Multiport Full-Speed Universal Serial Bus (USB) – Unidirectional Standard 6-pin Mode
The following tables assume testing over the recommended operating conditions.
Table 6-98. Low-/Full-Speed USB Timing Conditions Unidirectional Standard 6-pin Mode
TIMING CONDITION PARAMETER 1.8V, 3.3V UNIT
Input Conditions
tRInput signal rise time 2.0 ns
tFInput signal fall time 2.0 ns
Output Conditions
CLOAD Output load capacitance 15.0 pF
Table 6-99. Low-/Full-Speed USB Timing Requirements Unidirectional Standard 6-pin Mode
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
FSU1 td(Vp,Vm) Time duration, mmx_rxdp and mmx_rxdm low together during transition 14.0 ns
FSU2 td(Vp,Vm) Time duration, mmx_rxdp and mmx_rxdm high together during transition 8.0 ns
FSU3 td(RCVU0) Time duration, mmx_rrxcv undefine during a single end 0 (mmx_rxdp and 14.0 ns
mmx_rxdm low together)
FSU4 td(RCVU1) Time duration, mmx_rxrcv undefine during a single end 1 (mmx_rxdp and 8.0 ns
mmx_rxdm high together)
Table 6-100. Low-/Full-Speed USB Switching Characteristics Unidirectional Standard 6-pin Mode
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
FSU5 td(TXENL-DATV) Delay time, mmx_txen_n low to mmx_txdat valid 81.8 84.8 ns
FSU6 td(TXENL-SE0V) Delay time, mmx_txen_n low to mmx_txse0 valid 81.8 84.8 ns
FSU7 ts(DAT-SE0) Skew between mmx_txdat and mmx_txse0 transition 1.5 ns
FSU8 td(DATI-TXENH) Delay time, mmx_txdat invalid to mmx_txen_n high 81.8 ns
FSU9 td(SE0I-TXENH) Delay time, mmx_txse0 invalid to mmx_txen_n high 81.8 ns
tR(do) Rise time, mmx_txen_n 4.0 ns
tF(do) Fall time, mmx_txen_n 4.0 ns
tR(do) Rise time, mmx_txdat 4.0 ns
tF(do) Fall time, mmx_txdat 4.0 ns
tR(do) Rise time, mmx_txse0 4.0 ns
tF(do) Fall time, mmx_txse0 4.0 ns
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mmx_rxrcv
FSU5
FSU6 FSU7
FSU1
FSU1
FSU2
FSU2
FSU3 FSU4
FSU8
FSU9
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In mmx, x is equal to 0, 1, or 2.
Figure 6-47. Low-/Full-Speed USB Unidirectional Standard 6-pin Mode
6.6.3.2 Multiport Full-Speed Universal Serial Bus (USB) – Bidirectional Standard 4-pin Mode
The following tables assume testing over the recommended operating conditions.
Table 6-101. Low-/Full-Speed USB Timing Conditions Bidirectional Standard 4-pin Mode
TIMING CONDITION PARAMETER 1.8V, 3.3V UNIT
Input Conditions
tRInput signal rise time 2.0 ns
tFInput signal fall time 2.0 ns
Output Conditions
CLOAD Output load capacitance 15.0 pF
Table 6-102. Low-/Full-Speed USB Timing Requirements Bidirectional Standard 4-pin Mode
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
FSU10 td(DAT,SE0) Time duration, mmx_txdat and mmx_txse0 low together during 14.0 ns
transition
FSU11 td(DAT,SE0) Time duration, mmx_txdat and mmx_txse0 high together during 8.0 ns
transition
FSU12 td(RCVU0) Time duration, mmx_rrxcv undefine during a single end 0 14.0 ns
(mmx_txdat and mmx_txse0 low together)
FSU13 td(RCVU1) Time duration, mmx_rxrcv undefine during a single end 1 8.0 ns
(mmx_txdat and mmx_txse0 high together)
Table 6-103. Low-/Full-Speed USB Switching Characteristics Bidirectional Standard 4-pin Mode
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
FSU14 td(TXENL-DATV) Delay time, mmx_txen_n low to mmx_txdat valid 81.8 84.8 ns
FSU15 td(TXENL-SE0V) Delay time, mmx_txen_n low to mmx_txse0 valid 81.8 84.8 ns
FSU16 ts(DAT-SE0) Skew between mmx_txdat and mmx_txse0 transition 1.5 ns
FSU17 td(DATV-TXENH) Delay time, mmx_txdat invalid before mmx_txen_n high 81.8 ns
FSU18 td(SE0V-TXENH) Delay time, mmx_txse0 invalid before mmx_txen_n high 81.8 ns
tR(txen) Rise time, mmx_txen_n 4.0 ns
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FSU16
FSU14
FSU15
FSU10
FSU10
FSU11
FSU11
FSU12 FSU13
FSU17
FSU18
Transmit Receive
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Table 6-103. Low-/Full-Speed USB Switching Characteristics Bidirectional Standard 4-pin
Mode (continued)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
tF(txen) Fall time, mmx_txen_n 4.0 ns
tR(dat) Rise time, mmx_txdat 4.0 ns
tF(dat) Fall time, mmx_txdat 4.0 ns
tR(se0) Rise time, mmx_txse0 4.0 ns
tF(se0) Fall time, mmx_txse0 4.0 ns
In mmx, x is equal to 0, 1, or 2.
Figure 6-48. Low-/Full-Speed USB Bidirectional Standard 4-pin Mode
6.6.3.3 Multiport Full-Speed Universal Serial Bus (USB) – Bidirectional Standard 3-pin Mode
The following tables assume testing over the recommended operating conditions.
Table 6-104. Low-/Full-Speed USB Timing Conditions Bidirectional Standard 3-pin Mode
TIMING CONDITION PARAMETER 1.8V, 3.3V UNIT
Input Conditions
tRInput signal rise time 2.0 ns
tFInput signal fall time 2.0 ns
Output Conditions
CLOAD Output load capacitance 15.0 pF
Table 6-105. Low-/Full-Speed USB Timing Requirements Bidirectional Standard 3-pin Mode
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
FSU19 td(DAT,SE0) Time duration, mmx_txdat and mmx_txse0 low together during 14.0 ns
transition
FSU20 td(DAT,SE0) Time duration, mmx_tsdat and mmx_txse0 high together during 8.0 ns
transition
Table 6-106. Low-/Full-Speed USB Switching Characteristics Bidirectional Standard 3-pin Mode
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
FSU21 td(TXENL-DATV) Delay time, mmx_txen_n low to mmx_txdat valid 81.8 84.8 ns
FSU22 td(TXENL-SE0V) Delay time, mmx_txen_n low to mmx_txse0 valid 81.8 84.8 ns
FSU23 ts(DAT-SE0) Skew between mmx_txdat and mmx_txse0 transition 1.5 ns
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FSU21
FSU22
FSU19
FSU19
FSU20
FSU20
FSU24
FSU25
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Table 6-106. Low-/Full-Speed USB Switching Characteristics Bidirectional Standard 3-pin
Mode (continued)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
FSU24 td(DATI-TXENH) Delay time, mmx_txdat invalid to mmx_txen_n high 81.8 ns
FSU25 td(SE0I-TXENH) Delay time, mmx_txse0 invalid to mmx_txen_n high 81.8 ns
tR(do) Rise time, mmx_txen_n 4.0 ns
tF(do) Fall time, mmx_txen_n 4.0 ns
tR(do) Rise time, mmx_txdat 4.0 ns
tF(do) Fall time, mmx_txdat 4.0 ns
tR(do) Rise time, mmx_txse0 4.0 ns
tF(do) Fall time, mmx_txse0 4.0 ns
In mmx, x is equal to 0, 1, or 2.
Figure 6-49. Low-/Full-Speed USB Bidirectional Standard 3-pin Mode
6.6.4 Multiport High-Speed Universal Serial Bus (USB) Timing
In addition to the full-speed USB controller, a high-speed (HS) USB controller is instantiated inside the
AM3517/05. It allows high-speed transactions (up to 480 Mbit/s) on the USB ports 1 and 2.
• Port 1 and port 2:
– 12-bit master mode (SDR)
6.6.4.1 High-Speed Universal Serial Bus (USB) on Ports 1 and 2 12-bit Master Mode
The following tables assume testing over the recommended operating conditions.
Table 6-107. High-Speed USB Timing Conditions 12-bit Master Mode
TIMING CONDITION PARAMETER 1.8V, 3.3V UNIT
Input Conditions
tRInput signal rise time 2 ns
tFInput signal fall time 2 ns
Output Conditions
CLOAD Output load capacitance 3 pF
Table 6-108. High-Speed USB Timing Requirements 12-bit Master Mode(1)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
HSU3 ts(DIRV-CLKH) Setup time, hsusbx_dir valid before hsusbx_clk rising edge 7.5 ns
ts(NXTV-CLKH) Setup time, hsusbx_nxt valid before hsusbx_clk rising edge 7.5 ns
HSU4 th(CLKH-DIRIV) Hold time, hsusbx_dir valid after hsusbx_clk rising edge 0.2 ns
(1) In hsusbx, x is equal to 1 or 2.
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HSU1
HSU0
HSU1
HSU4
HSU2 HSU2 HSU6
HSU3
HSU5
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Table 6-108. High-Speed USB Timing Requirements 12-bit Master Mode(1) (continued)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
th(CLKH-NXT/IV) Hold time, hsusbx_nxt valid after hsusbx_clk rising edge 0.2 ns
HSU5 ts(DATAV-CLKH) Setup time, hsusbx_data[0:7] valid before hsusbx_clk rising edge 7.5 ns
HSU6 th(CLKH-DATIV) Hold time, hsusbx_data[0:7] valid after hsusbx_clk rising edge 0.2 ns
Table 6-109. High-Speed USB Switching Characteristics 12-bit Master Mode(1)
N O. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
HSU0 fp(CLK) hsusbx_clk clock frequency 60 MHz
tj(CLK) Jitter standard deviation(2), hsusbx_clk 200 ps
HSU1 td(CLKH-STPV) Delay time, hsusbx_clk high to output hsusbx_stp valid 13 ns
td(CLKH-STPIV) Delay time, hsusbx_clk high to output hsusbx_stp invalid 2 ns
HSU2 td(CLKH-DV) Delay time, hsusbx_clk high to output hsusbx_data[0:7] valid 13 ns
td(CLKH-DIV) Delay time, hsusbx_clk high to output hsusbx_data[0:7] invalid 2 ns
tR(do) Rise time, output signals 2 ns
tF(do) Fall time, output signals 2 ns
(1) In hsusbx, x is equal to 1 or 2.
(2) The jitter probability density can be approximated by a Gaussian function.
In hsusbx, x is equal to 1 or 2.
Figure 6-50. High-Speed USB 12-bit Master Mode
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6.6.5 USB0 OTG (USB2.0 OTG)
The AM3517/05 USB2.0 peripheral supports the following features:
• USB 2.0 peripheral at speeds high speed (HS: 480 Mb/s) and full speed (FS: 12 Mb/s)
• USB 2.0 host at speeds HS, FS, and low speed (LS: 1.5 Mb/s)
• All transfer modes (control, bulk, interrupt, and isochronous)
• 16 Transmit (TX) and 16 Receive (RX) endpoints in addition to endpoint 0
• FIFO RAM
– 32K endpoint
– Programmable size
• Integrated USB 2.0 High Speed PHY
• Connects to a standard Charge Pump for VBUS 5 V generation
• RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB
6.6.5.1 USB OTG Electrical Parameters
The USB OTG electrical parameters meet or exceed those specified in the following documents which can
be obtained from the USB Implementers Forum:
•Universal Serial Bus Specification, Revision 2.0, April 27, 2000
•On-The-Go Supplement to the USB 2.0 Specification, Revision 1.3, December 5, 2006
•Engineering Change Notice “Pull-up/pull-down resistors”, Universal Serial Bus Specification Revision
2.0
For additional information related to USB OTG electrical parameters, please see the respective
documents on the USB Implementers Forum web site (http://www.usb.org).
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6.6.6 High-End Controller Area Network Controller (HECC) Timing
The AM3517/05 device has a High-End Controller Area Network Controller (HECC). The HECC uses
established protocol to communicate serially with other controllers in harsh environments. The HECC is
fully compliant with the Controller Area Network (CAN) protocol, version 2.0B.
Key features of the HECC include the following:
• CAN, version 2.0B compliant
• 32 RX/TX message objects
• 32 receive identifier masks
• Programmable wake-up on bus activity
• Programmable interrupt scheme
• Automatic reply to a remote request
• Automatic re-transmission in case of error or loss of arbitration
• Protection against reception of a new message
• 32-bit time stamp
• Local network time counter
• Programmable priority register for each message
• Programmable transmission and reception time-out
• HECC/SCC mode of operation
• Standard-Extended Identifier
• Self-test mode
6.6.6.1 HECC Timing Requirements
Table 6-110. Timing Requirements for HECC Receive (see Figure 6-51)
1.8 V, 3.3 V
NO. UNIT
MIN MAX
1 f(baud) Maximum programmable baud rate 1 Mbps
2 tw(HECC_RX) Pulse duration, receive data bit H-1(1) H+3(1) ns
(1) These values are relative to H (where H = 1/(baud rate).
6.6.6.2 HECC Switching Characteristics
Table 6-111. Switching Characteristics Over Recommended Operating Conditions for HECC Transmit
(see Figure 6-51)
1.8 V, 3.3 V
NO. PARAMETER UNIT
MIN MAX
3 f(baud) Maximum programmable baud rate 1 Mbps
4 tw(HECC_TX) Pulse duration, transmit data bit H-1(1) H+3(1) ns
(1) These values are relative to H (where H = 1/(baud rate).
Figure 6-51. HECC Transmit/Receive Timing
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6.6.7 Ethernet Media Access Controller (EMAC)
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the AM3517/05 and
the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100
Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.
The EMAC controls the flow of packet data from the AM3517/05 device to the PHY. The MDIO module
controls PHY configuration and status monitoring.
Both the EMAC and the MDIO modules interface to the AM3517/05 device through a custom interface that
allows efficient data transmission and reception. This custom interface is referred to as the EMAC control
module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to
multiplex and control interrupts.
6.6.7.1 EMAC Electrical Data/ Timing
The following tables assume testing over the recommended operating conditions.
Table 6-112. RMII Input Timing Requirements
1.8V, 3.3V
NO. PARAMETER MIN TYP MAX UNIT
fc(REFCLK) Frequency, REF_CLK 50 MHz
ft (REFCLK) Frequency stability, REF_CLK +/-50 ppm
1 tc(REFCLK) Cycle Time, REF_CLK 20 ns
2 tw(REFCLKH) Pulse Width, REF_CLK High 7 13 ns
3 tw(REFCLKL) Pulse Width, REF_CLK Low 7 13 ns
6 tsu(RXD-REFCLK) Input Setup Time, RXD Valid before REF_CLK 4 ns
High
7 th(REFCLK-RXD) Input Hold Time, RXD Valid after REF_CLK High 2 ns
8 tsu(CRSDV-REFCLK) Input Setup Time, CRSDV Valid before 4 ns
REF_CLK High
9 th(REFCLK-CRSDV) Input Hold Time, CRSDV Valid after REF_CLK 2 ns
High
10 tsu(RXER-REFCLK) Input Setup Time, RXER Valid before REF_CLK 4 ns
High
11 th(REFCLKR-RXER) Input Hold Time, RXER Valid after REF_CLK 2 ns
High
Table 6-113. RMII Timing Conditions
TIMING CONDITION PARAMETER 1.8V, 3.3V UNIT
Input Conditions MIN MAX
tRInput signal rise time 1 5 ns
tFInput signal fall time 1 5 ns
Output Conditions
CLOAD Output load capacitance 5.5 pF
Table 6-114. RMII Output Switching Characteristics
1.8V, 3.3V
NO. PARAMETER MIN TYP MAX UNIT
4 td(REFCLK-TXD) Output Delay Time, REF_CLK High to TXD Valid 2.5 13 ns
5 td(REFCLK-TXEN) Output Delay Time, REF_CLK High to TXEN 2.5 13 ns
Valid
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1
2 3
5
4
6
7
9
10
11
5
REF_CLK
TXEN
TXD[1:0]
RXD[1:0]
CRS_DV
8
RXER_IN
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Figure 6-52. RMII Timing Diagram
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MDIO_D
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6.6.8 Management Data Input/Output (MDIO)
The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system.
The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to
interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO
module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the
negotiation results, and configure required parameters in the EMAC module for correct operation. The
module is designed to allow almost transparent operation of the MDIO interface, with very little
maintenance from the core processor. Only one PHY may be connected at any given time.
6.6.8.1 Management Data Input/Output (MDIO) Electrical Data/Timing
Table 6-115. Timing Requirements for MDIO Input (see Figure 6-53 and Figure 6-54)
No. PARAMETER UNIT
MIN MAX
1 tc(MD_CLK) Cycle time, MD_CLK 400 ns
4 tsu(MDIO-MDCLKH) Setup time, MDIO data input valid before MD_CLK high 20 ns
5 th(MDCLKH-MDIO) Hold time, MDIO data input valid after MDCLK high 0 ns
Figure 6-53. MDIO Input Timing
Table 6-116. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
(see Figure 6-54)
No. PARAMETER UNIT
MIN MAX
7 td(MDCLKL-MDIO) Delay time, MDCLK low to MDIO data output valid 0 100 ns
Figure 6-54. MDIO Output Timing
6.6.9 Universal Asynchronous Receiver/Transmitter (UART)
The AM3517/05 has four UARTs (one with Infrared Data Association [IrDA] and Consumer Infrared [CIR]
modes).
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Table 6-117. Timing Requirements for UARTx Receive(1)
1.8V, 3.3V
NO. UNIT
MIN MAX
4 tw(URXDB) Pulse duration, receive data bit (RXDn) .96U 1.05U ns
5 tw(URXSB) Pulse duration, receive start bit .96U 1.05U ns
(1) U = UART baud time = 1/programmed baud rate.
Table 6-118. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit(1)
1.8V, 3.3V
NO. PARAMETER UNIT
MIN MAX
UART0 Maximum programmable baud rate f(baud_15) 5
1 f(baud) UART0 Maximum programmable baud rate f(baud_30) 0.23 mbps
UART0 Maximum programmable baud rate f(baud_100) 0.115
2 tw(UTXDB) Pulse duration, transmit data bit, 15/30/100 pF U - 2 U + 2 ns
3 tw(UTXSB) Pulse duration, transmit start bit, 15/30/100 pF U - 2 U + 2 ns
(1) U = UART baud time = 1/programmed baud rate.
Figure 6-55. UART Transmit/Receive Timing
6.6.9.1 UART IrDA Interface
The IrDA module can operate in three different modes:
• Slow infrared (SIR) (≤115.2 Kbits/s)
• Medium infrared (MIR) (0.576 Mbits/s and 1.152 Mbits/s)
• Fast infrared (FIR) (4 Mbits/s)
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50%
10%
tf
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10%
tr
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Figure 6-56. UART IrDA Pulse Parameters
6.6.9.1.1 IrDA—Receive Mode
Table 6-119. UART IrDA—Signaling Rate and Pulse Duration—Receive Mode
ELECTRICAL PULSE DURATION
SIGNALING RATE UNIT
MIN NOMINAL MAX
SIR
2.4 Kbit/s 1.41 78.1 88.55 μs
9.6 Kbit/s 1.41 19.5 22.13 μs
19.2 Kbit/s 1.41 9.75 11.07 μs
38.4 Kbit/s 1.41 4.87 5.96 μs
57.6 Kbit/s 1.41 3.25 4.34 μs
115.2 Kbit/s 1.41 1.62 2.23 μs
MIR
0.576 Mbit/s 297.2 416 518.8 ns
1.152 Mbit/s 149.6 208 258.4 ns
FIR
4.0 Mbit/s (Single pulse) 67 125 164 ns
4.0 Mbit/s (Double pulse) 190 250 289 ns
Table 6-120. UART IrDA—Rise and Fall Time—Receive
Mode
PARAMETER MAX UNIT
tRRising time, 200 ns
uart3_rx_irrx
tFFalling time, 200 ns
uart3_rx_irrx
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6.6.9.1.2 IrDA—Transmit Mode
Table 6-121. UART IrDA—Signaling Rate and Pulse Duration—Transmit Mode
SIGNALING RATE ELECTRICAL PULSE DURATION UNIT
MIN NOMINAL MAX
SIR
2.4 Kbit/s 78.1 78.1 78.1 μs
9.6 Kbit/s 19.5 19.5 19.5 μs
19.2 Kbit/s 9.75 9.75 9.75 μs
38.4 Kbit/s 4.87 4.87 4.87 μs
57.6 Kbit/s 3.25 3.25 3.25 μs
115.2 Kbit/s 1.62 1.62 1.62 μs
MIR
0.576 Mbit/s 414 416 419 ns
1.152 Mbit/s 206 208 211 ns
FIR
4.0 Mbit/s (Single pulse) 123 125 128 ns
4.0 Mbit/s (Double pulse) 248 250 253 ns
6.6.10 HDQ / 1-Wire Interfaces
This module is intended to work with both the HDQ and the 1-Wire protocols. The protocols use a single
wire to communicate between the master and the slave. The protocols employ an asynchronous return to
1 mechanism where, after any command, the line is pulled high.
6.6.10.1 HDQ Protocol
Table 6-122 and Table 6-123 assume testing over the recommended operating conditions (see Figure 6-
57 through Figure 6-60).
Table 6-122. HDQ Timing Requirements
PARAMETER DESCRIPTION MIN MAX UNIT
tCYCD Bit window 253 s
tHW1 Reads 1 68
tHW0 Reads 0 180
tRSPS Command to host respond time(1)
(1) Defined by software.
Table 6-123. HDQ Switching Characteristics
PARAMETER DESCRIPTION MIN TYP MAX UNIT
tBBreak timing 193 s
tBR Break recovery 63
tCYCH Bit window 253
tDW1 Sends1 (write) 1.3
tDW0 Sends0 (write) 101
Figure 6-57. HDQ Break (Reset) Timing
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HDQ
tHW1
tHW0
tCYCH
030-096
HDQ
tDW1
tDW0
tCYCD
030-097
HDQ
Break
0_(LSB )
1 6 7_(MSB)
tRSPS
0_(LSB )
1
6
Command _byte_written Data_byte _received
030-098
1-WIRE
tRSTH
tPDLtPDHtRTSL
030-099
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Figure 6-58. HDQ Read Bit Timing (Data)
Figure 6-59. HDQ Write Bit Timing (Command/Address or Data)
Figure 6-60. HDQ Communication Timing
6.6.10.2 1-Wire Protocol
Table 6-124 and Table 6-125 assume testing over the recommended operating conditions (see Figure 6-
61 through Figure 6-63).
Table 6-124. 1-Wire Timing Requirements
PARAMETER DESCRIPTION MIN MAX UNIT
tPDH Presence pulse delay high 68 s
tPDL Presence pulse delay low 68 tPDH
tRDV + tREL Read bit-zero time 102
Table 6-125. 1-Wire Switching Characteristics
PARAMETER DESCRIPTION MIN TYP MAX UNIT
tRSTL Reset time low 484 s
tRSTH Reset time high 484
tSLOT Write bit cycle time 102
tLOW1 Write bit-one time 1.3
tLOW0 Write bit-zero time 101
tREC Recovery time 134
tLOWR Read bit strobe time 13
Figure 6-61. 1-Wire Break (Reset) Timing
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1-WIRE tLOWR
tRDV_and_ tREL
tSLOT_and_ tREC
030-100
1-WIRE tLOW1
tLOW0
tSLOT_and_tREC
030-101
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Figure 6-62. 1-Wire Read Bit Timing (Data)
Figure 6-63. 1-Wire Write Bit Timing (Command/Address or Data)
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6.6.11 I2C Interface
The multimaster I2C peripheral provides an interface between two or more devices via an I2C serial bus.
The I2C controller supports the multimaster mode which allows more than one device capable of
controlling the bus to be connected to it. Each I2C device is recognized by a unique address and can
operate as either transmitter or receiver, according to the function of the device. In addition to being a
transmitter or receiver, a device connected to the I2C bus can also be considered as master or slave when
performing data transfers. This data transfer is carried out via two serial bidirectional wires:
• An SDA data line
• An SCL clock line
The following sections illustrate the data transfer is in master or slave configuration with 7-bit addressing
format. The I2C interface is compliant with Philips I2C specification version 2.1. It supports standard mode
(up to 100K bits/s), fast mode (up to 400K bits/s) and high-speed mode (up to 3.4Mb/s) .
6.6.11.1 I2C Standard/Fast-Speed Mode
Table 6-126. I2C Standard/Fast-Speed Mode Timings
1.8V, 3.3-V
NO. PARAMETER(1) STANDARD FAST MODE UNIT
MODE
MIN MAX MIN MAX
fSCL Clock Frequency, i2cX_scl 100 400 kHz
I1 tw(SCLH) Pulse Duration, i2cX_scl high 4 0.6 s
I2 tw(SCLL) Pulse Duration, i2cX_scl low 4.7 1.3 s
I3 tsu(SDAV-SCLH) Setup time, i2cX_sda valid before i2cX_scl active level 250 100(2) ns
I4 th(SCLHSDAV) Hold time, i2cX_sda valid after i2cX_scl active level 3.45(3) 0.9(3) s
I5 tsu(SDAL-SCLH) Setup time, i2cX_scl high after i2cX_sda low (for a 4.7 0.6 s
START(4) condition or a repeated START condition)
I6 th(SCLHSDAH) Hold time, i2cX_sda low level after i2cX_scl high level 4 0.6 s
(STOP condition)
I7 th(SCLHRSTART) Hold time, i2cX_sda low level after i2cX_scl high level (for 4 0.6 s
a repeated START condition)
I8 tw(SDAH) Pulse duration, i2cX_sda high between STOP and START 4.7 1.3 s
conditions
tR(SCL) Rise time, i2cX_scl 1000 300 ns
tF(SCL) Fall time, i2cX_scl 300 300 ns
tR(SDA) Rise time, i2cX_sda 1000 300 ns
tF(SDA) Fall time, i2cX_sda 300 300 ns
CB Capacitive load for each bus line 60 60 pF
(1) In i2cX, X is equal to 1, 2, or 3.
(2) A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDAV-SCLH) 250 ns must then be
met. This is automatically the case if the device does not stretch the low period of the i2cx_scl. If such a device does stretch the low
period of the i2cx_scl, it must output the next data bit to the i2cx_sda line tr(SDA) max + tsu(SDAV-SCLH) = 1000 + 250 = 1250 ns (according
to the standard-mode I2C-bus specification) before the i2cx_scl line is released.
(3) The maximum th(SCLH-SDA) has only to be met if the device does not stretch the low period of the i2cx_scl signal.
(4) After this time, the first clock is generated.
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i2cX_sda
i2cX_scl
START REPEAT
STOPSTART
START
I1
I2
I3 I4
I5
I6I6 I7
I8
030-093
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Figure 6-64. I2C Standard/Fast Mode
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i2cX_sda
i2cX_scl
STOPSTART REPEAT
I1 I2 I3 I4I6I5 I7
030-094
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6.6.11.2 I2C High-Speed Mode
Table 6-127. I2C High-Speed Mode Timings(1) (2)
1.8V, 3.3V
NO. PARAMETER UNIT
MIN MAX
fSCL Clock frequency, i2cX_scl 3.4 MHz
I1 tw(SCLH) Pulse duration, i2cX_scl high 60(3) s
I2 tw(SCLL) Pulse duration, i2cX_scl low 160(3) s
I3 tsu(SDAV-SCLH) Setup time, i2cX_sda valid before i2cX_scl active level 10 ns
I4 th(SCLHSDAV) Hold time, i2cX_sda valid after i2cX_scl active level 70 s
I5 tsu(SDAL-SCLH) Setup time, i2cX_scl high after i2cX_sda low 160 s
(for a START(4) condition or a repeated START
condition)
I6 th(SCLHSDAH) Hold time, i2cX_sda low level after i2cX_scl high level 160 s
(STOP condition)
I7 th(SCLHRSTART) Hold time, i2cX_sda low level after i2cX_scl high level 160 ns
(for a repeated START condition)
tR(SCL) Rise time, i2cX_scl 10 40 ns
tR(SCL) Rise time, i2cX_scl after a repeated START condition 10 80 ns
and after a bit acknowledge
tF(SCL) Fall time, i2cX_scl 10 40 ns
tR(SDA) Rise time, i2cX_sda 10 80 ns
tF(SDA) Fall time, i2cX_sda 10 80 ns
(1) In i2cX, X is equal to 1, 2, or 3.
(2) The device provides (via the I2C bus) a hold time of at least 300 ns for the i2cx_sda signal (refer to the fall and rise time of i2cx_scl) to
bridge the undefined region of the falling edge of i2cx_scl.
(3) HS-mode master devices generate a serial clock signal with a high to low ratio of 1 to 2. tw(SCLL) > 2 tw(SCLH).
(4) After this time, the first clock is generated.
Figure 6-65. I2C High-Speed Mode(1) (2) (3)
(1) HS-mode master devices generate a serial clock signal with a high-to-low ratio of 1 to 2. tw(SCLL) > 2 x tw(SCLH).
(2) In i2cX, X is equal to 1, 2, or 3.
(3) After this time, the first clock is generated.
Table 6-128. Correspondence Standard vs. TI Timing References
AM3517/05 STANDARD-I2C
S/F Mode HS Mode
fSCL FSCL FSCLH
I1 tw(SCLH) THIGH THIGH
I2 tw(SCLL) TLOW TLOW
I3 tsu(SDAV-SCLH) TSU;DAT TSU;DAT
I4 th(SCLH-SDAV) TSU;DAT TSU;DAT
I5 tsu(SDAL-SCLH) TSU;STA TSU;STA
I6 th(SCLH-SDAH) THD;STA THD;STA
I7 th(SCLH-RSTART) TSU;STO TSU;STO
I8 tw(SDAH) TBUF
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6.7 Removable Media Interfaces
6.7.1 High-Speed Multimedia Memory Card (MMC) and Secure Digital IO Card (SDIO) Timing
The MMC/SDIO host controller provides an interface to high-speed and standard MMC, SD memory
cards, or SDIO cards. The application interface is responsible for managing transaction semantics. The
MMC/SDIO host controller deals with MMC/SDIO protocol at transmission level, packing data, adding
CRC, start/end bit, and checking for syntactical correctness.
There are three MMC interfaces on the AM3517/05:
• MMC/SD/SDIO Interface 1:
– 1.8-V/3.3-V support
– 8 bits
• MMC/SD/SDIO Interface 2:
– 1.8-V/3.3-V support
– 8 bits
– 4 bits with external transceiver allowing to support 1.8-V/3.3-V peripherals in 1.8-V mode operation.
Transceiver direction control signals are multiplexed with the upper four data bits.
• MMC/SD/SDIO Interface 3:
– 1.8-V/3.3-V support
– 8 bits
6.7.1.1 MMC/SD/SDIO in SD Identification Mode
The following tables assume testing over the recommended operating conditions and electrical
characteristic conditions.
Table 6-129. MMC/SD/SDIO Timing Conditions SD Identification Mode
TIMING CONDITION PARAMETER 1.8V, 3.3V UNIT
MIN MAX
SD Identification Mode
Input Conditions
trInput signal rise time 10 ns
tfInput signal fall time 10 ns
Output Conditions
CLOAD Output load capacitance 30 pF
Table 6-130. MMC/SD/SDIO Timing Requirements SD Identification Mode(1) (2) (3)(4)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
SD Identification Mode
MMC/SD/SDIO Interface 1
HSSD3/SD3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising 1198.4 ns
clock edge
HSSD4/SD4 tsu(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising 1249.2 ns
clock edge
MMC/SD/SDIO Interface 2
HSSD3/SD3 tsu(CMDV-CLKIH) Setup time, mmc2_cmd valid before mmc2_clk rising 1198.4 ns
clock edge
(1) Timing parameters refer to output clock specified in Table 6-131.
(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-131.
(3) Corresponding figures showing timing parameters are common with other interface modes. (See SD and HS SD modes).
(4) For more information, see the AM35x ARM Microprocessor Technical Reference Manual (literature number SPRUGR0).
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Table 6-130. MMC/SD/SDIO Timing Requirements SD Identification Mode(1) (2) (3)(4) (continued)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
HSSD4/SD4 tsu(CLKIH-CMDIV) Hold time, mmc2_cmd valid after mmc2_clk rising 1249.2 ns
clock edge
MMC/SD/SDIO Interface 3
HSSD3/SD3 tsu(CMDV-CLKIH) Setup time, mmc3_cmd valid before mmc3_clk rising 1198.4 ns
clock edge
HSSD4/SD4 tsu(CLKIH-CMDIV) Hold time, mmc3_cmd valid after mmc3_clk rising 1249.2 ns
clock edge
Table 6-131. MMC/SD/SDIO Switching Characteristics SD Identification Mode(1)(2)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
SD Identification Mode
HSSD1/SD1 tc(clk) Cycle time, output clk period 2500 ns
HSSD2/SD2 tW(clkH) Typical pulse duration, output clk high X(3)*PO(4) ns
HSSD2/SD2 tW(clkL) Typical pulse duration, output clk low Y(5)*PO(4) ns
tdc(clk) Duty cycle error, output clk 125 ns
tj(clk) Jitter standard deviation, output clk 200 ps
MMC/SD/SDIO Interface 1
tr(clk) Rise time, output clk 10 ns
tf(clkH) Fall time, output clk 10 ns
tr(clkL) Rise time, output data 10 ns
tf(clk) Fall time, output data 10 ns
HSSD5/SD5 td(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to mmc1_cmd 6.3 2492.7 ns
transition
MMC/SD/SDIO Interface 2
tr(clk) Rise time, output clk 10 ns
tf(clkH) Fall time, output clk 10 ns
tr(clkL) Rise time, output data 10 ns
tf(clk) Fall time, output data 10 ns
HSSD5/SD5 td(CLKOH-CMD) Delay time, mmc2_clk rising clock edge to mmc2_cmd 6.3 2492.7 ns
transition
MMC/SD/SDIO Interface 3
tr(clk) Rise time, output clk 10 ns
tf(clkH) Fall time, output clk 10 ns
tr(clkL) Rise time, output data 10 ns
tf(clk) Fall time, output data 10 ns
HSSD5/SD5 td(CLKOH-CMD) Delay time, mmc3_clk rising clock edge to mmc3_cmd 6.3 2492.7 ns
transition
(1) Corresponding figures showing timing parameters are common with other interface modes (see SD and HS SD modes).
(2) The jitter probability density can be approximated by a Gaussian function.
(3) The X parameter is defined as shown below.
(4) PO = output clk period in ns.
(5) The Y parameter is defined as shown below.
Table 6-132. X Parameter
CLKD X
1 or Even 0.5
Odd (trunc[CLKD/2]+1)/CLKD
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Table 6-133. Y Parameter
CLKD Y
1 or Even 0.5
Odd (trunc[CLKD/2])/CLKD
6.7.1.2 MMC/SD/SDIO in High-Speed MMC Mode
The following tables assume testing over the recommended operating conditions and electrical
characteristic conditions.
Table 6-134. MMC/SD/SDIO Timing Conditions High-Speed MMC Mode
TIMING CONDITION PARAMETER 1.8V, 3.3V UNIT
MIN MAX
High-Speed MMC Mode
Input Conditions
trInput signal rise time 0.19 3 ns
tfInput signal fall time 0.19 3 ns
Output Conditions
CLOAD Output load capacitance 30 pF
Table 6-135. MMC/SD/SDIO Timing Requirements High-Speed MMC Mode(1)(2)(3)(4)
NO. PARAMETER 1.8 V 3.3V UNIT
MIN MAX MIN MAX
High-Speed MMC Mode
MMC/SD/SDIO Interface 1
MMC3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk 2.13 2.41 ns
rising clock edge
MMC4 th(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk 3.47 2.09 ns
rising clock edge
MMC7 tsu(DATxV-CLKIH) Setup time, mmc1_datx valid before mmc1_clk 2.13 2.41 ns
rising clock edge
MMC8 th(CLKIH-DATxIV) Hold time, mmc1_datx valid after mmc1_clk 3.47 2.09 ns
rising clock edge
MMC/SD/SDIO Interface 2
MMC3 tsu(CMDV-CLKIH) Setup time, mmc2_cmd valid before mmc2_clk 2.88 3.23 ns
rising clock edge
MMC4 th(CLKIH-CMDIV) Hold time, mmc2_cmd valid after mmc2_clk 2.90 1.46 ns
rising clock edge
MMC7 tsu(DATxV-CLKIH) Setup time, mmc2_datx valid before mmc2_clk 2.88 3.23 ns
rising clock edge
MMC8 th(CLKIH-DATxIV) Hold time, mmc2_datx valid after mmc2_clk 2.90 1.46 ns
rising clock edge
MMC/SD/SDIO Interface 3
MMC3 tsu(CMDV-CLKIH) Setup time, mmc3_cmd valid before mmc3_clk 3.38 3.41 ns
rising clock edge
MMC4 th(CLKIH-CMDIV) Hold time, mmc3_cmd valid after mmc3_clk 2.83 1.46 ns
rising clock edge
MMC7 tsu(DATxV-CLKIH) Setup time, mmc3_datx valid before mmc3_clk 3.38 3.41 ns
rising clock edge
MMC8 th(CLKIH-DATxIV) Hold time, mmc3_datx valid after mmc3_clk 2.83 1.46 ns
rising clock edge
(1) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.
(2) Timing parameters refer to output clock specified in Table 6-136.
(3) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-136.
(4) Corresponding figures showing timing parameters are common with Standard MMC mode.
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Table 6-136. MMC/SD/SDIO Switching Characteristics High-Speed MMC Mode(1)(2)
N O. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
High-Speed MMC Mode
MMC1 tc(clk) Cycle time, output clk period 20.83 ns
MMC2 tW(clkH) Typical pulse duration, output clk high X(3)*PO(4) ns
MMC2 tW(clkL) Typical pulse duration, output clk low Y(5)*PO(4) ns
tdc(clk) Duty cycle error, output clk 1041.67 ps
tj(clk) Jitter standard deviation, output clk 200 ps
MMC/SD/SDIO Interface 1
tc(clk) Rise time, output clk 3 ns
tW(clkH) Fall time, output clk 3 ns
tW(clkL) Rise time, output data 3 ns
tdc(clk) Fall time, output data 3 ns
MMC5 td(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to mmc1_cmd 3.7 14.11 ns
transition
MMC6 td(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_datx 3.7 16.50 ns
transition
MMC/SD/SDIO Interface 2
tc(clk) Rise time, output clk 3 ns
tW(clkH) Fall time, output clk 3 ns
tW(clkL) Rise time, output data 3 ns
tdc(clk) Fall time, output data 3 ns
MMC5 td(CLKOH-CMD) Delay time, mmc2_clk rising clock edge to mmc2_cmd 3.7 14.11 ns
transition
MMC6 td(CLKOH-DATx) Delay time, mmc2_clk rising clock edge to mmc2_datx 3.7 16.50 ns
transition
MMC/SD/SDIO Interface 3
tc(clk) Rise time, output clk 3 ns
tW(clkH) Fall time, output clk 3 ns
tW(clkL) Rise time, output data 3 ns
tdc(clk) Fall time, output data 3 ns
MMC5 td(CLKOH-CMD) Delay time, mmc3_clk rising clock edge to mmc3_cmd 3.7 14.11 ns
transition
MMC6 td(CLKOH-DATx) Delay time, mmc3_clk rising clock edge to mmc3_datx 3.7 14.11 ns
transition
(1) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.
(2) The jitter probability density can be approximated by a Gaussian function.
(3) The X parameter is defined as shown below.
(4) PO = output clk period in ns.
(5) The Y parameter is defined as shown below.
Table 6-137. X Parameter
CLKD X
1 or Even 0.5
Odd (trunc[CLKD/2]+1)/CLKD
Table 6-138. Y Parameter
CLKD Y
1 or Even 0.5
Odd (trunc[CLKD/2])/CLKD
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For details about clock division factor CLKD, see the AM35x ARM Microprocessor Technical Reference
Manual (literature number SPRUGR0).
6.7.1.3 MMC/SD/SDIO in Standard MMC Mode and MMC Identification Mode
The following tables assume testing over the recommended operating conditions and electrical
characteristic conditions.
Table 6-139. MMC/SD/SDIO Timing Conditions Standard MMC Mode and MMC Identification Mode
TIMING CONDITION PARAMETER 1.8-V,3.3-V UNIT
MIN MAX
Standard MMC Mode and MMC Identification Mode
Input Conditions
trInput signal rise time 0.19 10 ns
tfInput signal fall time 0.19 10 ns
Output Conditions
CLOAD Output load capacitance 30 pF
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Table 6-140. MMC/SD/SDIO Timing Requirements Standard MMC Mode and MMC Identification
Mode(1)(2)(3)
NO. PARAMETER 1.8 V 3.3V UNIT
MIN MAX MIN MAX
Standard MMC Mode and MMC Identification Mode
MMC/SD/SDIO Interface 1
MMC3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before 2.13 2.41 ns
mmc1_clk rising clock edge
MMC4 th(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk 3.47 2.09 ns
rising clock edge
MMC7 tsu(DATxV-CLKIH) Setup time, mmc1_datx valid before 2.13 2.41 ns
mmc1_clk rising clock edge
MMC8 th(CLKIH-DATxIV) Hold time, mmc1_datx valid after mmc1_clk 3.47 2.09 ns
rising clock edge
MMC/SD/SDIO Interface 2
MMC3 tsu(CMDV-CLKIH) Setup time, mmc2_cmd valid before 2.88 3.23 ns
mmc2_clk rising clock edge
MMC4 th(CLKIH-CMDIV) Hold time, mmc2_cmd valid after mmc2_clk 2.90 1.46 ns
rising clock edge
MMC7 tsu(DATxV-CLKIH) Setup time, mmc2_datx valid before 2.88 3.23 ns
mmc2_clk rising clock edge
MMC8 th(CLKIH-DATxIV) Hold time, mmc2_datx valid after mmc2_clk 2.90 1.46 ns
rising clock edge
MMC/SD/SDIO Interface 3
MMC3 tsu(CMDV-CLKIH) Setup time, mmc3_cmd valid before 3.38 3.41 ns
mmc3_clk rising clock edge
MMC4 th(CLKIH-CMDIV) Hold time, mmc3_cmd valid after mmc3_clk 2.83 1.46 ns
rising clock edge
MMC7 tsu(DATxV-CLKIH) Setup time, mmc3_datx valid before 3.38 3.41 ns
mmc3_clk rising clock edge
MMC8 th(CLKIH-DATxIV) Hold time, mmc3_datx valid after mmc3_clk 2.83 1.46 ns
rising clock edge
(1) Timing parameters are referred to output clock specified in Table 6-141.
(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-141.
(3) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.
Table 6-141. MMC/SD/SDIO Switching Characteristics Standard MMC Mode and MMC Identification
Mode(1)(2)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
MMC Identification Mode
MMC1 tc(clk) Cycle time 2500 ns
MMC2 tW(clkH) Typical pulse duration, output clk high X(3)*PO(4) ns
MMC2 tW(clkL) Typical pulse duration, output clk low Y(5)*PO(4) ns
tdc(clk) Duty cycle error, output clk 2604.17 ns
tj(clk) Jitter standard deviation 200 ps
Standard MMC Mode
MMC1 tc(clk) Cycle time 2500 ns
MMC2 tW(clkH) Typical pulse duration, output clk high X(3)*PO(4) ns
MMC2 tW(clkL) Typical pulse duration, output clk low Y(5)*PO(4) ns
(1) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.
(2) The jitter probability density can be approximated by a Gaussian function.
(3) The X parameter is defined as shown below.
(4) PO = output clk period in ns.
(5) The Y parameter is defined as shown below.
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Table 6-141. MMC/SD/SDIO Switching Characteristics Standard MMC Mode and MMC Identification
Mode(1)(2) (continued)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
tdc(clk) Duty cycle error, output clk 2604.17 ps
tj(clk) Jitter standard deviation 200 ps
MMC/SD/SDIO Interface 1
tr(clk) Rise time, output clk 10 ns
tf(clkH) Fall time, output clk 10 ns
tr(clkL) Rise time, output data 10 ns
tf(clk) Fall time, output data 10 ns
MMC5 td(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to mmc1_cmd 4.3 47.78 ns
transition
MMC6 td(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_datx 4.3 47.78 ns
transition
MMC/SD/SDIO Interface 2
tr(clk) Rise time, output clk 10 ns
tf(clkH) Fall time, output clk 10 ns
tr(clkL) Rise time, output data 10 ns
tf(clk) Fall time, output data 10 ns
MMC5 td(CLKOH-CMD) Delay time, mmc2_clk rising clock edge to mmc2_cmd 4.3 47.78 ns
transition
MMC6 td(CLKOH-DATx) Delay time, mmc2_clk rising clock edge to mmc2_datx 4.3 47.78 ns
transition
MMC/SD/SDIO Interface 3
tr(clk) Rise time, output clk 10 ns
tf(clkH) Fall time, output clk 10 ns
tr(clkL) Rise time, output data 10 ns
tf(clk) Fall time, output data 10 ns
MMC5 td(CLKOH-CMD) Delay time, mmc3_clk rising clock edge to mmc3_cmd 4.3 47.78 ns
transition
MMC6 td(CLKOH-DATx) Delay time, mmc3_clk rising clock edge to mmc3_datx 4.3 47.78 ns
transition
Table 6-142. X Parameter
CLKD X
1 or Even 0.5
Odd (trunc[CLKD/2]+1)/CLKD
Table 6-143. Y Parameter
CLKD Y
1 or Even 0.5
Odd (trunc[CLKD/2])/CLKD
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mmcx_dat[3:0]
MMC3
MMC7
MMC4
MMC8
MMC1 MMC2
030-104
mmcx_clk
mmcx_cmd
mmcx_dat[3:0]
MMC5 MMC5
MMC6 MMC6
MMC1 MMC2
030-105
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For details about clock division factor CLKD, see the AM35x ARM Microprocessor Technical Reference
Manual (literature number SPRUGR0).
In mmcx, x is equal to 1, 2, or 3.
Figure 6-66. MMC/SD/SDIO High-Speed and Standard MMC Modes Data/Command Receive
In mmcx, x is equal to 1, 2, or 3.
Figure 6-67. MMC/SD/SDIO High-Speed and Standard MMC Modes Data/Command Transmit
6.7.1.4 MMC/SD/SDIO in High-Speed SD Mode
The following tables assume testing over the recommended operating conditions and electrical
characteristic conditions.
Table 6-144. MMC/SD/SDIO Timing Conditions High-Speed SD Mode
TIMING CONDITION PARAMETER 1.8V, 3.3V UNIT
MIN MAX
High-Speed SD Mode
Input Conditions
tRInput signal rise time 0.19 3 ns
tFInput signal fall time 0.19 3 ns
Output Conditions
CLOAD Output load capacitance 30 pF
Table 6-145. MMC/SD/SDIO Timing Requirements High-Speed SD Mode(1)(2)(3)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
High-Speed SD Mode
MMC/SD/SDIO Interface 1
HSSD3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising 5.61 ns
clock edge
HSSD4 th(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising 2.28 ns
clock edge
(1) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.
(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-146.
(3) Timing Parameters refer to output clock specified in Table 6-146.
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Table 6-145. MMC/SD/SDIO Timing Requirements High-Speed SD Mode(1)(2)(3) (continued)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
HSSD7 tsu(DATxV-CLKIH) Setup time, mmc1_datx valid before mmc1_clk rising 5.61 ns
clock edge
HSSD8 th(CLKIH-DATxIV) Hold time, mmc1_datx valid after mmc1_clk rising 2.28 ns
clock edge
MMC/SD/SDIO Interface 2
HSSD3 tsu(CMDV-CLKIH) Setup time, mmc2_cmd valid before mmc2_clk rising 5.61 ns
clock edge
HSSD4 th(CLKIH-CMDIV) Hold time, mmc2_cmd valid after mmc2_clk rising 2.28 ns
clock edge
HSSD7 tsu(DATxV-CLKIH) Setup time, mmc2_datx valid before mmc2_clk rising 5.61 ns
clock edge
HSSD8 th(CLKIH-DATxIV) Hold time, mmc2_datx valid after mmc2_clk rising 2.28 ns
clock edge
MMC/SD/SDIO Interface 3
HSSD3 tsu(CMDV-CLKIH) Setup time, mmc3_cmd valid before mmc3_clk rising 5.61 ns
clock edge
HSSD4 th(CLKIH-CMDIV) Hold time, mmc3_cmd valid after mmc3_clk rising 2.28 ns
clock edge
HSSD7 tsu(DATxV-CLKIH) Setup time, mmc3_datx valid before mmc3_clk rising 5.61 ns
clock edge
HSSD8 th(CLKIH-DATxIV) Hold time, mmc3_datx valid after mmc3_clk rising 2.28 ns
clock edge
Table 6-146. MMC/SD/SDIO Switching Characteristics High-Speed SD Mode(1)(2)
NO. PARAMETER 1.8 V, 3.3 V UNIT
MIN MAX
High-Speed SD Mode
HSSD1 tc(clk) Cycle time 20.83 ns
HSSD2 tW(clkH) Typical pulse duration, output clk high X(3)*PO(4) ns
HSSD2 tW(clkL) Typical pulse duration, output clk low Y(5)*PO(4) ns
tdc(clk) Duty cycle error, output clk 1041.67 ps
tj(clk) Jitter standard deviation 200 ps
MMC/SD/SDIO Interface 1
tr(clk) Rise time, output clk 3 ns
tf(clkH) Fall time, output clk 3 ns
tr(clkL) Rise time, output data 3 ns
tf(clk) Fall time, output data 3 ns
HSSD5 td(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to mmc1_cmd 3.72 14.11 ns
transition
HSSD6 td(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_datx 3.72 14.11 ns
transition
MMC/SD/SDIO Interface 2
tr(clk) Rise time, output clk 3 ns
tf(clkH) Fall time, output clk 3 ns
tr(clkL) Rise time, output data 3 ns
tf(clk) Fall time, output data 3 ns
(1) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.
(2) The jitter probability density can be approximated by a Gaussian function.
(3) The X parameter is defined as shown in Table 6-147.
(4) PO = output clk period in ns.
(5) The Y parameter is defined as shown in Table 6-148.
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mmcx_dat[3:0]
HSSD3
HSSD7
HSSD4
HSSD8
HSSD1 HSSD2
030-106
mmcx_clk
mmcx_cmd
mmcx_dat[3:0]
HSSD5 HSSD5
HSSD6 HSSD6
HSSD1 HSSD2
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Table 6-146. MMC/SD/SDIO Switching Characteristics High-Speed SD Mode(1)(2) (continued)
NO. PARAMETER 1.8 V, 3.3 V UNIT
MIN MAX
HSSD5 td(CLKOH-CMD) Delay time, mmc2_clk rising clock edge to mmc2_cmd 3.72 14.11 ns
transition
HSSD6 td(CLKOH-DATx) Delay time, mmc2_clk rising clock edge to mmc2_datx 3.72 14.11 ns
transition
MMC/SD/SDIO Interface 3
tr(clk) Rise time, output clk 3 ns
tf(clkH) Fall time, output clk 3 ns
tr(clkL) Rise time, output data 3 ns
tf(clk) Fall time, output data 3 ns
HSSD5 td(CLKOH-CMD) Delay time, mmc3_clk rising clock edge to mmc3_cmd 3.72 14.11 ns
transition
HSSD6 td(CLKOH-DATx) Delay time, mmc3_clk rising clock edge to mmc3_datx 3.72 14.11 ns
transition
Table 6-147. X Parameters
CLKD X
1 or Even 0.5
Odd (trunc[CLKD/2]+1)/CLKD
Table 6-148. Y Parameters
CLKD Y
1 or Even 0.5
Odd (trunc[CLKD/2])/CLKD
For details about clock division factor CLKD, see the AM35x ARM Microprocessor Technical Reference
Manual (literature number SPRUGR0).
In mmcx, x is equal to 1, 2, or 3.
Figure 6-68. MMC/SD/SDIO High-Speed SD Mode Data/Command Receive
In mmcx, x is equal to 1, 2, or 3.
Figure 6-69. MMC/SD/SDIO High-Speed SD Mode Data/Command Transmit
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6.7.1.5 MMC/SD/SDIO in Standard SD Mode
The following tables assume testing over the recommended operating conditions and electrical
characteristic conditions.
Table 6-149. MMC/SD/SDIO Timing Conditions Standard SD Mode
TIMING CONDITION PARAMETER 1.8V, 3.3V UNIT
MIN MAX
Standard SD Mode
Input Conditions
tRInput signal rise time 0.19 10 ns
tFInput signal fall time 0.19 10 ns
Output Conditions
CLOAD Output load capacitance 30 pF
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Table 6-150. MMC/SD/SDIO Timing Requirements Standard SD Mode(1)(2)(3)
NO. PARAMETER 1.8 V, 3.3V UNIT
MIN MAX
Standard SD Mode
MMC/SD/SDIO Interface 1
SD3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising clock 6.23 ns
edge
SD4 th(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising clock 19.37 ns
edge
SD7 tsu(DATxV-CLKIH) Setup time, mmc1_datx valid before mmc1_clk rising clock 6.23 ns
edge
SD8 th(CLKIH-DATxIV) Hold time, mmc1_datx valid after mmc1_clk rising clock 19.37 ns
edge
MMC/SD/SDIO Interface 2
SD3 tsu(CMDV-CLKIH) Setup time, mmc2_cmd valid before mmc2_clk rising clock 6.23 ns
edge
SD4 th(CLKIH-CMDIV) Hold time, mmc2_cmd valid after mmc2_clk rising clock 19.37 ns
edge
SD7 tsu(DATxV-CLKIH) Setup time, mmc2_datx valid before mmc2_clk rising clock 6.23 ns
edge
SD8 th(CLKIH-DATxIV) Hold time, mmc2_datx valid after mmc2_clk rising clock 19.37 ns
edge
MMC/SD/SDIO Interface 3
SD3 tsu(CMDV-CLKIH) Setup time, mmc3_cmd valid before mmc3_clk rising clock 6.23 ns
edge
SD4 th(CLKIH-CMDIV) Hold time, mmc3_cmd valid after mmc3_clk rising clock 19.37 ns
edge
SD7 tsu(DATxV-CLKIH) Setup time, mmc3_datx valid before mmc3_clk rising clock 6.23 ns
edge
SD8 th(CLKIH-DATxIV) Hold time, mmc3_datx valid after mmc3_clk rising clock 19.37 ns
edge
(1) Timing parameters refer to output clock specified in Table 6-151.
(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-151.
(3) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.
Table 6-151. MMC/SD/SDIO Switching Characteristics Standard SD Mode(1)(2)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
Standard SD Mode
SD1 tc(clk) Cycle time 41.67 ns
SD2 tW(clkH) Typical pulse duration, output clk high X(3)*PO(4) ns
SD2 tW(clkL) Typical pulse duration, output clk low Y(5)*PO(4) ns
tdc(clk) Duty cycle error, output clk 2083.33 ps
tj(clk) Jitter standard deviation 200 ps
MMC/SD/SDIO Interface 1
tr(clk) Rise time, output clk 10 ns
tf(clkH) Fall time, output clk 10 ns
tr(clkL) Rise time, output data 10 ns
tf(clk) Fall time, output data 10 ns
(1) The jitter probability density can be approximated by a Gaussian function.
(2) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.
(3) The X parameter is defined as shown in Table 6-152.
(4) PO = output clk period in ns.
(5) The Y parameter is defined as shown in Table 6-153.
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mmcx_dat[3:0]
SD3
SD7
SD4
SD8
SD1 SD2
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Table 6-151. MMC/SD/SDIO Switching Characteristics Standard SD Mode(1)(2) (continued)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
SD5 td(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to mmc1_cmd 6.13 35.53 ns
transition
SD6 td(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_datx 6.13 35.53 ns
transition
MMC/SD/SDIO Interface 2
tr(clk) Rise time, output clk 10 ns
tf(clkH) Fall time, output clk 10 ns
tr(clkL) Rise time, output data 10 ns
tf(clk) Fall time, output data 10 ns
SD5 td(CLKOH-CMD) Delay time, mmc2_clk rising clock edge to mmc2_cmd 6.13 35.53 ns
transition
SD6 td(CLKOH-DATx) Delay time, mmc2_clk rising clock edge to mmc2_datx 6.13 35.53 ns
transition
MMC/SD/SDIO Interface 3
tr(clk) Rise time, output clk 10 ns
tf(clkH) Fall time, output clk 10 ns
tr(clkL) Rise time, output data 10 ns
tf(clk) Fall time, output data 10 ns
SD5 td(CLKOH-CMD) Delay time, mmc3_clk rising clock edge to mmc3_cmd 6.13 35.53 ns
transition
SD6 td(CLKOH-DATx) Delay time, mmc3_clk rising clock edge to mmc3_datx 6.13 35.53 ns
transition
Table 6-152. X Parameter
CLKD X
1 or Even 0.5
Odd (trunc[CLKD/2]+1)/CLKD
Table 6-153. Y Parameter
CLKD Y
1 or Even 0.5
Odd (trunc[CLKD/2])/CLKD
For details about clock division factor CLKD, see the AM35x ARM Microprocessor Technical Reference
Manual (literature number SPRUGR0).
In mmcx, x is equal to 1, 2, or 3.
Figure 6-70. MMC/SD/SDIO Standard SD Mode Data/Command Receive
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SD5
SD6
SD5
SD6
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In mmcx, x is equal to 1, 2, or 3.
Figure 6-71. MMC/SD/SDIO Standard SD Mode Data/Command Transmit
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etk_d[15:0]
ETM0
ETM2
ETM3
ETM2
ETM1
ETM3
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6.8 Test Interfaces
The emulation and trace interfaces allow tracing activities of the following CPUs:
• ARM CortexTM-A8 through an Embedded Trace Macro-cell (ETM11) dedicated to enable real-time
trace of the ARM subsystem operations.
All processors can be emulated via JTAG ports.
6.8.1 Embedded Trace Macro Interface (ETM)
The following tables assume testing over the recommended operating conditions.
Table 6-154. Embedded Trace Macro Interface Switching Characteristics
NO. PARAMETER MIN MAX UNIT
f 1/tc(CLK) Frequency, etk_clk 166 MHz
ETM0 tc(CLK) Cycle time 6.02 ns
ETM1 tW(CLK) Clock pulse width, etk_clk 3.01 ns
ETM2 td(CLK-CTL) Delay time, etk_clk clock edge to etk_ctl transition -0.5 0.5 ns
ETM3 td(CLK-D) Delay time, etk_clk clock high to etk_d[15:0] transition -0.5 0.5 ns
Figure 6-72. Embedded Trace Macro Interface
6.8.2 JTAG Interfaces
AM3517/05 JTAG TAP controller handles standard IEEE JTAG interfaces. The following sections define
the timing requirements for several tools used to test the AM3517/05 processors as:
• Free running clock tool, like XDS560 and XDS510 tools
• Adaptive clock tool, like RealView ICE tool and Lauterbach tool
6.8.2.1 JTAG Free Running Clock Mode
The following tables assume testing over the recommended operating conditions and electrical
characteristic conditions.
Table 6-155. JTAG Timing Conditions Free Running Clock Mode
1.8 V 3.3 V
TIMING CONDITION PARAMETER UNIT
MAX MAX
Input Conditions
tRInput signal rise time 5 3 ns
tFInput signal fall time 5 3 ns
Output Conditions
CLOAD Output load capacitance 30 pF
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Table 6-156. JTAG Timing Requirements Free Running Clock Mode(1)(2)(3)
1.8V 3.3V
NO. PARAMETER UNIT
MIN MAX MIN MAX
JT4 tc(tck) Cycle time 20 20 ns
JT5 tw(tckL) Typical pulse duration, jtag_tck low 10 10 ns
JT6 tw(tckH) Typical pulse duration, jtag_tck high 10 10 ns
tdc(tck) Duty cycle error, jtag_tck -1250 1250 -1250 1250 ps
tj(tck) Cycle jitter -1250 1250 -1250 1250 ps
JT7 tsu(tdiV-rtckH) Setup time, jtag_tdi valid before jtag_rtck high 1.8 3.8 ns
JT8 th(tdiV-rtckH) Hold time, jtag_tdi valid after jtag_rtck high 0.7 2.7 ns
JT9 tsu(tmsV-rtckH) Setup time, jtag_tms valid before jtag_rtck high 1.8 3.8 ns
JT10 th(tmsV-rtckH) Hold time, jtag_tms valid after jtag_rtck high 0.7 2.7 ns
JT12 tsu(emuxV-rtckH) Setup time, jtag_emux 14.6 14.6 ns
JT13 th(emuxV-rtckH) Hold time,jtag_emux 2 2 ns
(1) Maximum cycle jitter supported by jtag _tck input clock.
(2) x = 0 to 1
(3) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.
Table 6-157. JTAG Switching Characteristics Free Running Clock Mode(1)(2)
1.8 V 3.3 V
NO. PARAMETER MIN MAX MIN MAX UNIT
JT1 tc(rtck) Cycle time(1), jtag_rtck period 20 20 ns
JT2 tw(rtckL) Typical pulse duration, jtag_rtck low 10 10 ns
JT3 tw(rtckH) Typical pulse duration, jtag_rtck high 10 10 ns
tdc(rtck) Duty cycle error, jtag_rtck -1250 1250 -1250 1250 ps
tj(rtck) Jitter standard deviation(2), jtag_rtck 33.33 33.33 ps
tR(rtck) Rise time, jtag_rtck 4 4 ns
tF(rtck) Fall time, jtag_rtck 4 4 ns
JT11 td(rtckL-tdoV) Delay time, jtag_rtck low to jtag_tdo valid -5.8 5.8 -8 8 ns
tR(tdo) Rise time, jtag_tdo 4 4 ns
tF(tdo) Fall time, jtag_tdo 4 4 ns
JT14 td(rtckH-emuxV) Delay time, jtag_rtck high to ,jtag_emux 2.7 15.1 2.7 15.1 ns
tR(emux) Rise time, jtag_emux 6 6 ns
tF(emux) Fall time, jtag_emux 6 6 ns
(1) Related with the jtag_rtck maximum frequency.
(2) The jitter probability density can be approximated by a Gaussian function.
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jtag_tdi
jtag_tms
jtag_emux(IN)
jtag_tdo
jtag_emux(OUT)
JT7
JT11
JT1
JT2 JT3
JT8
JT10JT9
JT4
JT5 JT6
JT12 JT13
JT14
030-113
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In jtag_emux, x is equal to 0 to 1.
Figure 6-73. JTAG Interface Timing Free Running Clock Mode
6.8.2.2 JTAG Adaptive Clock Mode
The following tables assume testing over the recommended operating conditions and electrical
characteristic conditions.
Table 6-158. JTAG Timing Conditions Adaptive Clock Mode
1.8 V 3.3 V
TIMING CONDITION PARAMETER UNIT
MAX MAX
Input Conditions
tRInput signal rise time 5 3 ns
tFInput signal fall time 5 3 ns
Output Conditions
CLOAD Output load capacitance 30 pF
Table 6-159. JTAG Timing Requirements Adaptive Clock Mode(1)(2)
1.8 V 3.3 V
NO. PARAMETER MIN MAX MIN MAX UNIT
JA4 tc(tck) Cycle time 20 20 ns
JA5 tw(tckL) Typical pulse duration, jtag_tck low 10 10 ns
JA6 tw(tckH) Typical pulse duration, jtag_tck high 10 10 ns
tdc(lclk) Duty cycle error, jtag_tck -2500 2500 -2500 2500 ps
tj(lclk) Cycle jitter -1500 1500 -1500 1500 ps
JA7 tsu(tdiV-tckH) Setup time, jtag_tdi valid before jtag_tck high 13.8 13.8 ns
JA8 th(tdiV-tckH) Hold time, jtag_tdi valid after jtag_tck high 13.8 13.8 ns
JA9 tsu(tmsV-tckH) Setup time, jtag_tms valid before jtag_tck high 13.8 13.8 ns
JA10 th(tmsV-tckH) Hold time, jtag_tms valid after jtag_tck high 13.8 13.8 ns
(1) Maximum cycle jitter supported by jtag _tck input clock.
(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.
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jtag_tdi
jtag_tms
jtag_rtck
jtag_tdo
JA1
JA2 JA3
JA4
JA5 JA6
JA7 JA8
JA10JA9
JA11
030-114
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Table 6-160. JTAG Switching Characteristics Adaptive Clock Mode(1)
1.8 V 3.3 V
NO. PARAMETER MIN MAX MIN MAX UNIT
JA1 tc(rtck) Cycle time 20 20 ns
JA2 tw(rtckL) Typical pulse duration, jtag_rtck low 10 10 ns
JA3 tw(rtckH) Typical pulse duration, jtag_rtck high 10 10 ns
tdc(rtck) Duty cycle error, jtag_rtck -2500 2500 -2500 2500 ps
tj(rtck) Jitter standard deviation 33.33 33.33 ps
tR(rtck) Rise time, jtag_rtck 4 4 ns
tF(rtck) Fall time, jtag_rtck 4 4 ns
JA11 td(rtckL-tdoV) Delay time, jtag_rtck low to jtag_tdo valid -14.6 14.6 -14.6 14.6 ns
tR(tdo) Rise time, jtag_tdo, 4 4 ns
tF(tdo) Fall time, jtag_tdo 4 4 ns
(1) The jitter probability density can be approximated by a Gaussian function.
Figure 6-74. JTAG Interface Timing Adaptive Clock Mode
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7 Package Characteristics
7.1 Package Thermal Resistance
Table 7-1 provides the thermal resistance characteristics for the recommended package types used on the
AM3517/05.
Table 7-1. AM3517/05 Thermal Resistance Characteristics(1)
BOARD TYPE
PACKAGE POWER (W) RJA(C/W) RJB(C/W) RJC(C/W) Figure 6-31
ZCN Pkg. 1.6 24.58 10.81 - 2S2P
ZER Pkg. 1.6 15.8 6 6 2S2P
(1) RJA (Theta-JA) = Thermal Resistance Junction-to-Ambient, C/W
RJB (Theta-JB) = Thermal Resistance Junction-to-Board, C/W
RJC (Theta-JC) = Thermal Resistance Junction-to-Case, C/W
7.2 Device Support
7.2.1 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
AM3517/05 microprocessors and support tools. Each device has one of three prefixes: X, P, or null (no
prefix). Texas Instruments recommends two of three possible prefix designators for its support tools:
TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering
prototypes (TMDX) through fully qualified production devices/tools (TMDS).
Device development evolutionary flow:
XExperimental device that is not necessarily representative of the final devices electrical
specifications and may not use production assembly flow. (TMX definition)
PPrototype device that is not necessarily the final silicon die and may not necessarily meet
final electrical specifications. (TMP definition)
null Production version of the silicon die that is fully qualified. (TMS definition)
Support tool development evolutionary flow:
TMDX Development support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS Fully qualified development support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
Developmental product is intended for internal evaluation purposes.
Production devices and TMDS development-support tools have been characterized fully, and the quality
and reliability of the device have been demonstrated fully. TIs standard warranty applies.
Predictions show that prototype devices (X or P), have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
For additional description of the device nomenclature markings, see the AM35x ARM Microprocessor
Silicon Errata (literature number SPRZ306).
Copyright © 2009–2012, Texas Instruments Incorporated Package Characteristics 215
Submit Documentation Feedback
Product Folder Link(s): AM3517 AM3505
PREFIX
X AM3517 A
X = Experimental Device
P = Prototype Device
blank = Production Device
DEVICE PACKAGE TYPE
ZCN = 491-pin sPBGA
ZER = 484-pin sPBGA
SILICON REVISION
ZCN ( )
blank = commercial temperature
A = extended temperature
( )
blank = no security
C = crypto enabled
AM3517, AM3505
SPRS550D –OCTOBER 2009–REVISED MARCH 2012
www.ti.com
Figure 7-1. Device Nomenclature
7.2.2 Documentation Support
7.2.2.1 Related Documentation from Texas Instruments
The following documents describe the AM3517/05 device. Copies of these documents are available on the
Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com.
The current documentation that describes the AM3517/05 ARM microprocessor, related peripherals, and
other technical collateral, is available in the product folder at: www.ti.com.
SPRUGR0 AM35x ARM Microprocessor Technical Reference Manual. Collection of documents
providing detailed information on the Sitara™ architecture including power, reset, and clock
control, interrupts, memory map, and switch fabric interconnect. Detailed information on the
microprocessor unit (MPU) subsystem as well a functional description of the peripherals
supported on AM3517/05 devices is also included.
7.2.2.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and
help solve problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.
7.2.2.3 Related Documentation from Other Sources
The following documents are related to the AM3517/05 device. Copies of these documents can be
obtained directly from the internet or from your Texas Instruments representative.
Cortex-A8 Technical Reference Manual. This is the technical reference manual for the Cortex-A8
processor. A copy of this document can be obtained via the internet at http://infocenter.arm.com. See the
AM35x ARM Microprocessor Silicon Errata (literature number SPRZ306) to determine the revision of the
Cortex-A8 core used on your device.
ARM Core Cortex™-A8 (AT400/AT401) Errata Notice. Provides a list of advisories for the different
revisions of the Cortex-A8 processor. Contact your TI representative for a copy of this document. See the
AM35x ARM Microprocessor Silicon Errata (literature number SPRZ306) to determine the revision of the
Cortex-A8 core used on your device.
216 Package Characteristics Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): AM3517 AM3505
AM3517, AM3505
www.ti.com
SPRS550D –OCTOBER 2009–REVISED MARCH 2012
7.3 Mechanical Data
The following packaging information reflects the most current data available for the designated device(s).
This data is subject to change without notice and without revision of this document.
Copyright © 2009–2012, Texas Instruments Incorporated Package Characteristics 217
Submit Documentation Feedback
Product Folder Link(s): AM3517 AM3505
PACKAGE OPTION ADDENDUM
www.ti.com 23-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
AM3505AZCN ACTIVE NFBGA ZCN 491 90 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
AM3505AZCNA ACTIVE NFBGA ZCN 491 90 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
AM3505AZCNAC ACTIVE NFBGA ZCN 491 90 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
AM3505AZCNC ACTIVE NFBGA ZCN 491 90 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
AM3505AZER ACTIVE BGA ZER 484 60 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
AM3505AZERA ACTIVE BGA ZER 484 60 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
AM3505AZERAC ACTIVE BGA ZER 484 60 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
AM3505AZERC ACTIVE BGA ZER 484 60 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
AM3517AZCN ACTIVE NFBGA ZCN 491 90 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
AM3517AZCNA ACTIVE NFBGA ZCN 491 1 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
AM3517AZCNAC ACTIVE NFBGA ZCN 491 90 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
AM3517AZCNC ACTIVE NFBGA ZCN 491 90 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
AM3517AZER ACTIVE BGA ZER 484 60 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
AM3517AZERA ACTIVE BGA ZER 484 60 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
AM3517AZERAC ACTIVE BGA ZER 484 60 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
AM3517AZERC ACTIVE BGA ZER 484 60 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
XAM3517AZCN OBSOLETE NFBGA ZCN 491 TBD Call TI Call TI
PACKAGE OPTION ADDENDUM
www.ti.com 23-Aug-2012
Addendum-Page 2
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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