High Speed, Video
Difference Amplifier
AD830
Rev. C
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FEATURES
Differential amplification
Wide common-mode voltage range: +12.8 V to −12 V
Differential voltage: ±2 V
High CMRR: 60 dB at 4 MHz
Built-in differential clipping level: ±2.3 V
Fast dynamic performance
85 MHz unity gain bandwidth
35 ns settling time to 0.1%
360 V/μs slew rate
Symmetrical dynamic response
Excellent video specifications
Differential gain error: 0.06%
Differential phase error: 0.08°
15 MHz (0.1 dB) bandwidth
Flexible operation
High output drive of ±50 mA min
Specified with both ±5 V and ±15 V supplies
Low distortion: THD = −72 dB @ 4 MHz
Excellent DC performance: 3 mV max input
Offset voltage
APPLICATIONS
Differential line receiver
High speed level shifter
High speed in-amp
Differential to single-ended conversion
Resistorless summation and subtraction
High speed analog-to-digital converter
CONNECTION DIAGRAM
AD830
1
2
3
4
8
7
6
5
C
G
M
G
M
X1
X2
Y1
Y2
V
P
OUT
NC
V
N
NC = NO CONNECT
00881-001
A = 1
Figure 1. 8-Lead Plastic PDIP (N), CERDIP (Q), and SOIC (RN) Packages
FREQUENCY ( Hz)
CMRR (dB)
110
30 10M
50
40
1k
70
60
80
90
100
1M100k10k
VS= ±5V
VS= ±15V
00881-002
Figure 2. Common-Mode Rejection Ratio vs. Frequency
Good gain flatness and excellent differential gain of 0.06% and
phase of 0.08° make the AD830 suitable for many video system
applications. Furthermore, the AD830 is suited for general-purpose
signal processing from dc to 10 MHz.
GENERAL DESCRIPTION
The AD830 is a wideband, differencing amplifier designed for use
at video frequencies but also useful in many other applications. It
accurately amplifies a fully differential signal at the input and
produces an output voltage referred to a user-chosen level. The
undesired common-mode signal is rejected, even at high
frequencies. High impedance inputs ease interfacing to finite
source impedances and, thus, preserve the excellent common-
mode rejection. In many respects, it offers significant
improvements over discrete difference amplifier approaches, in
particular in high frequency common-mode rejection.
The wide common-mode and differential voltage range of the
AD830 make it particularly useful and flexible in level shifting
applications but at lower power dissipation than discrete solutions.
Low distortion is preserved over the many possible differential and
common-mode voltages at the input and output.
9
–6
–21
10k 100k 1M 10M 100M 1G
–3
0
3
6
–18
–15
–12
–9
FREQ UE NCY (Hz )
GAIN (dB)
VS = ±5V
RL = 150Ω
CL = 33pF
CL = 4. 7pF
CL = 15p F
0
0881-003
Figure 3. Closed-Loop Gain vs. Frequency, Gain = +1
AD830* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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DOCUMENTATION
Application Notes
•AN-282: Fundamentals of Sampled Data Systems
•AN-649: Using the Analog Devices Active Filter Design
Tool
•AN-692: Universal Precision Op Amp Evaluation Board
Data Sheet
•AD830: High Speed, Video Difference Amplifier Data
Sheet
•AD830: Military Data Sheet
TOOLS AND SIMULATIONS
•AD830 SPICE Macro-Model
DESIGN RESOURCES
•AD830 Material Declaration
•PCN-PDN Information
•Quality And Reliability
•Symbols and Footprints
DISCUSSIONS
View all AD830 EngineerZone Discussions.
SAMPLE AND BUY
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TECHNICAL SUPPORT
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number.
DOCUMENT FEEDBACK
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AD830
Rev. C | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Connection Diagram ....................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 7
Maximum Power Dissipation ..................................................... 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 11
Traditional Differential Amplification .................................... 11
Problems With the Op Amp Based Approach ....................... 11
AD830 for Differential Amplification ..................................... 11
Advantageous Properties of the AD830 .................................. 11
Understanding the AD830 Topology ...................................... 11
Interfacing the Input .................................................................. 12
Supplies, Bypassing, and Grounding (Figure 34) ................... 14
AC-Coupled Line Receiver ....................................................... 17
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 20
REVISION HISTORY
3/10—Rev. B to Rev. C
Updated Format .................................................................. Universal
Changes to Ordering Guide .......................................................... 20
1/03—Rev. A to Rev. B.
Updated Ordering Guide ................................................................ 4
Change to Figure 30 ...................................................................... 14
Updated Outline Dimensions ..................................................... 15
AD830
Rev. C | Page 3 of 20
SPECIFICATIONS
VS = ±15 V, RLOAD = 150 Ω, CLOAD = 5 pF, TA = 25°C, unless otherwise noted.
Table 1.
AD830J/AD830A AD830S1
Parameter Conditions Min Typ Max Min Typ Max Unit
DYNAMIC CHARACTERISTICS
3 dB Small Signal Bandwidth Gain = +1, VOUT = 100 mV rms 75 85 75 85 MHz
0.1 dB Gain Flatness
Frequency
Gain = +1, VOUT = 100 mV rms 11 15 11 15 MHz
Differential Gain Error 0 V to 0.7 V, frequency =
4.5 MHz
0.06 0.09 0.06 0.09 %
Differential Phase Error 0 V to 0.7 V, frequency =
4.5 MHz
0.08 0.12 0.08 0.12 Degrees
Slew Rate 2 V step, RL = 500 Ω 360 360 V/μs
4 V step, RL = 500 Ω 350 350 V/μs
3 dB Large Signal Bandwidth Gain = +1, VOUT = 1 V rms 38 45 38 45 MHz
Settling Time, Gain = +1 VOUT = 2 V step, to 0.1% 25 25 ns
V
OUT = 4 V step, to 0.1% 35 35 ns
Harmonic Distortion 2 V p-p, frequency = 1 MHz −82 −82 dBc
2 V p-p, frequency = 4 MHz −72 −72 dBc
Input Voltage Noise frequency = 10 kHz 27 27 nV/√Hz
Input Current Noise 1.4 1.4 pA/√Hz
DC PERFORMANCE
Offset Voltage Gain = +1 ±1.5 ±3 ±1.5 ±3 mV
Gain = +1, TMIN − TMAX ±5 ±7 mV
Open-Loop Gain DC 64 69 64 69 dB
Gain Error RL = 1 kΩ, G = ±1 ±0.1 ±0.6 ±0.1 ±0.6 %
Peak Nonlinearity, RL = 1 kΩ, −1 V ≤ X ≤ +1 V 0.01 0.03 0.01 0.03 % FS
Gain = +1 −1.5 V ≤ X ≤ +1.5 V 0.035 0.07 0.035 0.07 % FS
−2 V ≤ X ≤ +2 V 0.15 0.4 0.15 0.4 % FS
Input Bias Current VIN = 0 V, 25°C to TMAX 5 10 5 10 μA
V
IN = 0 V, TMIN 7 13 8 17 μA
Input Offset Current VIN = 0 V, TMIN − TMAX 0.1 1 0.1 1 μA
INPUT CHARACTERISTICS
Differential Voltage Range VCM = 0 ±2.0 ±2.0 V
Differential Clipping Level2 Pin 1 and Pin 2 inputs only ±2.1 ±2.3 ±2.1 ±2.3 V
Common-Mode Voltage
Range
VDM = ±1 V −12.0 +12.8 −12.0 +12.8 V
CMRR DC, Pin 1/Pin 2, ±10 V 90 100 90 100 dB
DC, Pin 1/Pin 2, ±10 V,
T
MIN − TMAX 88 86 dB
Frequency = 4 MHz 55 60 55 60 dB
Input Resistance 370 370 kΩ
Input Capacitance 2 2 pF
OUTPUT CHARACTERISTICS
Output Voltage Swing RL ≥ 1 kΩ ±12 +13.8/−13.8 ±12 +13.8/−13.8 V
R
L ≥ 1 kΩ, ±16.5 VS ±13 +15.3/−14.7 ±13 +15.3/−14.7 V
Short-Circuit Current Short to ground ±80 ±80 mA
Output Current RL = 150 Ω ±50 ±50 mA
AD830
Rev. C | Page 4 of 20
AD830J/AD830A AD830S1
Parameter Conditions Min Typ Max Min Typ Max Unit
POWER SUPPLIES
Operating Range ±4 ±16.5 ± 4 ±16.5 V
Quiescent Current TMIN – TMAX 14.5 17 14.5 17 mA
+PSRR (to VP) DC, G = +1 86 86 dB
−PSRR (to VN) DC, G = +1 68 68 dB
PSRR DC, G = +1, ±5 to ±15 VS 66 71 66 71 dB
PSRR DC, G = +1, ±5 to ±15 VS
T
MIN − TMAX 62 68 60 68 dB
1 See the Standard Military Drawing 5962-9313001MPA for specifications.
2 Clipping level function on X channel only.
AD830
Rev. C | Page 5 of 20
VS = ±5 V, RLOAD = 150 Ω, CLOAD = 5 pF, TA = +25°C, unless otherwise noted.
Table 2.
AD830J/AD830A AD830S1
Parameter Conditions Min Typ Max Min Typ Max Units
DYNAMIC CHARACTERISTICS
3 dB Small Signal Bandwidth Gain = +1, VOUT = 100 mV rms 35 40 35 40 MHz
0.1 dB Gain Flatness Frequency Gain = +1, VOUT = 100 mV rms 5 6.5 5 6.5 MHz
Differential Gain Error 0 V to 0.7 V, frequency = 4.5 MHz,
Gain = +2 0.14 0.18 0.14 0.18 %
Differential Phase Error 0 V to 0.7 V, frequency = 4.5 MHz,
Gain = +2 0.32 0.4 0.32 0.4 Degrees
Slew Rate, Gain = +1 2 V step, RL = 500 Ω 210 210 V/μs
4 V step, RL = 500 Ω 240 240 V/μs
3 dB Large Signal Bandwidth Gain = +1, VOUT = 1 V rms 30 36 30 36 MHz
Settling Time VOUT = 2 V step, to 0.1% 35 35 ns
V
OUT = 4 V step, to 0.1% 48 48 ns
Harmonic Distortion 2 V p-p, frequency = 1 MHz −69 −69 dBc
2 V p-p, frequency = 4 MHz −56 −56 dBc
Input Voltage Noise Frequency = 10 kHz 27 27 nV/√Hz
Input Current Noise 1.4 1.4 pA/√Hz
DC PERFORMANCE
Offset Voltage Gain = +1 ±1.5 ±3 ±1.5 ±3 mV
Gain = +1, TMIN − TMAX ±4 ±5 mV
Open-Loop Gain DC 60 65 60 65 dB
Unity Gain Accuracy RL = 1 kΩ ±0.1 ±0.6 ±0.1 ±0.6 %
Peak Nonlinearity, RL= 1 kΩ −1 V ≤ X ≤ +1 V 0.01 0.03 0.01 0.03 % FS
−1.5 V ≤ X ≤ +1.5 V 0.045 0.07 0.045 0.07 % FS
−2 V ≤ X ≤ +2 V 0.23 0.4 0.23 0.4 % FS
Input Bias Current VIN = 0 V, 25°C to TMAX 5 10 5 10 μA
V
IN = 0 V, TMIN 7 13 8 17 μA
Input Offset Current VIN = 0 V, TMIN − TMAX 0.1 1 0.1 1 μA
INPUT CHARACTERISTICS
Differential Voltage Range VCM = 0 ±2.0 ±2.0 V
Differential Clipping Level2 Pin 1 and Pin 2 inputs only ±2.0 ±2.2 ±2.0 ±2.2 V
Common-Mode Voltage Range VDM = ±1 V −2.0 +2.9 −2.0 +2.9 V
CMRR DC, Pin 1/Pin 2, +4 V to −2 V 90 100 90 100 dB
DC, Pin 1/Pin 2, +4 V to −2 V,
T
MIN − TMAX 88 86 dB
Frequency = 4 MHz 55 60 55 60 dB
Input Resistance 370 370 kΩ
Input Capacitance 2 2 pF
OUTPUT CHARACTERISTICS
Output Voltage Swing RL ≥ 150 Ω ±3.2 ±3.5 ±3.2 ±3.5 V
R
L ≥ 150 Ω, ±4 VS ±2.2 −2.4/+2.7 ±2.2 −2.4/+2.7 V
Short-Circuit Current Short to ground −55/+70 −55/+70 mA
Output Current ±40 ±40 mA
AD830
Rev. C | Page 6 of 20
AD830J/AD830A AD830S1
Parameter Conditions Min Typ Max Min Typ Max Units
POWER SUPPLIES
Operating Range ±4 ±16.5 ±4 ±16.5 V
Quiescent Current TMIN − TMAX 13.5 16 13.5 16 mA
+PSRR (to VP) DC, G = +1, offset 86 86 dB
−PSRR (to VN) DC, G = +1, Offset 68 68 dB
PSRR (Dual Supply) DC, G = +1, ±5 to ±15 VS 66 71 66 71 dB
PSRR (Dual Supply) DC, G = +1, ±5 to ±15 VS
T
MIN − TMAX 62 68 60 68 dB
1 See Standard Military Drawing 5962-9313001MPA for specifications.
2 Clipping level function on X channel only.
AD830
Rev. C | Page 7 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage ±18 V
Internal Power Dissipation Observe derating
curves
Output Short-Circuit Duration Observe derating
curves
Common-Mode Input Voltage ±VS
Differential Input Voltage ±VS
Storage Temperature Range (Q) −65°C to +150°C
Storage Temperature Range (N) −65°C to +125°C
Storage Temperature Range (RN) −65°C to +125°C
Operating Temperature Range
AD830J 0°C to +70°C
AD830A −40°C to +85°C
AD830S −55°C to +125°C
Lead Temperature Range (Soldering 60 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD830 is limited by the associated rise in junction temperature.
For the plastic packages, the maximum safe junction
temperature is 145°C. For the CERDIP, the maximum junction
temperature is 175°C. If these maximums are exceeded
momentarily, proper circuit operation will be restored as soon
as the die temperature is reduced. Leaving the AD830 in the
overheated condition for an extended period can result in
permanent damage to the device. To ensure proper operation, it
is important to observe the recommended derating curves.
While the AD830 output is internally short-circuit protected,
this may not be sufficient to guarantee that the maximum
junction temperature is not exceeded under all conditions. If
the output is shorted to a supply rail for an extended period,
then the amplifier may be permanently destroyed.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θJA Unit
28-Lead PDIP Package 90 °C/W
8-Lead SOIC Package 155 °C/W
8-Lead CERDIP Package 11 °C/W
ESD CAUTION
2.5
090
1.5
0.5
–30
1.0
–50
2.0
70503010–10
AMBIENT T E M P ERATURE (°C)
TOTAL POWER DISSIPATION (W)
T
J
MAX = 145° C
8-L EAD PDIP
8-L EAD SOIC
00881-004
2.8
0.2 140
0.8
0.4
–40
0.6
–60
1.4
1.0
1.2
1.6
2.0
2.2
2.6
2.4
1.8
100 120806040200–20 AMBIENT TEMP E RATURE (°C)
TOTAL POWER DISSIPATION (W)
8-L EAD CE RDIP
TJ MAX = 175° C
00881-005
Figure 4. Maximum Power Dissipation vs. Temperature, PDIP and SOIC Packages Figure 5. Maximum Power Dissipation vs. Temperature, CERDIP Package
AD830
Rev. C | Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
±
FREQ UE NCY (Hz )
CMRR (d B)
110
30 10M
50
40
1k
70
60
80
90
100
1M100k10k
V
S
= ±15V
V
S
= ±5V
00881-006
Figure 6. Common-Mode Rejection Ratio vs. Frequency
FREQUENCY ( Hz)
–
50
–70
–90 M01k011M100k1k
–80
–60
HARMONIC DISTORTION (dBc)
±5V SUPPLIES
SECO ND HARMONIC
THIRD HARMONIC
±15V SUPPLIES
SECO ND HARMONIC
THIRD HARMONIC
V
OUT
= 2V p-p
R
L
= 150Ω
GAIN = +1
00881-007
Figure 7. Harmonic Distortion vs. Frequency
JUNCTI O N T EM P ERAT URE (°C)
INPUT CURRENT ( µ A)
9
3140
6
4
–40
5
–60
8
7
120806040200–20 100
00881-008
Figure 8. Input Bias Current vs. Temperature
±
±
±
FREQUE NCY (Hz)
PSRR (dB)
100
10 10M
30
20
1k
40
50
60
70
80
90
1M100k10k
TO V
P
@ ±15V
TO V
N
@ ±15V
TO V
P
@ ±5V
TO V
N
@ ±5V
00881-009
Figure 9. Power Supply Rejection Ratio vs. Frequency
±
FREQUENCY (Hz )
3
–12
–27 100k 10M 100M1M10k
–9
–6
–3
0
–24
–21
–18
–15
GAIN (dB)
1G
±15V
±5V
±10V
R
L
= 150Ω
C
L
= 4.7pF
00881-010
Figure 10. Closed-Loop Gain vs. Frequency G = +1
±
±
±
JUNCTI ON TE M P ERATURE ( °C)
INPUT OFFSET VOL TAGE (mV)
3
–4 140
–1
–3
–40
–2
–60
2
0
1
120100806040200–20
±5V
S
±10V
S
±15V
S
0
0881-011
Figure 11. Input Offset Voltage vs. Temperature
AD830
Rev. C | Page 9 of 20
0.10
0.03
0.01
0.02
0.06
0.04
0.05
0.07
0.08
0.09
1565
0.10
0.03
0.01
0
0
0.02
0.06
0.04
0.05
0.07
0.08
0.09
1413121110987 SUPPLY VOLTAGE (±V)
DIFFERENTIAL GAIN (%)
DIF FERE NT I AL PH ASE (Deg r ees)
PHASE
GAIN
GAIN = +2
RL = 500Ω
FRE Q = 4.5M Hz
00881-012
Figure 12. Differential Gain and Phase vs. Supply Voltage, RL = 500 Ω
–
40
–100 2.00
–70
–90
0.50
–80
0.25
–50
–60
1.751.251.00 1.500.75PE AK AMPLI TUDE ( V)
HARMONI C DI ST ORTI ON (d B)
HD3 ±5V
100kHz
HD2 ±15V
100kHz
HD2 ±5V
100kHz
HD3 ±15V
100kHz
0
0881-013
Figure 13. Harmonic Distortion vs. Peak Amplitude, Frequency = 100 kHz
50
10 M01100
40
20
1k
30
100k 1M10k
FREQUENCY (Hz )
INPUT VOLT AG E NO ISE (n V/√Hz)
0
0881-014
Figure 14. Noise Spectral Density
00
0.20
15
0.06
0.02
6
0.04
5
0.12
0.08
0.10
0.14
0.16
0.18
1413121110987 SUPPLY VOLT AGE (±V)
DIFFERENTIAL GAIN (%)
DIFFE RENTIAL PHASE ( Degrees)
0.40
0.12
0.04
0.08
0.24
0.16
0.20
0.28
0.32
0.36
PHASE
GAIN
GAIN = +2
R
L
= 150Ω
FRE Q = 4.5MHz
00881-015
Figure 15. Differential Gain and Phase vs. Supply Voltage, RL = 150 Ω
–
40
–100 2.00
–70
–90
0.50
–80
0.25
–50
–60
1.751.251.00 1.500.75PEAK AMPL IT UDE ( V)
HARMONIC DIS TORTION (dB)
HD2 ±5V
4MHz
HD3 ±5V
4MHz
HD2 ±15V
4MHz
HD3 ±15V
4MHz
0
0881-016
Figure 16. Harmonic Distortion vs. Peak Amplitude, Frequency = 4 MHz
JUNCTI ON T E M P ERATURE (°C)
QUIESCE NT SUPPLY CURRENT (mA)
15.00
12.25 140
13.00
12.50
–40
12.75
–60
13.75
13.25
13.50
14.00
14.25
14.50
14.75
120100806040200–20
±16.5V
S
±5V
S
00881-017
Figure 17. Supply Current vs. Junction Temperature
AD830
Rev. C | Page 10 of 20
3
–12
–27 1G1M 100M10M100k
–9
–6
–3
0
–24
–21
–18
–15
FREQUENCY (Hz )
UNIT Y GAIN CONNECT ION
GAI N OF 2 CONNECT IO N
9
–6
–21
–3
0
3
6
–18
–15
–12
–9
R
L
= 150 Ω
C
L
= 0pF
±15V
±5V
00881-018
Figure 18. Closed-Loop Gain vs. Frequency for the Three Common
Connections of Figure 16
100mV
V
S
= ±5V
20ns
0%
100
90
10
V
S
= ±15V
00881-019
Figure 19. Small Signal Pulse Response, RL = 150 Ω, CL = 4.7 pF, G = +1
9
–6
–21 1G100k 10M1M10k
–3
0
3
6
–18
–15
–12
–9
FREQUENCY (Hz )
GAIN (dB)
100M
V
S
= ±5V
R
L
= 150Ω
C
L
= 33pF
C
L
= 15pF
C
L
= 4.7pF
0
0881-020
Figure 20. Closed-Loop Gain vs. Frequency vs. CL, G = +1, VS = ±5 V
V
11
2
4
3
8
7
5
6
AD830
C
G
M
G
M
V
P
V
N
OUT
(a)
(b)
V
1
1
2
4
3
8
7
5
6
AD830
CA = 1
A = 1
G
M
G
M
V
P
V
N
OUT
V
OUT
= 2V
1
RESISTORLESS GAIN OF 2
V
OUT
= V
1
OP AMP CONNECTI ON
(c)
V
11
2
4
3
8
7
5
6
AD830
CA = 1
G
M
G
M
V
P
V
N
OUT
V
OUT
= V
1
GAIN OF 1
0
0881-021
Figure 21. Connection Diagrams
1V
V
S
= ±5V
20ns
0%
100
90
10
V
S
= ±15V
00881-022
Figure 22. Large Signal Pulse Response, RL = 150 Ω, CL = 4.7 pF, G = +1
9
–6
–21 1G100k 10M1M10k
–3
0
3
6
–18
–15
–12
–9
FREQUENCY ( Hz )
GAIN (dB)
100M
V
S
= ±15V
R
L
= 150ΩC
L
= 33pF
C
L
= 15pF
C
L
= 4.7pF
00881-023
Figure 23. Closed-Loop Gain vs. Frequency vs. CL, G = +1, VS = ±15 V
AD830
Rev. C | Page 11 of 20
THEORY OF OPERATION
TRADITIONAL DIFFERENTIAL AMPLIFICATION
In the past, when differential amplification was needed to reject
common-mode signals superimposed with a desired signal,
most often the solution used was the classic op amp based
difference amplifier shown in Figure 24. The basic function
VO = V1 − V2 is simply achieved, but the overall performance is
poor and the circuit possesses many serious problems that make
it difficult to realize a robust design with moderate to high
levels of performance.
V
1
V
OUT
V
2
R
1
R
2
R
3
R
4
ONLY IF R
1
= R
2
= R
3
= R
4
DOES V
OUT
= V
1
– V
2
00881-024
Figure 24. Op Amp Based Difference Amplifier
PROBLEMS WITH THE OP AMP BASED APPROACH
• Low common-mode rejection ratio (CMRR)
• Low impedance inputs
• CMRR highly sensitive to the value of source R
• Different input impedance for the + and − input
• Poor high frequency CMRR
• Requires very highly matched resistors, R1 to R4, to achieve
high CMRR
• Halves the bandwidth of the op amp
• High power dissipation in the resistors for large common-
mode voltage
AD830 FOR DIFFERENTIAL AMPLIFICATION
The AD830 amplifier was specifically developed to solve the
listed problems with the discrete difference amplifier approach.
Its topology, discussed in detail in the Understanding the AD830
Topolog y section, by design acts as a difference amplifier. The
circuit of Figure 25 shows how simply the AD830 is configured
to produce the difference of the two signals, V1 and V2, in which
the applied differential signal is exactly reproduced at the
output relative to a separate output common. Any common-
mode voltage present at the input is removed by the AD830.
V
1
V
OUT
I
Y
I
X
V
2
A = 1
V I
→
V I
→
V
OUT
= V
1
– V
2
00881-025
Figure 25. AD830 as a Difference Amplifier
ADVANTAGEOUS PROPERTIES OF THE AD830
• High common-mode rejection ratio (CMRR)
• High impedance inputs
• Symmetrical dynamic response for +1 and −1 Gain
• Low sensitivity to the value of source R
• Equal input impedance for the + and − input
• Excellent high frequency CMRR
• No halving of the bandwidth
• Constant power distortion versus common-mode voltage
• Highly matched resistors not needed
UNDERSTANDING THE AD830 TOPOLOGY
The AD830 represents Analog Devices first amplifier product to
embody a powerful alternative amplifier topology. Referred to
as active feedback, the topology used in the AD830 provides
inherent advantages in the handling of differential signals,
differing system commons, level shifting, and low distortion,
high frequency amplification. In addition, it makes possible the
implementation of many functions not realizable with single op
amp circuits or superior to op amp based equivalent circuits.
With this in mind, it is important to understand the internal
structure of the AD830.
The topology, reduced to its elemental form, is shown in Figure 26.
Nonideal effects, such as nonlinearity, bias currents, and limited
full scale, are omitted from this model for simplicity but are
discussed later. The key feature of this topology is the use of
two, identical voltage-to-current converters, GM, that make up
input and feedback signal interfaces. They are labeled with
inputs VX and VY, respectively. These voltage-to-current
converters possess fully differential inputs, high linearity, high
input impedance, and wide voltage range operation. This
enables the part to handle large amplitude differential signals; it
also provides high common-mode rejection, low distortion, and
negligible loading on the source. The label, GM, is meant to
convey that the transconductance is a large signal quantity,
unlike in the front end of most op amps. The two GM stage
current outputs, IX and IY, sum together at a high impedance
node, which is characterized by an equivalent resistance and
capacitance connected to an ac common. A unity voltage gain
stage follows the high impedance node to provide buffering
from loads. Relative to either input, the open-loop gain, AOL, is
set by the transconductance, GM, working into the resistance,
RP; AOL = GM × RP. The unity gain frequency, ω0 dB, for the open-
loop gain is established by the transconductance, GM, working
into the capacitance, CC; ω0 dB = GM/CC. The open-loop
description of the AD830 is shown below for completeness.
AD830
Rev. C | Page 12 of 20
V
X1
V
OUT
I
Y
I
X
C
C
A = 1
G
M
A
OLS
=G
M
R
P
V
X2
G
M
V
Y1
V
Y2
R
P
I
Z
I
X
= (V
X1
– V
X2
) G
M
I
Y
= (V
Y1
– V
Y2
) G
M
I
Z
= I
X
+ I
Y
1 + S (C
C
R
P
)
0
0881-026
Figure 26. Topology Diagram
V
X1
V
OUT
I
Y
I
X
C
C
A = 1
G
M
1
V
X2
G
M
V
Y1
V
Y2
V
X1
– V
X2
= V
Y2
– V
Y1
FOR V
Y2
= V
OUT
V
OUT
= (V
X1
– V
X2
+ V
Y1
)1 + S(C
C
/G
M
)
00881-027
Figure 27. Closed-Loop Connection
Precise amplification is accomplished through closed-loop
operation of this topology. Voltage feedback is implemented via
the Y GM stage where the output is connected to the −Y input
for negative feedback, as shown in Figure 27. An input signal is
applied across the X GM stage, either fully differential or single-
ended referred to common. It produces a current signal that is
summed at the high impedance node with the output current
from the Y GM stage. Negative feedback nulls this sum to a small
error current necessary to develop the output voltage at the high
impedance node. The error current is usually negligible, so the
null condition essentially forces the Y GM output stage current
to equal the exact X GM output current. Because the two
transconductances are identical, the differential voltage across
the Y inputs equals the negative of the differential voltage across
the X input; VY = −VX or, more precisely, VY2 − VY1 = VX1 − VX2.
This simple relation provides the basis to easily analyze any
function possible to synthesize with the AD830, including any
feedback situation.
The bandwidth of the circuit is defined by the GM and the
capacitor, CC. The highly linear GM stages give the amplifier a
single-pole response, excluding the output amplifier and
loading effects. It is important to note that the bandwidth and
general dynamic behavior is symmetrical (identical) for the
noninverting and the inverting connections of the AD830. In
addition, the input impedance and CMRR are the same for
either connection. This is very advantageous and unlike in a
voltage or current feedback amplifier where there is a distinct
difference in performance between the inverting and
noninverting gain. The practical importance of this cannot be
overemphasized and is a key feature offered by the AD830
amplifier topology.
INTERFACING THE INPUT
Common-Mode Voltage Range
The common-mode range of the AD830 is defined by the
amplitude of the differential input signal and the supply voltage.
The general definition of common-mode voltage, VCM, is
usually applied to a symmetrical differential signal centered
around a particular voltage, as illustrated in Figure 28. This is
the meaning implied here for common-mode voltage. The
internal circuitry establishes the maximum allowable voltage on
the input or feedback pins for a given supply voltage. This
constraint and the differential input voltage sets the common-
mode voltage limit. Figure 29 shows a curve of the common-
mode voltage range versus the differential voltage for three
supply voltage settings.
V
MAX
V
CM
V
PEAK
00881-028
Figure 28. Common-Mode Definition
DIFFERENTIAL INPUTVOLTAGE (V
PEAK
)
15
00
COMMON-MODEVOLT
2.0
A
GE (±V)
0.4 0.8 1.2 1.6
6
3
12
9
±5V =V
S
±15V = V
S
–V
CM
–V
CM
+V
CM
+V
CM
+V
CM
±10V = V
S
–V
CM
00881-029
Figure 29. Input Common-Mode Voltage Range vs. Differential Input Voltage
Differential Voltage Range
The maximum applied differential voltage is limited by the
clipping range of the input stages. This is nominally set at a
2.4 V magnitude and depicted in the cross plot (X-Y) in Figure 30.
The useful linear range of the input stages is set at 2 V but is
actually a function of the distortion required for a particular
application. The distortion increases for larger differential input
voltages. A plot of relative distortion versus the input differential
voltage is shown in Figure 13 and Figure 16. The distortion
characteristics impose a secondary limit to the differential input
voltage for high accuracy applications.
AD830
Rev. C | Page 13 of 20
10
0%
100
90
1V 1V
00881-030
Figure 30. Clipping Behavior
Choice of Polarity
The sign of the gain is easily selected by choosing the polarity
of the connections to the + and − inputs of the X GM stage.
Swapping between inverting and noninverting gain is possible
simply by reversing the input connections. The response of the
amplifier is identical in either connection, except for the sign
change.
The bandwidth, high impedance, and transient behavior of the
AD830 is symmetrical for both polarities of gain. This is very
advantageous and unlike an op amp.
Input Impedance
The relatively high input impedance of the AD830, for a
differential receiver amplifier, permits connections to modest
impedance sources without much loading or loss of common-
mode rejection. The nominal input resistance is 300 k. The
real limit to the upper value of the source resistance is in its
effect on common-mode rejection and bandwidth. If the source
resistance is in only one input, then the low frequency
common-mode rejection is lowered to ≈ RIN/RS. The source
resistance/input capacitance pole limits the bandwidth. Refer to
the following equation:
⎟
⎠
⎞
⎜
⎝
⎛××
π
=IN
SCRf 2
1
Furthermore, the high frequency common-mode rejection is
additionally lowered by the difference in the frequency response
caused by the RS × CIN pole. Therefore, to maintain good low
and high frequency common-mode rejection, it is recommended
that the source resistances of the + and − inputs be matched and
of modest value (≤10 k).
Handling Bias Currents
The bias currents are typically 4 A flowing into each pin of the
GM stages of the AD830. Because all applications possess some
finite source resistance, the bias current through this resistor
creates a voltage drop (IBIAS × RS). The relatively high input
impedance of the AD830 permits modest values of RS, typically
≤10 k. If the source resistance is in only one terminal, then an
objectionable offset voltage may result, for example, 4 A × 5
k = 20 mV. Placement of an equal value resistor in series with
mismatches in the resistances, a residual offset remains and is
likely to be greater than the bias current (offset current)
mismatches.
Applying Fee
the other input cancels the offset to first order. However, due to
dback
for use with gains from 1 to 100. Gains
hat
y
830 is defined by the differential
n
ge
e
The AD830 is intended
greater than one are simply set by a pair of resistors connected
as shown in the difference amplifier (Figure 40) with gain >1.
The value of the bottom resistor, R2, should be kept less than
1 k to ensure that the pole formed by CIN and the parallel
connection of R1 and R2 is sufficiently high in frequency so t
it does not introduce excessive phase shift around the loop and
destabilize the amplifier. A compensating resistor, equal to the
parallel combination of R1 and R2, should be placed in series
with the other Y GM stage input to preserve the high frequenc
common-mode rejection and to lower the offset voltage
induced by the input bias current.
Output Common Mode
The output swing of the AD
input voltage, the gain, and the output common. Depending o
the anticipated signal span, the output common (or ground)
may be set anywhere between the allowable peak output volta
in a manner similar to that described for input voltage common
mode. A plot of the peak output voltage versus the supply is
shown in Figure 31. A prediction of the common-mode rang
versus the peak output differential voltage can be easily derived
from the maximum output swing as VOCM = VMAX − VPEAK.
SUPPLY VOLTAGE (V)
15
0200
MAXIMUM OUTPUT S W ING (±V)
481216
6
3
12
9
V
P
V
N
00881-031
Figure 31. Maximum Output Swing vs. Supply
Output Cur
output current is set by the short-circuit
nto
rent
The absolute peak
current limiting, typically greater than 60 mA. The maximum
drive capability is rated at 50 mA but without a guarantee of
distortion performance. Best distortion performance is obtained
by keeping the output current ≤20 mA. Attempting to drive
large voltages into low valued resistances, for example, 10 V i
150 causes an apparent lowering of the limit for output signal
swing but is just the current limiting behavior.
AD830
Rev. C | Page 14 of 20
Driving Cap Loads
The AD830 is capable of driving modest sized capacitive loads
while maintaining its rated performance. Several curves of
bandwidth versus capacitive load are given in Figure 34 and
Figure 37. The AD830 was designed primarily as a low
distortion video speed amplifier but with a trade-off, for
example, giving up very large capacitive load driving capability.
If very large capacitive loads must be driven, the network shown
in Figure 32 should be used to ensure stable operation. If the
loss of gain caused by the resistor, RS, in series with the load is
objectionable, the optional feedback network shown may be
added to restore the lost gain.
+
V
S
V
OUT
R
S
36.5Ω
*OPTIONAL
FEEDBACK
NETW ORK
–V
S
AD830
1
2
3
4
8
7
6
5
A = 1
G
M
G
M
C
0.1µF
0.1µF
C
1
100pF
R
S
R
2
R
1
1kΩ
INPUT
SIGNAL
V
CM
Z
CM
00881-032
Figure 32. Circuit for Driving Large Capacitive Loads
FREQUENCY (Hz)
3
10k
CLOSED-LOOP AMPLITUDE RESPONSE (dB)
–27 100k 1M 10M 100M
±15V
±5V
–24
–21
–18
–15
–12
–9
–6
–3
0
00881-033
Figure 33. Closed-Loop Response vs. Frequency with 100 pF Load and Series
Resistor Compensation
SUPPLIES, BYPASSING, AND GROUNDING
(FIGURE 34)
The AD830 is capable of operating over a wide range of supply
voltages, both single and dual supplies. The coupling may be dc
or ac, provided the input and output voltages stay within the
specified common-mode voltage limits. For dual supplies, the
device works from ±4 V to ±16.5 V. Single-supply operation is
possible over 8 V to 33 V. It is also possible to operate the part
with split-supply voltages, for example, +24 V or −5 V for
special applications such as level shifting. The primary
constraint is that the total potential between the two supplies
does not exceed 33 V.
Inclusion of power supply bypassing capacitors is necessary to
achieve stable behavior and the specified performance. It is
especially important when driving low resistance loads. At
minimum, connect a 0.1 F ceramic capacitor at the supply lead
of the AD830 package. In addition, for the best bypassing, it is
best to connect a 0.01 F ceramic capacitor and 4.7 F tantalum
capacitor to the supply lead going to the AD830.
0.1µF0.01µF
V
P
AND
V
N
V
P
AND
V
N
4.7µF
LOAD
GND
LEAD
LOAD
GND
LEAD
0
0881-034
Figure 34. Supply Decoupling Options
The AD830 is designed to be capable of rejecting noise and
dissimilar potentials in the ground lines. Therefore, proper
care is necessary to realize the benefits of the differential
amplification of the part. Separation of the input and output
grounds is crucial in rejection of the common-mode noise at
the inputs and eliminating any ground drops on the input signal
line. For example, connecting the ground of a coaxial cable to
the AD830 output common (board ground) could degrade the
CMR and also introduce power-down loading on cable grounds.
However, it is also necessary as in any electronic system to
provide a return path for bias currents back to their original
power supply. This is accomplished by providing a connection
between the differing grounds through a modest impedance
labeled ZCM, for example, 100 .
Single-Supply Operation
The AD830 is capable of operating in single power supply
applications down to a voltage of 8 V, with the generalized
connection shown in Figure 35. There is a constraint on the
common-mode voltage at the input and output that establishes
the range for these voltages. Direct coupling may be used for
input and output voltages that lie in these ranges. Any gain
network applied needs to be referred to the output common
connection or have an appropriate offset voltage. In situations
where the signal lies at a common voltage outside the common-
mode range of the AD830, direct coupling does not work, so ac
coupling should be used. Figure 47 shows how to easily
accomplish coupling to the AD830. For single-supply operation
where direct coupling is desired, the input and output common-
mode curves (Figure 36 and Figure 37) should be used.
AD830
Rev. C | Page 15 of 20
V
P
V
OUT
AD830
1
2
3
4
8
7
6
5
A = 1
C
V
ICM
V
IN
V
OCM
V
OUT
= (V
IN
– V
ICM
) + V
OCM
G
M
G
M
00881-035
Figure 35. General Single-Supply Connection
DIFFERENTIAL INPUTVOLTAGE (V
PEAK
)
16
00
COMMON-MO DE VO LTAGE LIMI TS (±V)
0.4 1.2 1.60.8
8
4
12
2.0
V
P
= +30V
V
P
= +15V
V
P
= +10V
TO GND
20
24
28
30
00881-036
Figure 36. Input Common-Mode Range for Single Supply
SUPPLYVOLTAGE (V)
16
03010
MAXIMUM OUTPUT SWING (±V)
14 18 22 26
8
4
12
20
24
28
TO V
P
TO GND
0
0881-037
Figure 37. Output Swing Limit for Single Supply
Differential Line Receiver
The AD830 is specifically designed to perform as a differential
line receiver. The circuit in Figure 38 shows how simple it is to
configure the AD830 for this function. The signal from System A is
received differentially relative to the common of System A, and
that voltage is exactly reproduced relative to the common in
System B. The common-mode rejection versus frequency, shown
in Figure 6, is excellent, typically 100 dB at low frequencies.
The high input impedance permits the AD830 to operate as a
bridging amplifier across low impedance terminations with
negligible loading. The differential gain and phase specifications
are very good, as shown in Figure 12 for 500 and Figure 15
for 150 . The input and output common should be separated
to achieve the full CMR performance of the AD830 as a
differential amplifier. However, a common return path is
necessary between System A and System B.
COMMON IN
SYSTEM A
VN
AD830
1
2
3
4
8
7
6
5
A = 1
GM
GMC
VCM
ZCM
COMM O N IN
SYSTEM B
V
P
VOUT
0.1µF
0.1µF
INPUT
SIGNAL
V1
V2
VOUT = V1 – V2
0
0881-038
Figure 38. Differential Line Receiver
Wide Range Level Shifter
The wide common-mode range and accuracy of the AD830
allows easy level shifting of differential signals referred to an
input common-mode voltage to any new voltage defined at the
output. The inputs may be referenced to levels as high as 10 V at
the inputs with a ±2 V swing around 10 V. In the circuit in
Figure 39, the output voltage, VOUT, is defined by the simple
equation shown below. The excellent linearity and low distortion
are preserved over the full input and output common-mode
range. The voltage sources need not be of low impedance, since
the high input resistance and modest input bias current of the
AD830 V-to-I converters permit the use of resistive voltage
dividers as reference voltages.
GM
V
P
VOUT
INPUT
COMMON
VN
0.1µF
AD830
1
2
3
4
8
7
6
5
A = 1
C
0.1µF
INPUT
SIGNAL
V1
V2
OUTPUT
COMMON
V3
VOUT = V1 – V2 + V3
00881-039
GM
Figure 39. Differential Amplification with Level Shifting
Difference Amplifier with Gain > 1
The AD830 can provide instrumentation amplifier style and
differential amplification at gains greater than 1. The input
signal is connected differentially and the gain is set via feedback
resistors, as shown in Figure 40. The gain is G = (R2 + R1)/R2.
The AD830 can provide either inverting or noninverting
differential amplification. The polarity of the gain is established
by the polarity of the connection at the input. Feedback resistor,
R2, should generally be R2 ≤ 1 k to maintain closed-loop
AD830
Rev. C | Page 16 of 20
stability and also keep bias current induced offsets low. Highest
CMRR and lowest dc offsets are preserved by including a
compensating resistor in series with Pin 3. The gain may be as
high as 100.
0.1µF
0.1µF
V
P
V
OUT
V
N
AD830
1
2
3
4
8
7
6
5
A = 1
C
G
M
G
M
INPUT
SIGNAL
V
CM
Z
CM
V
1
V
2
R
1
R
2
R
2
R
1
V
OUT
= (V
1
– V
2
)(1 + R
1
/R
2
)
00881-040
Figure 40. Gain of G Differential Amplifier, G>1
Offsetting the Output With Gain
Some applications, such as ADCs, require that the signal be
amplified and also offset, typically to accommodate the input
range of the device. The AD830 can offset the output signal
very simply through Pin 3 even with gain > 1. The voltage
applied to Pin 3 must be attenuated by an appropriate factor so
that V3 × G = desired offset. In Figure 41, a resistive divider
from a voltage reference is used to produce the attenuated offset
voltage.
V
P
V
OUT
V
N
AD830
1
2
3
4
8
7
6
5
A = 1
G
M
G
M
C
0.1µF
0.1µF
INPUT
SIGNAL
V
CM
Z
CM
V
1
V
2
R
1
R
2
R
2
R
1
R
3
R
4
V
3
V
REF
V
OUT
= (V
1
– V
2
)(1 + R
1
/R
2
)
0
0881-041
Figure 41. Offsetting the Output with Differential Gain >1
Loop Through or Line Bridging Amplifier (Figure 42)
The AD830 is ideally suited for use as a video line bridging
amplifier. The video signal is tapped from the conductor of the
cable relative to its shield. The high input impedance of the
AD830 provides negligible loading on the cable. More significantly,
the benign loading is maintained while the AD830 is powered
down. Coupled with its good video load driving performance,
the AD830 is well suited for video cable monitoring applications.
V
P
V
OUT
V
N
AD830
1
2
3
4
8
7
6
5
A = 1
G
M
C
G
M
R
G
249Ω
OPTIONAL C
C
499Ω
499Ω
75Ω
75Ω
0.1µF
0.1µF
0
0881-042
Figure 42. Cable Tap Amplifier
Resistorless Summing
Direct, two input, resistorless summing is easily realized from
the general unity gain mode. By grounding VX2 and applying the
two inputs to VX1 and VY1, the output is the exact sum of the
applied voltages, V1 and V3, relative to common; VOUT = V1 + V3.
A diagram of this simple but potent application is shown below
in Figure 43. The AD830 summing circuit possesses several
virtues not present in the classic op amp based summing circuits.
It has high impedance inputs, no resistors, very precise summing,
high reverse isolation, and noninverting gain. Achieving this
function and performance with op amps requires significantly
more components.
V
P
OUT
V
N
AD830
1
2
3
4
8
7
6
5
A = 1
G
M
C
G
M
V
1
V
3
V
OUT
= V
1
+V
3
0
0881-043
Figure 43. Resistorless Summing Amplifier
2× Gain Bandwidth Line Driver
A gain of two, without the use of resistors, is possible with the
AD830. This is accomplished by grounding VX2, tying the VX1
and VY1 inputs together, and applying the input, VIN, to this
wired connection. The output is exactly twice the applied
voltage, VIN; VOUT = 2 × VIN. Figure 44 shows the connections
for this highly useful application. The most notable characteristic of
this alternative gain of +2 is that there is no loss of bandwidth as
in a voltage feedback op amp based gain of +2 where the
bandwidth is halved; therefore, the gain bandwidth is doubled.
In addition, this circuit is accurate without the need for any
precise valued resistors, as in the op amp equivalents, and it
possesses excellent differential gain and phase performance, as
shown in Figure 45 and Figure 46.
AD830
Rev. C | Page 17 of 20
75Ω
75Ω
V
P
V
OUT
V
N
AD830
1
2
3
4
8
7
6
5
A = 1
G
M
G
M
C
0.1µF
0.1µF
V
IN
00881-044
Figure 44. Full Bandwidth Line Driver (G = +2)
SUPPLYVOLTAG E (±V)
0.05
0.01
515
DIFFERENTIAL GAIN (%)
121731
0.04
0.06
0.07
0.09
4
GAIN
PHASE
GAIN = +2
R
L
= 150Ω
FREQ = 3.58MHz
0 TO 0. 7V
1110986
0.02
0.03
0.10
0.08
DIFFE RE NTIAL PHASE ( Degrees)
0.16
0.04
0.06
0.14
0.18
0.02
0.12
0.10
0.08
0.20
0
0881-045
FREQUE NCY (Hz )
0.2
10k
AMPL ITUDE RES PONSE ( dB)
–0.8 100k 1M 10M 100M
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1 VS = ±15V
RL = 150Ω
GAIN = +2 VS = ±10V
VS = ±5V
0
0881-046
Figure 46. 0.1 dB Gain Flatness for the Circuit of Figure 44
AC-COUPLED LINE RECEIVER
The AD830 is configurable as an ac-coupled differential
amplifier on a single- or bipolar-supply voltage. All that is
needed is inclusion of a few noncritical passive components, as
illustrated in Figure 47. A simple resistive network at the X GM
input establishes a common-mode bias. Here, the common
mode is centered at 6 V, but in principle can be any voltage
within the common-mode limits of the AD830. The 10 k
resistors to each input bias the X GM stage with sufficiently high
impedance to keep the input coupling corner frequency low, but
not too large so that residual bias current induced offset voltage
becomes troublesome. For dual-supply operation, the 10 k
resistors may go directly to ground. The output common is
conveniently set by a Zener diode for a low impedance
reference to preserve the high frequency CMR. However, a
simple resistive divider works fine, and good high frequency
CMR can be maintained by placing a compensating resistor in
series with the +Y input. The excellent CMRR response of the
circuit is shown in Figure 48. A plot of the 0.1 dB flatness from
10 Hz is also shown. With the use of 10 F capacitors, the CMR
is >90 dB down to a few tens of hertz. This level of performance
is almost impossible to achieve with discrete solutions.
Figure 45. Differential Gain and Phase for the Circuit of Figure 44
75Ω
75Ω
+12
V
V
OUT
1000µF
10µF
10µF
AD830
1
2
3
4
8
7
6
5
A = 1
G
M
G
M
C
0.1µF
Z
CM
75Ω
COAX
CABLE
+12V
4.7kΩ
6.8V
1N4736
INPUT
SIGNAL
R
T
10kΩ
10kΩ
2kΩ*
+V
S
10kΩ
10kΩ
*OPT IO NAL T UNI NG FOR IMPROVING
VERY LO W FREQ UENCY CMR.
00881-047
Figure 47. AC-Coupled Line Receiver
AD830
Rev. C | Page 18 of 20
FREQUENCY (Hz)
20
COMMON-MODE REJECTION (dB)
40
60
80
100
120
WI TH CI RCUI T TRIMM E D USING
EXTERNAL 2kΩ POTENTIOMETER
WITHOUT EXTERNAL
2kΩ POTENTIOMETER
10 100 1k 10k 100k 1M 10M 100M
0
0881-048
FREQUENCY ( Hz )
–0.910
AMPL ITUDE RE SPONS E (dB)
100 1k 10k 100k 1M 10M
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0
0881-049
Figure 48. Common-Mode Rejection vs. Frequency for Line Receiver Figure 49. Amplitude Response vs. Frequency for Line Receiver
AD830
Rev. C | Page 19 of 20
OUTLINE DIMENSIONS
COM PLI ANT TO JEDEC STANDARDS MS-001
CONT ROLLING DIM E NS IONS ARE IN INCHES; M IL L IMETER DI MENSIONS
(IN PARENT HE S ES) ARE ROUNDED-O FF INCH EQ UIVALENTS F OR
REFERENCE ONLY AND ARE NOT APP RO PRI ATE FOR USE IN DESIGN.
CORNER LE ADS MAY BE CONFIG URED AS WHOL E O R HAL F LE ADS.
070606-A
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
SEATING
PLANE
0.015
(0.38)
MIN
0.210 (5.33)
MAX
0.150 ( 3.81)
0.130 ( 3.30)
0.115 (2. 92)
0.070 ( 1.78)
0.060 ( 1.52)
0.045 ( 1.14)
8
14
5
0.280 ( 7.11)
0.250 ( 6.35)
0.240 ( 6.10)
0.100 (2.54)
BSC
0.400 ( 10 .16)
0.365 ( 9.27)
0.355 ( 9.02)
0.060 ( 1 .52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 ( 8.26)
0.310 ( 7.87)
0.300 ( 7.62)
0.195 ( 4.95)
0.130 ( 3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.005 (0.13)
MIN
Figure 50. 8-Lead Plastic Dual-in-Line Package [PDIP]
(N-8)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00(0.1968)
4.80(0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 51. 8-Lead Standard Small Outline Package [SOIC_N]
(R-8)
Dimensions shown in millimeters and (inches)
AD830
Rev. C | Page 20 of 20
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.310 (7.87)
0.220 (5.59)
0.005 (0.13)
MIN 0.055 (1.40)
MAX
0.100 (2.54) BSC
15°
0°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200 (5.08)
MAX
0.405 (10.29) MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36) 0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
14
58
Figure 52. 8-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-8)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model1
Temperature Range Package Description Package Option
AD830AN −40°C to +85°C 8-Lead PDIP N-8
AD830ANZ −40°C to +85°C 8-Lead PDIP N-8
AD830AR −40°C to +85°C 8-Lead SOIC_N R-8
AD830ARZ −40°C to +85°C 8-Lead SOIC_N R-8
AD830ARZ-REEL −40°C to +85°C 8-Lead SOIC_N R-8
AD830ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
AD830JR 0°C to +70°C 8-Lead SOIC_N R-8
AD830JR-REEL 0°C to +70°C 8-Lead SOIC_N R-8
AD830JR-REEL7 0°C to +70°C 8-Lead SOIC_N R-8
AD830JRZ 0°C to +70°C 8-Lead SOIC_N R-8
AD830JRZ-RL 0°C to +70°C 8-Lead SOIC_N R-8
AD830JRZ-R7 0°C to +70°C 8-Lead SOIC_N R-8
5962-9313001MPA2
−55°C to +125°C 8-Lead CERDIP Q-8
1 Z = RoHS Compliant Part.
2 See Standard Military Drawing 5962-9313001 MPA for specifications.
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registered trademarks are the property of their respective owners.
D00881-0-3/10(C)
