LTM8048
1
8048fg
For more information www.linear.com/LTM8048
INPUT VOLTAGE (V)
0
V
OUT1
CURRENT (mA)
330
230
130
280
180
80 10 20
8048 TA01b
30
5 15 25
TYPICAL APPLICATION
FEATURES DESCRIPTION
3.1VIN to 32VIN Isolated
µModule DC/DC Converter
with LDO Post Regulator
The LT M
®
8048 is an isolated flyback µModule DC/DC
converter with LDO post regulator. The LTM8048 has an
isolation rating of 725VDC. Included in the package are
the switching controller, power switches, transformer, and
all support components. Operating over an input voltage
range of 3.1V to 32V, the LTM8048 supports an output
voltage range of 2.5V to 13V, set by a single resistor. There
is also a linear post regulator whose output voltage is ad-
justable from 1.2V to 12V as set by a single resistor. Only
output, input, and bypass capacitors are needed to finish
the design. Other components may be used to control the
soft-start control and biasing.
The LTM8048 is packaged in a thermally enhanced, com-
pact (11.25mm × 9mm × 4.92mm) over-molded ball grid
array (BGA) package suitable for automated assembly by
standard surface mount equipment. The L
TM8048 is avail-
able with SnPb (BGA) or RoHS compliant terminal finish.
L, LT, LTC, LTM, Linear Technology, the Linear logo and µModule are registered trademarks of
Linear Technology Corporation. All other trademarks are the property of their respective owners.
APPLICATIONS
n Complete Switch Mode Power Supply
n 725VDC Isolation
n Wide Input Voltage Range: 3.1V to 32V
n VOUT1 Output:
Up to 440mA (VOUT1 = 2.5V, 24VIN)
2.5V to 13V Output Range
n VOUT2 Low Noise Linear Post Regulator:
Up to 300mA
1.2V to 12V Output Range
n Current Mode Control
n Programmable Soft-Start
n User Configurable Undervoltage Lockout
n SnPb or RoHS Compliant Finish
n Low Profile (11.25mm × 9mm × 4.92mm) Surface
Mount BGA Package
n Industrial Sensors
n Industrial Switches
n Ground Loop Mitigation
Total Output Current vs VIN
725V DC Isolated Low Noise µModule Regulator
725VDC ISOLATION
LTM8048
8048 TA01
VIN
3.1V TO 29V VOUT2
5V
5.7V
10µF
22µF
2.2µF
4.7µF 6.19k
162k
VOUT1
VOUT2
VIN
RUN
ADJ1
SS
BYPBIAS
GND
ADJ2
VOUT–
ISOLATION BARRIER
LTM8048
2
8048fg
For more information www.linear.com/LTM8048
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
VIN, RUN, BIAS ........................................................32V
ADJ1, SS .....................................................................5V
VOUT1 Relative to VOUT– ............................................16V
(VIN – GND) + (VOUT1 – VOUT–) .................................36V
VOUT2 Relative to VOUT– ..........................................+20V
ADJ2 Relative to VOUT– .............................................+7V
BYP Relative to VOUT– ............................................+0.6V
BIAS Above VIN ........................................................ 0.1V
GND to VOUT– Isolation (Note 2) ........................ 725VDC
Maximum Internal Temperature (Note 3) .............. 125°C
Maximum Solder Temperature .............................. 250°C
Storage Temperature.............................. –55°C to 125°C
(Note 1)
TOP VIEW
H
G
F
E
D
C
B
A
1234567
BANK 2
VOUT–BANK 1
VOUT1
BANK 4
GND
BIAS
RUN
ADJ2
BYP
ADJ1
SS
BANK 5
VIN
BANK 3
VOUT2
BGA PACKAGE
45-LEAD (11.25mm × 9mm × 4.92mm)
TJMAX = 125°C, θJA = 23.2°C/W, θJCbottom = 5.8°C/W, θJCtop = 23.2°C/W, θJB = 6.7°C/W
WEIGHT = 1.1g, θ VALUES DETERMINED PER JEDEC 51-9, 51-12
ORDER INFORMATION
PART NUMBER
PAD OR BALL
FINISH
PART MARKING*
PACKAGE TYPE MSL RATING TEMPERATURE RANGE (NOTE 3) DEVICE FINISH CODE
LTM8048EY#PBF SAC305 (RoHS) LTM8048Y e1 BGA 3 –40°C to 125°C
LTM8048IY#PBF SAC305 (RoHS) LTM8048Y e1 BGA 3 –40°C to 125°C
LTM8048IY SnPb (63/37) LTM8048Y e0 BGA 3 –40°C to 125°C
LTM8048MPY#PBF SAC305 (RoHS) LTM8048Y e1 BGA 3 –55°C to 125°C
LTM8048MPY SnPb (63/37) LTM8048Y e0 BGA 3 –55°C to 125°C
Consult Marketing for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping
container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Pb-free & Non-Pb-free Part Markings:
www.linear.com/leadfree
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures:
www.linear.com/umodule/pcbassembly
• BGA Package and Tray Drawings:
www.linear.com/packaging/
LTM8048
3
8048fg
For more information www.linear.com/LTM8048
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM8048 isolation is tested at 725VDC for one second in each
polarity.
Note 3: The LTM8048E is guaranteed to meet performance specifications
from 0°C to 125°C. Specifications over the –40°C to 125°C internal
temperature range are assured by design, characterization and correlation
with statistical process controls. LTM8048I is guaranteed to meet
specifications over the full –40°C to 125°C internal operating temperature
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, RUN = 12V (Note 3).
PARAMETER CONDITIONS MIN TYP MAX UNITS
Minimum Input DC Voltage BIAS = VIN l3.1 V
VOUT1 DC Voltage RADJ1 = 12.4k
RADJ1 = 6.98k
RADJ1 = 3.16k
l
4.75
2.5
5
12
5.25
V
V
V
VIN Quiescent Current VRUN = 0V
Not Switching
850
1 µA
µA
VOUT1 Line Regulation 6V ≤ VIN ≤ 31V, IOUT = 0.15A 1.7 %
VOUT1 Load Regulation 0.05A ≤ IOUT ≤ 0.2A 1.5 %
VOUT1 Ripple (RMS) IOUT = 0.1A 20 mV
Input Short Circuit Current VOUT1 Shorted 30 mA
RUN Pin Input Threshold RUN Pin Rising 1.18 1.24 1.30 V
RUN Pin Current VRUN = 1V
VRUN = 1.3V
2.5
0.1
µA
µA
SS Threshold 0.7 V
SS Sourcing Current SS = 0V –10 µA
BIAS Current VIN = 12V, BIAS = 5V, ILOAD1 = 100mA 8 mA
Minimum BIAS Voltage (Note 4) ILOAD1 = 100mA 3.1 V
LDO (VOUT2) Minimum Input DC Voltage (Note 5) 1.8 2.3 V
VOUT2 Voltage Range VOUT1 = 16V, RADJ2 Open, No Load (Note 5)
VOUT1 = 16V, RADJ2 = 41.2k, No Load (Note 5)
1.22
15.8
V
V
ADJ2 Pin Voltage VOUT1 = 2V, IOUT2 = 1mA (Note 5)
VOUT1 = 2V, IOUT2 = 1mA, E- and I-Grades (Note 5)
VOUT1 = 2V, IOUT2 = 1mA, MP-Grade (Note 5)
l
l
1.19
1.15
1.22
1.25
1.29
V
V
V
VOUT2 Line Regulation 2V < VOUT1 < 16V, IOUT2 = 1mA (Note 5) 1 5 mV
VOUT2 Load Regulation VOUT1 = 5V, 10mA < IOUT2 = 300mA (Note 5) 2 10 mV
LDO Dropout Voltage IOUT2 = 10mA (Note 5)
IOUT2 = 100mA (Note 5)
IOUT2 = 300mA (Note 5)
0.25
0.34
0.43
V
V
V
VOUT2 Ripple (RMS) CBYP = 0.01µF, IOUT2 = 300mA, BW = 100Hz to 100kHz (Note 5) 20 µVRMS
range. The LTM8048MP is guaranteed to meet specifications over the
full –55°C to 125°C internal operating temperature range. Note that
the maximum internal temperature is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
resistance and other environmental factors.
Note 4: This is the BIAS pin voltage at which the internal circuitry is
powered through the BIAS pin and not the integrated regulator. See BIAS
Pin Considerations for details.
Note 5: VRUN = 0V (Flyback not running), but the VOUT2 post regulator is
powered by applying a voltage to VOUT1.
LTM8048
4
8048fg
For more information www.linear.com/LTM8048
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Efficiency vs Load BIAS Current vs VOUT1 Load
Efficiency vs Load Efficiency vs Load Efficiency vs Load
VOUT1 CURRENT (mA)
0
EFFICIENCY (%)
90
70
80
60
50 100 300
8048 G01
500
200 400
12VIN
24VIN
VOUT1 = 2.5V
BIAS = 5V
VOUT1 CURRENT (mA)
0
EFFICIENCY (%)
100
90
70
80
60 100 300
8048 G04
350
200 25015050
12VIN
24VIN
VOUT1 = 8V
BIAS = 5V
VOUT1 CURRENT (mA)
0
EFFICIENCY (%)
100
90
70
80
60 100
8048 G05
250
20015050
12VIN
24VIN
VOUT1 = 12V
BIAS = 5V
8.5
8.0
6.0
7.0
5.0
4.0
6.5
7.5
5.5
4.5
VOUT1 CURRENT (mA)
0
BIAS CURRENT (mA)
100 300
8048 G06
500
200 400
12VIN
24VIN
VOUT1 = 2.5V
BIAS = 5V
VOUT1 CURRENT (mA)
0
EFFICIENCY (%)
90
70
80
60
50 100 300
8048 G02
400
200
12VIN
24VIN
VOUT1 = 3.3V
BIAS = 5V
VOUT1 CURRENT (mA)
0
EFFICIENCY (%)
90
70
80
60
50 100 300
8048 G03
350200 25015050
12VIN
24VIN
VOUT1 = 5V
BIAS = 5V
BIAS Current vs VOUT1 Load BIAS Current vs VOUT1 Load BIAS Current vs VOUT1 Load
VOUT1 CURRENT (mA)
0
BIAS CURRENT (mA)
8.5
8.0
6.0
7.0
5.0
4.0
6.5
7.5
5.5
4.5
100 300
8048 G07
400
200
12VIN
24VIN
VOUT1 = 3.3V
BIAS = 5V
VOUT1 CURRENT (mA)
BIAS CURRENT (mA)
10
6
8
4
7
9
5
8048 G08
12VIN
24VIN
VOUT1 = 5V
BIAS = 5V
0 100 300
350
200 25015050
VOUT1 CURRENT (mA)
BIAS CURRENT (mA)
12
11
10
6
8
4
7
9
5
8048 G09
12VIN
24VIN
VOUT1 = 8V
BIAS = 5V
0 100 300 350200 25015050
Unless otherwise noted, operating conditions are
as in Table 1 (TA = 25°C).
LTM8048
5
8048fg
For more information www.linear.com/LTM8048
TYPICAL PERFORMANCE CHARACTERISTICS
BIAS Current vs VOUT1 Load Maximum Load vs VIN Maximum Load vs VIN
0 100
250
20015050
VOUT1 CURRENT (mA)
BIAS CURRENT (mA)
13
12
11
10
6
8
4
7
9
5
8048 G10
12VIN
24VIN
VOUT1 = 12V
BIAS = 5V
VIN (V)
MAXIMUM V
OUT1
LOAD (mA)
500
450
400
200
300
100
250
350
150
8048 G11
BIAS = VIN IF VIN ≤ 5V
BIAS = 5V IF VIN > 5V
0 10
30
20 25155
2.5VOUT1
3.3VOUT1
5VOUT1
VIN (V)
MAXIMUM V
OUT1
LOAD (mA)
350
200
300
0
100
250
150
50
8048 12
BIAS = VIN IF VIN ≤ 5V
BIAS = 5V IF VIN > 5V
0 10
25
20155
8VOUT1
12VOUT1
Unless otherwise noted, operating conditions are
as in Table 1 (TA = 25°C).
Minimum Load vs VIN Minimum Load vs VIN
Input Current vs VIN
VOUT1 Shorted
Input Current vs VIN
VOUT2 Shorted
VIN (V)
MINIMUM V
OUT1
LOAD (mA)
40
35
30
10
20
0
15
25
5
8048 G13
0 10
30
20 25155
2.5VOUT1
3.3VOUT1
5VOUT1
VIN (V)
INPUT CURRENT (mA)
225
200
175
75
125
50
100
150
8048 G16
0
40
20 3010
VIN (V)
MINIMUM V
OUT1
LOAD (mA)
15
12
9
3
0
6
8048 G14
0 10
30
20 25155
8VOUT1
12VOUT1
VIN (V)
INPUT CURRENT (mA)
80
70
60
20
40
10
30
50
8048 G15
0 12
32
20 28241684
VOUT2 Dropout Voltage vs Load
VOUT2 LOAD CURRENT (mA)
V
OUT2
DROPOUT VOLTAGE (mV)
0.7
0.6
0.5
0.4
0.3
0.2
0
0.1
8048 G17
0 100
300
200 25015050
–40°C
125°C
25°C
VOUT2 = 3.3V
VOUT2 Output Ripple and Noise
500µV/DIV
8048 G26
1µs/DIV
MEASURED PER AN70,
USING HP461A AMPLIFIER,
150MHz BW
VIN = 12V
VOUT1 = 5.7V
VOUT2 = 5V
LTM8048
6
8048fg
For more information www.linear.com/LTM8048
Junction Temperature Rise vs
Load Current
VOUT2 LOAD CURRENT (mA)
TEMPERATURE RISE (°C)
10
9
8
4
6
0
5
7
2
3
1
8048 G18
0 100
300
200 25015050
3.3VIN
5VIN
12VIN
24VIN
VOUT2 = 1.2V
TYPICAL PERFORMANCE CHARACTERISTICS
Junction Temperature Rise vs
Load Current
Junction Temperature Rise vs
Load Current
Junction Temperature Rise vs
Load Current
Junction Temperature Rise vs
Load Current
Junction Temperature Rise vs
Load Current
VOUT2 LOAD CURRENT (mA)
TEMPERATURE RISE (°C)
10
9
8
4
6
0
5
7
2
3
1
8048 G19
0 100
300
200 25015050
3.3VIN
5VIN
12VIN
24VIN
VOUT2 = 1.5V
VOUT2 LOAD CURRENT (mA)
TEMPERATURE RISE (°C)
12
10
8
4
6
0
2
8048 G22
0 100
300
200 25015050
3.3VIN
5VIN
12VIN
24VIN
VOUT2 = 3.3V
VOUT2 LOAD CURRENT (mA)
TEMPERATURE RISE (°C)
10
9
8
4
6
0
5
7
2
3
1
8048 G20
0 100
300
200 25015050
3.3VIN
5VIN
12VIN
24VIN
VOUT2 = 1.8V
VOUT2 LOAD CURRENT (mA)
TEMPERATURE RISE (°C)
14
12
10
8
4
6
0
2
8048 G23
0 100
300
200 25015050
3.3VIN
5VIN
12VIN
24VIN
VOUT2 = 5V
VOUT2 LOAD CURRENT (mA)
TEMPERATURE RISE (°C)
10
9
8
4
6
0
5
7
2
3
1
8048 G21
0 100
300
200 25015050
3.3VIN
5VIN
12VIN
24VIN
VOUT2 = 2.5V
Unless otherwise noted, operating conditions are
as in Table 1 (TA = 25°C).
Junction Temperature Rise vs
Load Current
Junction Temperature Rise vs
Load Current
VOUT2 LOAD CURRENT (mA)
TEMPERATURE RISE (°C)
16
14
12
10
8
4
6
0
2
8048 G24
0 100
300
200 25015050
3.3VIN
5VIN
12VIN
24VIN
VOUT2 = 8V
VOUT2 LOAD CURRENT (mA)
TEMPERATURE RISE (°C)
16
14
12
10
8
4
6
0
2
8048 G25
0 100
250
20015050
3.3VIN
5VIN
12VIN
24VIN
VOUT2 = 12V
LTM8048
7
8048fg
For more information www.linear.com/LTM8048
PIN FUNCTIONS
VOUT1 (Bank 1): VOUT1 and VOUT– comprise the isolated
output of the LTM8048 flyback stage. Apply an external
capacitor between VOUT1 and VOUT–. Do not allow VOUT–
to exceed VOUT1.
VOUT– (Bank 2): VOUT– is the return for both VOUT1 and
VOUT2. VOUT1 and VOUT– comprise the isolated output of
the LTM8048. In most applications, the bulk of the heat
flow out of the LTM8048 is through the GND and VOUT–
pads, so the printed circuit design has a large impact on
the thermal performance of the part. See the PCB Layout
and Thermal Considerations sections for more details.
Apply an external capacitor between VOUT1 and VOUT–.
VOUT2 (Bank 3): The output of the secondary side linear
post regulator. Apply the load and output capacitor between
VOUT2 and VOUT–. See the Applications Information section
for more information on output capacitance and reverse
output characteristics.
GND (Bank 4): This is the primary side local ground of the
LTM8048 primary. In most applications, the bulk of the heat
flow out of the LTM8048 is through the GND and VOUT–
pads, so the printed circuit design has a large impact on
the thermal performance of the part. See the PCB Layout
and Thermal Considerations sections for more details.
VIN (Bank 5): VIN supplies current to the LTM8048’s inter-
nal regulator and to the integrated power switch. These
pins must be locally bypassed with an external, low ESR
capacitor.
ADJ2 (pin A2): This is the input to the error amplifier of the
secondary side LDO post regulator. This pin is internally
clamped to ±7V. The ADJ2 pin voltage is 1.22V referenced
to VOUT– and the output voltage range is 1.22V to 12V. Ap-
ply a resistor from this pin to VOUT–, using the equation
RADJ2 = 608.78/(VOUT2 – 1.22)kΩ. If the post regulator
is not used, leave this pin floating.
BYP (Pin B2): The BYP pin is used to bypass the refer-
ence of the LDO to achieve low noise performance from
the linear post regulator. The BYP pin is clamped internally
to ±0.6V relative to VOUT–. A small capacitor from VOUT2
to this pin will bypass the reference to lower the output
voltage noise. A maximum value of 0.01µF can be used
for reducing output voltage noise to a typical 20µVRMS
over a 100Hz to 100kHz bandwidth. If not used, this pin
must be left unconnected.
RUN (Pin F3): A resistive divider connected to VIN and this
pin programs the minimum voltage at which the LTM8048
will operate. Below 1.24V, the LTM8048 does not deliver
power to the secondary. Above 1.24V, power will be de-
livered to the secondary and 10µA will be fed into the SS
pin. When RUN is less than 1.24V, the pin draws 2.5µA,
allowing for a programmable hysteresis. Do not allow a
negative voltage (relative to GND) on this pin.
ADJ1 (Pins G7): Apply a resistor from this pin to GND to
set the output voltage VOUT1 relative to VOUT–, using the
recommended value given in Table 1. If Table 1 does not
list the desired VOUT1 value, the equation
RADJ1 =28.4 VOUT1
–0.879
( )
kΩ
may be used to approximate the value. To the seasoned
designer, this exponential equation may seem unusual. The
equation is exponential due to non-linear current sources
that are used to temperature compensate the regulation.
BIAS (Pin H5): This pin supplies the power necessary to
operate the LTM8048. It must be locally bypassed with a
low ESR capacitor of at least 4.7μF. Do not allow this pin
voltage to rise above VIN.
SS (Pin H6): Place a soft-start capacitor here to limit inrush
current and the output voltage ramp rate. Do not allow a
negative voltage (relative to GND) on this pin.
LTM8048
9
8048fg
For more information www.linear.com/LTM8048
OPERATION
The LTM8048 is a stand-alone isolated flyback switching
DC/DC power supply that can deliver up to 440mA of
output current. This module provides a regulated output
voltage programmable via one external resistor from 2.5V
to 13V. It is also equipped with a high performance linear
post regulator. The input voltage range of the LTM8048 is
3.1V to 32V. Given that the LTM8048 is a flyback converter,
the output current depends upon the input and output
voltages, so make sure that the input voltage is high
enough to support the desired output voltage and load
current. The Typical Performance Characteristics section
gives several graphs of the maximum load versus VIN for
several output voltages.
A simplified block diagram is given. The LTM8048 contains
a current mode controller, power switching element, power
transformer, power Schottky diode, a modest amount of
input and output capacitance and a high performance
linear post regulator.
The LTM8048 has a galvanic primary to secondary isola-
tion rating of 725VDC. This is verified by applying 725VDC
between the primary to secondary for 1 second and then
applying –725VDC for 1 second. For details please refer
to the Isolation and Working Voltage section.
An internal regulator provides power to the control cir-
cuitry. The bias regulator normally draws power from the
VIN pin, but if the BIAS pin is connected to an external
voltage higher than 3.1V, bias power will be drawn from
the external source, improving efficiency. VBIAS must not
exceed VIN. The RUN pin is used to turn on or off the
LTM8048, disconnecting the output and reducing the input
current to 1μA or less.
The LTM8048 is a variable frequency device. For a fixed
input and output voltage, the frequency increases as the
load increases. For light loads, the current through the
internal transformer may be discontinuous.
The post regulator is a high performance 300mA low
dropout regulator with micropower quiescent current and
shutdown. The device is capable of supplying 300mA at
a dropout voltage of 300mV. Output voltage noise can be
lowered to 20µVRMS over a 100Hz to 100kHz bandwidth
with the addition of a 0.01μF reference bypass capacitor.
Additionally, this reference bypass capacitor will improve
transient response of the regulator, lowering the settling
time for transient load conditions. The linear regulator is
protected against both reverse input and reverse output
voltages.
LTM8048
10
8048fg
For more information www.linear.com/LTM8048
APPLICATIONS INFORMATION
For most applications, the design process is straight
forward, summarized as follows:
1. Look at Table 1a (or Table 1b, if the post linear regula-
tor is used) and find the row that has the desired input
range and output voltage.
2. Apply the recommended CIN, COUT1, COUT2, RADJ1,
RADJ2 and CBYP if required.
3. Connect BIAS as indicated, or tie to an external source
up to 15V or VIN, whichever is less.
While these component combinations have been tested for
proper operation, it is incumbent upon the user to verify
proper operation over the intended system’s line, load and
environmental conditions. Bear in mind that the maximum
output current may be limited by junction temperature,
the relationship between the input and output voltage
magnitude and polarity and other factors. Please refer
to the graphs in the Typical Performance Characteristics
section for guidance.
Capacitor Selection Considerations
The CIN, COUT1 and COUT2 capacitor values in Table 1 are
the minimum recommended values for the associated op-
erating conditions. Applying capacitor values below those
indicated in Table 1 is not recommended, and may result
in undesirable operation. Using larger values is generally
acceptable, and can yield improved dynamic response, if
it is necessary. Again, it is incumbent upon the user to
verify proper operation over the intended system’s line,
load and environmental conditions.
Ceramic capacitors are small, robust and have very low
ESR. However, not all ceramic capacitors are suitable.
X5R and X7R types are stable over temperature and ap-
plied voltage and give dependable service. Other types,
including Y5V and Z5U have very large temperature and
voltage coefficients of capacitance. In an application cir-
cuit they may have only a small fraction of their nominal
capacitance resulting in much higher output voltage ripple
than expected.
A final precaution regarding ceramic capacitors concerns
the maximum input voltage rating of the LTM8048. A
ceramic input capacitor combined with trace or cable
inductance forms a high-Q (underdamped) tank circuit. If
the LTM8048 circuit is plugged into a live supply, the input
voltage can ring to much higher than its nominal value,
possibly exceeding the device’s rating. This situation is
easily avoided; see the Hot-Plugging Safely section.
LTM8048 Table 1a. Recommended Component Values and Configuration for Specific VOUT1 Voltages (TA = 25°C)
VIN VOUT1 VBIAS CIN COUT1 RADJ1
3.1V to 32V 2.5V 3.1V to 15V or Open 2.2µF, 50V, 1206 100µF, 6.3V, 1210 12.4k
3.1V to 32V 3.3V 3.1V to 15V or Open 2.2µF, 50V, 1206 100µF, 6.3V, 1210 10k
3.1V to 29V 5V 3.1V to 15V or Open 2.2µF, 50V, 1206 22µF, 16V, 1210 6.98k
3.1V to 26V 8V 3.1V to 15V or Open 2.2µF, 50V, 1206 22µF, 10V, 1206 4.53k
3.1V to 24V 12V 3.1V to 15V or Open 2.2µF, 25V, 0805 10µF, 16V, 1210 3.16k/12pF*
9V to 15V 2.5V VIN 2.2µF, 50V, 1206 100µF, 6.3V, 1210 12.4k
9V to 15V 3.3V VIN 2.2µF, 50V, 1206 47µF, 6.3V, 1210 10k
9V to 15V 5V VIN 2.2µF, 50V, 1206 22µF, 16V, 1210 6.98k
9V to 15V 8V VIN 2.2µF, 50V, 1206 22µF, 10V, 1206 4.53k
9V to 15V 12V VIN 2.2µF, 25V, 0805 10µF, 16V, 1210 3.16k
18V to 32V 2.5V 3.1V to 15V or Open 2.2µF, 50V, 1206 100µF, 6.3V, 1210 12.4k
18V to 32V 3.3V 3.1V to 15V or Open 2.2µF, 50V, 1206 47µF, 6.3V, 1210 10k
18V to 29V 5V 3.1V to 15V or Open 2.2µF, 50V, 1206 22µF, 16V, 1210 6.98k
18V to 26V 8V 3.1V to 15V or Open 2.2µF, 50V, 1206 22µF, 10V, 1206 4.53k
18V to 24V 12V 3.1V to 15V or Open 2.2µF, 50V, 1206 10µF, 16V, 1210 3.16k/12pF*
Note: Do not allow BIAS to exceed VIN, a bulk input capacitor is required.
*Connect 3.16k in parallel with 12pF from ADJ to GND.
LTM8048
11
8048fg
For more information www.linear.com/LTM8048
LTM8048 Table 1b. Recommended Component Values and Configuration for Specific VOUT2 Voltages (TA = 25°C)
VIN VOUT1 VOUT2 VBIAS CIN COUT1 COUT2 RADJ1 RADJ2
3.1V to 32V 1.71V 1.2V 3.1V to 15V or Open 2.2µF, 50V, 1206 100µF, 6.3V, 1210 10µF, 6.3V, 1206 16.5k Open
3.1V to 32V 2.02V 1.5V 3.1V to 15V or Open 2.2µF, 50V, 1206 100µF, 6.3V, 1210 10µF, 6.3V, 1206 14.7k 2.32M
3.1V to 32V 2.34V 1.8V 3.1V to 15V or Open 2.2µF, 50V, 1206 100µF, 6.3V, 1210 10µF, 6.3V, 1206 13.3k 1.07M
3.1V to 32V 3.08V 2.5V 3.1V to 15V or Open 2.2µF, 50V, 1206 100µF, 6.3V, 1210 10µF, 6.3V, 1206 10.5k 487k
3.1V to 32V 3.92V 3.3V 3.1V to 15V or Open 2.2µF, 50V, 1206 47µF, 6.3V, 1210 10µF, 6.3V, 1206 8.66k 294k
3.1V to 29V 5.7V 5V 3.1V to 15V or Open 2.2µF, 50V, 1206 22µF, 16V, 1210 10µF, 6.3V, 1206 6.19k 162k
3.1V to 26V 8.85V 8V 3.1V to 15V or Open 2.2µF, 50V, 1206 22µF, 10V, 1206 10µF, 10V, 1206 4.12k 88.7k
3.1V to 21V 13V 12V 3.1V to 15V or Open 2.2µF, 25V, 0805 10µF, 16V, 1210 10µF, 16V, 1206 2.94k/12pF* 56.2k
9V to 15V 1.71V 1.2V VIN 2.2µF, 50V, 1206 100µF, 6.3V, 1210 10µF, 6.3V, 1206 16.5k Open
9V to 15V 2.02V 1.5V VIN 2.2µF, 50V, 1206 100µF, 6.3V, 1210 10µF, 6.3V, 1206 14.7k 2.32M
9V to 15V 2.34V 1.8V VIN 2.2µF, 50V, 1206 100µF, 6.3V, 1210 10µF, 6.3V, 1206 13.3k 1.07M
9V to 15V 3.08V 2.5V VIN 2.2µF, 50V, 1206 100µF, 6.3V, 1210 10µF, 6.3V, 1206 10.5k 487k
9V to 15V 3.92V 3.3V VIN 2.2µF, 50V, 1206 47µF, 6.3V, 1210 10µF, 6.3V, 1206 8.66k 294k
9V to 15V 5.7V 5V VIN 2.2µF, 50V, 1206 22µF, 16V, 1210 10µF, 6.3V, 1206 6.19k 162k
9V to 15V 8.85V 8V VIN 2.2µF, 50V, 1206 22µF, 10V, 1206 10µF, 10V, 1206 4.12k 88.7k
9V to 15V 13V 12V VIN 2.2µF, 25V, 0805 10µF, 16V, 1210 10µF, 16V, 1206 2.94k/12pF* 56.2k
18V to 32V 1.71V 1.2V 3.1V to 15V or Open 2.2µF, 50V, 1206 100µF, 6.3V, 1210 10µF, 6.3V, 1206 16.5k Open
18V to 32V 2.02V 1.5V 3.1V to 15V or Open 2.2µF, 50V, 1206 100µF, 6.3V, 1210 10µF, 6.3V, 1206 14.7k 2.32M
18V to 32V 2.34V 1.8V 3.1V to 15V or Open 2.2µF, 50V, 1206 100µF, 6.3V, 1210 10µF, 6.3V, 1206 13.3k 1.07M
18V to 32V 3.08V 2.5V 3.1V to 15V or Open 2.2µF, 50V, 1206 100µF, 6.3V, 1210 10µF, 6.3V, 1206 10.5k 487k
18V to 32V 3.92V 3.3V 3.1V to 15V or Open 2.2µF, 50V, 1206 47µF, 6.3V, 1210 10µF, 6.3V, 1206 8.66k 294k
18V to 29V 5.7V 5V 3.1V to 15V or Open 2.2µF, 50V, 1206 22µF, 16V, 1210 10µF, 6.3V, 1206 6.19k 162k
18V to 26V 8.85V 8V 3.1V to 15V or Open 2.2µF, 50V, 1206 22µF, 10V, 1206 10µF, 10V, 1206 4.12k 88.7k
Note: Do not allow BIAS to exceed VIN, a bulk input capacitor is required.
*Connect 2.94k in parallel with 12pF from ADJ to GND.
APPLICATIONS INFORMATION
BIAS Pin Considerations
The BIAS pin is the output of an internal linear regulator
that powers the LTM8048’s internal circuitry. It is set to
3V and must be decoupled with a low ESR capacitor of at
least 4.7μF. The LTM8048 will run properly without apply-
ing a voltage to this pin, but will operate more efficiently
and dissipate less power if a voltage greater than 3.1V is
applied. At low VIN, the LTM8048 will be able to deliver
more output current if BIAS is 3.1V or greater. Up to 32V
may be applied to this pin, but a high BIAS voltage will
cause excessive power dissipation in the internal circuitry.
For applications with an input voltage less than 15V, the
BIAS pin is typically connected directly to the VIN pin. For
input voltages greater than 15V, it is preferred to leave the
BIAS pin separate from the VIN pin, either powered from
a separate voltage source or left running from the internal
regulator. This has the added advantage of keeping the
physical size of the BIAS capacitor small. Do not allow
BIAS to rise above VIN.
Soft-Start
For many applications, it is necessary to minimize the
inrush current at start-up. The built-in soft-start circuit
significantly reduces the start-up current spike and output
voltage overshoot by applying a capacitor from SS to GND.
When the LTM8048 is enabled, whether from VIN reaching
a sufficiently high voltage or RUN being pulled high, the
LTM8048 will source approximately 10µA out of the SS
pin. As this current gradually charges the capacitor from
SS to GND, the LTM8048 will correspondingly increase
the power delivered to the output, allowing for a graceful
turn-on ramp.
LTM8048
12
8048fg
For more information www.linear.com/LTM8048
APPLICATIONS INFORMATION
Isolation and Working Voltage
The LTM8048 isolation is tested by tying all of the primary
pins together, all of the secondary pins together and
subjecting the two resultant circuits to a differential of
±725VDC for one second. This establishes the isolation
voltage rating, but it does not determine the working volt-
age rating, which is subject to the application board layout
and possibly other factors. The metal to metal separation
of the primary and secondary throughout the LTM8048
substrate is 0.44mm.
ADJ and Line Regulation
For VOUT greater than 8V, a capacitor connected from ADJ
to GND improves line regulation. Figure 1 shows the ef-
fect of three capacitance values applied to ADJ for a load
of 15mA. No capacitance has poor line regulation, while
12pF has improved line regulation. As the capacitance
increases, the line regulation begins to degrade again, but
in the opposite direction as having too little capacitance.
Furthermore, too much capacitance from ADJ to GND may
increase the minimum load required for proper regulation.
resistor from the RADJ2 pin to GND; the value of RADJ2
can be calculated by the equation:
RADJ2 =
608.78
VOUT2 – 1.22 kΩ
VOUT1 to VOUT– Reverse Voltage
The LTM8048 cannot tolerate a reverse voltage from VOUT1
to VOUT– during operation. If VOUT– raises above VOUT1
during operation, the LTM8048 may be damaged. To protect
against this condition, a low forward drop power Schottky
diode has been integrated into the LTM8048, anti-parallel
to VOUT1/VOUT–. This can protect the output against many
reverse voltage faults. Reverse voltage faults can be both
steady state and transient. An example of a steady state
voltage reversal is accidentally misconnecting a powered
LTM8048 to a negative voltage source. An example of
transient voltage reversals is a momentary connection to
a negative voltage. It is also possible to achieve a VOUT1
reversal if the load is short-circuited through a long cable.
The inductance of the long cable forms an LC tank circuit
with the VOUT1 capacitance, which drive VOUT1 negative.
Avoid these conditions.
VOUT2 Post Regulator Bypass Capacitance and Low
Noise Performance
The VOUT2 linear regulator may be used with the addition
of a 0.01μF bypass capacitor from VOUT to the BYP pin
to lower output voltage noise. A good quality low leakage
capacitor, such as a X5R or X75 ceramic, is recommended.
This capacitor will bypass the reference of the regulator,
lowering the output voltage noise to as low as 20µVRMS.
Using a bypass capacitor has the added benefit of improv-
ing transient response.
Safety Rated Capacitors
Some applications require safety rated capacitors, which
are high voltage capacitors that are specifically designed
and rated for AC operation and high voltage surges. These
capacitors are often certified to safety standards such as UL
60950, IEC 60950 and others. In the case of the L
TM8048,
Figure 1. For Higher Output Voltages, the LTM8048 Requires
Some Capacitance from ADJ to GND for Proper Line Regulation
VOUT2 Post Regulator
VOUT2 is produced by a high performance low dropout
300mA regulator. At full load, its dropout is less than
430mV over temperature. Its output is set by applying a
VIN (V)
V
OUT
(V)
12.50
11.75
12.25
10.75
11.25
12.00
11.50
11.00
8048 F01
0 10
25
20155
NO CAP
12pF
18pF
LTM8048
13
8048fg
For more information www.linear.com/LTM8048
APPLICATIONS INFORMATION
a common application of a safety rated capacitor would
be to connect it from GND to VOUT–. To provide maximum
flexibility, the LTM8048 does not include any components
between GND and VOUT–. Any safety capacitors must be
added externally.
The specific capacitor and circuit configuration for any
application depends upon the safety requirements of
the system into which the LTM8048 is being designed.
Table 2 provides a list of possible capacitors and their
manufacturers.
Table 2. Safety Rated Capacitors
MANUFACTURER PART NUMBER DESCRIPTION
Murata Electronics GA343DR7GD472KW01L 4700pF, 250VAC, X7R,
4.5mm × 3.2mm
Capacitor
Johanson Dielectrics 302R29W471KV3E-****-SC 470pF, 250VAC,
X7R, 4.5mm × 2mm
Capacitor
Syfer Technology 1808JA250102JCTSP 100pF, 250VAC, C0G,
1808 Capacitor
The application of a capacitor from GND to VOUT– may
also reduce the high frequency output noise on the output.
PCB Layout
Most of the headaches associated with PCB layout have
been alleviated or even eliminated by the high level of
integration of the LTM8048. The LTM8048 is neverthe-
less a switching power supply, and care must be taken to
minimize electrical noise to ensure proper operation. Even
with the high level of integration, you may fail to achieve
specified operation with a haphazard or poor layout. See
Figure 2 for a suggested layout. Ensure that the grounding
and heat sinking are acceptable.
A few rules to keep in mind are:
1. Place the RADJ1 and RADJ2 resistors as close as possible
to their respective pins.
2. Place the CIN capacitor as close as possible to the VIN
and GND connections of the LTM8048.
3. Place the COUT1 capacitor as close as possible to VOUT1
and VOUT–. Likewise, place the COUT2 capacitor as close
as possible to VOUT2 and VOUT–.
4. Place the CIN and COUT capacitors such that their
ground current flow directly adjacent or underneath
the LTM8048.
5. Connect all of the GND connections to as large a copper
pour or plane area as possible on the top layer. Avoid
breaking the ground connection between the external
components and the LTM8048.
6. Use vias to connect the GND copper area to the board’s
internal ground planes. Liberally distribute these GND
vias to provide both a good ground connection and
thermal path to the internal planes of the printed circuit
board. Pay attention to the location and density of the
thermal vias in Figure 2. The LTM8048 can benefit from
the heat sinking afforded by vias that connect to internal
GND planes at these locations, due to their proximity
to internal power handling components. The optimum
number of thermal vias depends upon the printed
circuit board design. For example, a board might use
very small via holes. It should employ more thermal
vias than a board that uses larger holes.
Hot-Plugging Safely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
Figure 2. Layout Showing Suggested External Components,
Planes and Thermal Vias
8048 F02
BIAS
RUN
GND
ADJ2 BYP
ADJ1
LTM8048
SS
COUT2
COUT1
VOUT–
VOUT2 VIN
VOUT1
CIN
THERMAL/INTERCONNECT VIAS
LTM8048
14
8048fg
For more information www.linear.com/LTM8048
APPLICATIONS INFORMATION
bypass capacitor of the LTM8048. However, these capaci-
tors can cause problems if the LTM8048 is plugged into a
live supply (see Linear Technology Application Note 88 for
a complete discussion). The low loss ceramic capacitor
combined with stray inductance in series with the power
source forms an underdamped tank circuit, and the volt-
age at the VIN pin of the LTM8048 can ring to more than
twice the nominal input voltage, possibly exceeding the
LTM8048’s rating and damaging the part. A similar phe-
nomenon can occur inside the LTM8048 module, at the
output of the integrated EMI filter, with the same potential
of damaging the part. If the input supply is poorly con-
trolled or the user will be plugging the LTM8048 into an
energized supply, the input network should be designed
to prevent this overshoot. This can be accomplished by
installing a small resistor in series to VIN, but the most
popular method of controlling input voltage overshoot is
adding an electrolytic bulk capacitor to the VIN or fIN net.
This capacitor’s relatively high equivalent series resistance
damps the circuit and eliminates the voltage overshoot.
The extra capacitor improves low frequency ripple filter-
ing and can slightly improve the efficiency of the circuit,
though it can be a large component in the circuit.
Thermal Considerations
The LTM8048 output current may need to be derated if it
is required to operate in a high ambient temperature. The
amount of current derating is dependent upon the input
voltage, output power and ambient temperature. The
temperature rise curves given in the Typical Performance
Characteristics section can be used as a guide. These curves
were generated by the LTM8048 mounted to a 58cm2
4-layer FR4 printed circuit board. Boards of other sizes
and layer count can exhibit different thermal behavior, so
it is incumbent upon the user to verify proper operation
over the intended system’s line, load and environmental
operating conditions.
For increased accuracy and fidelity to the actual application,
many designers use FEA to predict thermal performance.
To that end, the Pin Configuration section of the data sheet
typically gives four thermal coefficients:
θ
JA: Thermal resistance from junction to ambient
θ
JCbottom: Thermal resistance from junction to the bot-
tom of the product case
θ
JCtop: Thermal resistance from junction to top of the
product case
θ
JCboard: Thermal resistance from junction to the printed
circuit board.
While the meaning of each of these coefficients may seem
to be intuitive, JEDEC has defined each to avoid confu-
sion and inconsistency. These definitions are given in
JESD 51-12, and are quoted or paraphrased as follows:
θJA is the natural convection junction-to-ambient air
thermal resistance measured in a one cubic foot sealed
enclosure. This environment is sometimes referred to
as still air although natural convection causes the air to
move. This value is determined with the part mounted to a
JESD 51-9 defined test board, which does not reflect an
actual application or viable operating condition.
θJCbottom is the junction-to-board thermal resistance with
all of the component power dissipation flowing through the
bottom of the package. In the typical µModule converter,
the bulk of the heat flows out the bottom of the package,
but there is always heat flow out into the ambient envi-
ronment. As a result, this thermal resistance value may
be useful for comparing packages but the test conditions
don’t generally match the user’s application.
θJCtop is determined with nearly all of the component power
dissipation flowing through the top of the package. As the
electrical connections of the typical µModule converter are
LTM8048
15
8048fg
For more information www.linear.com/LTM8048
Figure 3.
8048 F03
µMODULE DEVICE
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
CASE (TOP)-TO-AMBIENT
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
JUNCTION
AMBIENT
CASE (BOTTOM)-TO-BOARD
RESISTANCE
APPLICATIONS INFORMATION
on the bottom of the package, it is rare for an application
to operate such that most of the heat flows from the junc-
tion to the top of the part. As in the case of θJCbottom, this
value may be useful for comparing packages but the test
conditions don’t generally match the user’s application.
θJCboard is the junction-to-board thermal resistance where
almost all of the heat flows through the bottom of the
µModule converter and into the board, and is really the
sum of the θJCbottom and the thermal resistance of the
bottom of the part through the solder joints and through a
portion of the board. The board temperature is measured
a specified distance from the package, using a two-sided,
two-layer board. This board is described in JESD 51-9.
Given these definitions, it should now be apparent that none
of these thermal coefficients reflects an actual physical
operating condition of a µModule converter. Thus, none
of them can be individually used to accurately predict the
thermal performance of the product. Likewise, it would
be inappropriate to attempt to use any one coefficient to
correlate to the junction temperature vs load graphs given
in the product’s data sheet. The only appropriate way to
use the coefficients is when running a detailed thermal
analysis, such as FEA, which considers all of the thermal
resistances simultaneously.
A graphical representation of these thermal resistances
is given in Figure 3.
The blue resistances are contained within the µModule
converter, and the green are outside.
The die temperature of the LTM8048 must be lower than
the maximum rating of 125°C, so care should be taken in
the layout of the circuit to ensure good heat sinking of the
LTM8048. The bulk of the heat flow out of the LTM8048
is through the bottom of the module and the BGA pads
into the printed circuit board. Consequently a poor printed
circuit board design can cause excessive heating, result-
ing in impaired performance or reliability. Please refer to
the PCB Layout section for printed circuit board design
suggestions.
LTM8048
16
8048fg
For more information www.linear.com/LTM8048
TYPICAL APPLICATIONS
12V Flyback Converter with Low Noise Bypass
3.3V and 2.5V Flyback Converter
LTM8048
8048 TA04
VIN
3.5VDC TO 32VDC
V
OUT2
2.5V
V
OUT1
3.3V
10k
487k
4.7µF
VOUT1
VOUT2
VIN
RUN
ADJ1
SS
BYPBIAS
GND
ADJ2
VOUT–
ISOLATION BARRIER
725VDC ISOLATION
10µF
100µF
2.2µF
725VDC ISOLATION
LTM8048
8048 TA03
VIN
5VDC TO 23VDC
V
OUT2
12V
2.94k
56.2k
4.7µF
VOUT1
VOUT2
VIN
RUN
ADJ1
SS
BYPBIAS
GND
ADJ2
VOUT–
0.01µF
ISOLATION BARRIER
13V
10µF
10µF
5V
3.3V Flyback Converter
VOUT2 Output Current vs VIN
VOUT2 Output Current vs VIN
Total Output Current vs VIN
725VDC ISOLATION
LTM8048
8048 TA02
VIN
9V TO 15V
V
OUT2
3.3V
8.66k
294k
4.7µF
VOUT1
VOUT2
VIN
RUN
ADJ1
SS
BYPBIAS
GND
ADJ2
VOUT–
ISOLATION BARRIER
3.9V
10µF
47µF
2.2µF
VIN (V)
9
OUTPUT CURRENT (mA)
340
320
300
260
220
280
240
200 11 13
8048 TA02b
15
10 12 14
VIN (V)
5
OUTPUT CURRENT (mA)
250
230
210
190
170
150
110
70
130
90
50 15
8048 TA03b
25
10 20
VIN (V)
0
OUTPUT CURRENT (mA)
500
450
400
350
250
150
300
200
100 16
8048 TA04b
32
8 24
LTM8048
17
8048fg
For more information www.linear.com/LTM8048
PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION
A1 VOUT2 B1 VOUT2 C1 VOUT2 D1 - E1 GND F1 - G1 VIN H1 VIN
A2 ADJ2 B2 BYP C2 VOUT2 D2 - E2 GND F2 - G2 VIN H2 VIN
A3 VOUT–B3 VOUT–C3 VOUT–D3 - E3 GND F3 RUN G3 - H3 -
A4 VOUT–B4 VOUT–C4 VOUT–D4 - E4 GND F4 GND G4 GND H4 GND
A5 VOUT–B5 VOUT–C5 VOUT–D5 - E5 GND F5 GND G5 GND H5 BIAS
A6 VOUT1 B6 VOUT1 C6 VOUT1 D6 - E6 GND F6 GND G6 GND H6 SS
A7 VOUT1 B7 VOUT1 C7 VOUT1 D7 - E7 GND F7 GND G7 ADJ1 H7 GND
Pin Assignment Table
(Arranged by Pin Number)
PACKAGE DESCRIPTION
PACKAGE PHOTO
LTM8048
18
8048fg
For more information www.linear.com/LTM8048
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
5. PRIMARY DATUM -Z- IS SEATING PLANE
6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu
7 PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
!
PACKAGE TOP VIEW
4
PIN “A1”
CORNER
YX
aaa Z
aaa Z
DETAIL A
PACKAGE BOTTOM VIEW
3
SEE NOTES
H
G
F
E
D
C
B
A
1234567
PIN 1
BGA 45 1212 REV A
TRAY PIN 1
BEVEL PACKAGE IN TRAY LOADING ORIENTATION
COMPONENT
PIN “A1”
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS
BALL DESIGNATION PER JESD MS-028 AND JEP95
4
3
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
DETAIL A
Øb (45 PLACES)
DETAIL B
SUBSTRATE
0.27 – 0.37
3.95 – 4.05
// bbb Z
A
A1
b1
ccc Z
DETAIL B
PACKAGE SIDE VIEW
MOLD
CAP
Z
MX YZddd
MZeee
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
aaa
bbb
ccc
ddd
eee
MIN
4.72
0.50
4.22
0.71
0.60
NOM
4.92
0.60
4.32
0.78
0.63
11.25
9.0
1.27
8.89
7.62
MAX
5.12
0.70
4.42
0.85
0.66
0.15
0.10
0.20
0.30
0.15
NOTES
DIMENSIONS
TOTAL NUMBER OF BALLS: 45
A2
D
E
e
b
F
G
SUGGESTED PCB LAYOUT
TOP VIEW
0.000
0.635
1.905
0.635
3.175
1.905
4.445
3.175
4.445
3.810
2.540
1.270
3.810
2.540
1.270
0.3175
0.3175
0.000
4.1275
4.7625
LTMXXXXXX
µModule
BGA Package
45-Lead (11.25mm × 9.00mm × 4.92mm)
(Reference LTC DWG # 05-08-1869 Rev A)
7
SEE NOTES
LTM8048
19
8048fg
For more information www.linear.com/LTM8048
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 6/12 Added storage temperature range.
Clarify VOUT2 and ADJ1 pin function description.
Clarify RADJ2 equation.
Updated Related Parts table.
2
8
13
20
B 8/12 Add Safety Rated Capacitors section. 12
C 9/12 Correct Pin Assignment Table. 17
D 3/13 Updated Typical Application schematic.
Added Operating Conditions to Output Ripple graph.
Updated Related Parts table.
1
5
20
E 1/14 Revised RADJ1 value for 5VOUT and added minimum and maximum limits.
Revised RADJ1 value for 5VOUT in Table 1a.
3
10
F 1/14 Added SnPb Terminal Finish Option. 1, 2
G 7/15 Added ADJ and Line Regulation discussion. 12
LTM8048
20
8048fg
For more information www.linear.com/LTM8048
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
LINEAR TECHNOLOGY CORPORATION 2011
LT 0715 REV G • PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATION
5V Flyback Converter with Low Noise Bypass
725VDC ISOLATION
LTM8048
8048 TA05
VIN
15VDC TO 30VDC
V
OUT2
5V
6.19k
162k
4.7µF
VOUT1
VOUT2
VIN
RUN
ADJ1
SS
BYPBIAS
GND
ADJ2
VOUT–
0.01µF
ISOLATION BARRIER
5.7V
10µF
22µF
2.2µF
Total Output Current vs VIN
VIN (V)
15
OUTPUT CURRENT (mA)
400
380
360
340
320
300
260
220
280
240
200
8048 TA05b
30
2520
PART NUMBER DESCRIPTION COMMENTS
LTM8031 Ultralow EMI 1A µModule Regulator EN55022 Class B Compliant, 3.6V ≤ VIN ≤ 36V; 0.8V ≤ VOUT ≤ 10V
LTM8032 Ultralow EMI 2A µModule Regulator EN55022 Class B Compliant, 3.6V ≤ VIN ≤ 36V; 0.8V ≤ VOUT ≤ 10V
LTM8033 Ultralow EMI 3A µModule Regulator EN55022 Class B Compliant, 3.6V ≤ VIN ≤ 36V; 0.8V ≤ VOUT ≤ 24V
LTM4612 Ultralow EMI 5A µModule Regulator EN55022 Class B Compliant, 5V ≤ VIN ≤ 36V; 3.3V ≤ VOUT ≤ 15V
LTM8061 Li-Ion/Polymer µModule Battery Charger 4.95V ≤ VIN ≤ 32V, 2A Charge Current, 1-Cell and 2-Cell, 4.1V or 4.2V per Cell
LTM4613 Ultralow EMI 8A µModule Regulator EN55022 Class B Compliant, 5V ≤ VIN ≤ 36V; 3.3V ≤ VOUT ≤ 15V
LTM8047 725VDC Isolated µModule Converter 3.1V ≤ VIN ≤ 32V; 2.5V ≤ VOUT ≤ 12V
LTC2978 Octal Digital Power Supply Manager with EEPROM I2C/PMBus Interface, Configuration EEPROM, Fault Logging, 16-Bit ADC with
±0.25% TUE, 3.3V to 15V Operation
LTC2974 Quad Digital Power Supply Manager with EEPROM I2C/PMBus Interface, Configuration EEPROM, Fault Logging, Per Channel Voltage,
Current and Temperature Measurements
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTM8048
