HCPL-0720, HCPL-7720, HCPL-0721 and HCPL-7721 40 ns Propagation Delay, CMOS Optocoupler Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features Available in either an 8-pin DIP or SO-8 package style respectively, the HCPL-772X or HCPL-072X optocouplers utilize the latest CMOS IC technology to achieve outstanding performance with very low power consumption. The HCPL-772X/072X require only two bypass capacitors for complete CMOS compatability. * * * * * * * Basic building blocks of the HCPL-772X/072X are a CMOS LED driver IC, a high speed LED and a CMOS detector IC. A CMOS logic input signal controls the LED driver IC which supplies current to the LED. The detector IC incorporates an integrated photodiode, a high-speed transimpedance amplifier, and a voltage comparator with an output driver. Functional Diagram **VDD1 1 VI 2 * 3 GND1 4 8 IO VDD2** 7 NC* 6 VO 5 GND2 TRUTH TABLE (POSITIVE LOGIC) VI, INPUT H L LED1 SHIELD +5 V CMOS compatibility 20 ns maximum prop. delay skew High speed: 25 MBd 40 ns max. prop. delay 10 kV/s minimum common mode rejection -40 to 85C temperature range Safety and regulatory approvals UL recognized - 3750 Vrms for 1 min. per UL 1577 - 5000 Vrms for 1 min. per UL 1577 (for HCPL-772X option 020) CSA component acceptance notice #5 IEC/EN/DIN EN 60747-5-5 - VIORM = 630 Vpeak for HCPL-772X option 060 - VIORM = 567 Vpeak for HCPL-072X option 060 Applications V , OUTPUT LED1 O * Digital Hfieldbus OFF ON bus, SDS L * * * * isolation: CC-Link, DeviceNet, Profi- AC plasma display panel level shifting Multiplexed data transmission Computer peripheral interface Microprocessor system interface * Pin 3 is the anode of the internal LED and must be left unconnected for guaranteed data sheet performance. Pin 7 is not connected internally. ** A 0.1 F bypass capacitor must be connected between pins 1 and 4, and 5 and 8. TRUTH TABLE POSITIVE LOGIC VI LED1 Vo OUTPUT H OFF H L ON L CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Selection Guide 8-Pin DIP (300 Mil) Small Outline SO-8 Data Rate PWD HCPL-7721 HCPL-0721 25 MB 6 ns HCPL-7720 HCPL-0720 25 MB 8 ns Ordering Information HCPL-0720, HCPL-0721, HCPL-7720 and HCPL-7721 are UL Recognized with 3750 Vrms for 1 minute per UL1577. Option Part RoHS non RoHS Number Compliant Compliant Package Surface Mount Gull Wing Tape & Reel UL 5000 Vrms/ 1 Minute rating IEC/EN/DIN EN 60747-5-5 Quantity -000E no option -300E #300 X X 50 per tube -500E #500 X X 1000 per reel X 50 per tube HCPL-7720 -020E -020 300 mil X 50 per tube HCPL-7721 -320E -320 DIP-8 X X X 50 per tube X X X 1000 per reel -520E -520 -060E #060 X 50 per tube -360E #360 X X X 50 per tube -560E #560 X X X 1000 per reel -000E X X no option X X 100 per tube HCPL-0720 -500E #500 X X 1500 per reel HCPL-0721 -060E #060 X X X 100 per tube -560E #560 X X X 1500 per reel SO-8 X X To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: HCPL-7720-560E to order product of Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval and RoHS compliant. Example 2: HCPL-0721 to order product of Small Outline SO-8 package in Tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation `#XXX' is used for existing products, while (new) products launched since July 15, 2001 and RoHS compliant will use `-XXXE.' 2 Package Outline Drawing HCPL-772X 8-Pin DIP Package 9.65 0.25 (0.380 0.010) TYPE NUMBER 8 7 6 7.62 0.25 (0.300 0.010) 5 OPTION 060 CODE* 6.35 0.25 (0.250 0.010) DATE CODE A XXXXV YYWW 1 1.19 (0.047) MAX. 2 3 4 1.78 (0.070) MAX. 5 TYP. 3.56 0.13 (0.140 0.005) 4.70 (0.185) MAX. + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) 0.51 (0.020) MIN. 2.92 (0.115) MIN. 1.080 0.320 (0.043 0.013) 3 0.65 (0.025) MAX. 2.54 0.25 (0.100 0.010) DIMENSIONS IN MILLIMETERS AND (INCHES). *OPTION 300 AND 500 NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. Package Outline Drawing HCPL-772X Package with Gull Wing Surface Mount Option 300 LAND PATTERN RECOMMENDATION 9.65 0.25 (0.380 0.010) 6 7 8 1.016 (0.040) 5 6.350 0.25 (0.250 0.010) 1 3 2 10.9 (0.430) 4 2.0 (0.080) 1.27 (0.050) 9.65 0.25 (0.380 0.010) 1.780 (0.070) MAX. 1.19 (0.047) MAX. 7.62 0.25 (0.300 0.010) + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) 3.56 0.13 (0.140 0.005) 1.080 0.320 (0.043 0.013) 0.635 0.25 (0.025 0.010) 0.635 0.130 (0.025 0.005) 2.54 (0.100) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES). 12 NOM. NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. Package Outline Drawing HCPL-072X Outline Drawing (Small Outline SO-8 Package) LAND PATTERN RECOMMENDATION 8 7 5 5.994 0.203 (0.236 0.008) XXXV YWW 3.937 0.127 (0.155 0.005) PIN ONE 6 1 2 3 TYPE NUMBER (LAST 3 DIGITS) DATE CODE 7.49 (0.295) 4 0.406 0.076 (0.016 0.003) 1.9 (0.075) 1.270 BSC (0.050) 0.64 (0.025) * 5.080 0.127 (0.200 0.005) 3.175 0.127 (0.125 0.005) 7 1.524 (0.060) 0.432 45 X (0.017) 0 ~ 7 0.228 0.025 (0.009 0.001) 0.203 0.102 (0.008 0.004) * TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH) 5.207 0.254 (0.205 0.010) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX. OPTION NUMBER 500 NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX. 4 0.305 MIN. (0.012) Solder Reflow Thermal Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). NonHalide Flux should be used. Regulatory Information The HCPL-772X/072X have been approved by the following organizations: UL Recognized under UL 1577, component recognition program, File E55361. CSA Approved under CSA Component Acceptance Notice #5, File CA88324. IEC/EN/DIN EN 60747-5-5 Insulation and Safety Related Specifications Value Parameter Symbol 772X 072X Units Conditions Minimum External Air L(I01) 7.1 4.9 mm Gap (Clearance) Measured from input terminals to output terminals, shortest distance through air. Minimum External L(I02) 7.4 4.8 mm Tracking (Creepage) Measured from input terminals to output terminals, shortest distance path along body. Minimum Internal Plastic 0.08 0.08 mm Insulation thickness between emitter and Gap (Internal Clearance) detector; also known as distance through insulation. Tracking Resistance (Comparative Tracking Index) CTI 175 175 Volts Isolation Group IIIa IIIa All Avago data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum creepage and clearance require ments must be met as specified for individual equipment standards. For creepage, the shortest distance path along 5 DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. There are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* (Option 060) Description Symbol Characteristic HCPL-7720 HCPL-0720 HCPL-7721 HCPL-0721 Installation classification per DIN VDE 0110, Table 1 for rated mains voltage 150 Vrms for rated mains voltage 300 Vrms for rated mains voltage 600 Vrms I-IV I-IV I-IV I-IV I-III I-III Climatic Classification 55/85/21 55/85/21 Unit Pollution Degree (DIN VDE 0110/39) 2 2 Maximum Working Insulation Voltage VIORM 630 567 Vpeak Input-to-Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC VPR 1181 1063 Vpeak Input-to-Output Test Voltage, Method a* VIORM x 1.6 = VPR, Type and Sample Test, tm = 10 sec, Partial Discharge < 5 pC VPR 1008 907 Vpeak Highest Allowable Overvoltage (Transient Overvoltage, tini = 60 sec) VIOTM 8000 6000 Vpeak Safety Limiting Values - maximum values allowed in the event of a failure Case Temperature Input Current Output Power TS IS,INPUT PS,OUTPUT 175 230 600 150 150 600 C mA mW Insulation Resistance at TS, V10 = 500 V RIO 109 109 * Refer to the optocoupler section of the Isolation and Control Components Designer's Catalog, under Product Safety Regulations section, (IEC/ EN/DIN EN 60747-5-5) for a detailed description of Method a and Method b partial discharge test profiles. Note: These optocouplers are suitable for "safe electrical isolation" only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits. The surface mount classification is Class A in accordance with CECC 00802. Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature TS -55 125 C Ambient Operating Temperature[1] TA -40 +85 C Supply Voltages VDD1, VDD2 0 6.0 Volts Input Voltage VI -0.5 VDD1 +0.5 Volts Output Voltage VO -0.5 Average Output Current IO VDD2 +0.5 Volts 10 mA Lead Solder Temperature 260C for 10 sec., 1.6 mm below seating plane Solder Reflow Temperature Profile See Solder Reflow Temperature Profile Section Recommended Operating Conditions Parameter Symbol Min. Max. Units Ambient Operating Temperature TA -40 +85 C Supply Voltages VDD1, VDD2 4.5 5.5 V Logic High Input Voltage VIH 2.0 VDD1 V Logic Low Input Voltage VIL 0.0 0.8 V Input Signal Rise and Fall Times tr, tf 1.0 ms 6 Figure Figure 1, 2 Electrical Specifications Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications are at TA = +25 C, VDD1 = VDD2 = +5 V. Parameter Symbol Min. Typ. Max. Units Test Conditions DC Specifications Logic Low Input IDD1L 6.0 10.0 mA Supply Current Logic High Input IDD1H 1.5 3.0 mA Supply Current Output Supply Current IDD2L 5.5 9.0 mA IDD2H 7.0 9.0 Input Current II -10 10 A Logic High Output VOH 4.4 5.0 V Voltage 4.0 4.8 Logic Low Output VOL 0 0.1 V Voltage0.1 V 0.5 1.0 Switching Specifications Fig. VI = 0 V Note 2 VI = VDD1 IO = -20 A, VI = VIH IO = -4 mA, VI = VIH IO = 20 A, VI = VIL IO = 400 A, VI = VIL IO = 4 mA, VI = VIL 1, 2 Propagation Delay Time tPHL 20 40 ns CL = 15 pF 3, 6 3 to Logic Low Output CMOS Signal Levels Propagation Delay Time tPLH 23 40 ns to Logic High Output Pulse Width PW 40ns Data Rate25 MBd Pulse Width Distortion PWD 7721/0721 3 6 ns 7 4 |tPHL - tPLH| 7720/0720 3 8 ns Propagation Delay Skew tPSK20 5 Output Rise Time tR9ns (10 - 90%) Output Fall Time tF8ns (90 - 10%) Common Mode |CMH| 10 20 kV/s VI = VDD1, VO > 6 Transient Immunity at0.8 VDD1, Logic High OutputVCM = 1000 V Common Mode |CML| 10 20 VI = 0 V, VO > 0.8 V, Transient Immunity atVCM = 1000 V Logic Low Output Input Dynamic Power CPD160pF 7 Dissipation Capacitance Output Dynamic Power CPD2 10 Dissipation Capacitance 7 Package Characteristics Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Input-Output Momentary 072X VISO 3750 Vrms RH 50%, 8, 9, Withstand Voltage 772X 3750 t = 1 min., 10 Option 020 5000 TA = 25C Resistance RI-O 1012 VI-O = 500 Vdc 8 (Input-Output) Capacitance CI-O 0.6 pF f = 1 MHz (Input-Output) Input Capacitance CI3.011 Input IC Junction-to-Case -772X jci 145 C/W Thermocouple Thermal Resistance -072X 160 located at center Output IC Junction-to-Case -772X jco 140 underside of package Thermal Resistance -072X 135 Package Power Dissipation PPD 150 mW Notes: 1. Absolute Maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not guarantee functionality. 2. The LED is ON when VI is low and OFF when VI is high. 3. tPHL propagation delay is measured from the 50% level on the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. tPLH propagation delay is measured from the 50% level on the rising edge of the VI signal to the 50% level of the rising edge of the VO signal. 4. PWD is defined as |tPHL - tPLH|. %PWD (percent pulse width distortion) is equal to the PWD divided by pulse width. 5. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the recommended operating conditions. 6. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges. 7. Unloaded dynamic power dissipation is calculated as follows: CPD * VDD2 * f + IDD * VDD, where f is switching frequency in MHz. 8. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together. 9. In accordance with UL1577, each HCPL-072X is proof tested by applying an insulation test voltage 4500 VRMS for 1 second (leakage detection current limit, II-O 5 A). Each HCPL-772X is proof tested by applying an insulation test voltage 4500 Vrms for 1 second (leakage detection current limit. II-O 5 A.) 10. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Avago Application Note 1074 "Optocoupler Input-Output Endurance Voltage." 11. CI is the capacitance measured at pin 2 (VI). 2.2 5 0 C 25 C 85 C 2 1.9 1.8 1 1.7 0 1 2 3 4 5 VI (V) Figure 1. Typical output voltage vs. input voltage 8 27 TPLH, TPHL (ns) 3 0 29 0 C 25 C 85 C 2.0 VITH (V) 4 VO (V) 2.1 1.6 4.5 25 TPLH 23 TPHL 21 19 17 4.75 5 5.25 5.5 VDD1 (V) Figure 2. Typical input voltage switching threshold vs. input supply voltage 15 0 10 20 30 40 50 60 70 80 TA (C) Figure 3. Typical propagation delays vs. temperature 4 11 7 6 3 2 TF (ns) TR (ns) PWD (ns) 10 9 1 0 20 0 40 60 8 80 20 0 29 6 27 5 25 80 21 TPLH 19 20 25 30 35 40 45 3 2 0 15 50 20 25 CI (pF) STANDARD 8 PIN DIP PRODUCT 800 PS (mW) IS (mA) 700 600 500 400 300 (230) 200 100 0 25 50 75 100 125 150 175 200 TA - CASE TEMPERATURE - C 35 40 45 50 CI (pF) Figure 8. Typical pulse width distortion vs. output load capacitance OUTPUT POWER - PS, INPUT CURRENT - IS Figure 7. Typical propagation delays vs. output load capacitance 30 SURFACE MOUNT SO8 PRODUCT 800 PS (mW) IS (mA) 700 600 500 400 300 200 (150) 100 0 0 25 50 0 20 40 60 Figure 6. Typical fall time vs. temperature 1 15 15 2 TA (C) 4 TPHL 23 PWD (ns) TPLH, TPHL (ns) 60 Figure 5. Typical rise time vs. temperature 17 OUTPUT POWER - PS, INPUT CURRENT - IS 40 TA (C) Figure 4. Typical pulse width distortion vs. temperature 75 100 125 150 175 200 TA - CASE TEMPERATURE - C Figure 9. Thermal derating curve, dependence of safety limiting value with case temperature per IEC/EN/DIN EN 60747-5-5. 9 4 3 TA (C) 0 5 80 Application Information Bypassing and PC Board Layout The HCPL-772X/072X optocouplers are extremely easy to use. No external interface circuitry is required because the HCPL-772X/072X use high-speed CMOS IC technology allowing CMOS logic to be connected directly to the inputs and outputs. As shown in Figure 10, the only external components required for proper operation are two bypass capacitors. Capacitor values should be between 0.01 F and 0.1 F. For each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm. Figure 11 illustrates the recommended printed circuit board layout for the HPCL-772X/072X. VDD1 VDD2 8 1 C1 C2 VI 72X YWW 2 NC 3 GND1 7 NC 6 VO 5 4 GND2 C1, C2 = 0.01 F TO 0.1 F Figure 10. Recommended printed circuit board layout. VDD1 VDD2 72X YWW VI C1 C2 VO GND1 GND2 C1, C2 = 0.01 F TO 0.1 F Figure 11. Recommended printed circuit board layout Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew Propagation Delay is a figure of merit that describes how quickly a logic signal propagates through a system. The propagation delay from low to high (tPLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (tPHL) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low. See Figure 12. INPUT VI 5 V CMOS 50% tPLH OUTPUT VO 10% 0V tPHL 90% 90% Figure 12. 10 HCPL-0710 fig 13 10% VOH 2.5 V CMOS VOL Pulse-width distortion (PWD) is the difference between tPHL and tPLH and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20 - 30% of the minimum pulse width is tolerable. Propagation delay skew, tPSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delay is large enough it will determine the maximum rate at which parallel data can be sent through the optocouplers. VI Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either tPLH or tPHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). As illustrated in Figure 13,if the inputs of a group of optocouplers are switched either ON or OFF at the same time, tPSK is the difference between the shortest propagation delay, either tPLH or tPHL, and the longest propagation delay, either tPLH or tPHL. As mentioned earlier, tPSK can determine the maximum parallel data transmission rate. Figure 14 is the timing diagram of a typical parallel data application with both the clock and data lines being sent through the optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. In this case the data is assumed to be clocked off of the rising edge of the clock. 50% DATA INPUTS VO 2.5 V, CMOS CLOCK tPSK VI 50% DATA OUTPUTS VO 2.5 V, CMOS tPSK CLOCK tPSK Figure 13. Propagation delay skew waveform. Figure 14. Parallel data transmission example. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 14 shows that there will be uncertainty in both the data and clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tPSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. 11 The HCPL-772X/072X optocouplers offer the advantage of guaranteed specifications for propagation delays, pulse-width distortion, and propagation delay skew over the recommended temperature and power supply ranges. Digital Field Bus Communication Networks To date, despite its many drawbacks, the 4 - 20 mA analog current loop has been the most widely accepted standard for implementing process control systems. In today's manufacturing environment, however, automated systems are expected to help manage the process, not merely monitor it. With the advent of digital field bus communication networks such as CC-Link, DeviceNet, PROFIBUS, and Smart Distributed Systems (SDS), gone are the days of constrained information. Controllers can now receive multiple readings from field devices (sensors, actuators, etc.) in addition to diagnostic information. The physical model for each of these digital field bus communication networks is very similar as shown in Figure 15. Each includes one or more buses, an interface unit, optical isolation, transceiver, and sensing and/or actuating devices. CONTROLLER BUS INTERFACE OPTICAL ISOLATION TRANSCEIVER FIELD BUS TRANSCEIVER TRANSCEIVER TRANSCEIVER TRANSCEIVER OPTICAL ISOLATION OPTICAL ISOLATION OPTICAL ISOLATION OPTICAL ISOLATION BUS INTERFACE BUS INTERFACE BUS INTERFACE BUS INTERFACE XXXXXX YYY DEVICE CONFIGURATION MOTOR STARTER Figure 15. Typical field bus communication physical model 12 MOTOR CONTROLLER SENSOR Optical Isolation for Field Bus Networks To recognize the full benefits of these networks, Avago optocouplers are recommended to provide galvanic isolation. As network communication is bi-directional (involving receiving data from and transmitting data onto the network), two Avago optocouplers are needed. By providing galvanic isolation, data integrity is retained via noise reduction and the elimination of false signals. In addition, the network receives maximum protection from power system faults and ground loops. Within an isolated node, such as the DeviceNet Node shown in Figure 16, some of the node's components are referenced to a ground other than V- of the network. These components could include such things as devices with serial ports, parallel ports, RS-232 and RS-485 type ports. As shown in Figure 16, power from the network is used only for the transceiver and input (network) side of the optocouplers. Isolation of nodes connected to any of the three types of digital field bus networks is best achieved by using the HCPL-772X/072X optocouplers. For each network, the HCPL-772X/072X satisify the critical propagation delay and pulse width distortion requirements over the temperature range of 0 C to +85 C, and power supply voltage range of 4.5 V to 5.5 V. AC LINE NODE/APP SPECIFIC P/CAN HCPL 772x/072x 5 V REG. V+ (SIGNAL) V- (SIGNAL) V+ (POWER) V- (POWER) SIGNAL POWER NETWORK POWER SUPPLY Figure 16. Typical DeviceNet Node 13 GALVANIC ISOLATION BOUNDARY HCPL 772x/072x TRANSCEIVER DRAIN/SHIELD LOCAL NODE SUPPLY Implementing CC-Link with the HCPL772X/072X Power Supplies and Bypassing CC-Link (Control and Communication Link) is developed to merge control and information in the low-level network (field network) by PCs, thereby making the multivendor environment a reality. It has data control and message-exchange function, as well as bit control function, and operates at the speed up to 10 Mbps. The recommended CC-Link circuit is shown in Figure 17. Since the HCPL-772X/072X are fully compatible with CMOS logic level signals, the optocoupler is connected directly to the transceiver. Two bypass capacitors (with values between 0.01 F and 0.1 F) are required and should be located as close as possible to the input and output power supply pins of the HCPL-772X/072X. For each capacitor, the total lead length between both ends of capacitor and the power supply pins should not exceed 20 mm. The bypass capacitors are required because of the high speed digital nature of the signals inside the optocoupler. FIL DA DB DG Y Z SLD VDD2 (5 V) SN75ALS181NS VCC VCC A R B RE VDD1 VI 0.1 DE D VDD1 (5 V) HCPL-7720#500 GND1 VDD2 10 K VO 0.1 GND GND2 GND GND RD1 GND1 HCPL-7720#500 VDD2 0.1 VO GND VDD1 VI 0.1 GND SD FG HCPL-2611#560 VOE VDD 1K HC14 0.1 VO GND 10 K NC + - NC 390 HC14 MPU BOARD OUTPUT HCPL-2611#560 VOE VDD 1K 10 K Figure 17. Recommended CC-Link application circuit 14 HC14 0.1 VO GND NC + - NC 390 SDGATEON HC14 Implementing DeviceNet and SDS with the HCPL772X/072X Isolated Node Powered by the Network With transmission rates up to 1 Mbit/s, both DeviceNet and SDS are based upon the same broadcast-oriented, communications protocol -- the Controller Area Network (CAN). Three types of isolated nodes are recommended for use on these networks: Isolated Node Powered by the Network (Figure 18), Isolated Node with Transceiver Powered by the Network (Figure 19), and Isolated Node Providing Power to the Network (Figure 20). This type of node is very flexible and as can be seen in Figure 18, is regarded as "isolated" because not all of its components have the same ground reference. Yet, all components are still powered by the network. This node contains two regulators: one is isolated and powers the CAN controller, node-specific application and isolated (node) side of the two optocouplers while the other is non-isolated. The non-isolated regulator supplies the transceiver and the non-isolated (network) half of the two optocouplers. NODE/APP SPECIFIC P/CAN HCPL 772x/072x ISOLATED SWITCHING POWER SUPPLY HCPL 772x/072x GALVANIC ISOLATION BOUNDARY REG. TRANSCEIVER DRAIN/SHIELD V+ (SIGNAL) V- (SIGNAL) V+ (POWER) V- (POWER) SIGNAL POWER NETWORK POWER SUPPLY Figure 18. Isolated node powered by the network. Isolated Node with Transceiver Powered by the Network *Bus V+ Sensing Figure 19 shows a node powered by both the network and another source. In this case, the transceiver and isolated (network) side of the two optocouplers are powered by the network. The rest of the node is powered by the AC line which is very beneficial when an application requires a significant amount of power. This method is also desirable as it does not heavily load the network. It is suggested that the Bus V+ sense block shown in Figure 19 be implemented. A locally powered node with an un-powered isolated Physical Layer will accumulate errors and become bus-off if it attempts to transmit. The Bus V+ sense signal would be used to change the BOI attribute of the DeviceNet Object to the "auto-reset" (01) value. Refer to Volume 1, Section 5.5.3. This would cause the node to continually reset until bus power was detected. Once power was detected, the BOI attribute would be returned to the "hold in bus-off" (00) value. The BOI attribute should not be left in the "auto-reset" (01) value since this defeats the jabber protection capability of the CAN error confinement. Any inexpensive low frequency optical isolator can be used to implement this feature. More importantly, the unique "dual-inverting" design of the HCPL-772X/072X ensure the network will not "lockup" if either AC line power to the node is lost or the node powered-off. Specifically, when input power (VDD1) to the HCPL-772X/072X located in the transmit path is eliminated, a RECESSIVE bus state is ensured as the HCPL772X/ 072X output voltage (VO) go HIGH. 15 AC LINE NON ISO 5V NODE/APP SPECIFIC P/CAN HCPL 772x/072x HCPL 772x/072x *HCPL 772x/072x GALVANIC ISOLATION BOUNDARY REG. TRANSCEIVER DRAIN/SHIELD V+ (SIGNAL) V- (SIGNAL) V+ (POWER) V- (POWER) SIGNAL POWER NETWORK POWER SUPPLY * OPTIONAL FOR BUS V + SENSE Figure 19. Isolated node with transceiver powered by the network. Isolated Node Providing Power to the Network Figure 20 shows a node providing power to the network. The AC line powers a regulator which provides 5 V locally. The AC line also powers a 24 V isolated supply, which powers the network, and another 5 V regulator, which, in turn, powers the transceiver and isolated (network) side of the two optocouplers. This method is recommended when there is a limited number of devices on the network, which do not require much power, thus eliminating the need for separate power supplies. More importantly, the unique "dual-inverting" design of the HCPL-772X/072X ensure the network will not "lockup" if either AC line power to the node is lost or the node powered-off. Specifically, when input power (VDD1) to the HCPL-772X/072X located in the transmit path is eliminated, a RECESSIVE bus state is ensured as the HCPL772X/ 072X output voltage (VO) go HIGH. AC LINE DeviceNet Node NODE/APP SPECIFIC 5 V REG. P/CAN HCPL 772x/072x ISOLATED SWITCHING POWER SUPPLY HCPL 772x/072x GALVANIC ISOLATION BOUNDARY 5 V REG. TRANSCEIVER DRAIN/SHIELD SIGNAL POWER Figure 20. Isolated node providing power to the network. 16 V+ (SIGNAL) V- (SIGNAL) V+ (POWER) V- (POWER) Power Supplies and Bypassing The recommended DeviceNet application circuit is shown in Figure 21. Since the HCPL-772X/072X are fully compatible with CMOS logic level signals, the optocoup ler is connected directly to the CAN transceiver. Two bypass capacitors (with values between 0.01 and 0.1 F) are required and should be located as close as possible GALVANIC ISOLATION BOUNDARY ISO 5 V 1 VDD1 TX0 2 VIN 0.01 F 3 5V HCPL-772x HCPL-072x + 0.01 F 7 TxD VO 6 GND2 5 + 7 4 CAN+ 3 SHIELD 2 CAN- CANL REF 1 V- VREF RXD 0.01 F 3 HCPL-772x HCPL-072x 5 V+ CANH GND GND1 4 6 VO 8 VDD2 ISO 5 V VCC Rs 5 GND2 D1 30 V VIN 2 VDD1 1 5V Figure 21. Recommended DeviceNet application circuit Implementing PROFIBUS with the HCPL-772X/072X An acronym for Process Fieldbus, PROFIBUS is essentially a twisted-pair serial link very similar to RS-485 capable of achieving high-speed communication up to 12 MBd. As shown in Figure 22, a PROFIBUS Controller (PBC) establishes the connection of a field automation unit (control or central processing station) or a field device to the transmission medium. The PBC consists of the line transceiver, optical isolation, frame character transmitter/receiver (UART), and the FDL/APP processor with the interface to the PROFIBUS user. PROFIBUS USER: CONTROL STATION (CENTRAL PROCESSING) OR FIELD DEVICE USER INTERFACE FDL/APP PROCESSOR UART PBC OPTICAL ISOLATION TRANSCEIVER MEDIUM Figure 22. PROFIBUS Controller (PBC) 17 + 82C250 C4 0.01 F GND 0.01 F LINEAR OR SWITCHING REGULATOR VDD2 8 4 GND1 RX0 to the input and output power-supply pins of the HCPL772X/072X. For each capacitor, the total lead length between both ends of the capacitor and the power supply pins should not exceed 20 mm. The bypass capacitors are required because of the high-speed digital nature of the signals inside the optocoupler. C1 0.01 F 500 V R1 1M Power Supplies and Bypassing The recommended PROFIBUS application circuit is shown in Figure 23. Since the HCPL-772X/072X are fully compatible with CMOS logic level signals, the optocoup ler is connected directly to the transceiver. Two bypass capacitors (with values between 0.01 and 0.1 F) are required and should be located as close as possible to the input and output power-supply pins of the HCPL772X/072X. For each capacitor, the total lead length between both ends of the capacitor and the power supply pins should not exceed 20 mm. The bypass capacitors are required because of the high-speed digital nature of the signals inside the optocoupler. Being very similar to multi-station RS485 systems, the HCPL-061N optocoupler provides a transmit disable function which is necessary to make the bus free after each master/slave transmission cycle. Specifically, the HCPL-061N disables the transmitter of the line driver by putting it into a high state mode. In addition, the HCPL061N switches the RX/TX driver IC into the listen mode. The HCPL-061N offers HCMOS compatibility and the high CMR performance (1 kV/s at VCM = 1000 V) essential in industrial communication interfaces. GALVANIC ISOLATION BOUNDARY 5V ISO 5 V 8 VDD2 VDD1 1 VIN 2 7 0.01 F 6 VO Rx ISO 5 V HCPL-772x HCPL-072x 1 R 0.01 F 3 0.01 F GND1 4 5 GND2 4 3 5V ISO 5 V 1 VDD1 2 VIN Tx HCPL-772x HCPL-072x 3 0.01 F 4 GND1 D B GND 5 VO 6 GND2 5 ISO 5 V 5V Tx ENABLE 1, 0 k 1 VCC 8 VE 7 2 ANODE HCPL-061N 3 CATHODE 4 VO 6 0.01 F 680 GND 5 Figure 23. Recommended PROFIBUS application circuit For product information and a complete list of distributors, please go to our website: + RT 7 SHIELD - DE 0.01 F 7 A 6 SN75176B 2 RE VDD2 8 8 VCC www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright (c) 2005-2013 Avago Technologies. All rights reserved. Obsoletes AV01-0565EN AV02-0876EN - April 5, 2013 0.01 F 1M