Features
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Optimum Technology
Matching® Applied
GaAs HBT
InGaP HBT
GaAs MESFET
SiGe BiCMOS
Si BiCMOS
SiGe HBT
GaAs pHEMT
Si CMOS
Si BJT
GaN HEMT
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Product Description
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InP HBT
LDMOS
RF MEMS
FPD1500SOT89CE
LOW-NOISE HIGH-LINEARITY PACKAGED
pHEMT
The FPD1500SOT89CE is a packaged depletion mode AlGaAs/InGaAs pseudomor-
phic High Electron Mobility Transistor (pHEMT). It features a 0.25Pmx1500Pm
Schottky barrier gate, defined by high-resolution stepper-based photolithography.
The double recessed gate structure minimizes parasitics to optimize performance.
The epitaxial structure is designed for improved linearity over a range of bias condi-
tions and input power levels.
27.5dBm Output Power
(P1dB)
17dB Small-Signal Gain
(SSG)
0.9dB Noise Figure
42dBm OIP3
50% Power-Added Efficiency
FPD1500SOT89CE: RoHS
Compliant
Applications
Drivers or Output Stages in
PCS/Cellular Base Station
Transmitter Amplifiers
High Intercept-point LNAs
WLL, WLAN, and Other Types
of Wireless Infrastructure
Systems.
DS130523
9
Package: SOT89
FPD1500SOT8
9CE Low-Noise
High-Linearity
Packaged
pHEMT
Parameter Specification Unit Condition
Min. Typ. Max.
P1dB Gain Compression 26.0 27.5 dBm VDS=5V, IDS =50% IDSS
Small-Signal Gain (SSG) 15.5 17 dB VDS=5V, IDS=50% IDSS
PAE 50 % VDS=5V, IDS=50% IDSS, POUT =P1dB
Noise Figure (NF) 0.9 dB VDS=5V, IDS=50% IDSS; VDS =5V, IDS=25% IDSS
OIP338 40 dBm VDS =5V, IDS=50% IDSS. Matched for optimal
power.
42 dBm Matched for best IP3
Saturated Drain-Source Current (IDSS) 375 465 550 mA VDS=1.3V, VGS =0V
Maximum Drain-Source Current
(IMAX)750 mA VDS=1.3V, VGS |+1V
Transconductance (GM) 400 ms VDS=1.3V, VGS =0V
Gate-Source Leakage Current (IGSO) 1 15 PAV
GS=-5V
Pinch-Off Voltage (VP) |0.7| |1.0| |1.3| V VDS=1.3V, IDS=1.5mA
Gate-Source Breakdown Voltage
(VBDGS)|12| |16| V IGS=1.5mA
Gate-Drain Breakdown Voltage
(VBDGD)|12| |16| V IGD=1.5mA
Thermal Resistivity (TJC) * 60 qC/W
*Note: TAMBIENT =22°C, RF specifications measured at f=1850GHz using CW signal (except as noted).
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FPD1500SOT89CE
Biasing Guidelines
Active bias circuits provide good performance stabilization over variations of operating temperature, but require a larger num-
ber of components compared to self-bias or dual-biased. Such circuits should include provisions to ensure that gate bias is
applied before drain bias.
Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage supply for depletion-mode
devices.
For standard Class A operation, an operating point of 50% of IDSS is recommended. A small amount of RF gain expansion prior
to the onset of compression is normal for this operating point. A class A/B Bias of 25% to 33% of IDSS to achieve better OIP3
and Noise Figure performance is suggested.
Absolute Maximum Ratings1
Parameter Rating Unit
Drain-Source Voltage (VDS)
(-3V<VGS<-0.5V)
8V
Gate-Source Voltage (VGS)
(0V<VDS <+8V)
-3 V
Drain-Source Current (IDS)
(For VDS>2V)
IDSS
Gate Current (IG) (Forward or reverse) 15 mA
RF Input Power (PIN)2
(Under any acceptable bias state)
350 mW
Channel Operating Temperature (TCH)
(Under any acceptable bias state)
175 °C
Storage Temperature (TSTG)
(Non-Operating Storage)
-55 to 150 °C
Total Power Dissipation (PTOT)3, 4 2.3 W
Gain Compression
(Under bias conditions) 5dB
Simultaneous Combination of Limits6
(2 or more max. limits)
Notes:
1TAMBIENT =22°C unless otherwise noted; exceeding any one of these absolute max-
imum ratings may cause permanent damage to the device.
2Max. RF input limit must be further limited if input VSWR>2.5:1.
3Users should avoid exceeding 80% of 2 or more Limits simultaneously.
4Total Power Dissipation (PTOT) defined as (PDC +PIN)–POUT, where PDC: DC Bias
Power, PIN: RF Input Power, POUT: RF Output Power.
Total Power Dissipation to be de-rated as follows above 22°C:
PTOT =2.3-(0.016W/°C)xTPACK, where TPACK =source tab lead temperature
above 22°C. (Coefficient of de-rating formula is Thermal Conductivity.)
Exampe: For a 65°C carrier temperature: PTOT =2.3W-(0.016x(65-22))=1.61W
Caution! ESD sensitive device.
Exceeding any one or a combination of the Absolute Maximum Rating conditions may
cause permanent damage to the device. Extended application of Absolute Maximum
Rating conditions to the device may reduce device reliability. Specified typical perfor-
mance or functional operation of the device under Absolute Maximum Rating condi-
tions is not implied.
RoHS status based on EUDirective2002/95/EC (at time of this document revision).
The information in this publication is believed to be accurate and reliable. However, no
responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any
infringement of patents, or other rights of third parties, resulting from its use. No
license is granted by implication or otherwise under any patent or patent rights of
RFMD. RFMD reserves the right to change component circuitry, recommended appli-
cation circuitry and specifications at any time without prior notice.
Not For New Design
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FPD1500SOT89CE
Frequency Response
Temperature Response
Device tuned for minimum noise figure.
0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8
Frequency (GHz)
Biased @ 5V 50%IDSS
0
5
10
15
20
25
30
35
Mag S21 & MSG
MSG
S21
Biased @ 5V, 200m A
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0.5
0.9
1. 3
1.7
2.1
2.5
2.9
3.3
3.7
4.1
4.5
4.9
5.3
5.7
Fr e quency (GHz)
Noise FIgure (dB)
N. F . ( d B)
Evaluation board tuned for maximum power.
Biased @ 5V, 50%IDSS
Data tak en on Ev al Boa rd at 1.85 GHz
12.0
13.0
14.0
15.0
16.0
17.0
18.0
-20
-10
0
10
20
30
40
50
60
70
80
90
Temperature (C)
SSG (dB)
20. 0
21. 0
22. 0
23. 0
24. 0
25. 0
26. 0
27. 0
28. 0
29. 0
30. 0
P1dB (dBm)
SSG (dB)
P1dB (dBm)
Biased @ 5V , 33 %IDSS
Data take n on Ev al boa rd @ 1.85GHz
.00
.10
.20
.30
.40
.50
.60
.70
-20
-10
0
10
20
30
40
50
60
70
80
90
Temp era tu re ( C)
Noise Figure (dB)
N.F. (dB
)
Not For New Design
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FPD1500SOT89CE
Typical Tuned RF Performance
Typical I-V Characteristics
Note: Typical power and efficiency are shown above. The devices were biased nominally at VDS=5V, IDS =50% of IDSS, at a test
frequency of 1.85GHz. The test devices were tuned (input and output) for maximum output power at 1dB gain compression.
Note: pHEMT devices have enhanced intermodulation per-
formance. This yields OIP3 values of about
P1dB+14dBm. This IMD enhancement is affected by the
quiescent bias and the matching applied to the device.
Power Transfer Characteristic
13.00
15.00
17.00
19.00
21.00
23.00
25.00
27.00
29.00
- 2.00 0.0 0 2.0 0 4. 00 6. 00 8 .00 1 0.00 1 2.00 14.00 16.00
Inpu t Po wer (dB m)
Out put P ower ( dBm
-.5 0
.00
.50
1.00
1.50
2.00
2.50
3.00
3.50
Gain Comp ression (dB
)
P out Comp Point
Drain Effici ency and P AE
.00%
10 .00%
20 .00%
30 .00%
40 .00%
50 .00%
60 .00%
70 .00%
- 2.00 0.00 2.00 4 .00 6.0 0 8.00 1 0.00 12 .00 14.0 0 16.00
Inp ut Po wer (dB m)
PAE (%
)
.00%
10.00 %
20.00 %
30.00 %
40.00 %
50.00 %
60.00 %
70.00 %
Dr ain E fficiency (
%
PAE Eff.
Typical Intermodulati on Performanc e
V D S = 5V ID S = 50 % IDS S a t f = 1. 85 GHz
15.00
17.00
19.00
21.00
23.00
25.00
-1. 0 0 1 .00 3.00 5.00 7.00 9.00 11.00
Input Power (dBm)
Ou tp u t P o we r (d Bm
)
-55.00
-50.00
-45.00
-40.00
-35.00
-30.00
-25.00
-20.00
-15.00
-10.00
3rd Oder IM Poroducts (dB
c
Pout Im3, dB c
Note: The recommended method for measuring IDSS, or any
particular IDS, is to set the Drain-Source voltage (VDS) at 1.3V.
This measurement point avoids the onset of spurious self-
oscillation which would normally distort the current measure-
ment (this effect has been filtered from the I-V curves pre-
sented above). Setting the VDS>1.3V will generally cause
errors in the current measurements, even in stabilized circuits.
DC IV C ur v es F PD15 0 0SO T 89
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Drain-Sou rce Vo ltage (V)
Drain-Source Current (A)
VG=-1.5V
VG- 1.2 5 V
VG=-1.00V
VG=-0.75V
VG=-0.5V
VG=-0.25V
VG=0V
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FPD1500SOT89CE
Typical Output Plane Power Contours
(VDS=5V, IDS =50% IDSS)
Typical Scattering Parameters
(50: System)
1850 MHz
Contours swept with a constant input power, set so that optimum P1dB is
achieved at the point of output match.
Input (Source plane) *s:
0.74168.2º
0.15+j0.1 (normalized)
7.5+j5.0:
Nominal IP3 performance is obtained with this input plane match, and
the output plane match as shown.
900 MHz
Contours swept with a constant input power, set so that optimum P1dB is
achieved at the point of output match.
Input (Source plane) *s:
0.67103.6 º
0.30+j0.74 (normalized)
15+j37.0:
Nominal IP3 performance is obtained with this input plane match, and
the output plane match as shown.
0
10
.0
10.0
-10.0
5.
0
5.0
-5.0
2.
0
2.
0
-
2.
0
3
.
0
3. 0
-3.0
4.
0
4.0
-4.0
0.
2
0.2
-0.2
0.
4
0.4
-0.4
0.
6
0.
6
-
0.
6
0.
8
0.
8
-
0.
8
Swp Ma x
159
Swp Min
1
28 dBm
26 dBm
25dBm
24dBm
23 d B m
2
2dBm
27dBm
0
1.
0
1.
0
-
1.
0
10
.0
10
.
0
-10.0
5.
0
5. 0
-5.0
2.
0
2.
0
-
2.
0
3.
0
3.0
-
3
.
0
4.
0
4.0
-
4
.
0
0.
2
0. 2
-0.2
0.
4
0.4
-0.4
0.
6
0.
6
-
0.
6
0
.
8
0.
8
-
0.
8
Swp Max
12 3
Swp M in
1
28 d Bm
26 d B m
25dBm
24 dB m
23dBm
22dBm
27dBm
0
1. 0 1. 0-1 .0
10.0
10
.0
-1
0.
0
5.0
5.
0
-5
.0
2.0
2. 0
-2 .
0
3. 0
3. 0
-3 .0
4.0
4.
0
-4
.0
0. 2
0
.
2
-
0
.2
0.4
0.
4
-0
.4
0.6
0
.
6
-
0
.6
0. 8
0.
8
-0
.8
FPD1500SOT89 5V / 50%IDSS
Swp Max
8GHz
Swp Min
0.5GHz
S11
1 GH z
1.5 GHz
2 GHz
2.5 G Hz
3 GHz
3.5 GHz
4 GH z
5 GHz 6 GHz
7 GH z
0
1.
0
1.
0
-
1.
0
10
.0
10.0
-10.0
5.
0
5.0
-5 . 0
2.
0
2.
0
-
2.
0
3.
0
3.0
-3.0
4.
0
4.0
-4.0
0.
2
0.2
-0.2
0.
4
0.4
-0.4
0
.
6
0.
6
-
0.
6
0.
8
0.
8
-
0.
8
FPD1500SOT89 5V / 50%IDSS
Swp Max
8GHz
Swp Min
0. 5 GH z
S22
1 GHz
2 GH z
3 GHz
4 GHz
5 GH z
6
GHz 7 GHz
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FPD1500SOT89CE
Typical Sample of RF Performance
Parameter Median Standard Deviation Test Limit CPK
Small-Signal Gain 15.5 0.20 14.5 1.7
Noise Figure 0.91 0.03 1.20 3.2
Output Power (P1dB) 25.2 0.25 24.5 0.93
3rd-Order Intercept 38.7 1.1 36.5 0.67
Note: The devices were tested by a high-speed automatic test system in a matched circuit based on a 2GHz evaluation board.
This circuit is a dual-bias single-pole lowpass topology, and the devices were biased at VDS=4.5V, IDS =120mA, test
frequency=2.0GHz. The performance data is summarized below:
Small Signal Gain
0
2000
4000
6000
8000
10000
12000
14000
13 14 15 16 1 7 18
Gain (dB)
Co unt
Noise Figure
0
1000
2000
3000
4000
5000
6000
0.6 0.7 0.8 0.9 1 1.1 1.2 1.3
NF (dB)
Co unt
Output Power at 1dB Gain Compression
0
2000
4000
6000
8000
10000
12000
14000
23 24 25 26 27 28
P1d B (d Bm)
Co unt
Output 3rd
-Order Intercept Point
0
1000
2000
3000
4000
5000
6000
30 32 34 36 38 40 42 44
IP3 (d Bm)
Co unt
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FPD1500SOT89CE
Reference Design (0.9GHz)
Note: OIP3 measured at 15dBm per tone.
Evaluation Board Layout
Component Values
Evaluation board material: 31mil thick FR4 with 1/2oz.
Cu on both sides.
DC-blocking capacitors are ATC series 600S. A tantalum
1.0μF is used at the drain terminal. All other capacitors
are 0603 and 0805 standard chip capacitors. A 0603
size 20: chip resistor from Vishay is used on the gate DC
bias line for stability.
Parameter Typical Unit
Gain 20 dB
P1dB 27 dBm
OIP339 dBm
NF 0.7 dB
S11 -5 dB
S22 -15 dB
VD5V
VG-0.4 to -0.6 V
ID200 mA
Component Value Description
Lg 47nH LL 1608 Toko chip inductor
Ld 47nH LL 1608 Toko chip inductor
L1 12nH LL 1005 Toko chip inductor
L2 4.7nH LL 1005 Toko chip inductor
C1 5.6pF ATC 600S chip capacitor
33pF
Lg
33pF L1
0.01uF 20O
L2
+1.0uF
Q1 C1
33pF
Ld
33pF
0.01uF +
Vg V d
1.45"
0.63"
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33pF 33pF
20 Ohm
33pF
33pF
0.01uF
0.01uF 1.0uF
Vd-Vg
47 nH 47 nH
L1
L2
C1
RF I N RF OU T
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FPD1500SOT89CE
Reference Design (1.85GHz)
Note: OIP3 measured at 15dBm per tone.
Evaluation Board Layout
Component Values
Evaluation board material: 31mil thick FR4 with 1/2oz.
Cu on both sides.
DC-blocking capacitors are ATC series 600S. A tantalum
1.0μF is used at the drain terminal. All other capacitors
are 0603 and 0805 standard chip capacitors. A 0603
size 20: chip resistor from Vishay is used on the gate DC
bias line for stability.
Parameter Typical Unit
Gain 16 dB
P1dB 27 dBm
OIP341 dBm
NF 0.9 dB
S11 -9 dB
S22 -14 dB
VD5V
VG-0.4 to -0.6 V
ID200 mA
Component Value Description
Lg 27nH LL 1608 Toko chip inductor
Ld 27nH LL 1608 Toko chip inductor
L1 1.5nH LL 1005 Toko chip inductor
L2 4.7nH LL 1005 Toko chip inductor
C1 2.2pF ATC 600S chip capacitor
33pF
Lg
33pF L1
0.01uF 20 O
L2
+1.0uF
Q1 C1
33pF
Ld
33pF
0.01uF +
Vg Vd
1.45"
0.63"
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33pF 33pF
20 Ohm
33pF
33pF
0.01uF
0.01uF 1.0uF
Vd-Vg
27 nH 27 nH
L1
L2
C1
RF IN RF OUT
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FPD1500SOT89CE
Reference Design (2.4GHz to 2.6GHz)
Note: OIP3 measured at 15dBm per tone.
Evaluation Board Layout
Component Values
Evaluation board material: 31mil thick FR4 with 1/2oz.
Cu on both sides.
DC-blocking capacitors are ATC series 600S. A tantalum
1.0μF is used at the drain terminal. All other capacitors
are 0603 and 0805 standard chip capacitors. A 0603
size 20: chip resistor from Vishay is used on the gate DC
bias line for stability.
Parameter @ 2.4GHz @ 2.6GHz Unit
Gain 12.5 12.4 dB
P1dB 28 28 dBm
OIP339 40 dBm
NF 1.0 0.9 dB
S11 -14 -16 dB
S22 -5 -6 dB
VD55V
VG-0.4 to -0.6 -0.4 to -0.6 V
ID200 200 mA
Component Value Description
Lg 18nH LL 1608 Toko chip inductor
Ld 18nH LL 1608 Toko chip inductor
L1 0.0nH no component (Cu tab)
L2 3.9nH LL 1005 Toko chip inductor
C1 and C2 1.0pF ATC 600S chip capacitor
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20
O
33pF
C1
0.01uF
Lg
L1
33p FC2
L2
33 pF
Q1
33 pF
+
Ld
0.01uF
+1.0uF
Vg Vd
1.45"
0.63"
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33pF 33pF
20 Ohm
33pF
33pF
0.01uF
0.01uF 1.0uF
Vd-Vg
18 nH 18 nH
L2
C2
RF IN RF OU T
C1
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FPD1500SOT89CE
S-Parameters
(Biased @ 5V, 50% IDSS)
FREQ[GHz] S11m S11a S21m S21a S12m S12a S22m S22a
0.500 0.865 -91.9 18.828 121.6 0.027 52.3 0.293 -130.2
0.750 0.763 -118.7 14.373 107.4 0.033 46.3 0.287 -141.8
1.000 0.728 -136.4 11.562 95.9 0.038 42.6 0.293 -154.9
1.250 0.714 -149.6 9.707 87.0 0.043 39.6 0.285 -162.6
1.500 0.701 -162.1 8.254 79.1 0.047 37.4 0.284 -172.6
1.750 0.694 -171.3 7.225 71.2 0.052 34.6 0.288 -178.7
2.000 0.692 179.8 6.460 64.2 0.057 32.1 0.279 175.2
2.250 0.684 171.3 5.820 57.4 0.061 29.4 0.279 168.4
2.500 0.685 163.7 5.320 50.7 0.067 26.1 0.271 161.9
2.750 0.683 155.8 4.884 44.6 0.071 23.5 0.273 153.9
3.000 0.681 148.1 4.506 37.8 0.076 19.7 0.273 147.1
3.250 0.692 141.4 4.199 31.4 0.080 16.0 0.276 138.5
3.500 0.690 134.1 3.913 25.1 0.085 12.4 0.290 131.2
3.750 0.698 127.7 3.651 18.8 0.089 8.5 0.302 124.2
4.000 0.706 120.8 3.418 12.7 0.093 4.6 0.318 118.0
4.250 0.711 114.3 3.207 6.5 0.096 0.5 0.335 112.5
4.500 0.730 108.9 3.018 0.8 0.100 -3.5 0.349 107.0
4.750 0.742 103.2 2.834 -5.0 0.102 -7.4 0.367 101.4
5.000 0.757 98.2 2.672 -10.6 0.105 -11.1 0.381 96.3
5.250 0.765 92.4 2.531 -16.1 0.108 -14.6 0.396 91.7
5.500 0.769 87.7 2.408 -21.7 0.111 -18.6 0.406 87.3
5.750 0.790 83.4 2.300 -26.9 0.114 -22.2 0.417 83.2
6.000 0.847 77.1 2.263 -33.3 0.121 -27.1 0.457 79.0
6.250 0.830 73.0 2.139 -38.4 0.122 -30.6 0.457 75.1
6.500 0.850 67.3 2.046 -45.2 0.124 -36.0 0.476 68.2
6.750 0.826 63.8 1.926 -49.9 0.125 -39.1 0.471 62.2
7.000 0.829 60.2 1.839 -54.7 0.127 -42.7 0.471 55.5
7.250 0.828 56.4 1.763 -59.5 0.128 -46.1 0.470 50.2
7.500 0.823 52.8 1.698 -64.6 0.130 -49.9 0.477 44.5
7.750 0.836 48.9 1.641 -69.8 0.133 -54.2 0.491 39.2
8.000 0.855 44.5 1.580 -75.7 0.135 -58.9 0.507 33.8
8.250 0.858 38.3 1.512 -81.5 0.135 -63.5 0.531 29.3
8.500 0.855 32.9 1.442 -86.8 0.136 -68.0 0.552 24.7
8.750 0.863 27.9 1.374 -92.3 0.136 -72.8 0.575 21.2
9.000 0.874 22.0 1.311 -97.5 0.136 -77.2 0.596 17.7
9.250 0.875 16.9 1.247 -102.5 0.135 -81.6 0.618 15.4
9.500 0.885 11.9 1.182 -107.8 0.134 -86.4 0.637 13.0
9.750 0.890 7.4 1.124 -112.5 0.133 -91.4 0.652 11.0
10.000 0.895 3.8 1.069 -117.4 0.131 -96.4 0.663 8.0
10.250 0.897 0.5 1.012 -121.7 0.128 -101.8 0.673 5.1
10.500 0.899 -2.9 0.975 -126.0 0.125 -106.8 0.680 2.5
10.750 0.902 -5.6 0.928 -130.2 0.120 -111.1 0.693 0.0
11.000 0.902 -8.1 0.894 -134.3 0.117 -114.6 0.698 -2.9
11.250 0.907 -10.5 0.865 -138. 4 0.115 -118.0 0.701 -6.0
11.500 0.913 -13.5 0.845 -142. 1 0.114 -120.9 0.695 -9.7
11.750 0.912 -16.4 0.822 -146. 4 0.114 -124.3 0.691 -13.3
12.000 0.908 -19.4 0.806 -150. 7 0.117 -128.3 0.684 -18.1
Not For New Design
11 of 12DS130523
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (
(+1) 336-678-5570
or s
sales-support@rfmd.com
.
FPD1500SOT89CE
Part Identification
Package Outline
Dimensions in millimeters (mm)
Tape and Reel Dimensions and Part Orientation
Tape and Reel information on this material is in accordance with EIA-481-1 except where exceptions are identified
Device Footprint
Units in inches
Not For New Design
12 of 12 DS130523
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (
(+1) 336-678-5570
or s
sales-support@rfmd.com
.
FPD1500SOT89CE
Preferred Assembly Instructions
This package is compatible with both lead-free and leaded solder reflow processes as defined within IPC/JEDEC J-STD-020C.
The maximum package temperature should not exceed 260°C.
Handling Precautions
To avoid damage to the devices, care should be exercised during handling. Proper Electro-
static Discharge (ESD) precautions should be observed at all stages of storage, handling,
assembly, and testing.
ESD Rating
These devices should be treated as Class 0 (0V to 250V) using the human body model as defined in JEDEC Standard No. 22-
A114. Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263.
MSL Rating
The device has an MSL rating of Level 2. To determine this rating, preconditioning was performed to the device per the Pb-free
solder profile defined within IPC/JEDEC J-STD-020C, moisture/reflow sensitivity classification for non-hermetic solid state sur-
face mount devices.
Application Notes and Design Data
Application Notes and design data including S-parameters, noise paramters, and device model are available on request and
from www.rfmd.com.
Disclaimers
An MTTF of 7.4 million hours at a channel temperature of 150°C is achieved for the process used to manufacture this device.
Disclaimers
This product is not designed for use in any space-based or life-sustaining/supporting equipment.
Ordering Information
Ordering Code Description
FPD1500SOT89CESQ Sample bag with 25 pieces
FPD1500SOT89CESR 7" Reel with 100 pieces
FPD1500SOT89CE 7" Reel with 1000 pieces
FPD1500SOT89PCK 1.85GHz PCBA with 5-piece sample bag
Not For New Design