Copyright ANPEC Electronics Corp.
Rev. A.3 - Nov., 2009
APW7120A
www.anpec.com.tw1
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
5V to 12V Supply Voltage, 8-PIN, Synchronous Buck PWM Controller
•Operating with Single 5~12V Supply Voltage or
Two Supply Voltages
•Drive Dual Low Cost N-Channel MOSFETs
- Adaptive Shoot-Through Protection
•Built-in Feedback Compensation
- Voltage-Mode PWM Control
- 0~100% Duty Ratio
- Fast Transient Response
•±2% 0.8V Reference
- Over Line, Load Regulation, and Operating
Temperature
•Programmable Over-Current Protection
- Using RDS(ON) of Low-Side MOSFET
•Hiccup-Mode Under-Voltage Protection
•118% Over-Voltage Protection
•Adjustable Output Voltage
•Small Converter Size
- 300kHz Constant Switching Frequency
- Small SOP-8 Package
•Built-In Digital Soft-Start
•Shutdown Control Using an External MOSFET
•Lead Free and Green Devices Available
(RoHS Compliant)
Features
Applications
General Description
The APW7120A is a fixed 300kHz frequency, voltage mode,
and synchronous PWM controller. The device drives two
low cost N-channel MOSFETs and is designed to work
with single 5~12V or two supply voltage(s), providing ex-
cellent regulation for load transients.
The APW7120A integrates controls, monitoring and pro-
tection functions into a single 8-pin package to provide a
low cost and perfect power solution.
A power-on-reset (POR) circuit monitors the VCC supply
voltage to prevent wrong logic controls. An internal 0.8V
reference provides low output voltage down to 0.8V for
further applications. An built-in digital soft-start with fixed
soft-start interval prevents the output voltage from over-
shoot as well as limiting the input current. The controller’s
over-current protection monitors the output current by
using the voltage drop across the low-side MOSFET’s
RDS(ON), eliminating the need of a current sensing resistor.
Additional under voltage and over voltage protections
monitor the voltage on FB pin for short-circuit and over-
voltage protections. The over-current protection cycles the
soft-start function until 4 over-current events are counted.
Pulling and holding the voltage on OCSET pin below
0.15V with an open drain device shuts down the controller.
Pin Cinfiguration
SOP-8
(Top View)
•Motherboard
•Graphics Card
•High Current, Up to 20A, DC-DC Converters
1
2
3
4
8
7
6
5
PHASE
OCSET
FB
VCC
BOOT
UGATE
GND
LGATE
Copyright ANPEC Electronics Corp.
Rev. A.3 - Nov., 2009
APW7120A
www.anpec.com.tw2
Ordering and Marking Information
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Symbol Parameter Rating Unit
VCC VCC Supply Voltage (VCC to GND) -0.3 ~ 16 V
VBOOT BOOT Voltage (BOOT to PHASE) -0.3 ~ 16 V
UGATE Voltage (UGATE to PHASE)
<400ns pulse width
>400ns pulse width
-5 ~ VBOOT+0.3
-0.3 ~ VBOOT+0.3 V
LGATE Voltage (LGATE to GND)
<400ns pulse width
>400ns pulse width
-5 ~ VCC+0.3
-0.3 ~ VCC+0.3 V
PHASE Voltage (PHASE to GND)
<400ns pulse width
>400ns pulse width
-10 ~ 30
-3 ~ 16 V
VI/O Input Voltage (OCSET, FB to GND) -0.3 ~ 7 V
Maximum Junction Temperature 150 oC
TSTG Storage Temperature -65 ~ 150 oC
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 oC
Absolute Maximum Ratings (Note 1)
Thermal Characteristics
Symbol Parameter Typical Value Unit
θJA Junction-to-Ambient Resistance in Free Air (Note 2)
SOP-8
160 oC/W
APW7120A
Handling Code
Temperature Range
Package Code
Package Code
K : SOP-8
Operating Ambient Temperature Range
E : -20 to 70 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APW7120A K : APW7120A
XXXXX XXXXX - Date Code
Assembly Material
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Copyright ANPEC Electronics Corp.
Rev. A.3 - Nov., 2009
APW7120A
www.anpec.com.tw3
Symbol
Parameter Range Unit
VCC VCC Supply Voltage 4.5 ~ 13.2 V
VOUT Converter Output Voltage 0.8 ~ 70%VIN V
VIN Converter Input Voltage 2.2 ~ 13.2 V
IOUT Converter Output Current 0 ~ 20 A
TA Ambient Temperature -20 ~ 70 oC
TJ Junction Temperature -20 ~ 125 oC
Recommended Operating Conditions (Note 3)
Electrical Characteristics
Unless otherswise specified, these specifications apply over VCC = 12V, VBOOT = 12V and TA = -20 ~ 70oC. Typical values
are at TA = 25oC.
APW7120A
Symbol
Parameter Test Conditions Min.
Typ.
Max.
Unit
SUPPLY CURRENT
IVCC VCC Nominal Supply Current UGATE and LGATE Open - 2.1 6 mA
VCC Shutdown Supply Current - 1.5 4 mA
POWER-ON-RESET
Rising VCC Threshold 3.8 4.1 4.4 V
Hysteresis 0.1 0.45
0.6 V
OSCILLATOR
FOSC Free Running Frequency 250
300
350
kHz
∆VOSC Ramp Amplitude - 1.5 - VP-P
REFERENCE VOLTAGE
VREF Reference Voltage Measured at FB Pin - 0.8 - V
Accuracy TA =-20~70°C -2.0
- +2.0
%
Line Regulation VCC=12 ~ 5V - 0.05
0.5 %
ERROR AMPLIFIER
DC Gain - 86 - dB
FP1 First Pole Frequency - 0.4 - Hz
FZ Zero Frequency - 0.4 - kHz
FP2 Second Pole Frequency - 430
- kHz
Average UGATE Duty Range 0 - 70 %
FB Input Current - - 0.1 µA
PWM CONTROLLER GATE DRIVERS
UGATE Source VBOOT-PHASE =12V, VUGATE-PHASE =6V 1.0 2.0 - A
UGATE Sink VBOOT-PHASE =12V, VUGATE-PHASE=1V - 3.5 7 Ω
LGATE Source VCC=12V, VLGATE=6V 1.0 1.9 - A
LGATE Sink VCC=12V, VLGATE=1V - 2.6 5 Ω
TD Dead-Time Guaranteed by Design - 40 100
ns
Note 3: Please refer to the typical application circuit.
Copyright ANPEC Electronics Corp.
Rev. A.3 - Nov., 2009
APW7120A
www.anpec.com.tw4
APW7120A
Symbol
Parameter Test Conditions Min.
Typ.
Max.
Unit
PROTECTIONS
IOCSET OCSET Current Source VPHASE=0V, Normal Operation 35 40 45 µA
Over-Current Reference Voltage TA =-20~70°C 0.37
0.4 0.43
V
UVFB FB Under-Voltage Threshold VFB Falling 62 67 72 %
FB Under-Voltage Hysteresis - 45 - mV
Over-Voltage Threshold VFB Rising 114
118
122
%
SOFT-START AND SHUTDOWN
TSS Soft-Start Interval 2 3.8 5 ms
OCSET Shutdown Threshold Falling VOCSET 0.1 0.15
0.3 V
OCSET Shutdown Hysteresis - 40 - mV
Electrical Characteristics (Cont.)
Unless otherswise specified, these specifications apply over VCC = 12V, VBOOT = 12V and TA = -20 ~ 70oC. Typical values
are at TA = 25oC.
Copyright ANPEC Electronics Corp.
Rev. A.3 - Nov., 2009
APW7120A
www.anpec.com.tw5
Typical Operating Characteristics
Junction Temperature (oC)
Reference Voltage vs. Junction
Temperature
Reference Voltage, VREF (V)
Switching Frequency vs. Junction
Temperature
Junction Temperature (oC)
Switching Frequency, FOSC (kHz)
OCSET Current vs. Junction TemperatureVCC POR Threshold Voltage vs.
Junction Temperature
Junction Temperature (oC)
OCSET Current, IOCSET (µA)
Junction Temperature (oC)
VCC POR Threshold Voltage (V)
-50 -25 0 25 50 75 100 125 150
0.788
0.790
0.792
0.794
0.796
0.798
0.800
0.802
0.804
0.806
0.808
0.810
0.812
-50 -25 0 25 50 75 100 125 150
250
260
270
280
290
300
310
320
330
340
350
-50 -25 0 25 50 75 100 125 150
35
36
37
38
39
40
41
42
43
44
45
-50 -25 0 25 50 75 100 125 150
3.4
3.5
3.6
3.7
3.8
3.9
4.0
4.1
4.2
4.3
4.4
Rising VCC
Falling VCC
Junction Temperature (oC)
OCSET Shutdown Threshold Voltage
vs. Junction Temperature
OCSET Shutdown Threshold Voltage (V)
-50 -25 0 25 50 75 100 125 150
0.10
0.12
0.14
0.16
0.18
0.20 Falling VOCSET
Copyright ANPEC Electronics Corp.
Rev. A.3 - Nov., 2009
APW7120A
www.anpec.com.tw6
Operating Waveforms
(Refer to the typical application circuit, VBAIS=VIN=+12V supplied by an ATX Power Supply)
1. Load Transient Response : IOUT = 0A -> 15A -> 0A
- IOUT slew rate = ±7.5A/µs
Ch1 : VOUT, 100mV/Div, AC,
Ch2 : IOUT, 10A/Div
Ch3 : VUGATE, 20V/Div, DC
Time : 5µs/Div
BW = 20 MHz
Ch1 : VOUT, 100mV/Div, AC,
Ch2 : IOUT, 10A/Div
Ch3 : VUGATE, 20V/Div, DC
Time : 40µs/Div
BW = 20 MHz
Ch1 : VOUT, 100mV/Div, AC,
Ch2 : IOUT, 10A/Div
Ch3 : VUGATE, 20V/Div, DC
Time : 5µs/Div
BW = 20 MHz
IOUT = 0A -> 15AIOUT = 0A -> 15A -> 0AIOUT = 15A -> 0A
11
33
22
11
33
22
11
33
22
VOUT
VUGATE
IOUT
VUGATE
IOUT
VOUT
VOUT=1.8V VOUT
IOUT
0A
15A
VUGATE
2. UGATE and LGATE Switching Waveforms
Rising VUGATE
Ch1 : VUGATE, 5V/Div, DC
Time : 20ns/DivCh2 : VLGATE, 2V/Div, DC
BW = 500 MHz
Falling VUGATE
Ch1 : VUGATE, 5V/Div, DC
Time : 20ns/DivCh2 : VLGATE, 2V/Div, DC
BW = 500 MHz
VUGATE
1,21,2
IOUT = 15A
VLGATE
1,21,2
VUGATE
VLGATE
Copyright ANPEC Electronics Corp.
Rev. A.3 - Nov., 2009
APW7120A
www.anpec.com.tw7
Operating Waveforms (Cont.)
3. Powering ON / OFF
Powering ONPowering OFF
Ch1 : VCC, 2V/Div, DC
Ch3 : IL, 10A/Div, DC
BW = 20 MHz
Ch2 : VOUT, 1V/Div, DC
Time : 10ms/Div
22
VCC
IL
VOUT
22
VCC
IL
VOUT
(Refer to the typical application circuit, VBIAS=VIN=+12V supplied by an ATX Power Supply)
VCC=VIN=5V
RL=0.12Ω
11
33
VCC=VIN=5V
RL=0.12Ω
11
33
Ch1 : VCC, 2V/Div, DC
Ch3 : IL, 10A/Div, DC
BW = 20 MHz
Ch2 : VOUT, 1V/Div, DC
Time : 5ms/Div
Powering ONPowering OFF
22
VCC
IL
VOUT
22
VCC
IL
VOUT
11
33
11
33
VCC=VIN=12V
RL=0.12Ω
VCC=VIN=12V
RL=0.12Ω
Ch1 : VCC, 5V/Div, DC
Ch3 : IL, 10A/Div, DC
BW = 20 MHz
Ch2 : VOUT, 1V/Div, DC
Time : 5ms/Div
Ch1 : VCC, 5V/Div, DC
Ch3 : IL, 10A/Div, DC
BW = 20 MHz
Ch2 : VOUT, 1V/Div, DC
Time : 10ms/Div
Copyright ANPEC Electronics Corp.
Rev. A.3 - Nov., 2009
APW7120A
www.anpec.com.tw8
4. Enabling and Shutting Down
Enabling by Releasing OCSET Pin
Ch1 : VOUT, 1V/Div, DC
Ch3 : VOCSET, 2V/Div, DC
BW = 20 MHz
Ch2 : VUGATE, 20V/Div, DC
Time : 2ms/Div
Shutting Down by Pulling OCSET Low
Ch1 : VOUT, 1V/Div, DC
Ch3 : VOCSET, 2V/Div, DC
BW = 20 MHz
Ch2 : VUGATE, 20V/Div, DC
Time : 2ms/Div
11
33
22
VOUT
VUGATE
VOCSET
IOUT=2A
VOUT
VUGATE
VOCSET
11
33
22
Operating Waveforms (Cont.)
(Refer to the typical application circuit, VBIAS=VIN=+12V supplied by an ATX Power Supply)
5. Over-Current Protection
No Connecting a shutdown MOSFET
at OCSET Pin
Ch1 : VOUT, 1V/Div, DC
Time : 5ms/DivCh2 : IL, 10A/Div, DC
BW = 20 MHz
Connecting a shutdown MOSFET
(2N7002) at OCSET Pin
Ch1 : VOUT, 1V/Div, DC
Time : 5ms/DivCh2 : IL, 10A/Div, DC
BW = 20 MHz
IL
11
22
VOUT
IL
11
22
VOUT
ROCSET=15k
APM2512 ROCSET=15k
APM2512
Copyright ANPEC Electronics Corp.
Rev. A.3 - Nov., 2009
APW7120A
www.anpec.com.tw9
6. OCSET Voltage RC Delay
Ch1 : VOCSET, 0.5V/Div, DC
Time : 2µS/Div
Ch2 : IL, 10A/Div, DC
BW = 20 MHzCh1 : VOCSET, 0.5V/Div, DC
Time : 2µ S/Div
Ch2 : IL, 10A/Div, DC
BW = 20 MHz
VOCSET
IL
CProber=8pF
OCPOCP
1,21,2
IL
OCPOCP
1,21,2
VOCSET
No Connecting a shutdown MOSFET
at OCSET PinConnecting a shutdown MOSFET
(2N7002) at OCSET Pin
CProber=8pF
C2N7002=44pF (measured)
Operating Waveforms (Cont.)
(Refer to the typical application circuit, VBIAS=VIN=+12V supplied by an ATX Power Supply)
7. Short-Circuit Test
Ch1 : VOUT, 1V/Div, DC
Time : 5ms/DivCh2 : IL, 10A/Div, DC
BW = 20 MHz
11
22
VOUT
IL
UVP
OCP OCP OCP OCP
Shorted by a wire
6. OCSET Voltage RC Delay
Ch1 : VOCSET, 0.5V/Div, DC
Time : 2µS/Div
Ch2 : IL, 10A/Div, DC
BW = 20 MHz
IL
VOCSET
OCPOCP
1,21,2
Connecting a shutdown MOSFET
(APM2322) at OCSET Pin
CProber=8pF
CAPM2322=89pF (measured)
Copyright ANPEC Electronics Corp.
Rev. A.3 - Nov., 2009
APW7120A
www.anpec.com.tw10
Pin Description
PIN
NO. NAME FUNCTION
1 BOOT This pin provides ground referenced bias voltage to the high-
side MOSFET driver. A bootstrap circuit with
a diode connected to 5~12V is used to create a voltage suitable to drive a logic-level N-channel MOSFET.
2 UGATE Connect this pin to the high-side N-channel MOSFET gate. This pin provides gate drive for the high-side
MOSFET.
3 GND The GND terminal provides return path for the IC bias current and the low-side MOSFET driver pull-
low
current. Connect the pin to the system ground via very low impedance layout on PCBs.
4 LGATE Connect this pin to the low-side N-channel MOSFET gate. This pin provides gate drive for the low-
side
MOSFET.
5 VCC Connect this pin to a 5~12V supply voltage. This pin provides bias supply for the co
ntrol circuitry and the
low-side MOSFET driver. The voltage at this pin is monitored for the Power-On-Reset (POR) purpose.
6 FB
This pin is the inverting input of the internal Gm amplifier. Connect this pin to the output (VOUT
) of the
converter via an external resistor divider for closed-
loop operation. The output voltage set by the resistor
divider is determined using the following formula:
(V) )
R2
R1
1 (0.8VVOUT +⋅=
where R1 is the resistor connected from VOUT to FB , and R2 is the resistor connected from F
B to GND.
The FB pin is also monitored for under and over-voltage events.
7 OCSET
The OCSET is a dual-function input pin for over-
current protection and shutdown control. Connect a
resistor (ROCSET) from this pin to the Drain of the low-side MOSFET. This resistor, an internal 40µ
A current
source (IOCSET), and the MOSFET on-resistance (RDSON) set the converter over-current trip level (IPEAK
)
according to the following formula:
(A)
R0.4V-RA40
IDSON
OCSET
PEAK ⋅
=µ
Pulling and holding this pin below 0.15V with an open dra
in device, with very low parasitic capacitor, shuts
down the IC with floating output and also resets the over-
current counter. Releasing OCSET pin initiates a
new soft-start and the converter works again.
8 PHASE
The pin provides return path for the high-side MOSFET driver pull-
low current. Connect this pin to the
high-side MOSFET source.
Copyright ANPEC Electronics Corp.
Rev. A.3 - Nov., 2009
APW7120A
www.anpec.com.tw11
Block Diagram
Typical Application Circuit
C3, C4 : 820µF/16V , ESR=25mΩ
C6, C7 : 1000µF/6.3V, ESR=30mΩ
VCC
Power-On-
Reset
VCC
OCSET
UGATE
LGATE
Oscillator
Gate
Control
VREF
0.8V
Soft-Start
and Fault
Logic
FOSC
300kHz
PHASE
Gm
Amplifier
FB PWM
Inhibit
40µA
COMP
67%VREF UV
GND
POR
Soft-Start
OC
BOOT
Regulator
3VCC
OV
118%VREF
3VCC
0.4V
0.15V
Enable
2.5V
VIN
+5/12V
VOUT
1.8V/15A
C5
1µFC3, C4
820µF x2
C6, C7
1000µF x2
L2
1.5µH
Q1
APM2512
UGATE
LGATE 4
BOOT
1
GND
3
VCC
5PHASE 8
Q2
APM2512
C1
1µF
2
U1
APW7120A
FB
6
OCSET 7
R2
1.2k
C2
0.1µF
Q3
2N7002
Shutdown
R4
2.2
L1
1µH
R5
+5V/12V
C8
0.1µF
R1
1.5k
R3
200
D1
1N4148
VBIAS
Copyright ANPEC Electronics Corp.
Rev. A.3 - Nov., 2009
APW7120A
www.anpec.com.tw12
Function Description
Power-On-Reset (POR)
The APW7120A monitors the VCC voltage (VCC) for Power-
On-Reset function, preventing wrong logic operation dur-
ing powering on. When the VCC voltage is ready, the
APW7120A starts a start-up process and then ramps the
output voltage up to the target voltage.
Soft-Start
The APW7120A has a built-in digital soft-start to control
the output voltage rise and limit the current surge at the
start-up. During soft-start, an internal ramp connected to
the one of the positive inputs of the Gm amplifier rises up
from 0V to 2V to replace the reference voltage (0.8V) until
the ramp voltage reaches the reference voltage. The soft-
start interval is about 3.2ms typical, independent of the
converter’s input and output voltages.
Over-Current Protection (OCP)
The over-current function protects the switching converter
against over-current or short-circuit conditions. The con-
troller senses the inductor current by detecting the drain-
to-source voltage, product of the inductor’s current and
the on-resistance, of the low-side MOSFET during it’s on-
state. This method enhances the converter’s efficiency
and reduces cost by eliminating a current sensing
resistor.
A resistor (ROCSET), connected from the OCSET to the low-
side MOSFET’s drain, programs the over-current trip level.
An internal 40µA (typical) current source flowing through
the ROCSET develops a voltage (VROCSET) across the ROCSET.
When the VOCSET (VROCSET+ VDS of the low-side MOSFET) is
less than the internal over-current reference voltage (0.
4V, typical), the IC shuts off the converter and then ini-
tiates a new soft-start process. After 4 over-current events
are counted, the device turns off both high-side and low-
side MOSFETs and the converter’s output is latched to be
floating.
Please pay attention to the RC delay effect. It causes
the OCP trip level to be the function of the operating
duty. The parasitic capacitance (including the capacitance
inside the OCSET, external PCB trace capacitance and
the COSS of the shutdown MOSFET) must be minimized,
especially selecting a shutdown MOSFET with very small
COSS. The OCP trip level follows the duty to increase a little
at low operating duty, but very much at high operating
duty, like the RC delay curve. Due to load regulation or
current-limit, heavy load normally reduces converter’s
input voltage and increases the power loses. During heavy
load, the APW7120A regulates the output voltage by ex-
pending the duty. This rises up the OCP trip level at the
same time.
Under-Voltage Protection (UVP)
The under-voltage function monitors the FB voltage (VFB)
to protect the converter against short-circuit conditions.
When the VFB falls below the falling UVP threshold (67%
VREF), the APW7120A shuts off the converter. After a pre-
ceding delay, which starts at the beginning of the under-
voltage shutdown, the APW7120A initiates a new soft-
start to resume regulating. The under-voltage protection
shuts off and then re-starts the converter repeatedly with-
out latching. The function is disabled during soft-start
process.
Over-Voltage Protection (OVP)
The over-voltage protection monitors the FB voltage to
prevent the output from over-voltage. When the output
voltage rises to 118% of the nominal output voltage, the
APW7120A turns on the low-side MOSFET until the out-
put voltage falls below the OVP threshold, regulating the
output voltage around the OVP thresholds.
Adaptive Shoot-Through Protection
The gate driver incorporates adaptive shoot-through pro-
tection to high-side and low-side MOSFETs from con-
ducting simultaneously and shorting the input supply. This
is accomplished by ensuring the falling gate has turned
off one MOSFET before the other is allowed to rise.
During turn-off of the low-side MOSFET, the LGATE volt-
age is monitored until it reaches a 1.5V threshold, at which
time the UGATE is released to rise after a constant delay.
During turn-off of the high-side MOSFET, the UGATE-to-
PHASE voltage is also monitored until it reaches a 1.5V
threshold, at which time the LGATE is released to rise
after a constant delay.
Copyright ANPEC Electronics Corp.
Rev. A.3 - Nov., 2009
APW7120A
www.anpec.com.tw13
Function Description (Cont.)
Shutdown Control
Pulling the OCSET voltage below 0.15V by an open drain
transistor, shown in typical application circuit, shuts down
the APW7120A PWM controller. In shutdown mode, the
UGATE and LGATE are pulled to PHASE and GND
respectively, the output is floating.
Copyright ANPEC Electronics Corp.
Rev. A.3 - Nov., 2009
APW7120A
www.anpec.com.tw14
Application Information
For a through hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid tanta-
lum capacitors can be used, but caution must be exer-
cised with regard to the capacitor surge current rating.
Input Capacitor Selection
Use small ceramic capacitors for high frequency
decoupling and bulk capacitors to supply the surge cur-
rent needed each time high-side MOSFET(Q1) turns on.
Place the small ceramic capacitors physically close to the
MOSFETs and between the drain of Q1 and the source of
low-side MOSFET(Q2).
The important parameters for the bulk input capacitor are
the voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and cur-
rent ratings above the maximum input voltage and larg-
est RMS current required by the circuit. The capacitor volt-
age rating should be at least 1.25 times greater than the
maximum input voltage and a voltage rating of 1.5 times
is a conservative guideline. The RMS current of the bulk
input capacitor is calculated as the following equation :
VIN
VOUT
CIN
COUT
L
Q1
UGATE
Q2
LGATE
ESR
ILIOUT
IQ1
ICOUT
IOUT
VUGATE
T=1/FOSC
IL
IQ1
ICOUT
IOUT
I
I
VOUT
DT
VOUT
Figure 1. Buck Converter Waveforms
Output Capacitor Selection
An output capacitor is required to filter the output and sup-
ply the load transient current. The filtering requirements
are a function of the switching frequency and the ripple
current. The output ripple is the sum of the voltages, hav-
ing phase shift, across the ESR and the ideal output
capacitor. The peak-to-peak voltage of the ESR is calcu-
lated as the following equations :
..(3).......... (V) ESRI V
.(2).......... (A)
LFD)-(1V
I
(1) ........... (V) VDV
ESR
OSC
OUT
INOUT
⋅∆=⋅
⋅
=∆
⋅
=
The peak-to-peak voltage of the ideal output capacitor is
calculated as the following equation :
(4) ....... (V)
CF8I
VOUTOSC
COUT ⋅⋅ ∆
=∆
For general applications using bulk capacitors, the ∆VCOUT
is much smaller than the VESR and can be ignored.
Therefore, the AC peak-to-peak output voltage is shown
below:
.(5).......... (V) ESRI VOUT ⋅∆=∆
The load transient requirements are the function of the
slew rate (di/dt) and the magnitude of the transient load
current. These requirements are generally met with a
mix of capacitors and careful layout. Modern components
and loads are capable of producing transient load rates
(A) D)-(1DI IOUTRMS ⋅⋅=
Copyright ANPEC Electronics Corp.
Rev. A.3 - Nov., 2009
APW7120A
www.anpec.com.tw15
Application Information (Cont.)
Output Capacitor Selection (Cont.)
The response time to a transient is different for the appli-
cation of load and the removal of load. The following equa-
above 1A/ns. High frequency capacitors initially supply
the transient and slow the current load rate seen by the
bulk capacitors. The bulk filter capacitor values are gener-
ally determined by the ESR (Effective Series Resistance)
and voltage rating requirements rather than actual ca-
pacitance requirements.
High frequency decoupling capacitors should be placed
as close to the power pins of the load as physically
possible. Be careful not to add inductance in the circuit
board wiring that could cancel the usefulness of these
low inductance components.
An aluminum electrolytic capacitor’s ESR value is related
to the case size with lower ESR available in larger case
sizes. However, the Equivalent Series Inductance (ESL)
of these capacitors increases with case size and can re-
duce the usefulness of the capacitor to high slew-rate
transient loading. In most cases, multiple electrolytic ca-
pacitors of small case size perform better than a single
large case capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s re-
sponse time to the load transient. The inductor value de-
termines the converter’s ripple current and the ripple
voltage, see equations (2) and (5). Increasing the value of
inductance reduces the ripple current and voltage.
However, the large inductance values reduce the
converter’s response time to a load transient.
One of the parameters limiting the converter’s response
to a load transient is the time required to change the in-
ductor current. Given a sufficiently fast control loop design,
the APW7120A will provide either 0% or 85%(Average)
duty cycle in response to a load transient. The response
time is the time required to slew the inductor current from
an initial current value to the transient current level. Dur-
ing this interval the difference between the inductor cur-
rent and the transient current level must be supplied by
the output capacitor. Minimizing the response time can
minimize the output capacitance required.
VIL
t ,
VV IL
tOUT
TRAN
FALL
OUTIN
TRAN
RISE ⋅
=
−
⋅
=
where
ITRAN is the transient load current step, tRISE is the response
time to the application of load, and tFALL is the response
time to the removal of load. The worst case response
time can be either at the application or removal of load.
Be sure to check both of these equations at the transient
load current. These requirements are minimum and
maximum output levels for the worst case response time.
MOSFET Selection
In high-current applications, the MOSFET power
dissipation, package selection and heatsink are the domi-
nant design factors. The power dissipation includes two
loss components, conduction loss and switching loss.
The conduction losses are the largest component of
power dissipation for both the high-side and the low-side
MOSFETs. These losses are distributed between the two
MOSFETs according to duty factor (see the equations
below). Only the high-side MOSFET has switching losses,
since the low-side MOSFETs body diode or an external
Schottky rectifier across the lower MOSFET clamps the
switching node before the synchronous rectifier turns on.
These equations assume linear voltage-current transi-
tions and do not adequately model power loss due the
reverse-recovery of the low-side MOSFET’s body diode.
The gate-charge losses are dissipated by the APW7120A
and don’t heat the MOSFETs. However, large gate-charge
increases the switching interval, tSW which increases the
high-side MOSFET switching losses. Ensure that both
MOSFETs are within their maximum junction tempera-
ture at high ambient temperature by calculating the tem-
perature rise according to package thermal-resistance
specifications. A separate heatsink may be necessary
depending upon MOSFET power, package type, ambient
temperature and air flow.
D)-(1RIP
FtVI
2
1
DRIP
DSON
2
OUTSide-Low
OSCSWINOUTDSON
2
OUTSide-High
⋅⋅=
⋅⋅⋅⋅+⋅⋅=
tions give the approximate response time interval for ap-
plication and removal of a transient load:
Where
tSW is the switching interval
Copyright ANPEC Electronics Corp.
Rev. A.3 - Nov., 2009
APW7120A
www.anpec.com.tw16
Application Information (Cont.)
Feedback Compensation
The figure 2 shows the control system of the APW7120,
which consists of an internal voltage-mode PWM
modulator, an output L-C filter, a resistor-divider and an
internal compensation network. The R and C are the
equivalent series resistance (ESR) and capacitance of
the output capacitor; the L is the inductance of the output
inductor.
Figure 2. APW7120 Control System
The transfer functions are defined as following:
R2R1
R2
(S)V(S)V
A1(S) O
FB +
==
on)Compensati (Internal
(S)V(S)V
A2(S) FB
COMP
=
V
V
(S)V(S)V
A3(S) OSC
IN
COMP
PHASE ∆
==
1SCRSCL1SCR
(S)V(S)V
A4(S) 2
PHASE
OUT +⋅⋅+⋅⋅ +⋅⋅
==
OUT
CL O
FBCOMPPHASEOUT
OFBCOMPPHASE
V(S)
A(S) V(S)
V(S)V(S)V(S)V(S)
V(S)V(S)V(S)V(S)
A1(S)A2(S)A3(S)A4(S)
=
=⋅⋅⋅
=⋅⋅⋅
where A1(S) is the transfer function of the resistor-divider,
A2(S) is the transfer function of the feedback compensa-
tion network, A3(S) is the transfer function of the PWM
modulator, A4(S) is the transfer function of the output LC
filter, and ACL(S) is the transfer function of the closed-loop
control system. Refer to figure 3. The Pole and Zero fre-
)(F 0.4kHzFZZA21 =
)(F 430kHzFP2PA21 =
LCx2
1
FPA41,2 π
=
xRxC21
FZA41 π
=
R2
R1
VOUT
APW7120
VFB
R
C
0.8V
FB
VO
L
VOSC=1.6V
Driver
VPHASE
VIN
VCOMP
Internal
Compensation
Network
UGATE
LGATE
where the FPA21 (or FP2) and FZA21 (or Fz) are the Pole and
Zero frequencies of the A2(S), the FPA41,2 and FZA41 are the
double-Pole and Zero frequencies of the A4(S), the VIN is
the input voltage of the PWM converter and the load resis-
tance of the converter is very large. For good converter
stability, the values of the L, C, and R must be selected to
meet the following criteria:
1. Make sure the double-pole frequency (FPA41,2) of the
output filter is bigger than the zero frequency (FZA21) of
the internal compensation network.
2. The following equation must be true:
01.2)
C
L
R
1
log(2)
R2R1
R2
log()
V
V
log( OSC
IN >+⋅⋅−
+
+
∆
3. The converter crossover frequency (FCO) must be in the
range of 10%~30% of minimum FOSC of the converter.
The FCO is calculated by using the following equations:
72)
C
L
R
1
log(40
)
R2R1R2
log(20)
V
V
log(20F at Gain OSC
IN
ZA41
+⋅⋅−
+
⋅+
∆
⋅=
OSC_MINZA41
20
FZA41 at Gain
COOSC_MIN F 30% F10FF 10% ≤
⋅=≤
4. The values of L, C, and R selected must meet the
equations above over the operaing temperature,
voltage, and current ranges.
quencies of the A1(S), A2(S), A3(S), and ACL(S) are shown
or calculated as the following equations:
Copyright ANPEC Electronics Corp.
Rev. A.3 - Nov., 2009
APW7120A
www.anpec.com.tw17
Application Information (Cont.)
Feedback Compensation (Cont.)
Layout Consideration
In high power switching regulator, a correct layout is im-
portant to ensure proper operation of the regulator.
In general, interconnecting impedances should be mini-
mized by using short, wide printed circuit traces. Signal
and power grounds are to be kept separate and finally
combined using ground plane construction or single point
grounding. Figure 4 illustrates the layout, with bold lines
indicating high current paths. Components along the bold
lines should be placed close together. Below is a check-
list for your layout:
1. Begin the layout by placing the power components first.
Orient the power circuitry to chieve a clean power flow
path. If possible, make all the connections on one side
of the PCB with wide, copper filled areas.
2. Connect the ground of feedback divider directly to the
GND pin of the IC using a dedicated ground trace.
3. The VCC decoupling capacitor should be right next to
the VCC and GND pins. Capacitor CBOOT should be con-
nected as close to the BOOT and PHASE pins as
possible.
4. Minimize the length and increase the width of the trace
between UGATE/LGATE and the gates of the MOSFETs
to reduce the impedance driving the MOSFETs.
5. Use an dedicated trace to connect the ROCSET and the
Drain pad of the low-side MOSFET, Kevin connection,
for accurate current sensing.
Figure 3. Converter Gain vs. Frequency
6. Keep the switching nodes (UGATE, LGATE, and PHASE)
away from sensitive small signal nodes since these
nodes are fast moving signals. Therefore, keep traces
to these nodes as short as possible.
7. Place the decoupling ceramic capacitor CHF near the
Drain of the high-side MOSFET as close as possible.
The bulk capacitors CIN are also placed near the Drain.
8. Place the Source of the high-side MOSFET and the
Drain of the low-side MOSFET as close as possible.
Minimizing the impedance with wide layout plane be-
tween the two pads reduces the voltage bounce of the
node.
9. Use a wide power ground plane, with low impedance,
to connects the CHF, CIN, COUT, Schottky diode and the
Source of the low-side MOSFET to provide a low im-
pedance path between the components for large and
high frequency switching currents.
-60
-40
-20
0
20
40
60
80
100
100 1K 10K 100K 1M 10M
Compensation Gain
Frequency (f, Hz)
Gain (dB)
FZA21
FPA21
Converter Gain
PWM &Filter Gain
FCO
FZA41
FPA41,2
VIN
VOUT
Q1
L1
4
8
2
U
1
1
5
COUT
CIN
+
+
APW7120A
UGATE
LGATE
VCC
PHASE
BOOT
CHF
Q2
Figure 4. Recommended Layout Digram
Copyright ANPEC Electronics Corp.
Rev. A.3 - Nov., 2009
APW7120A
www.anpec.com.tw18
Package Information
SOP-8D
e
E
E1
SEE VIEW A
cb
h X 45
°
A
A1A2
L
VIEW A
0.25
SEATING PLANE
GAUGE PLANE
Note: 1. Follow JEDEC MS-012 AA.
2. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.
3. Dimension “E” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
S
Y
M
B
O
LMIN. MAX.
1.75
0.10
0.17 0.25
0.25
A
A1
c
D
E
E1
e
h
L
MILLIMETERS
b0.31 0.51
SOP-8
0.25 0.50
0.40 1.27
MIN. MAX.
INCHES
0.069
0.004
0.012 0.020
0.007 0.010
0.010 0.020
0.016 0.050
0
0.010
1.27 BSC 0.050 BSC
A2 1.25 0.049
0
°
8
°
0
°
8
°
3.80
5.80
4.80
4.00
6.20
5.00 0.189 0.197
0.228 0.244
0.150 0.157
Copyright ANPEC Electronics Corp.
Rev. A.3 - Nov., 2009
APW7120A
www.anpec.com.tw19
Carrier Tape & Reel Dimensions
H
T1
A
d
A
E1
A
B
W
F
T
P0
OD0
BA0
P2
K0
B0
SECTION B-B
SECTION A-A
OD1
P1
Application
A H T1 C d D W E1 F
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.05
P0 P1 P2 D0 D1 T A0 B0 K0
SOP-8
4.0±0.10
8.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
6.40±0.20
5.20±0.20
2.10±0.20
(mm)
Package Type Unit Quantity
SOP-8 Tape & Reel 2500
Devices Per Unit
Copyright ANPEC Electronics Corp.
Rev. A.3 - Nov., 2009
APW7120A
www.anpec.com.tw20
Taping Direction Information
Classification Profile
SOP-8
USER DIRECTION OF FEED
Copyright ANPEC Electronics Corp.
Rev. A.3 - Nov., 2009
APW7120A
www.anpec.com.tw21
Classification Reflow Profiles
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Average ramp-up rate
(Tsmax to TP) 3 °C/second max. 3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL) 183 °C
60-150 seconds 217 °C
60-150 seconds
Peak package body Temperature
(Tp)* See Classification Temp in table 1 See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc) 20** seconds 30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max. 6 °C/second max.
Time 25°C to peak temperature 6 minutes max. 8 minutes max.
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
350-2000 Volume mm3
>2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
≥2.5 mm 250 °C 245 °C 245 °C
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
≥350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C
Reliability Test Program
Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ 125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
HBM MIL-STD-883-3015.7 VHBM≧2KV
MM JESD-22, A115 VMM≧200V
Latch-Up JESD 78 10ms, 1tr≧100mA
Copyright ANPEC Electronics Corp.
Rev. A.3 - Nov., 2009
APW7120A
www.anpec.com.tw22
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
