[AK4482] AK4482 111dB 192kHz 24-Bit 2ch DAC GENERAL DESCRIPTION The AK4482 is a cost-effective 24-bit DAC for digital audio equipments. The modulator uses AKM's multi-bit architecture, delivering wide dynamic range. The AK4482 has fully differential switched-cap filter outputs, removing the need for AC coupling capacitors and increasing performance for systems with excessive clock jitter. The AK4482 support up to 216kHz sampling rate, ideal for BD and AC-3 amplifier systems. It is housed in a space saving 16pin TSSOP package. FEATURES Sampling Rate: 8kHz 216kHz 128 x Over Sampling (Normal Speed Mode) 64 x Over Sampling (Double Speed Mode) 32 x Over Sampling (Quad Speed Mode) 24 Bit 8 x FIR Digital Filter - High Quality Sound Short Delay Sharp Roll-off Filter (less than 6/fs) - High Quality Sound Short Delay Slow Roll-off Filter (less than 6/fs) - Sharp Roll-off Filter - Slow Roll-off Filter Optimized Layout for Sound Quality SCF Digital De-emphasis (32kHz, 44.1kHz, 48kHz) Soft Mute Digital ATT (256 Steps) Digital I/F Format: 24Bit MSB justified, 24/20/16Bit LSB justified, I2S Master Clock: 256fs, 384fs, 512fs or 768fs (Normal Speed Mode) 128fs, 192fs, 256fs or 384fs (Double Speed Mode) 128fs or 192fs (Quad Speed Mode) THD+N: -100dB Dynamic Range: 111dB High Tolerance to Clock Jitter Power Supply: 4.75 5.25V Package: 16pin TSSOP (6.4mm x 5.0mm) MS1408-E-01 2012/05 -1- [AK4482] MCLK VDD CSN CCLK P Interface De-emphasis Control VSS Clock Divider DZFL CDTI DZFR LRCK BICK SDTI Audio Data Interface 8X Interpolator Modulator SCF 8X Interpolator Modulator SCF AOUTL+ AOUTLAOUTR+ AOUTR- PDN MS1408-E-01 2012/05 -2- [AK4482] Ordering Guide -40 +85C 16pin TSSOP (0.65mm pitch) Evaluation board for AK4482 AK4482VT AKD4482 Pin Layout MCLK 1 16 DZFL BICK 2 15 DZFR SDTI 3 14 VDD LRCK 4 13 VSS PDN 5 12 AOUTL+ CSN 6 11 AOUTL- CCLK 7 10 AOUTR+ CDTI 8 9 AOUTR- Top View PIN/Function No. 1 Pin Name MCLK I/O I Function Master Clock Input Pin An external TTL clock should be input on this pin. 2 BICK I Audio Serial Data Clock Pin 3 SDTI I Audio Serial Data Input Pin 4 LRCK I L/R Clock Pin 5 PDN I Power-Down Mode Pin When at "L", the AK4482 is in the power-down mode and is held in reset. The AK4482 should always be reset upon power-up. 6 CSN I Chip Select Pin 7 CCLK I Control Data Input Pin 8 CDTI I Control Data Input Pin 9 AOUTRO Rch Negative Analog Output Pin 10 AOUTR+ O Rch Positive Analog Output Pin 11 AOUTLO Lch Negative Analog Output Pin 12 AOUTL+ O Lch Positive Analog Output Pin 13 VSS Ground Pin 14 VDD Power Supply Pin 15 DZFR O Rch Data Zero Input Detect Pin 16 DZFL O Lch Data Zero Input Detect Pin Note 1. All input pins must not be left floating. MS1408-E-01 2012/05 -3- [AK4482] ABSOLUTE MAXIMUM RATING (VSS=0V; Note 2) Parameter Power Supply Input Current (any pins except for supplies) Input Voltage Ambient Operating Temperature Storage Temperature Note 2. All voltages with respect to ground. Symbol VDD IIN VIND Ta Tstg min -0.3 -0.3 -40 -65 max 6.0 10 VDD+0.3 85 150 Unit V mA V C C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS=0V; Note 2) Parameter Power Supply Symbol VDD min 4.75 typ 5.0 max 5.25 Unit V * AKM assumes no responsibility for the usage beyond the conditions in this data sheet. MS1408-E-01 2012/05 -4- [AK4482] ANALOG CHARACTERISTICS (Ta = 25C; VDD = 5.0V; fs = 44.1kHz; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input Data; Measurement frequency = 20Hz 20kHz; RL 2k; unless otherwise specified) Parameter min typ max Unit Resolution 24 Bits Dynamic Characteristics (Note 3) THD+N fs=44.1kHz 0dBFS -100 -90 dB BW=20kHz -60dBFS -48 dB fs=96kHz 0dBFS -97 -90 dB BW=40kHz -60dBFS -45 dB fs=192kHz 0dBFS -97 dB BW=40kHz -60dBFS -45 dB Dynamic Range (-60dBFS with A-weighted) (Note 4) 105 111 dB S/N (A-weighted) (Note 5) 105 111 dB Interchannel Isolation (1kHz) 90 110 dB Interchannel Gain Mismatch 0.2 0.5 dB DC Accuracy Gain Drift 100 ppm/C Output Voltage (Note 6) Vpp 2.25 2.4 2.55 Load Resistance (Note 7) 2 k Power Supplies Power Supply Current (VDD) 20 Normal Operation (PDN = "H", fs=44.1kHz) 30 mA 24 Double Operation (PDN = "H", fs=96kHz) 36 mA 30 Quad Operation (PDN = "H", fs=192kHz) 45 mA 10 Power-Down Mode (PDN = "L") (Note 8) 100 A Note 3. Measured by Audio Precision, System Two. Refer to the evaluation board manual. Note 4. 100dB at 16bit data. Note 5. S/N does not depend on input data size. Note 6. Full-scale voltage(0dB). Output voltage scales with the VDD voltage. AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = 2.4VppxVDD/5 Note 7. Regarding Load Resistance, AC load is 4k (min) with a DC cut capacitor. Note 8. All digital input pins including (MCLK, BICK and LRCK) are fixed to VDD or VSS. MS1408-E-01 2012/05 -5- [AK4482] SHARP ROLL-OFF FILTER CHARACTERISTICS (Ta = 25C; VDD = 4.75 5.25V; fs = 44.1kHz; SD = "0"; SLOW = "0") Parameter Symbol min typ max Unit Digital filter PB 0 20.0 kHz Passband 0.05dB (Note 9) 22.05 kHz -6.0dB Stopband (Note 9) SB 24.1 kHz Passband Ripple PR -0.005 dB 0.0001 Stopband Attenuation SA 70 dB Group Delay (Note 10) GD 27 1/fs Digital Filter + SCF Frequency Response 20.0kHz fs=44.1kHz FR -0.2/+0.2 dB 40.0kHz fs=96kHz FR -0.3/+0.3 dB 80.0kHz fs=192kHz FR -1/+0.1 dB Note 9. The passband and stopband frequencies scale with fs (system sampling rate). For example, PB=0.4535xfs (@0.05dB), SB=0.546xfs. Note 10. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data of both channels to input register to the output of analog signal. SLOW ROLL-OFF FILTER CHARACTERISTICS (Ta = 25C; VDD = 4.75~5.25V; fs = 44.1kHz; SD = "0"; SLOW = "1") Parameter Symbol min PB 0 39.2 -0.07 72 - typ max Unit 18.2 8.1 - - kHz kHz kHz dB dB 1/fs - dB dB dB Digital Filter Passband 0.04dB -3.0dB Stopband Passband Ripple Stopband Attenuation Group Delay (Note 11) (Note 11) (Note 10) SB PR SA GD +0.02 27 Digital Filter + SCF FR -5/+0.1 20.0kHz fs=44.kHz fs=96kHz 40.0kHz FR -4/+0.1 80.0kHz fs=192kHz FR -5/+0.1 Note 11. The passband and stopband frequencies scale with fs (system sampling rate). For example, PB=0.185xfs (@0.04dB), SB=0.888xfs. Frequency Response MS1408-E-01 2012/05 -6- [AK4482] SHORT DELAY SHARP ROLL-OFF FILTER CHARACTERISTICS (Ta = 25C; VDD = 4.75 5.25V; fs = 44.1kHz; SD = "1"; SLOW = "0") Parameter Symbol min typ max Unit Digital filter PB 0 20.0 kHz Passband 0.05dB (Note 9) 22.05 kHz -6.0dB Stopband (Note 9) SB 24.1 kHz Passband Ripple PR -0.0080 +0.0016 dB Stopband Attenuation SA 56.5 dB Group Delay (Note 10) GD 6 1/fs Digital Filter + SCF Frequency Response 20.0kHz fs=44.1kHz FR -0.2/+0.2 dB 40.0kHz fs=96kHz FR -0.3/+0.3 dB 80.0kHz fs=192kHz FR -1/+0.1 dB Note 9. The passband and stopband frequencies scale with fs (system sampling rate). For example, PB=0.4535xfs (@0.05dB), SB=0.546xfs. Note 10. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data of both channels to input register to the output of analog signal. SHORT DELAY SLOW ROLL-OFF FILTER CHARACTERISTICS (Ta = 25C; VDD = 4.75~5.25V; fs = 44.1kHz; SD = "1"; SLOW = "1") Parameter Symbol min (Note 11) PB (Note 11) SB PR SA GD 0 39.2 0.00 62.4 - typ max Unit 18.2 8.1 - - kHz kHz kHz dB dB 1/fs - dB dB dB max 0.8 0.4 10 Unit V V V V A Digital Filter Passband 0.04dB -3.0dB Stopband Passband Ripple Stopband Attenuation Group Delay (Note 10) 0.02 5 Digital Filter + SCF FR +0.1/-5 20.0kHz fs=44.kHz 40.0kHz fs=96kHz FR +0.1/-4 80.0kHz fs=192kHz FR +0.1/-5 Note 11. The passband and stopband frequencies scale with fs (system sampling rate). For example, PB=0.185xfs (@0.04dB), SB=0.888xfs. Frequency Response DC CHARACTERISTICS (Ta = 25C; VDD = 4.75 5.25V) Parameter Symbol min High-Level Input Voltage VIH 2.2 Low-Level Input Voltage VIL High-Level Output Voltage (Iout = -80A) VOH VDD-0.4 Low-Level Output Voltage (Iout = 80A) VOL Input Leakage Current Iin - MS1408-E-01 typ - 2012/05 -7- [AK4482] SWITCHING CHARACTERISTICS (Ta = 25C; VDD = 4.75 5.25V; CL = 20pF) Parameter Symbol min typ fCLK 2.048 11.2896 Master Clock Frequency Duty Cycle dCLK 40 LRCK Frequency 8 fsn Normal Speed Mode 60 fsd Double Speed Mode 120 fsq Quad Speed Mode 45 Duty Duty Cycle Audio Interface Timing BICK Period Normal Speed Mode tBCK 1/128fs Double/Quad Speed Mode tBCK 1/64fs BICK Pulse Width Low tBCKL 30 Pulse Width High tBCKH 30 tBLR 20 BICK "" to LRCK Edge (Note 12) tLRB 20 LRCK Edge to BICK "" (Note 12) tSDH 20 SDTI Hold Time tSDS 20 SDTI Setup Time Control Interface Timing CCLK Period tCCK 200 CCLK Pulse Width Low tCCKL 80 Pulse Width High tCCKH 80 CDTI Setup Time tCDS 40 CDTI Hold Time tCDH 40 CSN High Time tCSW 150 tCSS 50 CSN "" to CCLK "" tCSH 50 CCLK "" to CSN "" Reset Timing tPD 150 PDN Pulse Width (Note 13) Note 12. BICK rising edge must not occur at the same time as LRCK edge. Note 13. The AK4480 can be reset by bringing the PDN pin "L" to "H" upon power-up. MS1408-E-01 max 41.472 60 Unit MHz % 54 108 216 55 kHz kHz kHz % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2012/05 -8- [AK4482] Timing Diagram 1/fCLK VIH MCLK VIL tCLKH tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tSDS tSDH VIH SDTI VIL Serial Interface Timing MS1408-E-01 2012/05 -9- [AK4482] VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS C1 CDTI tCDH C0 R/W VIH A4 VIL WRITE Command Input Timing tCSW VIH CSN VIL tCSH VIH CCLK CDTI VIL D3 D2 D1 D0 VIH VIL WRITE Data Input Timing tPD PDN VIL Power-down Timing MS1408-E-01 2012/05 - 10 - [AK4482] OPERATION OVERVIEW System Clock The external clocks, which are required to operate the AK4482, are MCLK, BICK and LRCK. MCLK should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the delta-sigma modulator. There are two modes for setting MCLK frequency, Manual Setting Mode and Auto Setting Mode. In manual setting mode (ACKS bit = "0": Register 00H), sampling speed is set by DFS1-0 bits (Table 1) and the MCLK frequency in each speed mode is set automatically (Table 2~Table 4). The AK4482 is in auto setting mode when a reset is released (PDN = ""). In auto setting mode, sampling speed and MCLK frequency are detected automatically (Table 5). Then the initial master clock is set to the appropriate frequency (Table 6) so that DIF1-0 bits setting are not necessary. The AK4482 is automatically placed in power saving mode when MCLK or LRCK is stopped during normal operation, and the analog output goes to AVDD/2 (typ). When MCLK and LRCK are input again, the AK4482 is powered up. After exiting reset following power-up, the AK4482 is not fully operational until MCLK and LRCK are input. DFS1 bit DFS0 bit Sampling Rate (fs) 0 0 Normal Speed Mode 8kHz~54kHz 0 1 Double Speed Mode 60kHz~108kHz 1 0 Quad Speed Mode 120kHz~216kHz (default) Table 1. Sampling Speed (Manual Setting Mode) LRCK fs 32.0kHz 44.1kHz 48.0kHz 256fs 8.1920MHz 11.2896MHz 12.2880MHz MCLK 384fs 512fs 12.2880MHz 16.3840MHz 16.9344MHz 22.5792MHz 18.4320MHz 24.5760MHz 768fs 24.5760MHz 33.8688MHz 36.8640MHz BICK 64fs 2.0480MHz 2.8224MHz 3.0720MHz Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode) LRCK fs 88.2kHz 96.0kHz 128fs 11.2896MHz 12.2880MHz MCLK 192fs 256fs 16.9344MHz 22.5792MHz 18.4320MHz 24.5760MHz 384fs 33.8688MHz 36.8640MHz BICK 64fs 5.6448MHz 6.1440MHz Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode) LRCK fs 176.4kHz 192.0kHz MCLK 128fs 192fs 22.5792MHz 33.8688MHz 24.5760MHz 36.8640MHz BICK 64fs 11.2896MHz 12.2880MHz Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode) MS1408-E-01 2012/05 - 11 - [AK4482] MCLK 512fs 768fs 256fs 384fs 128fs 192fs Sampling Speed Normal Double Quad Table 5. Sampling Speed (Auto Setting Mode: Default) LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz 128fs 22.5792 24.5760 192fs 33.8688 36.8640 MCLK (MHz) 256fs 384fs 22.5792 33.8688 24.5760 36.8640 - 512fs 16.3840 22.5792 24.5760 - 768fs 24.5760 33.8688 36.8640 - Sampling Speed Normal Double Quad Table 6. System Clock Example (Auto Setting Mode) Audio Serial Interface Format Data is shifted in via the SDTI pin using BICK and LRCK inputs. Five data formats are supported and selected by the DIF2-0 bits as shown in Table 7. In all formats the serial data is MSB-first, 2's compliment format and is latched on the rising edge of BICK. Mode 2 can be used for 20-bit and 16-bit MSB justified formats by zeroing the unused LSBs. Mode 0 1 2 3 4 DIF2 bit 0 0 0 0 1 DIF1 bit 0 0 1 1 0 DIF0 bit 0 1 0 1 0 SDTI Format 16bit LSB justified 20bit LSB justified 24bit MSB justified 24bit I2S Compliment 24bit LSB justified BICK 32fs 40fs 48fs 48fs 48fs Figure Figure 1 Figure 2 Figure 3 Figure 4 Figure 2 (default) Table 7. Audio Data Format MS1408-E-01 2012/05 - 12 - [AK4482] LRCK 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 BICK (32fs) SDTI Mode 0 15 14 6 1 0 5 14 4 15 3 16 2 1 17 0 31 15 0 14 6 5 14 1 4 15 3 16 2 1 17 0 31 15 14 0 1 0 1 0 1 BICK (64fs) SDTI Mode 0 Don't care 15 14 Don't care 0 15 14 0 15:MSB, 0:LSB Lch Data Rch Data Figure 1. Mode 0 Timing LRCK 0 1 8 9 10 11 12 31 0 1 8 9 10 11 12 31 BICK (64fs) SDTI Mode 1 Don't care 19 0 Don't care 19 0 Don't care 19 0 19 0 19:MSB, 0:LSB SDTI Mode 4 Don't care 23 22 21 20 23 22 20 21 23:MSB, 0:LSB Lch Data Rch Data Figure 2. Mode 1, 4 Timing LRCK 0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 BICK (64fs) SDTI 23 22 1 0 Don't care 23 22 1 0 Don't care 23 22 23:MSB, 0:LSB Lch Data Rch Data Figure 3. Mode 2 Timing MS1408-E-01 2012/05 - 13 - [AK4482] LRCK 0 1 2 3 23 24 25 31 0 1 2 3 23 24 25 31 0 1 BICK (64fs) SDTI 0 1 23 22 Don't care 23 22 1 0 Don't care 23 23:MSB, 0:LSB Lch Data Rch Data Figure 4. Mode 3 Timing De-emphasis Filter A digital de-emphasis filter is available for 32kHz, 44.1kHz or 48kHz sampling rates (tc = 50/15s). It is enabled and disabled with DEM1-0 bits. In double speed mode and quad speed mode, the digital de-emphasis filter is off. DEM1 bit DEM0 bit Mode 0 0 1 1 0 1 0 1 44.1kHz OFF 48kHz 32kHz (default) Table 8. De-emphasis Filter Control (Normal Speed Mode) Output Volume The AK4482 includes channel independent digital output volume control (ATT) with 256 levels at linear step including MUTE. This volume control is in front of the DAC and it can attenuate the input data from 0dB to -48dB and mute. When changing output levels, transitions are executed in soft change; thus no switching noise occurs during these transitions. Transition times when changing one level and all levels are shown below. Sampling Speed Normal Speed Mode Double Speed Mode Quad Speed Mode Transition Time 1 Level 256 to 0 4LRCK 1020LRCK 8LRCK 2040LRCK 16LRCK 4080LRCK Table 9. ATT Transition Time Zero Detection The AK4482 has channel-independent zero detect function. When the input data at each channel is continuously zeros for 8192 LRCK cycles, the DZF pin of each channel goes to "H". The DZF pin of each channel immediately returns to "L" if the input data of each channel is not zero after becoming "H". When the RSTN bit is "0", the DZF pins of both channels become "H". The DZF pins of both channels become "L" in 4 ~ 5/fs if the input data are not "0" after RSTN bit returns to "1". The DZF pins of both channels go to "H" only if the input data for both channels are continuously zeros for 8192 LRCK cycles when DZFM bit is set to "1". The zero detect function can be disabled by setting the DZFE bit. In this case, DZF pins of both channels are always "L". The DZFB bit can invert the polarity of the DZF pin. MS1408-E-01 2012/05 - 14 - [AK4482] Soft Mute Operation The soft mute operation is performed at digital domain. When the SMUTE bit set to "1", the output signal is attenuated by - during ATT_DATA x ATT transition time (Table 9) from the current ATT level. When the SMUTE bit is returned to "0", the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA x ATT transition time. If the soft mute is cancelled before attenuating - after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission. SMUTE bit ATT Level (1) (1) (3) Attenuation - GD (2) GD AOUT DZF pin (4) 8192/fs Note: (1) ATT_DATA x ATT transition time (Table 9). For example, this time is 1020LRCK cycles (1020/fs) at ATT_DATA=255 in Normal Speed Mode. (2) The analog output corresponding to the digital input has group delay (GD). (3) If the soft mute is cancelled before attenuating - after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. (4) When the input data for each channel is continuously zeros for 8192 LRCK cycles, the DZF pin for each channel goes to "H". The DZF pin immediately returns to "L" if input data are not zero. Figure 5. Soft Mute and Zero Detection Function System Reset The AK4482 should be reset once by bringing the PDN pin = "L" upon power-up. The reset and power-down mode are released by MCLK input, and the internal timing starts clocking by a rising edged of LRCK after exiting the power down mode by MCLK. The AK4482 is in power-down state until MCLK and LRCK are input. MS1408-E-01 2012/05 - 15 - [AK4482] Power ON/OFF Timing The AK4482 is placed in power-down mode by bringing the PDN pin "L" and the registers are initialized. The analog outputs are floating (Hi-Z). As some click noise occurs at the edge of the PDN signal, the analog output should be muted externally if the click noise influences system application. The AK4482 can be reset by setting RSTN bit to "0". In this case, the registers are not initialized and the corresponding analog outputs become 2.3V(@VDD=5V) (typ). As some click noise occurs at the edge of RSTN signal, the analog output should be muted externally if the click noise influences system application. VDD pin PDN pin (1) Internal State Normal Operation DAC In (Digital) "0"data "0"data GD DAC Out (Analog) (3) Reset (2) (4) GD (3) (4) (5) Clock In MCLK,LRCK,BICK Don't care Don't care (7) DZFL/DZFR External Mute (6) Mute ON Mute ON Notes: (1) After VDD is powered-up, the PDN pin should be "L" for 150ns. (2) The analog output corresponding to digital input has group delay (GD). (3) Analog outputs are floating (Hi-Z) in power-down mode. (4) Click noise occurs at the edge of PDN signal. This noise is output even if "0" data is input. (5) MCLK, BICK and LRCK clocks can be stopped in power-down mode (PDN pin= "L"). (6) Mute the analog output externally if click noise (4) adversely affect system performance The timing example is shown in this figure. (7) DZFL/R pins are "L" in the power-down mode (PDN pin = "L"). Figure 6. Power-down/up Sequence Example MS1408-E-01 2012/05 - 16 - [AK4482] Reset Function (1) RESET by RSTN bit = "0" When RSTN bit = "0", the AK4482's digital section is powered down but the internal register values are not initialized. The analog outputs become VCML/R voltage and DZF pins of both L and R channels become "H". Figure 7 shows the example of reset by RSTN bit. RSTN bit 3~4/fs (5) 2~3/fs (5) Internal RSTN bit Internal State Normal Operation P D/A In (Digital) d "0 " data (1) D/A Out (Analog) Normal O peration D igital Block GD GD (3) (2) (3) (1) 2/ fs(4) DZF (6) Note: (1) The analog output corresponding to digital input has group delay (GD). (2) The analog outputs are 2.3V(@VDD=5.0 typ.) when RSTN bit = "0". (3) Click noise occurs at the edges (" ") of the internal timing of RSTN bit. This noise is output even if "0" data is input. (4) The DZF pins become "H" when the RSTN bit is set to "0", and return to "L" in 2/fs after the RSTN bit is changed to "1". (5) There is a delay, 3 ~ 4/fs from RSTN bit "0" to the internal RSTN bit "0", and 2 ~ 3/fs from RSTN bit "1" to the internal RSTN bit "1". (6) Mute the analog output externally if click noise (3) or Hi-z output (2) influences system applications. The timing example is shown in this figure. Figure 7. Reset Timing Example MS1408-E-01 2012/05 - 17 - [AK4482] (2) RESET by MCLK or LRCK/WCK stop The AK4482 is automatically placed in reset state when MCLK or LRCK is stopped during PCM mode (RSTN pin ="H"), and the analog outputs become floating (Hi-z). When MCLK and LRCK are input again, the AK4482 exit reset state and starts the operation. Zero detect function is not available when MCLK or LRCK is stopped. VDD pin PDN pin (1) Internal State Power-down D/A In (Digital) Power-down Normal Operation Normal Operation (3) GD D/A Out (Analog) Digital Circuit Power-down (2) GD (4) Hi-Z (5) (2) (4) (4) (5) Clock In MCLK, LRCK Stop MCLK, LRCK External MUTE (6) (6) (6) Notes: (1) After VDD is powered-up, the PDN pin should be "L" for 150ns. (2) The analog output corresponding to digital input has group delay (GD). (3) The digital data can be stopped. Click noise after MCLK or LRCK is input again can be reduced by inputting "0" data during this period. (4) Click noise occurs within 3 4LRCK cycles from rising edge ( ) of PDN signal or MCLK inputs. This noise is output even if "0" data is input. (5) MCLK, BICK and LRCK clocks can be stopped in reset mode (MCLK or LRCK stopped). (6) Mute the analog output externally if click noise (4) influences system applications. The timing example is shown in this figure. Figure 8. Reset Timing Example 2 MS1408-E-01 2012/05 - 18 - [AK4482] Mode Control Interface Functions of the AK4482 can be controlled by registers. Internal registers may be written to through3-wire P interface pins: CSN, CCLK and CDTI. The data on this interface consists of Chip address (2-bits, C1/0, fixed to "01"), Read/Write (1-bit; fixed to "1"), Register address (MSB first, 5-bits) and Control data (MSB first, 8-bits). The AK4482 latches the data on the rising edge of CCLK, so data should be clocked in on the falling edge. Writing data is valid when CSN "". The clock speed of CCLK is 5MHz (max). The CSN pin should be "H" when not accessing to the registers. Setting the PDN pin to "L" resets the registers to their default values. In serial control mode, the internal timing circuit is reset by the RSTN bit, but the registers are not initialized. CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C1-C0: R/W: A4-A0: D7-D0: Chip Address (Fixed to "01") READ/WRITE (Fixed to "1", Write only) Register Address Control Data Figure 9. Control I/F Timing * The AK4482 does not support the read command. C1-0 and R/W are fixed to "011". * When the AK4482 is in power down mode (PDN pin = "L") or the MCLK is not provided, a writing into the control registers is prohibited. Register Map Addr 00H 01H 02H 03H 04H Register Name Control 1 Control 2 Control 3 Lch ATT Rch ATT D7 D6 D5 D4 D3 D2 D1 D0 ACKS DZFE 0 ATT7 ATT7 0 DZFM 0 ATT6 ATT6 0 SLOW 0 ATT5 ATT5 DIF2 DFS1 0 ATT4 ATT4 DIF1 DFS0 0 ATT3 ATT3 DIF0 DEM1 DZFB ATT2 ATT2 PW DEM0 0 ATT1 ATT1 RSTN SMUTE SD ATT0 ATT0 Notes: For addresses from 05H to 1FH, data must not be written. When the PDN pin goes "L", the registers are initialized to their default values. When RSTN bit goes "0", the only internal timing is reset and the registers are not initialized to their default values. All data can be written to the register even if PW or RSTN bit is "0". MS1408-E-01 2012/05 - 19 - [AK4482] Register Definitions Addr 00H D7 D6 D5 D4 D3 D2 D1 D0 Control 1 Register Name ACKS 0 0 DIF2 DIF1 DIF0 PW RSTN default 1 0 0 0 1 0 1 1 RSTN: Internal timing reset control 0: Reset. All registers are not initialized. 1: Normal Operation When MCLK frequency or DFS changes, the AK4382A should be reset by PDN pin or RSTN bit. PW: Power down control 0: Power down. All registers are not initialized. 1: Normal Operation DIF2-0: Audio data interface formats (Table 7) Initial: "010", Mode 2 ACKS: Master Clock Frequency Auto Setting Mode Enable 0: Disable, Manual Setting Mode 1: Enable, Auto Setting Mode Master clock frequency is detected automatically at ACKS bit "1". In this case, the setting of DFS1-0 are ignored. When this bit is "0", DFS1-0 set the sampling speed mode. Addr 01H Register Name D7 D6 D5 D4 D3 D2 D1 D0 Control 2 DZFE DZFM SLOW DFS1 DFS0 DEM1 DEM0 SMUTE default 0 0 0 0 0 0 1 0 SMUTE: Soft Mute Enable 0: Normal operation 1: DAC outputs soft-muted DEM1-0: De-emphasis Response (Table 8) Initial: "01", OFF DFS1-0: Sampling speed control 00: Normal Speed Mode 01: Double Speed Mode 10: Quad Speed Mode When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise occurs. SLOW: Slow Roll-off Filter Enable 0: Sharp Roll-off Filter 1: Slow Roll-off Filter DZFM: Data Zero Detect Mode 0: Channel Separated Mode 1: Channel ANDed Mode If the DZFM bit is set to "1", the DZF pins of both channels go to "H" only when the input data at both channels are continuously zeros for 8192 LRCK cycles. MS1408-E-01 2012/05 - 20 - [AK4482] DZFE: Data Zero Detect Enable 0: Disable 1: Enable Zero detect function can be disabled by DZFE bit "0". In this case, the DZF pins of both channels are always "L". Addr 02H Register Name D7 D6 D5 D4 D3 D2 D1 D0 Control 3 0 0 0 0 0 DZFB 0 SD default 0 0 0 0 0 0 0 0 SD: Digital filter Setting 0: Sharp roll off filter or Slow roll off filter 1: Short delay Sharp roll off filter or Short delay Slow roll off filter SD bit 0 0 1 1 SLOW bit 0 1 0 1 Mode Sharp roll-off filter Slow roll-off filter Short delay Sharp roll-off filter Short delay Slow roll-off filter Table 10 Digital Filter setting (default) DZFB: Inverting Enable of DZF 0: DZF goes "H" at Zero Detection 1: DZF goes "L" at Zero Detection Addr 03H 04H Register Name Lch ATT Rch ATT default D7 ATT7 ATT7 D6 ATT6 ATT6 D5 ATT5 ATT5 D4 ATT4 ATT4 D3 ATT3 ATT3 D2 ATT2 ATT2 D1 ATT1 ATT1 D0 ATT0 ATT0 1 1 1 1 1 1 1 1 ATT = 20 log10 (ATT_DATA / 255) [dB] 00H: Mute MS1408-E-01 2012/05 - 21 - [AK4482] SYSTEM DESIGN Figure 10 shows the system connection diagram. An evaluation board (AKD4482) demonstrates the optimum layout, power supply arrangements and measurement results. Mas ter Clock 1 MCLK DZFL 16 64fs 2 BICK DZFR 15 24bit Audio Data 3 SDTI VDD 14 fs Reset & Power down Microcontroller Digital Ground 0.1u 4 LRCK V SS 13 5 PDN AOUTL+ 12 6 CSN AOUTL- 11 7 CCLK AOUTR+ 10 8 CDTI AOUTR- 9 AK4482 + Analog Supply 5V 1 0u Lc h LPF Lch MUTE Lch Out Rch LPF Rch MUTE Rch Out Analog Ground Figure 10. Typical Connection Diagram Notes: - LRCK = fs, BICK=64fs. - When AOUT drives a capacitive load, some resistance should be added in series between AOUT and the capacitive load. - All input pins except pull-down pins should not be allowed to float. MS1408-E-01 2012/05 - 22 - [AK4482] 1. Grounding and Power Supply Decoupling VDD and VSS are supplied from the analog supply and should be separated from the system digital supply. Decoupling capacitors, especially 0.1F ceramic capacitors for high frequency bypass, should be placed as near to VDD as possible. The differential voltage between VDD and VSS pins set the analog output range. 2. Analog Output The analog outputs are fully differential outputs at 2.4Vpp x VDD/5V, centered around 2.3V (typ). The differential outputs are summed externally, VAOUT = (AOUT+)-(AOUT-) between AOUT+ and AOUT-. If the summing gain is 1, the output range is 4.8Vpp (typ.@VDD = 5V). The bias voltage of the external summing circuit is supplied externally. The input data format is two's complement. The output voltage (VAOUT) is positive full scale for 7FFFFFH (@24-bits) and negative full scale for 800000H (@24-bits). The ideal VAOUT is 0V for 000000H(@24-bits). The internal switched capacitor filters (SCF) attenuate the noise generated by the delta sigma modulator beyond the audio passband. AOUT+/- DC off-set can be reduced without AC coupling capacitors since the AK4482 output is differential. Figure 11 and Figure 12 show examples of an external LPF circuit summing the differential outputs with an op-amp. 4.7k 4.7k AOUTR1 470p Vop 3300p 4.7k AOUT+ Vop Analog Out R1 4.7k 470p 1k BIAS 47u 0.1u When R1=200 fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz When R1=180 fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz 1k Figure 11. External 2nd order LPF Circuit Example (using op-amp with single power supply) 4.7k 4.7k AOUTR1 470p +Vop 3300p AOUT+ 4.7k Analog Out R1 4.7k 470p -Vop When R1=200 fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz When R1=180 fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz Figure 12. External 2nd order LPF Circuit Example (using op-amp with dual power supplies) MS1408-E-01 2012/05 - 23 - [AK4482] PACKAGE 16pin TSSOP (Unit: mm) 1.1 (max) *5.00.1 16 9 8 1 0.13 M 6.40.2 *4.40.1 A 0.65 0.220.1 0.170.05 Detail A 0.50.2 0.10.1 Seating Plane 0.10 NOTE: Dimension "*" does not include mold flash. 0-10 Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy, Halogen (Bromine and Chlorine) free Cu Solder (Pb free) plate MS1408-E-01 2012/05 - 24 - [AK4482] MARKING 4482VT XXXYY Pin #1 indication Date Code : XXXYY (5 digits) XXX: Date Code YY: Lot# Marketing Code : 4482VT 1) 2) 3) REVISION HISTORY Date (Y/M/D) 12/04/26 12/05/08 Revision 00 01 Reason First Edition Error Correction Page Contents 6 SHARP ROLL OFF FILTER Measurement conditions: DEM=OFF SD= "0" SLOW ROLL OFF FILTER Measurement conditions: AVDD=DVDD VDD DEM=OFF SD= "0" SHORT DELAY SHARP ROLL OFF FILTER Measurement conditions: DEM=OFF SD= "1" SHORT DELAY SLOW ROLL OFF FILTER Measurement conditions: AVDD=DVDD VDD DEM=OFF SD= "1" Register Map 02H, D0: MD SD Register Definitions 02H, D0: MD SD 7 19 21 MS1408-E-01 2012/05 - 25 - [AK4482] IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS1408-E-01 2012/05 - 26 -