Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LM321 SNOS935C - FEBRUARY 2001 - REVISED DECEMBER 2014 LM321 Low Power Single Operational Amplifier 1 Features 3 Description * The LM321 brings performance and economy to low power systems. With a high unity gain frequency and a specified 0.4-V/s slew rate, the quiescent current is only 430-A/amplifier (5 V). The input common mode range includes ground and therefore the device is able to operate in single supply applications as well as in dual supply applications. It is also capable of comfortably driving large capacitive loads. 1 * * * * * * (VCC = 5 V, TA = 25C. Typical values unless specified.) Gain-Bandwidth Product 1 MHz Low Supply Current 430 A Low Input Bias Current 45 nA Wide Supply Voltage Range 3 V to 32 V Stable With High Capacitive Loads Single Version of LM324 2 Applications * * * * * Chargers Power Supplies Industrial: Controls, Instruments Desktops Communications Infrastructure The LM321 is available in the SOT-23 package. Overall the LM321 is a low power, wide supply range performance operational amplifier that can be designed into a wide range of applications at an economical price without sacrificing valuable board space. Device Information(1) PART NUMBER LM321 PACKAGE BODY SIZE (NOM) SOT (5) 2.90 mm x 1.60 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Schematic 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM321 SNOS935C - FEBRUARY 2001 - REVISED DECEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 6.5 6.6 3 3 4 4 4 6 Absolute Maximum Ratings ..................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. 7.3 Feature Description................................................... 7 7.4 Device Functional Modes.......................................... 8 8 Application and Implementation .......................... 9 8.1 Application Information.............................................. 9 8.2 Typical Applications ................................................ 10 9 Power Supply Recommendations...................... 13 10 Layout................................................................... 13 10.1 Layout Guidelines ................................................. 13 10.2 Layout Example .................................................... 14 11 Device and Documentation Support ................. 15 Detailed Description .............................................. 7 11.1 Trademarks ........................................................... 15 11.2 Electrostatic Discharge Caution ............................ 15 11.3 Glossary ................................................................ 15 7.1 Overview ................................................................... 7 7.2 Functional Block Diagram ......................................... 7 12 Mechanical, Packaging, and Orderable Information ........................................................... 15 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (March 2013) to Revision C * Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Changes from Revision A (March 2013) to Revision B * 2 Page Page Changed layout of National Data Sheet to TI format ........................................................................................................... 13 Submit Documentation Feedback Copyright (c) 2001-2014, Texas Instruments Incorporated Product Folder Links: LM321 LM321 www.ti.com SNOS935C - FEBRUARY 2001 - REVISED DECEMBER 2014 5 Pin Configuration and Functions DBV Package 5-Pin SOT-23 Top View Pin Functions PIN NAME I/O NO. DESCRIPTION +IN 1 I Noninverting input V- 2 -- -IN 3 I Inverting input OUTPUT 4 O Output V+ 5 -- Positive (highest) power supply Negative (lowest) power supply 6 Specifications 6.1 Absolute Maximum Ratings (1) MIN Differential Input Voltage Input Current (VIN < -0.3 V) MAX Supply Voltage (2) Supply Voltage (V+ - V-) -0.3 Input Voltage Output Short Circuit to GND, V+ 15 V and TA = 25C Junction Temperature (3) (4) Mounting Temperature: Infrared (10 sec) Storage temperature, Tstg (2) (3) (4) 50 mA 32 V 32 V 150 C 260 C 215 C 150 C Continuous Mounting Temperature: Lead temperature (Soldering, 10 sec) (1) UNIT -65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector base junction of the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the operational amplifer to go to the V+ voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This is not destructive and normal output states will re-establish when the input voltage, which was negative, again returns to a value greater than -0.36V (at 25C). Short circuits from the output V+ can cause excessive heating and eventual destruction. When considering short circuits to ground the maximum output current is approximately 40mA independent of the magnitude of V+. At values of supply voltage in excess of +15V, continuous short circuits can exceed the power dissipation ratings and cause eventual destruction. The maximum power dissipation is a function of TJ(MAX), JA , and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ JA. All numbers apply for packages soldered directly onto a PC board. 6.2 ESD Ratings V(ESD) (1) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) VALUE UNIT 300 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright (c) 2001-2014, Texas Instruments Incorporated Product Folder Links: LM321 3 LM321 SNOS935C - FEBRUARY 2001 - REVISED DECEMBER 2014 www.ti.com 6.3 Recommended Operating Conditions Temperature Range MIN MAX -40 85 C 3 30 V Supply Voltage UNIT 6.4 Thermal Information LM321 THERMAL METRIC (1) DBV UNIT 5 PINS RJA (1) Junction-to-ambient thermal resistance 265 C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics Unless otherwise specified, all limits specified for at TA = 25C; V+ = 5 V, V- = 0 V, VO = 1.4 V PARAMETER VOS TEST CONDITIONS MIN TYP (1) Input Offset Voltage 2 (1) , -40C TJ 85C IOS 5 -40C TJ 85C Input Bias Current (2) 45 AV (3) V+ = 30 V Large Signal Voltage Gain (V+ = 15 V, RL = 2k, VO = 1.4 V to 11.4 V) 25 (V+ = 15 V, RL = 2k, VO = 1.4 V to 11.4 V), -40C TJ 85C 15 , for CMRR > = 50dB V+ - 2 , for CMRR > = 50dB, -40C RS 10k, V+ 5 V to 30 V 65 100 CMRR Common Mode Rejection Ratio RS 10k 65 85 Output Swing VOH VOL IS Supply Current, No Load V = 30 V, RL = 2k, -40C TJ 85C 26 V+ = 30 V, RL = 10k, -40C TJ 85C 27 V+ = 5 V, RL = 10k, -40C TJ 85C V+ = 5 V V+ = 5 V, -40C TJ 85C V+ = 30 V V+ = 30 V, -40C TJ 85C ISOURCE ISINK Output Current Sourcing Output Current Sinking (1) (2) (3) 4 V dB V 5 20 0.430 1.15 0.7 1.2 0.660 2.85 1.5 3 20 40 VID = +1 V, V+ = 15 V, VO = 2 V, -40C TJ 85C 10 20 VID = -1 V, V+ = 15 V, VO = 2 V 10 20 5 8 12 100 VID = -1 V, V+ = 15 V, VO = 0.2 V nA dB 28 VID = +1 V, V+ = 15 V, VO = 2 V VID = -1 V, V+ = 15 V, VO = 2 V, -40C TJ 85C nA V/mV Power Supply Rejection Ratio VO mV 100 PSRR + UNIT V+ - 1.5 0 (3) V = 30 V TJ 85C 250 500 Input Common-Mode Voltage Range + 50 150 -40C TJ 85C VCM 7 9 Input Offset Current IB MAX mV mA mA mA A VO 1.4 V, RS = 0 with V+ from 5 V to 30 V; and over the full input common-mode range (0 V to V+ - 1.5 V) at 25C. The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the state of the output so no loading change exists on the input lines. The input common-mode voltage of either input signal voltage should not be allowed to go negative by more than 0.3 V (at 25C). The upper end of the common-mode voltage range is V+ - 1.5 V at 25C, but either or both inputs can go to +32 V without damage, independent of the magnitude of V+. Submit Documentation Feedback Copyright (c) 2001-2014, Texas Instruments Incorporated Product Folder Links: LM321 LM321 www.ti.com SNOS935C - FEBRUARY 2001 - REVISED DECEMBER 2014 Electrical Characteristics (continued) Unless otherwise specified, all limits specified for at TA = 25C; V+ = 5 V, V- = 0 V, VO = 1.4 V PARAMETER TEST CONDITIONS + IO Output Short Circuit to Ground V = 15 V (4) Slew Rate V = 15 V, RL = 2k, VIN = 0.5 to 3 V, CL = 100pF, Unity Gain GBW Gain Bandwidth Product V+ = 30 V, f = 100kHz, VIN = 10 mV, RL =2k, CL = 100 pF m Phase Margin THD Total Harmonic Distortion (4) TYP MAX 40 85 UNIT mA + SR en MIN f = 1kHz, AV = 20dB, RL = 2k, VO = 2VPP, CL = 100 pF, V+ = 30 V + Equivalent Input Noise Voltage f = 1kHz, RS = 100, V = 30 V 0.4 V/s 1 MHz 60 degrees 0.015% 40 nV/Hz Short circuits from the output V+ can cause excessive heating and eventual destruction. When considering short circuits to ground the maximum output current is approximately 40mA independent of the magnitude of V+. At values of supply voltage in excess of +15V, continuous short circuits can exceed the power dissipation ratings and cause eventual destruction. Submit Documentation Feedback Copyright (c) 2001-2014, Texas Instruments Incorporated Product Folder Links: LM321 5 LM321 SNOS935C - FEBRUARY 2001 - REVISED DECEMBER 2014 www.ti.com 6.6 Typical Characteristics Unless otherwise specified, VS = 5 V, single supply, TA = 25C. 6 Figure 1. Small Signal Pulse Response Figure 2. Large Signal Pulse Response Figure 3. Supply Current vs. Supply Voltage Figure 4. Sinking Current vs Output Voltage Figure 5. Source Current vs. Output Voltage Figure 6. Open Loop Frequency Response Submit Documentation Feedback Copyright (c) 2001-2014, Texas Instruments Incorporated Product Folder Links: LM321 LM321 www.ti.com SNOS935C - FEBRUARY 2001 - REVISED DECEMBER 2014 7 Detailed Description 7.1 Overview The LM321 operational amplifer can operate with a single or dual power supply voltage, has true-differential inputs, and remains in the linear mode with an input common-mode voltage of 0 VDC. This amplifier operates over a wide range of power supply voltages, with little change in performance characteristics. At 25C amplifier operation is possible down to a minimum supply voltage of 3 V. Large differential input voltages can be easily accommodated and, as input differential voltage protection diodes are not needed, no large input currents result from large differential input voltages. The differential input voltage may be larger than V+ without damaging the device. Protection should be provided to prevent the input voltages from going negative more than -0.3 VDC (at 25C). An input clamp diode with a resistor to the IC input terminal can be used. 7.2 Functional Block Diagram 7.3 Feature Description To reduce the power supply drain, the amplifier has a class A output stage for small signal levels which converts to class B in a large signal mode. This allows the amplifiers to both source and sinks large output currents. Therefore both NPN and PNP external current boost transistors can be used to extend the power capability of the basic amplifiers. The output voltage needs to raise approximately 1 diode drop above ground to bias the on chip vertical PNP transistor for output current sinking applications. For AC applications, where the load is capacitively coupled to the output of the amplifier, a resistor should be used, from the output of the amplifier to ground to increase the class A bias current and to reduce distortion. Capacitive loads which are applied directly to the output of the amplifier reduce the loop stability margin. Values of 50 pF can be accommodated using the worst-case non-inverting unity gain connection. Large closed loop gains or resistive isolation should be used if large load capacitance must be driven by the amplifier. The bias network of the LM321 establishes a supply current which is independent of the magnitude of the power supply voltage over the range of from 3 VDC to 30 VDC. Output short circuits either to ground or to the positive power supply should be of short time duration. Units can be destroyed, not as a result of the short circuit current causing metal fusing, but rather due to the large increase in IC chip dissipation which will cause eventual failure due to excessive junction temperatures. The larger value of output source current which is available at 25C provides a larger output current capability at elevated temperatures than a standard IC operational amplifer. Submit Documentation Feedback Copyright (c) 2001-2014, Texas Instruments Incorporated Product Folder Links: LM321 7 LM321 SNOS935C - FEBRUARY 2001 - REVISED DECEMBER 2014 www.ti.com 7.4 Device Functional Modes 7.4.1 Common-Mode Voltage Range The input common-mode voltage range of the LM321 series extends from 300 mV below ground to 32 V for normal operation. The typical performance in this range is summarized in Table 1: Table 1. Typical Performance Range (Vs = 5 V) PARAMETER Input voltage range MIN TYP -0.3 Offset voltage 32 2 Offset voltage drift (TA = -40C to 85C) CMRR 65 85 PSRR 65 100 Gain bandwidth product (GBP) MAX UNIT V 7 mV 9 V/C dB dB 1 MHz Slew rate 0.4 V/s Phase margin 60 Equivalent input noise voltage 40 nV/Hz 8 Submit Documentation Feedback Copyright (c) 2001-2014, Texas Instruments Incorporated Product Folder Links: LM321 LM321 www.ti.com SNOS935C - FEBRUARY 2001 - REVISED DECEMBER 2014 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LM321 operational amplifer can operate with a single or dual power supply voltage, has true-differential inputs, and remain in the linear mode with an input common-mode voltage of 0 VDC. This amplifier operates over a wide range of power supply voltages, with little change in performance characteristics. At 25C amplifier operation is possible down to a minimum supply voltage of 3 V. Large differential input voltages can be easily accommodated and, as input differential voltage protection diodes are not needed, no large input currents result from large differential input voltages. The differential input voltage may be larger than V+ without damaging the device. Protection should be provided to prevent the input voltages from going negative more than -0.3 VDC (at 25C).An input clamp diode with a resistor to the IC input terminal can be used. To reduce the power supply drain, the amplifier has a class A output stage for small signal levels which converts to class B in a large signal mode. This allows the amplifiers to both source and sink large output currents. Therefore both NPN and PNP external current boost transistors can be used to extend the power capability of the basic amplifiers. The output voltage needs to raise approximately 1 diode drop above ground to bias the onchip vertical PNP transistor for output current sinking applications. For AC applications, where the load is capacitively coupled to the output of the amplifier, a resistor should be used, from the output of the amplifier to ground to increase the class A bias current and to reduce distortion. Capacitive loads which are applied directly to the output of the amplifier reduce the loop stability margin. Values of 50pF can be accommodated using the worst-case non-inverting unity gain connection. Large closed loop gains or resistive isolation should be used if large load capacitance must be driven by the amplifier. The bias network of the LM321 establishes a supply current which is independent of the magnitude of the power supply voltage over the range of from 3 VDC to 30 VDC. Output short circuits either to ground or to the positive power supply should be of short time duration. Units can be destroyed, not as a result of the short circuit current causing metal fusing, but rather due to the large increase in IC chip dissipation which will cause eventual failure due to excessive junction temperatures. The larger value of output source current which is available at 25C provides a larger output current capability at elevated temperatures than a standard IC operational amplifer. The circuits presented in the section on typical applications emphasize operation on only a single power supply voltage. If complementary power supplies are available, all of the standard operational amplifer circuits can be used. In general, introducing a pseudo-ground (a bias voltage reference of V+/2) will allow operation above and below this value in single power supply systems. Many application circuits are shown which take advantage of the wide input common-mode voltage range which includes ground. In most cases, input biasing is not required and input voltages which range to ground can easily be accommodated. Submit Documentation Feedback Copyright (c) 2001-2014, Texas Instruments Incorporated Product Folder Links: LM321 9 LM321 SNOS935C - FEBRUARY 2001 - REVISED DECEMBER 2014 www.ti.com 8.2 Typical Applications 8.2.1 Noninverting DC Gain (0-V Input = 0-V Output) Figure 7. Non-Inverting DC Gain Schematic (0-V Input = 0-V Output) 8.2.1.1 Design Requirements * * Supply voltage (up to 32 V) Phase margin: 60 8.2.1.2 Detailed Design Procedure * * * Connect 1-M feedback resistor between the output and the inverting terminal of the amplifier. Connect 10-k resistor between the inverting terminal and ground. Place the resistor as close to the inverting pin as possible. Connect power supply and input voltages. 8.2.1.3 Application Curve * R not needed due to temperature independent Figure 8. Gain of the Noninverting Amplifier 10 Submit Documentation Feedback Copyright (c) 2001-2014, Texas Instruments Incorporated Product Folder Links: LM321 LM321 www.ti.com SNOS935C - FEBRUARY 2001 - REVISED DECEMBER 2014 Typical Applications (continued) 8.2.2 DC Summing Amplifier (VIN's 0 VDC and VO VDC) The summing amplifier, a special case of the inverting amplifier, is shown in Figure 7. The circuit gives an inverted output which is equal to the weighted algebraic sum of all four inputs. The gain of any input of this circuit is equal to the ratio of the appropriate input resistor to the feedback resistor. The advantage of this circuit is that there is no interaction between inputs and operations such as summing and weighted averaging are implemented very easily. Where: V0 = V1 + V2 - V3 - V4, (V1 + V2) (V3 + V4) to keep VO > 0 VDC Figure 9. DC Summing Amplifier Schematic (VIN's 0 VDC and VO VDC) 8.2.3 Amplitude Modulator Circuit The modulator circuit is shown in Figure 10. PWM signal is used to switch the MOSFET. When the MOSFET is on, the circuit acts as an inverting amplifier with gain 1. When The MOSFET is off, the inverting and non-inverting signals cancel each other out. Therefore, the output switches from -VIN to GND at the carrier frequency. Figure 10. Amplitude Modulator Circuit Schematic Submit Documentation Feedback Copyright (c) 2001-2014, Texas Instruments Incorporated Product Folder Links: LM321 11 LM321 SNOS935C - FEBRUARY 2001 - REVISED DECEMBER 2014 www.ti.com Typical Applications (continued) 8.2.4 Power Amplifier Power amplifier application circuit is shown in Figure 11. Voltage gain is set by R1 and R2. The output of the amplifier is connected to the base of BJT which amplifies the current. Current gain is set by , current gain of a BJT. The resulting output provides high power to the load. Differential voltage supplies are necessary. V0 = 0 VDC for VIN = 0 VDC, AV = 10 Figure 11. Power Amplifier Schematic 8.2.5 LED Driver LM321 operating as an LED driver is shown in Figure 12. The output of the amplifier sets the current through the diode. The voltage across the LED is assumed constant. Figure 12. LED Driver Schematic 8.2.6 Fixed Current Sources Operational amplifier can be used to provide fixed current source to multiple loads. The output voltage of the amplifier is connected to bases of bipolar transistors. The feedback is provided from the drain of a BJT to the inverting terminal of the amplifier. Currents in the second and later BJTs are set by the ratio of R1 and R2. Figure 13. Fixed Current Sources Schematic 12 Submit Documentation Feedback Copyright (c) 2001-2014, Texas Instruments Incorporated Product Folder Links: LM321 LM321 www.ti.com SNOS935C - FEBRUARY 2001 - REVISED DECEMBER 2014 Typical Applications (continued) 8.2.7 Lamp Driver Similar to the LED driver, LM321 can be used as a lamp driver. The output of the amplifier is to be connected to the base of a bipolar transistor which will drive *output current of the amplifier through the lamp. Figure 14. Lamp Driver Schematic 9 Power Supply Recommendations The LM321 is specified for operation up to 32 V; many specifications apply from -40C to 85C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in Typical Characteristics. Place 0.1-F bypass capacitors close to the power-supply terminals to reduce errors coupling in from noisy or high-impedance power supplies. For more detailed information on bypass capacitor placement, see Layout. 10 Layout 10.1 Layout Guidelines For best operational performance of the device, use good printed circuit board (PCB) layout practices, including: * Noise can propagate into analog circuitry through the power pins of the circuit as a whole and operational amplifer itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. - Connect low-ESR, 0.1-F ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single supply applications. * Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds paying attention to the flow of the ground current. For more detailed information refer to Circuit Board Layout Techniques, SLOA089. * In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace. * Place the external components as close to the device as possible. As shown in Figure 15, keeping RF and RG close to the inverting input minimizes parasitic capacitance. * Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. * Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials. Submit Documentation Feedback Copyright (c) 2001-2014, Texas Instruments Incorporated Product Folder Links: LM321 13 LM321 SNOS935C - FEBRUARY 2001 - REVISED DECEMBER 2014 www.ti.com 10.2 Layout Example Figure 15. PCB Layout Example 14 Submit Documentation Feedback Copyright (c) 2001-2014, Texas Instruments Incorporated Product Folder Links: LM321 LM321 www.ti.com SNOS935C - FEBRUARY 2001 - REVISED DECEMBER 2014 11 Device and Documentation Support 11.1 Trademarks All trademarks are the property of their respective owners. 11.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.3 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2001-2014, Texas Instruments Incorporated Product Folder Links: LM321 15 PACKAGE OPTION ADDENDUM www.ti.com 11-Jan-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LM321MF NRND SOT-23 DBV 5 1000 Non-RoHS & Green Call TI Call TI -40 to 85 A63A LM321MF/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A63A LM321MFX NRND SOT-23 DBV 5 3000 Non-RoHS & Green Call TI Call TI -40 to 85 A63A LM321MFX/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 85 A63A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Jan-2021 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) LM321MF SOT-23 DBV 5 1000 178.0 8.4 LM321MF/NOPB SOT-23 DBV 5 1000 178.0 LM321MFX SOT-23 DBV 5 3000 178.0 LM321MFX/NOPB SOT-23 DBV 5 3000 178.0 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM321MF SOT-23 DBV 5 1000 210.0 185.0 35.0 LM321MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LM321MFX SOT-23 DBV 5 3000 210.0 185.0 35.0 LM321MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 0.90 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. 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