March 2002 AS7C33512NTD16A AS7C33512NTD18A (R) 3.3V 512K x 16/18 65$0ZLWK17'TM Features * * * * * * * * * * * * * * * * * Organization: 524,288 words x 16 or 18 bits NTDTM1 architecture for efficient bus operation Fast clock speeds to 166 MHz in LVTTL/LVCMOS Fast clock to data access: 3.0/3.5/3.8/4.0/5.0 ns Fast OE access time: 3.5/3.8/4.0/5.0 ns Fully synchronous register-to-register operation "Flow-through" or "Pipeline" modes Asynchronous output enable control Available in100-pin TQFP and 119-ball BGA package Byte write enables Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ 30 mW typical standby power in power down mode Self-timed WRITE cycles "Interleaved" or "Linear burst" modes Snooze mode for standby operation 1. NTDTM is a trademark of Alliance Semiconductor Corporation. Logic block diagram 19 A[18:0] D Q 19 Address register Burst logic CLK D Q Write delay addr. registers CLK CE0 CE1 CE2 R/W Control logic BWa BWb CLK Write Buffer ADV / LD FT LBO CLK ZZ DQ [a:b] 19 18/16 D Data Q Input Register 512K x 16/18 SRAM Array 18/16 18/16 CLK 18/16 18/16 CLK CLK CEN Output OE Register 18/16 OE DQ[a:b] Selection Guide -166 -150 -133 -100 Units 6 6.6 7.5 10 ns 150 133 100 MHz 3.0/3.5 3.8 4 5 ns Maximum operating current 475 425 400 300 mA Maximum standby current 130 110 100 90 mA Maximum CMOS standby current (DC) 30 30 30 30 mA Minimum cycle time Maximum pipelined clock frequency Maximum pipelined clock access time 166 1 1 3.0 ns available on 166 MHz parts with "H" suffix. For further information see page 7 and last page with ordering codes. 3/11/02; v.1.8H Alliance Semiconductor 1 of 12 Copyright (c) Alliance Semiconductor. All rights reserved. AS7C33512NTD16A AS7C33512NTD18A (R) Ball and pin assignment Pin Configuration for 512 x 181 for 119-ball BGA A B C D E F G H J K L M N P R T U 1 VDDQ NC NC DQb NC VDDQ NC DQb VDDQ NC DQb VDDQ DQb NC NC NC VDDQ 2 A CE1 A NC DQb NC DQb NC VDD DQb NC DQb NC DQPb A A NC 3 A A A VSS VSS VSS BWb VSS NC VSS VSS VSS VSS VSS LBO A NC 4 ADSP ADV/LD VDD NC CE0 OE A R/W VDD CLK NC CEN A12 A02 VDD NC NC 5 A A A VSS VSS VSS VSS VSS NC VSS BWa VSS VSS VSS FT A NC 6 A CE2 A DQPa NC DQa NC DQa VDD NC DQa NC DQa NC A A NC 7 VDDQ NC NC NC DQa VDDQ DQa NC VDDQ DQa NC VDDQ NC DQa NC ZZ VDDQ 1 Note pins 6D and 2P are NC for x16. 2 A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. TQFP 14 x 20mm* A18 A8 A9 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A10 NC NC VDDQ VSSQ NC DQpa/NC DQa DQa VSSQ VDDQ DQa DQa VSS VSS VDD ZZ DQa DQa VDDQ VSSQ DQa DQa NC NC VSSQ VDDQ NC NC NC LBO A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC NC A11 A12 A13 A14 A15 A16 A17 VDDQ VSSQ NC NC DQb DQb VSSQ VDDQ DQb DQb FT VDD VDD VSS DQb DQb VDDQ VSSQ DQb DQb DQpb/NC NC VSSQ VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1& A6 A7 CE0 CE1 NC NC BWb BWa CE2 VDD VSS CLK R/W CEN OE ADV/LD Pin arrangement for TQFP * Pins 24 and 74 are NC in x16 3/11/02; v.1.8H Alliance Semiconductor 2 of 12 AS7C33512NTD16A AS7C33512NTD18A (R) Functional description The AS7C33512NTD16A/18A family is a high performance CMOS 8 Mbit synchronous Static Random Access Memory (SRAM) organized as 524,288 words x 16 or 18 bits and incorporates a LATE LATE Write. This variation of the 8Mb sychronous SRAM uses the No Turnaround Delay (NTDTM) architecture, featuring an enhanced write operation that improves bandwidth over pipeline burst devices. In a normal pipeline burst device, the write data, command, and address are all applied to the device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead' cycles for valid data to become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or read-modify-write operations. NTDTM devices use the memory bus more efficiently by introducing a write 'latency' which matches the two (one)cycle pipeline (flowthrough) read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With NTDTM, write and read operations can be used in any order without producing dead bus cycles. Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 16/18 bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two clock cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for normal operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs (refer to synchronous truth table on page 4.) In pipeline mode, a two cycle deselect latency allows pending read or write operations to be completed. Use the ADV/LD (burst advance) input to perform burst read, write and deselect operations. When ADV/LD is high, external addresses, chip select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations, including burst, can be stalled using the CEN=1, the clock enable input. The AS7C33512NTD16A and AS7C33512NTD18A operate with a 3.3V 5% power supply for the device core (VDD). DQ circuits use a separate power supply (VDDQ) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin 14x20 mm TQFP and a 119-ball 14x20 mm BGA package. Capacitance Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN Address and control pins VIN = 0V 5 pF I/O capacitance CI/O I/O pins VIN = VOUT = 0V 7 pF Burst Order Linear Burst Order Interleaved Burst Order Starting Address First increment Second increment Third increment 3/11/02; v.1.8H 00 01 10 11 LBO=1 01 10 00 11 11 00 10 01 11 10 01 00 Alliance Semiconductor Starting Address First increment Second increment Third increment 00 01 10 11 LBO=0 01 10 10 11 11 00 00 01 3 of 12 11 00 01 10 AS7C33512NTD16A AS7C33512NTD18A (R) Signal descriptions Signal I/O Properties Description Clock. All inputs except OE, FT, LBO, and ZZ are synchronous to this clock. CLK I CLOCK CEN I SYNC Clock enable. When de-asserted HIGH, the clock input signal is masked. A, A0, A1 I SYNC Address. Sampled when all chip enables are active and ADV/LD is asserted. DQ[a,b] I/O SYNC Data. Driven as output when the chip is enabled and OE is active. CE0, CE1, CE2 I SYNC Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted. Are ignored when ADV/LD is HIGH. ADV/LD I SYNC Advance or Load. When sampled HIGH, the internal burst address counter will increment in the order defined by the LBO input value. (refer to table on page 2) When LOW, a new address is loaded. R/W I SYNC A HIGH during LOAD initiates a READ operation. A LOW during LOAD initiates a WRITE operation. Is ignored when ADV/LD is HIGH. BW[a,b] I SYNC Byte write enables. Used to control write on individual bytes. Sampled along with WRITE command and BURST WRITE. OE I ASYNC Asynchronous output enable. I/O pins are not driven when OE is inactive. LBO I STATIC Count mode. When driven High, count sequence follows Intel XOR convention. When driven Low, count sequence follows linear convention. This input should be static when the device is in operation. FT I STATIC Flow-through mode.When low, enables single register flow-through mode. Connect to VDD if unused or for pipelined operation. ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to VSS if unused. NC - - No connects. Note that pin 84 will be used for future address expansion to 18Mb density. Absolute maximum ratings Parameter Symbol Min Max Unit VDD, VDDQ -0.5 +4.6 V Input voltage relative to GND (input pins) VIN -0.5 VDD + 0.5 V Input voltage relative to GND (I/O pins) VIN -0.5 VDDQ + 0.5 V Power dissipation PD - 1.8 W DC output current IOUT - 50 mA Storage temperature (plastic) Tstg -65 +150 C Temperature under bias Tbias -65 +135 C Power supply voltage relative to GND Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability. 3/11/02; v.1.8H Alliance Semiconductor 4 of 12 AS7C33512NTD16A AS7C33512NTD18A (R) Synchronous truth table CE0 CE1 CE2 ADV/LD R/W BW[a,b] OE CEN Address source CLK Operation H X X L X X X L NA L to H Deselect, high-Z X L X L X X X L NA L to H Deselect, high-Z X X H L X X X L NA L to H Deselect, high-Z L H L L H X X L External L to H Begin read L H L L L L X L External L to H Begin write 1 X X X H X X X L Burst counter L to H Burst2 X X X X X X X H Stall L to H Inhibit the CLK 1 Should be low for Burst write, unless a specific byte/s need/s to be inhibited 2 Refer to state diagram below. Key: X = Don't Care, L = Low, H = High. State Diagram for NTD SRAM Burst Read Read Read Burst Read ad Re Burst W rit e Write Read Dsel Dsel l Dse Write Dsel ite Wr Burst Write Write Dsel Dse l Rea d Burst Burst Write Burst Recommended operating conditions Parameter Symbol Min Nominal Max VDD 3.135 3.3 3.6 VSS 0.0 0.0 0.0 3.3V I/O supply voltage VDDQ 3.135 3.3 3.6 VSSQ 0.0 0.0 0.0 2.5V I/O supply voltage VDDQ 2.35 2.5 2.65 VSSQ 0.0 0.0 0.0 VIH 2.0 - VDD + 0.3 Supply voltage Input voltages 1 Address and control pins I/O pins Ambient operating temperature 2 VIL -0.5 - 0.8 VIH 2.0 - VDDQ + 0.3 2 VIL -0.5 - 0.8 TA 0 - 70 1 Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications. 2 VIL min = -2.0V for pulse width less than 0.2 x tRC. 3/11/02; v.1.8H Alliance Semiconductor 5 of 12 Unit V V V V V C AS7C33512NTD16A AS7C33512NTD18A (R) TQFP thermal resistance Description Conditions Thermal resistance (junction to ambient)1 Thermal resistance (junction to top of case)1 Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 Symbol Typical Units 1-layer JA 40 C/W 4-layer JA 22 C/W JC 8 C/W 1 This parameter is sampled. DC electrical characteristics -166 Parameter -150 -133 -100 Symbol Test conditions Input leakage current |ILI|1 VDD = Max, VIN = GND to VDD - 2 - 2 - 2 - 2 A Output leakage current |ILO| OE VIH, VDD = Max, VOUT = GND to VDD - 2 - 2 - 2 - 2 A ICC2 CE0 = VIL, CE1 = VIH, CE2 = VIL, f = fMax, IOUT = 0 mA - 475 - 425 - 400 - 300 mA ISB Deselected, f = fMax, ZZ VIL - 130 - 110 - 100 - 90 ISB1 Deselected, f = 0, ZZ 0.2V all VIN 0.2V or VDD - 0.2V - 30 - 30 - 30 - 30 ISB2 Deselected, f = fMax, ZZ VDD - 0.2V All VIN VIL or VIH - 30 - 30 - 30 - 30 VOL IOL = 8 mA, VDDQ = 3.465V - 0.4 - 0.4 - 0.4 - 0.4 VOH IOH = -4 mA, VDDQ = 3.135V 2.4 - 2.4 - 2.4 - 2.4 - Operating power supply current Standby power supply current Output voltage Min Max Min Max Min Max Min Max Unit mA V 1 LBO pin has an internal pull-up and input leakage = 10 A. 2 ICC give with no output loading. ICC increases with faster cycle times and greater output loading. DC electrical characteristics for 2.5V I/O operation -166 Parameter Output leakage current Output voltage 3/11/02; v.1.8H -150 -133 -100 Symbol Test conditions Min Max Min Max Min Max Min Max Unit |ILO| OE VIH, VDD = Max, VOUT = GND to VDD -1 1 -1 1 -1 1 -1 1 VOL IOL = 2 mA, VDDQ = 2.65V - 0.7 - 0.7 - 0.7 - 0.7 VOH IOH = -2 mA, VDDQ = 2.35V 1.7 - 1.7 - 1.7 - 1.7 - Alliance Semiconductor 6 of 12 A V AS7C33512NTD16A AS7C33512NTD18A (R) Timing characteristics over operating range -166 H Parameter -166 -150 -133 -100 Unit Notes1 Symbol Min Max Min Max Min Max Min Max Min Clock frequency fMax - 166 - 166 - 150 - 133 - Cycle time (pipelined mode) tCYC 6 - 6 - 6.6 - 7.5 - 10 - ns Cycle time (flow-through mode) tCYCF 10 - 10 - 10 - 12 - 12 - ns Clock access time (pipelined mode)- 3.3V VDDQ tCD 3.3V - 3.0 - 3.5 - 3.8 - 4.0 - 5.0 ns Clock access time (pipelined mode)- 2.5V VDDQ tCD 2.5V - 4.0 - 4.0 - 4.3 - 4.5 - 5.0 ns Clock access time (flow-through mode) tCDF - 9 - 9 - 10 - 10 - 12 ns Output enable LOW to data valid tOE - 3.5 - 3.5 - 3.8 - 4.0 - 5.0 ns Clock HIGH to output Low Z tLZC 0 - 0 - 0 - 0 - 0 - ns 2,3,4 Data output invalid from clock HIGH tOH 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - ns 2 Output enable LOW to output Low Z tLZOE 0 - 0 - 0 - 0 - 0 - ns 2,3,4 Output enable HIGH to output High Z tHZOE - 3.0 - 3.5 - 3.8 - 4.0 - 4.5 ns 2,3,4 Clock HIGH to output High Z tHZC - 3.0 - 3.5 - 3.8 - 4.0 - 5.0 ns 2,3,4 tOHOE 0 - 0 - 0 - 0 - 0 - ns Clock HIGH pulse width tCH 2.4 - 2.4 - 2.5 - 2.5 - 3.5 - ns 5 Clock LOW pulse width tCL 2.4 - 2.4 - 2.5 - 2.5 - 3.5 - ns 5 Address setup to clock HIGH tAS 1.2 - 1.5 - 1.5 - 1.5 - 2.0 - ns 6 Data setup to clock HIGH tDS 1.2 - 1.5 - 1.5 - 1.5 - 2.0 - ns 6 Write setup to clock HIGH tWS 1.2 - 1.5 - 1.5 - 1.5 - 2.0 - ns 6,7 Chip select setup to clock HIGH tCSS 1.2 - 1.5 - 1.5 - 1.5 - 2.0 - ns 6,8 ADV/LD setup to clock HIGH tADVS 1.2 - 1.5 - 1.5 - 1.5 - 2.0 - ns 6 Clock enablesetup to clock HIGH tCENS 1.2 - 1.5 - 1.5 - 1.5 - 2.0 - ns 6 Address hold from clock HIGH tAH 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - ns 6 Data hold from clock HIGH tDH 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - ns 6 Write hold from clock HIGH tWH 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - ns 6,7 Chip select hold from clock HIGH tCSH 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - ns 6,8 ADV/LD hold from clock HIGH tADVH 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - ns 6 Clock enable hold from clock HIGH tCENH 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - ns 6 Output enable HIGH to invalid output Max 100 MHz 1 Refer to "notes" on page 10. 3/11/02; v.1.8H Alliance Semiconductor 7 of 12 AS7C33512NTD16A AS7C33512NTD18A (R) Key to switching waveforms Rising input Falling input Undefined/don't care Timing waveform of read/write cycle W&+ W&<& W&/ &/. W&(16 W&(1+ &(1 &( t&6+ W&66 &(&( W$'9+ $'9/' W:6 W:+ 5: W:6 W:+ %:Q W$6 W$+ $''5(66 $ $ $ $ $ W'6 ' $ ' $ W2( W/=& 4 $ ' $Y $ W+=& W&' W'+ '4 SLSHOLQH $ 4 $ 4 $Y0 ' $ 4 $ W2+ W+=2( W/=2( 2( '4 IORZWKURXJK &RPPDQG WRITE D(A1) ' $ WRITE D(A2) ' $ BURST WRITE D(A2Y01) 4 $ ' $< READ Q(A3) READ Q(A4) 4 $ 4 $Y BURST WRITE READ D(A5) Q(A4Y01) ' $ READ Q(A6) 4 $ WRITE D(A7) DSEL Note: Y = XOR when LBO = HIGH/No Connect; Y = ADD when LBO = LOW. BW[a:b] is don't care. 3/11/02; v.1.8H Alliance Semiconductor 8 of 12 AS7C33512NTD16A AS7C33512NTD18A (R) NOP, stall and deselect cycles &/. &(1 &( &(&( $'9/' 5: %:Q $''5(66 $ $ 4 $ '4 SLSHOLQH '4 IORZWKRXJK &RPPDQG 4 $ READ Q(A1) 4 $Y 4 $Y STALL BURST Q(A1Y01) ' $ 4 $Y ' $ 4 $Y10 BURST DSEL Q(A1Y10) $ BURST DSEL WRITE D(A2) BURST WRITE BURST NOP D(A2Y10) NOP D(A2Y01) D(A3) Note: Y = XOR when LBO = HIGH/No Connect; Y = ADD when LBO = LOW. 3/11/02; v.1.8H Alliance Semiconductor 9 of 12 AS7C33512NTD16A AS7C33512NTD18A (R) AC test conditions * Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C. * Input pulse level: GND to 3V. See Figure A. Thevenin equivalent: * Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A. +3.3V for 3.3V I/O; /+2.5V for 2.5V I/O * Input and output timing reference levels: 1.5V. +3.0V 90% 10% GND 90% 10% Figure A: Input waveform DOUT Z0 = 50 50 VL = 1.5V for 3.3V I/O; 30 pF* = VDDQ/2 for 2.5V I/O Figure B: Output load (A) DOUT 353/1538 319/1667 5 pF* GND *including scope and jig capacitance Figure C: Output load(B) Notes: 1) For test conditions, see "AC Test Conditions", Figures A, B, C 2) This paracmeter measured with output load conditon in Figure C. 3) This parameter is sampled, but not 100% tested. 4) tHZOE is less than tLZOE and tHZC is less than tLZC at any given temperature and voltage. 5) tCH measured HIGH above VIH and tCL measured as LOW below VIL 6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled. 7) Write refers to R/W, BW[a:d]. 8) Chip select refers to CE0, CE1, CE2. 3/11/02; v.1.8H Alliance Semiconductor 10 of 12 AS7C33512NTD16A AS7C33512NTD18A (R) Package Dimensions 100-pin quad flat pack (TQFP) Hd TQFP Min Max A1 A2 b c D E e Hd He L L1 D 0.05 0.15 1.35 1.45 0.22 0.38 0.09 0.20 13.90 14.10 19.90 20.10 0.65 nominal 15.90 16.10 21.90 22.10 0.45 0.75 1.00 nominal 0 7 b e He E Dimensions in millimeters c L1 L A1 A2 119-ball Ball Grid Array (BGA) All measurements are in mm in the table. The diagram has meaurements in inches in parentheses Min Typical Max A 1.27 B 13.80 14.00 14.20 B1 7.82 C 21.80 22.00 22.20 C1 20.23 D 0.71 0.76 0.81 E 2.40 E1 0.56 E2 0.50 0.60 0.70 F 12.00 F1 0.70 - 3/11/02; v.1.8H Alliance Semiconductor 11 of 12 AS7C33512NTD16A AS7C33512NTD18A (R) Ordering information Package &Width TQFP x16 TQFP x16 TQFP x18 TQFP x18 BGA x16 BGA x16 BGA x18 BGA x18 -166 H MHz -166 MHz -150 MHz AS7C33512NTD16A- AS7C33512NTD16A166TQC AS7C33512NTD16A150TQC AS7C33512NTD16A- AS7C33512NTD16A133TQC 100TQC AS7C33512NTD16A166TQI AS7C33512NTD16A150TQI AS7C33512NTD16A- AS7C33512NTD16A133TQI 100TQI AS7C33512NTD18A166TQC AS7C33512NTD18A150TQC AS7C33512NTD18A- AS7C33512NTD18A133TQC 100TQC AS7C33512NTD18A166TQI AS7C33512NTD18A150TQI AS7C33512NTD18A- AS7C33512NTD18A133TQI 100TQI AS7C33512NTD16A166BC AS7C33512NTD16A150BC AS7C33512NTD16A- AS7C33512NTD16A133BC 100BC AS7C33512NTD16A166BI AS7C33512NTD16A150BI AS7C33512NTD16A- AS7C33512NTD16A133BI 100BI AS7C33512NTD18A166BC AS7C33512NTD18A150BC AS7C33512NTD18A- AS7C33512NTD18A133BC 100BC AS7C33512NTD18A166BI AS7C33512NTD18A150BI AS7C33512NTD18A- AS7C33512NTD18A133BI 100BI 166HTQC AS7C33512NTD16A166HTQI AS7C33512NTD18A166HTQC AS7C33512NTD18A166HTQI AS7C33512NTD16A166HBC AS7C33512NTD16A166HBI AS7C33512NTD18A166HBC AS7C33512NTD18A166HBI -133 MHz -100 MHz Part numbering guide AS7C 33 512 NTD 16/18 A -XXX (H) TQ or B C/I 1 2 3 4 5 6 7 8 9 1. Alliance Semiconductor SRAM prefix 2. Operating voltage: 33=3.3V 3. Organization: 512=512K 4. NTDTM = No-Turn Around Delay. Pipeline-Flowthrough (each device works in both modes) 5. Organization: 16=x16; 18=x18 6. Production version: A=first production version 7. Clock speed (MHz); "H" indicates faster clock access time. 8. Package type: TQ=TQFP; B=BGA 9. Operating temperature: C=Commercial (0 C to 70 C); I=Industrial (-40 C to 85 C) 3/11/02; v.1.8H Alliance Semiconductor 12 of 12 (c) Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. 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