March 2002
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C33512NTD16A
AS7C33512NTD18A
3.3V 512K × 16/18 65$0ZLWK17'TM
3/11/02; v.1.8H Alliance Semiconductor 1 of 12
Features
• Organization: 524,288 words × 16 or 18 bits
•NTD™1 architecture for efficient bus operation
• Fast clock speeds to 166 MHz in LVTTL/LVCMOS
• Fast clock to data access: 3.0/3.5/3.8/4.0/5.0 ns
•Fast OE
access time: 3.5/3.8/4.0/5.0 ns
• Fully synchronous register-to-register operation
• “Flow-through” or “Pipeline” modes
• Asynchronous output enable control
1. NTD™ is a trademark of Alliance Semiconductor Corporation.
• Available in100-pin TQFP and 119-ball BGA package
• Byte write enables
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• 30 mW typical standby power in power down mode
• Self-timed WRITE cycles
• “Interleaved” or “Linear burst” modes
• Snooze mode for standby operation
Selection Guide
-166 –150 –133 –100 Units
Minimum cycle time 6 6.6 7.5 10 ns
Maximum pipelined clock frequency 166 150 133 100 MHz
Maximum pipelined clock access time 3.0/3.51
1 3.0 ns available on 166 MHz parts with “H” suffix. For further information see page 7 and last page with ordering codes.
3.8 4 5 ns
Maximum operating current 475 425 400 300 mA
Maximum standby current 130 110 100 90 mA
Maximum CMOS standby current (DC) 30 30 30 30 mA
Write Buffer
Address
DQ
CLK
register
Output
Register
DQ[a:b]
18/16
18/16
19
19
CLK
CE0
CE1
CE2
A[18:0]
OE
CLK
CEN
Control
CLK
logic
Data
DQ
CLK
Input
Register
18/16
18/16
OE
512K x 16/18
SRAM
Array
R/W
DQ [a:b]
BWa
BWb
CLK
Q
D
FT
ADV / LD
LBO
Burst logic
addr. registers
Write delay
18/16
19
Logic block diagram
ZZ
18/16
CLK
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Pin Configuration for 512 x 181 for 119-ball BGA
1 Note pins 6D and 2P are NC for x16.
123 4 567
AVDDQ AAADSPAAV
DDQ
BNC CE1 A ADV/LD ACE2NC
CNC A A VDD AANC
DDQbNC VSS NC VSS DQPa NC
ENC DQb VSS CE0 VSS NC DQa
FVDDQ NC VSS OE VSS DQa VDDQ
GNC DQb BWb AV
SS NC DQa
HDQbNC VSS R/W VSS DQa NC
JVDDQ VDD NC VDD NC VDD VDDQ
KNC DQb VSS CLK VSS NC DQa
LDQb NC VSS NC BWa DQa NC
MVDDQ DQb VSS CEN VSS NC VDDQ
NDQb NC VSS A12
2 A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst
counter if burst is desired.
VSS DQa NC
PNC DQPb VSS A02VSS NC DQa
RNC A LBO VDD FT ANC
TNCAANCAAZZ
UVDDQ NC NC NC NC NC VDDQ
Pin arrangement for TQFP
LBO
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
NC
NC
A11
A12
A13
A14
A15
A16
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A6
A7
CE0
CE1
NC
NC
BWb
BWa
CE2
V
DD
V
SS
CLK
CEN
ADV/
LD
1&
A18
A8
A9
A17
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQb
DQb
V
SSQ
V
DDQ
DQb
DQb
FT
V
DD
V
DD
V
SS
DQb
DQb
V
DDQ
V
SSQ
DQb
DQb
DQpb/NC
NC
V
SSQ
V
DDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A10
NC
NC
V
DDQ
V
SSQ
NC
DQpa/NC
DQa
DQa
V
SSQ
V
DDQ
DQa
DQa
V
SS
ZZ
DQa
DQa
V
DDQ
V
SSQ
DQa
DQa
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
V
SS
V
DD
TQFP 14 × 20mm*
R/
W
OE
* Pins 24 and 74 are NC in x16
Ball and pin assignment
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AS7C33512NTD18A
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Functional description
The AS7C33512NTD16A/18A family is a high performance CMOS 8 Mbit synchronous Static Random Access Memory (SRAM) organized as
524,288 words × 16 or 18 bits and incorporates a LATE LATE Write.
This variation of the 8Mb sychronous SRAM uses the No Turnaround Delay (NTD™) architecture, featuring an enhanced write operation that
improves bandwidth over pipeline burst devices. In a normal pipeline burst device, the write data, command, and address are all applied to the
device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead' cycles for valid data to
become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or read-modify-write
operations.
NTD™ devices use the memory bus more efficiently by introducing a write 'latency' which matches the two (one)cycle pipeline (flowthrough)
read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With NTD™, write and
read operations can be used in any order without producing dead bus cycles.
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 16/18 bit writes.
Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two clock
cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for
normal operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs (refer to
synchronous truth table on page 4.) In pipeline mode, a two cycle deselect latency allows pending read or write operations to be completed.
Use the ADV/LD (burst advance) input to perform burst read, write and deselect operations. When ADV/LD is high, external addresses, chip
select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device
operations, including burst, can be stalled using the CEN=1, the clock enable input.
The AS7C33512NTD16A and AS7C33512NTD18A operate with a 3.3V ± 5% power supply for the device core (VDD). DQ circuits use a sepa-
rate power supply (VDDQ) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin 14×20 mm TQFP and a 119-ball
14×20 mm BGA package.
Capacitance
Parameter Symbol Signals Test conditions Max Unit
Input capacitance CIN Address and control pins VIN = 0V 5 pF
I/O capacitance CI/O I/O pins VIN = VOUT = 0V 7 pF
Burst Order
Interleaved Burst Order
LBO=1
Linear Burst Order
LBO=0
Starting Address00011011 Starting Address00011011
First increment01001110 First increment01101100
Second increment10110001 Second increment10110001
Third increment11100100 Third increment11000110
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Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions may affect reliability.
Signal descriptions
Signal I/O Properties Description
CLK I CLOCK Clock. All inputs except OE, FT, LBO, and ZZ are synchronous to this clock.
CEN I SYNC Clock enable. When de-asserted HIGH, the clock input signal is masked.
A, A0, A1 I SYNC Address. Sampled when all chip enables are active and ADV/LD is asserted.
DQ[a,b] I/O SYNC Data. Driven as output when the chip is enabled and OE is active.
CE0, CE1,
CE2 ISYNC
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted. Are
ignored when ADV/LD is HIGH.
ADV/LD ISYNC
Advance or Load. When sampled HIGH, the internal burst address counter will increment in
the order defined by the LBO input value. (refer to table on page 2) When LOW, a new
address is loaded.
R/W ISYNC
A HIGH during LOAD initiates a READ operation. A LOW during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is HIGH.
BW[a,b] ISYNC
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
OE I ASYNC Asynchronous output enable. I/O pins are not driven when OE is inactive.
LBO ISTATIC
Count mode. When driven High, count sequence follows Intel XOR convention. When
driven Low, count sequence follows linear convention. This input should be static when the
device is in operation.
FT ISTATIC
Flow-through mode.When low, enables single register flow-through mode. Connect to VDD
if unused or for pipelined operation.
ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to VSS if unused.
NC - - No connects. Note that pin 84 will be used for future address expansion to 18Mb density.
Absolute maximum ratings
Parameter Symbol Min Max Unit
Power supply voltage relative to GND VDD, VDDQ –0.5 +4.6 V
Input voltage relative to GND (input pins) VIN –0.5 VDD + 0.5 V
Input voltage relative to GND (I/O pins) VIN –0.5 VDDQ + 0.5 V
Power dissipation PD–1.8W
DC output current IOUT –50mA
Storage temperature (plastic) Tstg –65 +150 °C
Temperature under bias Tbias –65 +135 °C
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Key: X = Don’t Care, L = Low, H = High.
State Diagram for NTD SRAM
Synchronous truth table
CE0 CE1 CE2 ADV/LD R/W BW[a,b] OE CEN Address source CLK Operation
H X X L X X X L NA L to H Deselect, high-Z
X L X L X X X L NA L to H Deselect, high-Z
X X H L X X X L NA L to H Deselect, high-Z
L H L L H X X L External L to H Begin read
L H L L L L X L External L to H Begin write
XXX H X X
1
1 Should be low for Burst write, unless a specific byte/s need/s to be inhibited
X L Burst counter L to H Burst2
2 Refer to state diagram below.
X X X X X X X H Stall L to H Inhibit the CLK
Recommended operating conditions
Parameter Symbol Min Nominal Max Unit
Supply voltage VDD 3.135 3.3 3.6 V
VSS 0.0 0.0 0.0
3.3V I/O supply
voltage
VDDQ 3.135 3.3 3.6 V
VSSQ 0.0 0.0 0.0
2.5V I/O supply
voltage
VDDQ 2.35 2.5 2.65 V
VSSQ 0.0 0.0 0.0
Input voltages1
1 Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.
Address and
control pins
VIH 2.0 – VDD + 0.3 V
VIL –0.52
2 VIL min = –2.0V for pulse width less than 0.2 × tRC.
–0.8
I/O pins VIH 2.0 – VDDQ + 0.3 V
VIL –0.52–0.8
Ambient operating temperature TA0–70
°C
Dsel
Dsel
Read
Read
Burst
Burst
Write
Read
Write
Burst
Read
Read
Write
Dsel
Read
Burst
Write
Dsel
Dsel
Write
Write
Burst
Dsel
Burst
Burst
Write
Read
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TQFP thermal resistance
Description Conditions Symbol Ty p i c a l Units
Thermal resistance
(junction to ambient)1
1 This parameter is sampled.
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
1–layer θJA 40 °C/W
4–layer θJA 22 °C/W
Thermal resistance
(junction to top of case)1θJC 8°C/W
DC electrical characteristics
Parameter Symbol Test conditions
–166 –150 –133 –100
UnitMin Max Min Max Min Max Min Max
Input leakage
current |ILI|1
1 LBO pin has an internal pull-up and input leakage = ±10 µA.
VDD = Max, VIN = GND to VDD –2–2–2–2µA
Output leakage
current |ILO|OE ≥ VIH, VDD = Max,
VOUT = GND to VDD –2–2–2–2µA
Operating power
supply current ICC2
2 ICC give with no output loading. ICC increases with faster cycle times and greater output loading.
CE0 = VIL, CE1 = VIH, CE2 = VIL,
f = fMax, IOUT = 0 mA – 475 – 425 – 400 – 300 mA
Standby power
supply current
ISB Deselected, f = fMax, ZZ ≤ VIL – 130 – 110 – 100 – 90
mA
ISB1 Deselected, f = 0, ZZ ≤ 0.2V
all VIN ≤ 0.2V or ≥ VDD – 0.2V –30–30–30–30
ISB2
Deselected, f = f
Max
, ZZ
≥
V
DD
– 0.2V
All VIN ≤ VIL or ≥ VIH –30–30–30–30
Output voltage VOL IOL = 8 mA, VDDQ = 3.465V – 0.4 – 0.4 – 0.4 – 0.4 V
VOH IOH = –4 mA, VDDQ = 3.135V 2.4 – 2.4 – 2.4 – 2.4 –
DC electrical characteristics for 2.5V I/O operation
Parameter Symbol Test conditions
–166 –150 –133 –100
UnitMin Max Min Max Min Max Min Max
Output leakage
current |ILO|OE ≥ VIH, VDD = Max,
VOUT = GND to VDD –11–11–11–11µA
Output voltage VOL IOL = 2 mA, VDDQ = 2.65V – 0.7 – 0.7 – 0.7 – 0.7 V
VOH IOH = –2 mA, VDDQ = 2.35V 1.7 – 1.7 – 1.7 – 1.7 –
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Timing characteristics over operating range
Parameter Symbol
-166 H –166 –150 –133 –100
Unit Notes1
1 Refer to “notes” on page 10.
Min Max Min Max Min Max Min Max Min Max
Clock frequency
fMax – 166 – 166 – 150 – 133 – 100 MHz
Cycle time (pipelined mode)
tCYC 6 – 6 – 6.6 – 7.5 – 10 – ns
Cycle time (flow-through mode)
tCYCF 10 – 10 – 10 – 12 – 12 – ns
Clock access time (pipelined mode)- 3.3V V
DDQ
tCD 3.3V–3.0–3.5–3.8–4.0–5.0ns
Clock access time (pipelined mode)- 2.5V V
DDQ
tCD 2.5V–4.0–4.0–4.3–4.5–5.0ns
Clock access time (flow-through mode)
tCDF –9–9–10–10–12ns
Output enable LOW to data valid
tOE –3.5–3.5–3.8–4.0–5.0ns
Clock HIGH to output Low Z
tLZC 0–0–0–0–0–ns2,3,4
Data output invalid from clock HIGH
tOH 1.5 – 1.5 – 1.5 – 1.5 – 1.5 – ns 2
Output enable LOW to output Low Z
tLZOE 0–0–0–0–0–ns2,3,4
Output enable HIGH to output High Z
tHZOE –3.0–3.5–3.8–4.0–4.5ns 2,3,4
Clock HIGH to output High Z
tHZC –3.0–3.5–3.8–4.0–5.0ns 2,3,4
Output enable HIGH to invalid output
tOHOE 0–0–0–0–0–ns
Clock HIGH pulse width
tCH 2.4 – 2.4 – 2.5 – 2.5 – 3.5 – ns 5
Clock LOW pulse width
tCL 2.4 – 2.4 – 2.5 – 2.5 – 3.5 – ns 5
Address setup to clock HIGH
tAS 1.2 – 1.5 – 1.5 – 1.5 – 2.0 – ns 6
Data setup to clock HIGH
tDS 1.2 – 1.5 – 1.5 – 1.5 – 2.0 – ns 6
Write setup to clock HIGH
tWS 1.2 – 1.5 – 1.5 – 1.5 – 2.0 – ns 6,7
Chip select setup to clock HIGH
tCSS 1.2 – 1.5 – 1.5 – 1.5 – 2.0 – ns 6,8
ADV/LD
setup to clock HIGH
tADVS 1.2 – 1.5 – 1.5 – 1.5 – 2.0 – ns 6
Clock enable
setup to clock HIGH
tCENS 1.2 – 1.5 – 1.5 – 1.5 – 2.0 – ns 6
Address hold from clock HIGH
tAH 0.5 – 0.5 – 0.5 – 0.5 – 0.5 – ns 6
Data hold from clock HIGH
tDH 0.5 – 0.5 – 0.5 – 0.5 – 0.5 – ns 6
Write hold from clock HIGH
tWH 0.5 – 0.5 – 0.5 – 0.5 – 0.5 – ns 6,7
Chip select hold from clock HIGH
tCSH 0.5 – 0.5 – 0.5 – 0.5 – 0.5 – ns 6,8
ADV/LD
hold from clock HIGH
tADVH 0.5 – 0.5 – 0.5 – 0.5 – 0.5 – ns 6
Clock enable hold from clock HIGH
tCENH 0.5 – 0.5 – 0.5 – 0.5 – 0.5 – ns 6
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Key to switching waveforms
Timing waveform of read/write cycle
Note: Ý = XOR when LBO = HIGH/No Connect; Ý = ADD when LBO = LOW.
BW[a:b] is don’t care.
Undefined/don’t careFalling inputRising input
W&+ W&<&
W&/
W&(16
W2+
W2(
&/.
&(1
&(&(
$'9/'
5:
$''5(66
'4
2(
&RPPDQG
W+=2(
%:Q
$$ $ $$ $$
'$ '$ 4$
'$
'$Ý
4$
4$
4$Ý0
W&(1+
W'6
W'+ W/=&
W&' W+=&
W/=2(
BURST
WRITE
D(A2Ý01)
READ
Q(A3)
READ
Q(A4)
BURST
READ
Q(A4Ý01)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DSEL
WRITE
D(A1) WRITE
D(A2)
W&66
W$'9+
W:6
W:+
W:6
W:+
t&6+
W$6
W$+
'4
'$ '$ 4$
'$
'$<
4$
4$
4$Ý
SLSHOLQH
IORZWKURXJK
&(
®
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AS7C33512NTD18A
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NOP, stall and deselect cycles
Note: Ý = XOR when LBO = HIGH/No Connect; Ý = ADD when LBO = LOW.
&/.
&(1
&(&(
$'9/'
5:
$''5(66
'4
&RPPDQG
%:Q
$ $
4$ '$
4$Ý
4$Ý
BURST
Q(A1Ý01)
STALL DSEL BURST
DSEL
WRITE
D(A2)
BURST
NOP
D(A2Ý01)
WRITE
NOP
D(A3)
$
'4
4$ '$
4$Ý
4$Ý10
READ
Q(A1)
BURST
Q(A1Ý10)
BURST
D(A2Ý10)
&(
SLSHOLQH
IORZWKRXJK
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AC test conditions
Z
0
= 50
Ω
D
OUT
50
Ω
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
GND
90%
10%
+3.0V
• Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C.
• Input pulse level: GND to 3V. See Figure A.
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
V
L
= 1.5V
for 3.3V I/O;
= V
DDQ
/2
for 2.5V I/O
Thevenin equivalent:
Notes:
1) For test conditions, see “AC Test Conditions”, Figures A, B, C
2) This paracmeter measured with output load conditon in Figure C.
3) This parameter is sampled, but not 100% tested.
4) tHZOE is less than tLZOE and tHZC is less than tLZC at any given temperature and voltage.
5) tCH measured HIGH above VIH and tCL measured as LOW below VIL
6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must mee
t
the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
7) Write refers to R/W, BW[a:d].
8) Chip select refers to CE0, CE1, CE2.
353
Ω/1538Ω
5 pF*
319
Ω/1667Ω
D
OUT
GND
Figure C: Output load(B)
*including scope
and jig capacitance
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
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Package Dimensions
100-pin quad flat pack (TQFP)
TQFP
Min Max
A1 0.05 0.15
A2 1.35 1.45
b0.220.38
c0.090.20
D 13.90 14.10
E 19.90 20.10
e 0.65 nominal
Hd 15.90 16.10
He 21.90 22.10
L0.450.75
L1 1.00 nominal
α0° 7°
Dimensions in millimeters
A1 A2
L1
L
c
He E
Hd
D
b
e
α
119-ball Ball Grid Array (BGA)
All measurements are in mm in
the table. The diagram has
meaurements in inches in
parentheses
Min Typical Max
A - 1.27 -
B 13.80 14.00 14.20
B1 - 7.82 -
C 21.80 22.00 22.20
C1 - 20.23 -
D 0.71 0.76 0.81
E- -2.40
E1 - 0.56 -
E2 0.50 0.60 0.70
F - 12.00 -
F1 - 0.70 -
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© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks
of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development,
significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,
any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties
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Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not
convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-
supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes
all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
®
1. Alliance Semiconductor SRAM prefix
2. Operating voltage: 33=3.3V
3. Organization:
512
=
512
K
4. NTD™ = No-Turn Around Delay. Pipeline-Flowthrough (each device works in both modes)
5. Organization: 16=x16; 18=x18
6. Production version: A=first production version
7. Clock speed (MHz); “H” indicates faster clock access time.
8. Package type: TQ=TQFP; B=BGA
9. Operating temperature: C=Commercial (
0
°
C to 70
°
C); I=Industrial (
-40
°
C to 85
°
C)
Ordering information
Package
&Width -166 H MHz –166 MHz –150 MHz –133 MHz –100 MHz
TQFP x16
AS
7C33512NTD16A
-
166HTQC
AS7C33512NTD16A-
166TQC
AS7C33512NTD16A-
150TQC
AS7C33512NTD16A-
133TQC
AS7C33512NTD16A-
100TQC
TQFP x16
AS
7C33512NTD16A
-
166HTQI
AS7C33512NTD16A-
166TQI
AS7C33512NTD16A-
150TQI
AS7C33512NTD16A-
133TQI
AS7C33512NTD16A-
100TQI
TQFP x18
AS
7C33512NTD18A
-
166HTQC
AS7C33512NTD18A-
166TQC
AS7C33512NTD18A-
150TQC
AS7C33512NTD18A-
133TQC
AS7C33512NTD18A-
100TQC
TQFP x18
AS
7C33512NTD18A
-
166HTQI
AS7C33512NTD18A-
166TQI
AS7C33512NTD18A-
150TQI
AS7C33512NTD18A-
133TQI
AS7C33512NTD18A-
100TQI
BGA x16
AS
7C33512NTD16A
-
166HBC
AS7C33512NTD16A-
166BC
AS7C33512NTD16A-
150BC
AS7C33512NTD16A-
133BC
AS7C33512NTD16A-
100BC
BGA x16
AS
7C33512NTD16A
-
166HBI
AS7C33512NTD16A-
166BI
AS7C33512NTD16A-
150BI
AS7C33512NTD16A-
133BI
AS7C33512NTD16A-
100BI
BGA x18
AS
7C33512NTD18A
-
166HBC
AS7C33512NTD18A-
166BC
AS7C33512NTD18A-
150BC
AS7C33512NTD18A-
133BC
AS7C33512NTD18A-
100BC
BGA x18
AS
7C33512NTD18A
-
166HBI
AS7C33512NTD18A-
166BI
AS7C33512NTD18A-
150BI
AS7C33512NTD18A-
133BI
AS7C33512NTD18A-
100BI
Part numbering guide
AS7C 33 512 NTD 16/18 A–XXX (H) TQ or B C/I
1
23
45678
9
