SN74ABT18652PMG4 - Texas Instruments

SN74ABT18652

SCAN TEST DEVICE

WITH 18-BIT TRANSCEIVER AND REGISTER

SCBS132B – AUGUST 1992 – REVISED JANUAR Y 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Member of the Texas Instruments

Widebus Family

Compatible With IEEE Std 1149.1-1990

(JTAG) Test Access Port and

Boundary-Scan Architecture

Includes D-Type Flip-Flops and Control

Circuitry to Provide Multiplexed

Transmission of Stored and Real-Time Data

Two Boundary-Scan Cells Per I/O for

Greater Flexibility

SCOPE Instruction Set

– IEEE Std 1149.1-1990 Required

Instructions, Optional INTEST, and

P1149.1A CLAMP and HIGHZ

– Parallel Signature Analysis at Inputs

With Masking Option

– Pseudorandom Pattern Generation From

Outputs

– Sample Inputs/Toggle Outputs

– Binary Count From Outputs

– Device Identification

– Even-Parity Opcodes

18 19

21 22 23 24

63 62 61 60 5964 58 56 55 5457

25 26 27 28 29

53 52

51 50 49

30 31 32

1OEBA

GND

1CLKAB

TDO

1A2

1A1

1SAB

1SBA

1OEAB

1B1

1B2

TMS

1CLKBA

GND

1B3

2A9

GND

2SAB

2CLKAB

2A7

2A8

2OEBA

TDI

2CLKBA

2SBA

2OEAB

2B9

TCK

GND

2B8

1A3

1A4

1A5

GND

1A6

1A7

1A8

1A9

VCC

2A1

2A2

2A3

GND

2A4

2A5

2A6

1B4

1B5

1B6

GND

1B7

1B8

1B9

VCC

2B1

2B2

2B3

2B4

GND

2B5

2B6

2B7

PM PACKAGE

(TOP VIEW)

description

This scan test device with an 18-bit bus transceiver and register is a member of the T exas Instruments SCOPE

testability IC family. This device supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex

circuit board assemblies. Scan access to the test circuitry is accomplished via the four-wire test access port

(TAP) interface.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE and Widebus are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

SN74ABT18652

SCAN TEST DEVICE

WITH 18-BIT TRANSCEIVER AND REGISTER

SCBS132B – AUGUST 1992 – REVISED JANUARY 2002

2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

In the normal mode, this device is an 18-bit bus transceiver and register that allows for multiplexed transmission

of data directly from the input bus or from the internal registers. It can be used either as two 9-bit transceivers

or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data

appearing at the device pins or to perform a self-test on the boundary test cells. Activating the T AP in the normal

mode does not affect the functional operation of the SCOPE bus transceivers and registers.

Data flow in each direction is controlled by clock (CLKAB and CLKBA), select (SAB and SBA), and

output-enable (OEAB and OEBA) inputs. For A-to-B data flow , data on the A bus is clocked into the associated

registers on the low-to-high transition of CLKAB. When SAB is low , real-time A data is selected for presentation

to the B bus (transparent mode). When SAB is high, stored A data is selected for presentation to the B bus

(registered mode). When OEAB is high, the B outputs are active. When OEAB is low, the B outputs are in the

high-impedance state. Control for B-to-A data flow is similar to that for A-to-B data flow but uses CLKBA, SBA,

and OEBA inputs. Since the OEBA input is active-low, the A outputs are active when OEBA is low and are in

the high-impedance state when OEBA is high. Figure 1 illustrates the four fundamental bus-management

functions that can be performed with the SN74ABT18652.

In the test mode, the normal operation of the SCOPE bus transceivers and registers is inhibited, and the test

circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can

perform boundary scan test operations according to the protocol described in IEEE Std 1149.1-1990.

Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI),

test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally , the test circuitry can perform

other testing functions, such as parallel signature analysis on data inputs and pseudorandom pattern generation

from data outputs. All testing and scan operations are synchronized to the TAP interface.

Additional flexibility is provided in the test mode through the use of two boundary scan cells (BSCs) for each

I/O pin. This allows independent test data to be captured and forced at either bus (A or B). A PSA/COUNT

instruction is also included to ease the testing of memories and other circuits where a binary count addressing

scheme is useful.

ORDERING INFORMATION

TAPACKAGE†ORDERABLE

PART NUMBER TOP-SIDE

MARKING

–40°C to 85°C LQFP – PM Tray SN74ABT18652PM ABT18652

†Package drawings, standard packing quantities, thermal data, symbolization, and PCB

design guidelines are available at www.ti.com/sc/package.

SN74ABT18652

SCAN TEST DEVICE

WITH 18-BIT TRANSCEIVER AND REGISTER

SCBS132B – AUGUST 1992 – REVISED JANUARY 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLE

(normal mode, each 9-bit section)

INPUTS DATA I/O

OPERATION OR FUNCTION

OEAB OEBA CLKAB CLKBA SAB SBA A1–A9 B1–B9

OPERATION

FUNCTION

L H L L X X Input disabled Input disabled Isolation

L H ↑↑X X Input Input Store A and B data

X H ↑L X X Input Unspecified†Store A, hold B

H H ↑↑X‡X Input Output Store A in both registers

LXL ↑X X Unspecified†Input Hold A, store B

L L ↑↑XX

‡Output Input Store B in both registers

L L X X X L Output Input Real-time B data to A bus

L L X X X H Output Input Stored B data to A bus

H H X X L X Input Output Real-time A data to B bus

H H X X H X Input Output Stored A data to B bus

H L L L H H Output Output Stored A data to B bus and

stored B data to A bus

†The data output functions can be enabled or disabled by a variety of level combinations at the OEAB or OEBA inputs. Data input functions are

always enabled, i.e., data at the bus terminals is stored on every low-to-high transition on the clock inputs.

‡Select control = L: clocks can occur simultaneously.

Select control = H: clocks must be staggered in order to load both registers.

SN74ABT18652

SCAN TEST DEVICE

WITH 18-BIT TRANSCEIVER AND REGISTER

SCBS132B – AUGUST 1992 – REVISED JANUARY 2002

4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

REAL-TIME TRANSFER

BUS B TO BUS A REAL-TIME TRANSFER

BUS A TO BUS B

STORAGE FROM

A, B, OR A AND B TRANSFER STORED DATA

TO A AND/OR B

BUS B

BUS A

BUS B

BUS A

BUS B

BUS A

BUS B

BUS A

OEAB

CLKAB

XCLKBA

XSAB

XSBA

LCLKAB

XCLKBA

XSAB

LSBA

HCLKAB CLKBA

XSAB

XSBA

XCLKAB CLKBA SAB SBA

HXX

HL X HH

↑↑

OEBA

OEAB OEBA

OEAB OEBA X

Figure 1. Bus-Management Functions

SN74ABT18652

SCAN TEST DEVICE

WITH 18-BIT TRANSCEIVER AND REGISTER

SCBS132B – AUGUST 1992 – REVISED JANUARY 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Boundary-Scan Register

One of Nine Channels

1OEAB

1OEBA

1CLKBA

1SBA

1CLKAB

1SAB

1A1 1B1

One of Nine Channels

2OEAB

2OEBA

2CLKBA

2SBA

2CLKAB

2SAB

2A1 2B1

Boundary-Control

Instruction

TDI

TMS

TCK

TDO

TAP

Controller

VCC

Bypass Register

Identification

VCC GND

SN74ABT18652

SCAN TEST DEVICE

WITH 18-BIT TRANSCEIVER AND REGISTER

SCBS132B – AUGUST 1992 – REVISED JANUARY 2002

6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI: Except I/O ports (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O ports (see Note 1) –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high state or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . .

Current into any output in the low state, IO 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θJA (see Note 2) 34°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

MIN MAX UNIT

VCC Supply voltage 4.5 5.5 V

VIH High-level input voltage 2 V

VIL Low-level input voltage 0.8 V

VIInput voltage 0 VCC V

IOH High-level output current –32 mA

IOL Low-level output current 64 mA

∆t/∆vInput transition rise or fall rate 10 ns/V

TAOperating free-air temperature –40 85 °C

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

SN74ABT18652

SCAN TEST DEVICE

WITH 18-BIT TRANSCEIVER AND REGISTER

SCBS132B – AUGUST 1992 – REVISED JANUARY 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Note 4)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

VIK VCC = 4.5 V, II = –18 mA –1.2 V

VCC = 4.5 V, IOH = –3 mA 2.5

VOH

VCC = 5 V, IOH = –3 mA 3

VCC =45V

IOH = –24 mA

CC =

IOH = –32 mA 2

VOL

VCC =45V

IOL = 48 mA

CC =

IOL = 64 mA 0.55

VCC =55V

CLK, OEAB, OEBA, S, TCK ±1

µA

CC =

A or B ports ±100 µ

IIH VCC = 5.5 V, VI = VCC,TDI, TMS 10 µA

IIL VCC = 5.5 V, VI = GND, TDI, TMS –150 µA

IOZH‡VCC = 5.5 V, VO = 2.7 V 50 µA

IOZL‡VCC = 5.5 V, VO = 0.5 V –50 µA

Ioff VCC = 0, VI or VO ≤ 5.5 V ±100 µA

ICEX VCC = 5.5 V, VO = 5.5 V Outputs high 50 µA

IO§VCC = 5.5 V, VO = 2.5 V –50 –200 mA

V55VI0

Outputs high 5.5

ICC VCC = 5.5 V, IO = 0,

VI=V

CC or GND

A or B ports Outputs low 38¶mA

VCC

GND

Outputs disabled 5

∆ICC#VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND 2.5 mA

CiVI = 2.5 V or 0.5 V, Control inputs 3 pF

Cio VO = 2.5 V or 0.5 V, A or B ports 10 pF

CoVO = 2.5 V or 0.5 V, TDO 8 pF

NOTE 4: Preliminary specifications based on SPICE analysis

†All typical values are at VCC = 5 V, TA = 25°C.

‡The parameters IOZH and IOZL include the input leakage current.

§Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

¶If both A and B ports are low, ICCL is 76 mA.

#This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (normal mode) (see Note 4 and Figure 2)

MIN MAX UNIT

fclock Clock frequency CLKAB or CLKBA 100 MHz

twPulse duration CLKAB or CLKBA high or low 4 ns

tsu Setup time A before CLKAB↑ or B before CLKBA↑4.5 ns

thHold time A after CLKAB↑ or B after CLKBA↑0 ns

NOTE 4: Preliminary specifications based on SPICE analysis

SN74ABT18652

SCAN TEST DEVICE

WITH 18-BIT TRANSCEIVER AND REGISTER

SCBS132B – AUGUST 1992 – REVISED JANUARY 2002

8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (test mode) (see Note 4 and Figure 2)123

MIN MAX UNIT

fclock Clock frequency TCK 50 MHz

twPulse duration TCK high or low 8 ns

A, B, CLK, OEAB, OEBA, or S before TCK↑4.5

tsu Setup time TDI before TCK↑7.5 ns

TMS before TCK↑3

A or B after TCK↑1

Hold time

CLK, OEAB, OEBA, or S after TCK↑0

Hold

time

TDI after TCK↑0.5

TMS after TCK↑0.5

tdDelay time Power up to TCK↑50 ns

trRise time VCC power up 1µs

NOTE 4: Preliminary specifications based on SPICE analysis

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (normal mode) (see Note 4 and Figure 2)

PARAMETER FROM

(INPUT) TO

(OUTPUT) MIN MAX UNIT

fmax CLKAB or CLKBA 100 MHz

tPLH

AorB

BorA

2 5.4

tPHL

2 6.6

tPLH

CLKAB or CLKBA

BorA

2.5 8

tPHL

CLKAB

CLKBA

2.5 7.4

tPLH

SAB or SBA

BorA

2 7.5

tPHL

SAB

SBA

2 8

tPZH

OEAB

2.5 8.6

tPZL

OEAB

3 9.3

tPZH

OEBA

2 6.9

tPZL

OEBA

2.5 7.9

tPHZ

OEAB

3 10.5

tPLZ

OEAB

2 8.5

tPHZ

OEBA

3 8.4

tPLZ

OEBA

1.5 6.5

NOTE 4: Preliminary specifications based on SPICE analysis

SN74ABT18652

SCAN TEST DEVICE

WITH 18-BIT TRANSCEIVER AND REGISTER

SCBS132B – AUGUST 1992 – REVISED JANUARY 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (test mode) (see Note 4 and Figure 2)123

PARAMETER FROM

(INPUT) TO

(OUTPUT) MIN MAX UNIT

fmax TCK 50 MHz

tPLH

TCK↓

AorB

2.5 13.5

tPHL

TCK↓

2.5 12.5

tPLH

TCK↓

TDO

2 6.5

tPHL

TCK↓

TDO

2 6.5

tPZH

TCK↓

AorB

4.5 14.2

tPZL

TCK↓

5 15.5

tPZH

TCK↓

TDO

2 7

tPZL

TCK↓

TDO

3 7.5

tPHZ

TCK↓

AorB

4 17

tPLZ

TCK↓

3 16

tPHZ

TCK↓

TDO

3 9

tPLZ

TCK↓

TDO

3 7.5

NOTE 4: Preliminary specifications based on SPICE analysis

SN74ABT18652

SCAN TEST DEVICE

WITH 18-BIT TRANSCEIVER AND REGISTER

SCBS132B – AUGUST 1992 – REVISED JANUARY 2002

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

1.5 V

tsu

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

7 V

Open

GND

500 Ω

Data Input

Timing Input 1.5 V 3 V

0 V

1.5 V 1.5 V

3 V

0 V

3 V

0 V

1.5 V

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

tPLH

tPHL

tPLH

VOH

VOL

1.5 V 1.5 V 3 V

0 V

1.5 V1.5 V

Input

1.5 V

Output

Control

Output

W aveform 1

S1 at 7 V

(see Note B)

Output

W aveform 2

S1 at Open

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

1.5 V1.5 V

3.5 V

0 V

1.5 V VOL + 0.3 V

1.5 V VOH – 0.3 V

≈0 V

3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

7 V

Open

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2. 5 n s , tf≤ 2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

1.5 V

Figure 2. Load Circuit and Voltage Waveforms

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

SN74ABT18652PM ACTIVE LQFP PM 64 160 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

SN74ABT18652PMG4 ACTIVE LQFP PM 64 160 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 18-Sep-2008

Addendum-Page 1

MECHANICAL DATA

MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PM (S-PQFP-G64) PLASTIC QUAD FLATPACK

4040152/C 1 1/96

17 0,13 NOM

0,25

0,45

0,75

Seating Plane

0,05 MIN

Gage Plane

0,27

0,17

10,20

11,80

12,20

9,80

7,50 TYP

1,60 MAX

1,45

1,35

0,08

0,50 M

0,08

0°–7°

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

D. May also be thermally enhanced plastic with leads connected to the die pads.

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