SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O - APRIL 1998 - REVISED JANUARY 2011 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER OE RCLK SRCLK SRCLR QH QC QD QE QF QG QH 16 QC QB 1 15 2 3 14 4 13 5 12 6 11 7 10 8 9 QD QE NC QF QG QA SER OE RCLK SRCLK SRCLR 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 SER OE NC RCLK SRCLK SRCLR 16 GND NC QH 1 SN54LV595A . . . FK PACKAGE (TOP VIEW) QH QB QC QD QE QF QG QH GND SN74LV595A . . . RGY PACKAGE (TOP VIEW) VCC SN54LV595A . . . J OR W PACKAGE SN74LV595A . . . D, DB, NS, OR PW PACKAGE (TOP VIEW) QH D D QB D Operation Shift Register Has Direct Clear Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) D D <0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25C Support Mixed-Mode Voltage Operation on All Ports 8-Bit Serial-In, Parallel-Out Shift GND D D Ioff Supports Partial-Power-Down Mode NC VCC QA D 2-V to 5.5-V VCC Operation D Max tpd of 7.1 ns at 5 V D Typical VOLP (Output Ground Bounce) NC - No internal connection description/ordering information The 'LV595A devices are 8-bit shift registers designed for 2-V to 5.5-V VCC operation. ORDERING INFORMATION PACKAGE TA QFN - RGY SN74LV595ARGYR Tube of 40 SN74LV595ADG3 Reel of 2500 SN74LV595ADR SOP - NS Reel of 2000 SN74LV595ANSR 74LV595A SSOP - DB Reel of 2000 SN74LV595ADBR LV595A Tube of 90 SN74LV595APW Reel of 2000 SN74LV595APWRG3 Reel of 250 SN74LV595APWT CDIP - J Tube of 25 SNJ54LV595AJ SNJ54LV595AJ CFP - W Tube of 150 SNJ54LV595AW SNJ54LV595AW LCCC - FK Tube of 55 SNJ54LV595AFK SNJ54LV595AFK TSSOP - PW -55C to 125C TOP-SIDE MARKING Reel of 1000 SOIC - D -40C 40C to 85C ORDERABLE PART NUMBER LV595A LV595A LV595A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright (c) 2005-2011, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O - APRIL 1998 - REVISED JANUARY 2011 description/ordering information (continued) These devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable (OE) input is high, all outputs except QH are in the high-impedance state. Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. FUNCTION TABLE INPUTS 2 SER SRCLK X X X X X X L SRCLR FUNCTION RCLK OE X X H Outputs QA-QH are disabled. X X L Outputs QA-QH are enabled. L X X Shift register is cleared. H X X First stage of the shift register goes low. Other stages store the data of previous stage, respectively. H H X X First stage of the shift register goes high. Other stages store the data of previous stage, respectively. X X X X Shift-register data is stored in the storage register. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O - APRIL 1998 - REVISED JANUARY 2011 logic diagram (positive logic) OE RCLK SRCLR SRCLK SER 13 12 10 11 14 1D Q C1 R 3D C3 Q 15 2D Q C2 R 3D C3 Q 1 2D Q C2 R 3D C3 Q 2 2D Q C2 R 3D C3 Q 3 2D Q C2 R 3D C3 Q 4 2D Q C2 R 3D C3 Q 5 2D Q C2 R 3D C3 Q 6 2D Q C2 R 3D C3 Q 7 9 QA QB QC QD QE QF QG QH QH Pin numbers shown are for the D, DB, J, NS, PW, RGY, and W packages. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O - APRIL 1998 - REVISED JANUARY 2011 timing diagram SRCLK SER RCLK SRCLR OE IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII QA QB QC QD QE QF QG QH QH NOTE: 4 IIII implies that the output is in 3-State mode. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O - APRIL 1998 - REVISED JANUARY 2011 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Output voltage range applied in the high or low state, VO (see Notes 1 and 2) . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82C/W (see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64C/W (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108C/W (see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. The package thermal impedance is calculated in accordance with JESD 51-5. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O - APRIL 1998 - REVISED JANUARY 2011 recommended operating conditions (see Note 5) SN54LV595A VCC Supply voltage VCC = 2 V VIH High level input voltage High-level MIN MAX 2 5.5 1.5 Low level input voltage Low-level VI Input voltage VO Output voltage VCC x 0.7 VCC x 0.7 VCC = 4.5 V to 5.5 V VCC x 0.7 VCC x 0.7 t/v Input transition rise or fall rate 0.5 TA 0.5 VCC x 0.3 VCC x 0.3 VCC = 3 V to 3.6 V VCC x 0.3 VCC x 0.3 VCC x 0.3 5.5 0 5.5 High or low state 0 VCC 0 VCC 3-state 0 5.5 0 5.5 -50 -50 VCC = 2.3 V to 2.7 V -2 -2 VCC = 3 V to 3.6 V -8 -8 -16 -16 50 50 VCC = 2.3 V to 2.7 V 2 2 VCC = 3 V to 3.6 V 8 8 VCC = 4.5 V to 5.5 V 16 16 VCC = 2.3 V to 2.7 V 200 200 VCC = 3 V to 3.6 V 100 100 20 20 Operating free-air temperature -55 125 V VCC x 0.3 0 VCC = 4.5 V to 5.5 V V V VCC = 2.3 V to 2.7 V VCC = 2 V Low level output current Low-level 5.5 VCC x 0.7 VCC = 4.5 V to 5.5 V IOL 2 UNIT 1.5 VCC x 0.7 VCC = 2 V High level output current High-level MAX VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V IOH MIN VCC = 2.3 V to 2.7 V VCC = 2 V VIL SN74LV595A -40 85 V V A mA A mA ns/V C NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O - APRIL 1998 - REVISED JANUARY 2011 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS SN54LV595A VCC MIN IOH = -50 A 2 V to 5.5 V IOH = -2 mA 2.3 V QH IOH = -6 mA QA-QH IOH = -8 mA QH IOH = -12 mA QA-QH IOH = -16 mA TYP SN74LV595A MAX VCC-0.1 3V 45V 4.5 MIN TYP MAX VCC-0.1 2 2 2.48 2.48 2.48 2.48 3.8 3.8 3.8 3.8 V IOL = 50 A 2 V to 5.5 V 0.1 0.1 IOL = 2 mA 2.3 V 0.4 0.4 0.44 0.44 0.44 0.44 0.55 0.55 QH IOL = 6 mA QA-QH IOL = 8 mA QH IOL = 12 mA QA-QH IOL = 16 mA 3V 45V 4.5 II VI = 5.5 V or GND IOZ VO = VCC or GND, ICC VI = VCC or GND, Ioff VI or VO = 0 to 5.5 V Ci VI = VCC or GND UNIT V 0.55 0.55 0 to 5.5 V 1 1 A QA-QH 5.5 V 5 5 A IO = 0 5.5 V 20 20 A 0 5 5 A 3.3 V 3.5 3.5 pF timing requirements over recommended operating free-air temperature range, VCC = 2.5 V 0.2 V (unless otherwise noted) (see Figure 1) TA = 25C MIN tw Pulse duration Setup time th Hold time MAX MIN 7 7.5 7.5 RCLK high or low 7 7.5 7.5 SRCLR low 6 6.5 6.5 5.5 5.5 5.5 SRCLK before RCLK SRCLR low before RCLK SRCLR high (inactive) before SRCLK MIN SN74LV595A SRCLK high or low SER before SRCLK tsu MAX SN54LV595A SER after SRCLK 8 9 9 8.5 9.5 9.5 4 4 4 1.5 1.5 1.5 MAX UNIT ns ns ns This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O - APRIL 1998 - REVISED JANUARY 2011 timing requirements over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1) TA = 25C MIN tw Pulse duration th Hold time MAX SN74LV595A MIN 5.5 5.5 5.5 5.5 5.5 5.5 5 5 5 3.5 3.5 3.5 SRCLK before RCLK 8 8.5 8.5 SRCLR low before RCLK 8 9 9 SRCLR high (inactive) before SRCLK MIN RCLK high or low SER before SRCLK Setup time SN54LV595A SRCLK high or low SRCLR low tsu MAX SER after SRCLK 3 3 3 1.5 1.5 1.5 MAX UNIT ns ns ns This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register. timing requirements over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1) TA = 25C MIN tw Pulse duration Setup time th Hold time MAX SN74LV595A MIN 5 5 5 5 5 5.2 5.2 5.2 SER before SRCLK 3 3 3 SRCLK before RCLK 5 5 5 SRCLR low before RCLK 5 5 5 2.5 2.5 2.5 2 2 2 SER after SRCLK MAX UNIT 5 ns ns ns This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 8 MIN RCLK high or low SRCLR high (inactive) before SRCLK SN54LV595A SRCLK high or low SRCLR low tsu MAX POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O - APRIL 1998 - REVISED JANUARY 2011 switching characteristics over recommended operating VCC = 2.5 V 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tPLH tPHL tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ RCLK QH SRCLR QH OE QH QA-Q OE QA-Q QH RCLK QA-Q QH SRCLK QH SRCLR QH OE OE TA = 25C temperature SN54LV595A SN74LV595A LOAD CAPACITANCE MIN TYP CL = 15 pF 65* 80* 45* 45 CL = 50 pF 60 70 40 40 QH QA-Q SRCLK free-air CL = 15 p pF MAX MIN MAX MIN MAX 8.4* 14.2* 1* 15.8* 1 15.8 8.4* 14.2* 1* 15.8* 1 15.8 9.4* 19.6* 1* 22.2* 1 22.2 9.4* 19.6* 1* 22.2* 1 22.2 8.7* 14.6* 1* 16.3* 1 16.3 8.2* 13.9* 1* 15* 1 15 18.1* 1* 20.3* 1 20.3 8.3* 13.7* 1* 15.6* 1 15.6 QA-Q QH QH QA-Q UNIT MHz 10.9* CL = 50 p pF range, 9.2* 15.2* 1* 16.7* 1 16.7 11.2 17.2 1 19.3 1 19.3 11.2 17.2 1 19.3 1 19.3 13.1 22.5 1 25.5 1 25.5 13.1 22.5 1 25.5 1 25.5 12.4 18.8 1 21.1 1 21.1 10.8 17 1 18.3 1 18.3 13.4 21 1 23 1 23 12.2 18.3 1 19.5 1 19.5 14 20.9 1 22.6 1 22.6 ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O - APRIL 1998 - REVISED JANUARY 2011 switching characteristics over recommended operating VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tPLH tPHL tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ RCLK QH SRCLR QH OE QH QA-Q OE SRCLK QH SRCLR QH OE CL = 15 pF 80* 120* 70* 70 CL = 50 pF 55 105 50 50 CL = 50 pF p QA-Q QH QH QA-Q MIN MAX MIN MAX 1* 13.5* 1 13.5 6* 11.9* 1* 13.5* 1 13.5 6.6* 13* 1* 15* 1 15 6.6* 13* 1* 15* 1 15 6.2* 12.8* 1* 13.7* 1 13.7 6* 11.5* 1* 13.5* 1 13.5 7.8* 11.5* 1* 13.5* 1 13.5 6.1* 14.7* 1* 15.2* 1 15.2 6.3* 14.7* 1* 15.2* 1 15.2 7.9 15.4 1 17 1 17 7.9 15.4 1 17 1 17 9.2 16.5 1 18.5 1 18.5 9.2 16.5 1 18.5 1 18.5 9 16.3 1 17.2 1 17.2 7.8 15 1 17 1 17 9.6 15 1 17 1 17 8.1 15.7 1 16.2 1 16.2 9.3 15.7 1 16.2 1 16.2 * DALLAS, TEXAS 75265 range, UNIT MHz 11.9* PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 MAX 6* * On products compliant to MIL-PRF-38535, this parameter is not production tested. 10 SN74LV595A TYP QA-Q QH QA-Q QH SN54LV595A MIN CL = 15 pF p RCLK OE TA = 25C temperature LOAD CAPACITANCE QH QA-Q SRCLK free-air ns ns SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O - APRIL 1998 - REVISED JANUARY 2011 switching characteristics over recommended operating VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tPLH tPHL tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ RCLK TA = 25C QH SRCLR QH OE QH QA-Q OE QA-Q QH SRCLK QH SRCLR QH OE SN74LV595A TYP CL = 15 pF 135* 170* 115* 115 CL = 50 pF 120 140 95 95 CL = 15 p pF CL = 50 p pF QA-Q QH OE SN54LV595A MIN QA-Q QH RCLK temperature LOAD CAPACITANCE QH QA-Q SRCLK free-air QH QA-Q MAX MIN MAX MIN MAX range, UNIT MHz 4.3* 7.4* 1* 8.5* 1 8.5 4.3* 7.4* 1* 8.5* 1 8.5 4.5* 8.2* 1* 9.4* 1 9.4 4.5* 8.2* 1* 9.4* 1 9.4 4.5* 8* 1* 9.1* 1 9.1 4.3* 8.6* 1* 10* 1 10 5.4* 8.6* 1* 10* 1 10 2.4* 6* 1* 7.1* 1 7.1 2.7* 5.1* 1* 7.2* 1 7.2 5.6 9.4 1 10.5 1 10.5 5.6 9.4 1 10.5 1 10.5 6.4 10.2 1 11.4 1 11.4 6.4 10.2 1 11.4 1 11.4 6.4 10 1 11.1 1 11.1 5.7 10.6 1 12 1 12 6.8 10.6 1 12 1 12 3.5 10.3 1 11 1 11 3.4 10.3 1 11 1 11 ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25C (see Note 6) SN74LV595A PARAMETER MIN TYP MAX UNIT VOL(P) Quiet output, maximum dynamic VOL 0.3 V VOL(V) Quiet output, minimum dynamic VOL -0.2 V VOH(V) Quiet output, minimum dynamic VOH 2.8 V VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage 2.31 V 0.99 V UNIT NOTE 6: Characteristics are for surface-mount packages only. operating characteristics, TA = 25C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = 50 pF, pF f = 10 MHz VCC TYP 3.3 V 111 5V 114 pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O - APRIL 1998 - REVISED JANUARY 2011 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point RL = 1 k From Output Under Test CL (see Note A) S1 VCC Open TEST GND CL (see Note A) tw 50% VCC 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC tPLH In-Phase Output tPHL Out-of-Phase Output 0V VCC Output Control 50% VCC tPHL 50% VCC tPZL VOH 50% VCC VOL tPLH VOH 50% VCC 50% VCC 0V VOLTAGE WAVEFORMS PULSE DURATION 50% VCC VCC 50% VCC Data Input 0V th tsu VCC 50% VCC VCC 50% VCC Timing Input Input Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS Input S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) 0V tPLZ 50% VCC VCC VOL + 0.3 V VOL tPHZ tPZH VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 50% VCC VOH - 0.3 V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 3 ns, tf 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 11-Feb-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV595ADE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV595ADG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV595ADR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV595ADRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV595ADRG3 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) SN74LV595ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV595ANSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV595ANSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV595ANSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV595APWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV595APWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV595APWRG3 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) SN74LV595APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV595APWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV595APWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV595APWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 CU SN Samples (Requires Login) SN74LV595AD CU SN (3) Level-1-260C-UNLIM Level-1-260C-UNLIM PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 11-Feb-2011 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) SN74LV595ARGYR ACTIVE VQFN RGY 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN74LV595ARGYRG4 ACTIVE VQFN RGY 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF SN74LV595A : * Automotive: SN74LV595A-Q1 * Enhanced Product: SN74LV595A-EP NOTE: Qualified Version Definitions: Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 11-Feb-2011 * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects * Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74LV595ADRG4 Package Package Pins Type Drawing SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74LV595ANSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74LV595APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV595APWR TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 SN74LV595APWRG3 TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 SN74LV595APWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV595APWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV595ARGYR VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV595ADRG4 SN74LV595ANSR SOIC D 16 2500 333.2 345.9 28.6 SO NS 16 2000 367.0 367.0 38.0 SN74LV595APWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74LV595APWR TSSOP PW 16 2000 364.0 364.0 27.0 SN74LV595APWRG3 TSSOP PW 16 2000 364.0 364.0 27.0 SN74LV595APWRG4 TSSOP PW 16 2000 367.0 367.0 35.0 SN74LV595APWT TSSOP PW 16 250 367.0 367.0 35.0 SN74LV595ARGYR VQFN RGY 16 3000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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