SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414O − APRIL 1998 − REVISED JANUARY 2011
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D2-V to 5.5-V VCC Operation
DMax tpd of 7.1 ns at 5 V
DTypical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
DTypical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
DSupport Mixed-Mode Voltage Operation on
All Ports
D8-Bit Serial-In, Parallel-Out Shift
DIoff Supports Partial-Power-Down Mode
Operation
DShift Register Has Direct Clear
DLatch-Up Performance Exceeds 250 mA Per
JESD 17
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SN54LV595A ...J OR W PACKAGE
SN74LV595A . . . D, DB, NS,
OR PW PACKAGE
(TOP VIEW)
SN54LV595A . . . FK PACKAGE
(TOP VIEW)
NC − No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
QB
QC
QD
QE
QF
QG
QH
GND
VCC
QA
SER
OE
RCLK
SRCLK
SRCLR
QH′
3212019
910111213
4
5
6
7
8
18
17
16
15
14
SER
OE
NC
RCLK
SRCLK
QD
QE
NC
QF
QG
Q
NC
SRCLR
H
GND
NC
C
QB
VCC
QA
Q
H
Q′
SN74LV595A . . . RGY PACKAGE
(TOP VIEW)
116
89
2
3
4
5
6
7
15
14
13
12
11
10
QA
SER
OE
RCLK
SRCLK
SRCLR
QC
QD
QE
QF
QG
QH
Q
Q V
GND
CC
B
H′
description/ordering information
The ’LV595A devices are 8-bit shift registers designed for 2-V to 5.5-V VCC operation.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN − RGY Reel of 1000 SN74LV595ARGYR LV595A
SOIC D
Tube of 40 SN74LV595ADG3
LV595A
SOIC − D Reel of 2500 SN74LV595ADR LV595A
40°C to 85°C
SOP − NS Reel of 2000 SN74LV595ANSR 74LV595A
−40°C to 85°CSSOP − DB Reel of 2000 SN74LV595ADBR LV595A
Tube of 90 SN74LV595APW
TSSOP − PW Reel of 2000 SN74LV595APWRG3 LV595A
TSSOP PW
Reel of 250 SN74LV595APWT
LV595A
CDIP − J Tube of 25 SNJ54LV595AJ SNJ54LV595AJ
−55°C to 125°CCFP − W Tube of 150 SNJ54LV595AW SNJ54LV595AW
LCCC − FK Tube of 55 SNJ54LV595AFK SNJ54LV595AFK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright © 2005−2011, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414O − APRIL 1998 − REVISED JANUARY 2011
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
These devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register.
The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage
register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output
for cascading. When the output-enable (OE) input is high, all outputs except QH′ are in the high-impedance
state.
Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both
clocks are connected together, the shift register always is one clock pulse ahead of the storage register.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
INPUTS
FUNCTION
SER SRCLK SRCLR RCLK OE FUNCTION
X X X X H Outputs QA−QH are disabled.
XX X X L Outputs QA−QH are enabled.
XX L X X Shift register is cleared.
L↑H X X First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
H↑H X X First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
X X X ↑XShift-register data is stored in the storage register.
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414O − APRIL 1998 − REVISED JANUARY 2011
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
3D
C3
1D
C1
R
3D
C3
2D
C2
R
3D
C3
2D
C2
R
3D
C3
2D
C2
R
3D
C3
2D
C2
R
3D
C3
2D
C2
R
3D
C3
2D
C2
R
3D
C3
2D
C2
R
13
12
10
11
14
15
1
2
3
4
5
6
7
9
QA
QB
QC
QD
QE
QF
QG
QH
QH′
OE
SRCLR
RCLK
SRCLK
SER
Pin numbers shown are for the D, DB, J, NS, PW, RGY, and W packages.
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414O − APRIL 1998 − REVISED JANUARY 2011
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing diagram
SRCLK
SER
RCLK
SRCLR
OE
ÎÎÎÎÎ
ÎÎÎÎÎ
QA
ÎÎÎÎÎ
ÎÎÎÎÎ
QB
ÎÎÎÎÎ
ÎÎÎÎÎ
QC
ÎÎÎÎÎ
ÎÎÎÎÎ
QD
ÎÎÎÎÎ
ÎÎÎÎÎ
QE
ÎÎÎÎÎ
ÎÎÎÎÎ
QF
ÎÎÎÎÎ
ÎÎÎÎÎ
QG
ÎÎÎÎÎ
ÎÎÎÎÎ
QH
QH′
ÎÎÎÎ
implies that the output is in 3-State mode.NOTE:
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414O − APRIL 1998 − REVISED JANUARY 2011
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range applied in the high or low state, VO (see Notes 1 and 2) −0.5 V to VCC + 0.5 V. . . . . .
Input clamp current, IIK (VI < 0) −20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): DB package 82°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): NS package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 4): RGY package 39°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414O − APRIL 1998 − REVISED JANUARY 2011
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 5)
SN54LV595A SN74LV595A
UNIT
MIN MAX MIN MAX UNIT
VCC Supply voltage 2 5.5 2 5.5 V
VCC = 2 V 1.5 1.5
V
VCC = 2.3 V to 2.7 V VCC ×0.7 VCC ×0.7
V
VIH High-level input voltage VCC = 3 V to 3.6 V VCC ×0.7 VCC ×0.7 V
VCC = 4.5 V to 5.5 V VCC ×0.7 VCC ×0.7
VCC = 2 V 0.5 0.5
V
VCC = 2.3 V to 2.7 V VCC ×0.3 VCC ×0.3
V
VIL Low-level input voltage VCC = 3 V to 3.6 V VCC ×0.3 VCC ×0.3 V
VCC = 4.5 V to 5.5 V VCC ×0.3 VCC ×0.3
VIInput voltage 0 5.5 0 5.5 V
V
High or low state 0 VCC 0 VCC
V
VOOutput voltage 3-state 0 5.5 0 5.5 V
VCC = 2 V −50 −50 μA
I
VCC = 2.3 V to 2.7 V −2−2
IOH High-level output current VCC = 3 V to 3.6 V −8−8mA
VCC = 4.5 V to 5.5 V −16 −16
mA
VCC = 2 V 50 50 μA
I
VCC = 2.3 V to 2.7 V 2 2
IOL Low-level output current VCC = 3 V to 3.6 V 8 8 mA
VCC = 4.5 V to 5.5 V 16 16
mA
VCC = 2.3 V to 2.7 V 200 200
Δt/ΔvInput transition rise or fall rate VCC = 3 V to 3.6 V 100 100 ns/V
Δt/Δv
VCC = 4.5 V to 5.5 V 20 20
ns/V
TAOperating free-air temperature −55 125 −40 85 °C
NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414O − APRIL 1998 − REVISED JANUARY 2011
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
V
SN54LV595A SN74LV595A
UNIT
PARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN TYP MAX UNIT
IOH = −50 μA2 V to 5.5 V VCC−0.1 VCC−0.1
IOH = −2 mA 2.3 V 2 2
V
QH′IOH = −6 mA
3 V
2.48 2.48
V
VOH QA−QHIOH = −8 mA 3 V 2.48 2.48 V
QH′IOH = −12 mA
45 V
3.8 3.8
QA−QHIOH = −16 mA 4.5 V 3.8 3.8
IOL = 50 μA2 V to 5.5 V 0.1 0.1
IOL = 2 mA 2.3 V 0.4 0.4
V
QH′IOL = 6 mA
3 V
0.44 0.44
V
VOL QA−QHIOL = 8 mA 3 V 0.44 0.44 V
QH′IOL = 12 mA
45 V
0.55 0.55
QA−QHIOL = 16 mA 4.5 V 0.55 0.55
IIVI = 5.5 V or GND 0 to 5.5 V ±1±1μA
IOZ VO = VCC or GND, QA−QH5.5 V ±5±5μA
ICC VI = VCC or GND, IO = 0 5.5 V 20 20 μA
Ioff VI or VO = 0 to 5.5 V 0 5 5 μA
CiVI = VCC or GND 3.3 V 3.5 3.5 pF
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ±0.2 V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54LV595A SN74LV595A
UNIT
MIN MAX MIN MAX MIN MAX UNIT
SRCLK high or low 7 7.5 7.5
twPulse duration RCLK high or low 7 7.5 7.5 ns
tw
Pulse duration
SRCLR low 6 6.5 6.5
ns
SER before SRCLK↑5.5 5.5 5.5
t
Setup time
SRCLK↑ before RCLK↑†8 9 9
ns
tsu Setup time SRCLR low before RCLK↑8.5 9.5 9.5 ns
SRCLR high (inactive) before SRCLK↑4 4 4
thHold time SER after SRCLK↑1.5 1.5 1.5 ns
†This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414O − APRIL 1998 − REVISED JANUARY 2011
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ±0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54LV595A SN74LV595A
UNIT
MIN MAX MIN MAX MIN MAX UNIT
SRCLK high or low 5.5 5.5 5.5
twPulse duration RCLK high or low 5.5 5.5 5.5 ns
tw
Pulse duration
SRCLR low 5 5 5
ns
SER before SRCLK↑3.5 3.5 3.5
t
Setup time
SRCLK↑ before RCLK↑†8 8.5 8.5
ns
tsu Setup time SRCLR low before RCLK↑8 9 9 ns
SRCLR high (inactive) before SRCLK↑3 3 3
thHold time SER after SRCLK↑1.5 1.5 1.5 ns
†This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
timing requirements over recommended operating free-air temperature range, VCC = 5 V ±0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54LV595A SN74LV595A
UNIT
MIN MAX MIN MAX MIN MAX UNIT
SRCLK high or low 5 5 5
twPulse duration RCLK high or low 5 5 5 ns
tw
Pulse duration
SRCLR low 5.2 5.2 5.2
ns
SER before SRCLK↑3 3 3
t
Setup time
SRCLK↑ before RCLK↑†5 5 5
ns
tsu Setup time SRCLR low before RCLK↑5 5 5 ns
SRCLR high (inactive) before SRCLK↑2.5 2.5 2.5
thHold time SER after SRCLK↑2 2 2 ns
†This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414O − APRIL 1998 − REVISED JANUARY 2011
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO LOAD TA = 25°C SN54LV595A SN74LV595A
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE MIN TYP MAX MIN MAX MIN MAX UNIT
f
CL = 15 pF 65* 80* 45* 45
MHz
fmax CL = 50 pF 60 70 40 40 MHz
tPLH
RCLK
Q Q
8.4* 14.2* 1* 15.8* 1 15.8
tPHL
RCLK QA−QH8.4* 14.2* 1* 15.8* 1 15.8
tPLH
SRCLK
Q
9.4* 19.6* 1* 22.2* 1 22.2
tPHL
SRCLK QH′9.4* 19.6* 1* 22.2* 1 22.2
tPHL SRCLR QH′CL = 15 pF 8.7* 14.6* 1* 16.3* 1 16.3 ns
tPZH
OE
Q Q
Lp
8.2* 13.9* 1* 15* 1 15
tPZL
OE QA−QH10.9* 18.1* 1* 20.3* 1 20.3
tPHZ
OE
Q Q
8.3* 13.7* 1* 15.6* 1 15.6
tPLZ
OE QA−QH9.2* 15.2* 1* 16.7* 1 16.7
tPLH
RCLK
Q Q
11.2 17.2 1 19.3 1 19.3
tPHL
RCLK QA−QH11.2 17.2 1 19.3 1 19.3
tPLH
SRCLK
Q
13.1 22.5 1 25.5 1 25.5
tPHL
SRCLK QH′13.1 22.5 1 25.5 1 25.5
tPHL SRCLR QH′CL = 50 pF 12.4 18.8 1 21.1 1 21.1 ns
tPZH
OE
Q Q
Lp
10.8 17 1 18.3 1 18.3
tPZL
OE QA−QH13.4 21 1 23 1 23
tPHZ
OE
Q Q
12.2 18.3 1 19.5 1 19.5
tPLZ
OE QA−QH14 20.9 1 22.6 1 22.6
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414O − APRIL 1998 − REVISED JANUARY 2011
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ±0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO LOAD TA = 25°C SN54LV595A SN74LV595A
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE MIN TYP MAX MIN MAX MIN MAX UNIT
f
CL = 15 pF 80* 120* 70* 70
MHz
fmax CL = 50 pF 55 105 50 50 MHz
tPLH
RCLK
Q Q
6* 11.9* 1* 13.5* 1 13.5
tPHL
RCLK QA−QH6* 11.9* 1* 13.5* 1 13.5
tPLH
SRCLK
Q
6.6* 13* 1* 15* 1 15
tPHL
SRCLK QH′6.6* 13* 1* 15* 1 15
tPHL SRCLR QH′CL = 15 pF 6.2* 12.8* 1* 13.7* 1 13.7 ns
tPZH
OE
Q Q
Lp
6* 11.5* 1* 13.5* 1 13.5
tPZL
OE QA−QH7.8* 11.5* 1* 13.5* 1 13.5
tPHZ
OE
Q Q
6.1* 14.7* 1* 15.2* 1 15.2
tPLZ
OE QA−QH6.3* 14.7* 1* 15.2* 1 15.2
tPLH
RCLK
Q Q
7.9 15.4 1 17 1 17
tPHL
RCLK QA−QH7.9 15.4 1 17 1 17
tPLH
SRCLK
Q
9.2 16.5 1 18.5 1 18.5
tPHL
SRCLK QH′9.2 16.5 1 18.5 1 18.5
tPHL SRCLR QH′CL = 50 pF 9 16.3 1 17.2 1 17.2 ns
tPZH
OE
Q Q
Lp
7.8 15 1 17 1 17
tPZL
OE QA−QH9.6 15 1 17 1 17
tPHZ
OE
Q Q
8.1 15.7 1 16.2 1 16.2
tPLZ
OE QA−QH9.3 15.7 1 16.2 1 16.2
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414O − APRIL 1998 − REVISED JANUARY 2011
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ±0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO LOAD TA = 25°C SN54LV595A SN74LV595A
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE MIN TYP MAX MIN MAX MIN MAX UNIT
f
CL = 15 pF 135* 170* 115* 115
MHz
fmax CL = 50 pF 120 140 95 95 MHz
tPLH
RCLK
Q Q
4.3* 7.4* 1* 8.5* 1 8.5
tPHL
RCLK QA−QH4.3* 7.4* 1* 8.5* 1 8.5
tPLH
SRCLK
Q
4.5* 8.2* 1* 9.4* 1 9.4
tPHL
SRCLK QH′4.5* 8.2* 1* 9.4* 1 9.4
tPHL SRCLR QH′CL = 15 pF 4.5* 8* 1* 9.1* 1 9.1 ns
tPZH
OE
Q Q
Lp
4.3* 8.6* 1* 10* 1 10
tPZL
OE QA−QH5.4* 8.6* 1* 10* 1 10
tPHZ
OE
Q Q
2.4* 6* 1* 7.1* 1 7.1
tPLZ
OE QA−QH2.7* 5.1* 1* 7.2* 1 7.2
tPLH
RCLK
Q Q
5.6 9.4 1 10.5 1 10.5
tPHL
RCLK QA−QH5.6 9.4 1 10.5 1 10.5
tPLH
SRCLK
Q
6.4 10.2 1 11.4 1 11.4
tPHL
SRCLK QH′6.4 10.2 1 11.4 1 11.4
tPHL SRCLR QH′CL = 50 pF 6.4 10 1 11.1 1 11.1 ns
tPZH
OE
Q Q
Lp
5.7 10.6 1 12 1 12
tPZL
OE QA−QH6.8 10.6 1 12 1 12
tPHZ
OE
Q Q
3.5 10.3 1 11 111
tPLZ
OE QA−QH3.4 10.3 1 11 111
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 6)
PARAMETER
SN74LV595A
UNIT
PARAMETER MIN TYP MAX UNIT
VOL(P) Quiet output, maximum dynamic VOL 0.3 V
VOL(V) Quiet output, minimum dynamic VOL −0.2 V
VOH(V) Quiet output, minimum dynamic VOH 2.8 V
VIH(D) High-level dynamic input voltage 2.31 V
VIL(D) Low-level dynamic input voltage 0.99 V
NOTE 6: Characteristics are for surface-mount packages only.
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS VCC TYP UNIT
C
Power dissipation capacitance
C 50 pF
f 10 MHz
3.3 V 111
pF
Cpd Power dissipation capacitance CL = 50 pF, f = 10 MHz 5 V 114 pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414O − APRIL 1998 − REVISED JANUARY 2011
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈VCC
0 V
50% VCC VOL + 0.3 V
50% VCC ≈0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
TEST S1
VCC
0 V
50% VCC
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1
VCC
RL = 1 kΩ
GND
From Output
Under Test
CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
50% VCC
50% VCC 50% VCC
50% VCC
50% VCC 50% VCC
50% VCC 50% VCC
VOH − 0.3 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 11-Feb-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74LV595AD ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV595ADE4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV595ADG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV595ADR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV595ADRE4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV595ADRG3 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM
SN74LV595ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV595ANSR ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV595ANSRE4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV595ANSRG4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV595APWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV595APWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV595APWRG3 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM
SN74LV595APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV595APWT ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV595APWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV595APWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 11-Feb-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74LV595ARGYR ACTIVE VQFN RGY 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN74LV595ARGYRG4 ACTIVE VQFN RGY 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV595A :
•Automotive: SN74LV595A-Q1
•Enhanced Product: SN74LV595A-EP
NOTE: Qualified Version Definitions:
PACKAGE OPTION ADDENDUM
www.ti.com 11-Feb-2011
Addendum-Page 3
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LV595ADRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74LV595ANSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74LV595APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LV595APWR TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1
SN74LV595APWRG3 TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1
SN74LV595APWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LV595APWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LV595ARGYR VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LV595ADRG4 SOIC D 16 2500 333.2 345.9 28.6
SN74LV595ANSR SO NS 16 2000 367.0 367.0 38.0
SN74LV595APWR TSSOP PW 16 2000 367.0 367.0 35.0
SN74LV595APWR TSSOP PW 16 2000 364.0 364.0 27.0
SN74LV595APWRG3 TSSOP PW 16 2000 364.0 364.0 27.0
SN74LV595APWRG4 TSSOP PW 16 2000 367.0 367.0 35.0
SN74LV595APWT TSSOP PW 16 250 367.0 367.0 35.0
SN74LV595ARGYR VQFN RGY 16 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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