For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
EVALUATION KIT AVAILABLE
General Description
The MAX16955 is a current-mode, synchronous PWM
step-down controller designed to operate with input volt-
ages from 3.5V to 36V while using only 50μA of quies-
cent current at no load. The switching frequency is
adjustable from 220kHz to 1MHz by an external resistor
and can be synchronized to an external clock up to
1.1MHz. The MAX16955 output voltage is pin program-
mable to be either 5V fixed, or adjustable from 1V to
10V. The wide input voltage range, along with its ability
to operate in dropout during undervoltage transients,
makes it ideal for automotive and industrial applications.
The MAX16955 operates in fixed-frequency PWM mode
and low quiescent current skip mode. It features an
enable logic input, which is compatible up to 42V to
disable the device and reduce its shutdown current to
10μA. Protection features include overcurrent limit,
overvoltage, undervoltage, and thermal shutdown with
automatic recovery. The device also features a power-
good monitor to ease power-supply sequencing.
The MAX16955 is available in a thermally enhanced 16-
pin TSSOP package with exposed pad and is specified
for operation over the -40°C to +125°C automotive tem-
perature range.
Applications
Automotive
Industrial
Military
Point of Load
Features
oWide 3.5V to 36V Input Voltage Range
o42V Input Transient Tolerance
oHigh Duty Cycle During Undervoltage Transients
o220kHz to 1MHz Adjustable Switching Frequency
oCurrent-Mode Control Architecture
oAdjustable (1V to 10V) Output Voltage with ±2%
Accuracy
oThree Operating Modes
50µA Ultra-Low Quiescent Current Skip Mode
Forced Fixed-Frequency Mode
External Frequency Synchronization
oLowest BOM Count, Current-Mode Control
Architecture
oPower-Good Output
oEnable Input Compatible from 3.3V Logic Level to
42V
oCurrent-Limit, Thermal Shutdown, and
Overvoltage Protection
o-40°C to +125°C Automotive Temperature Range
oAutomotive Qualified
19-5791; Rev 4; 7/14
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX16955AUE+
-40°C to +125°C
16 TSSOP-EP*
MAX16955AUE/V+
-40°C to +125°C
16 TSSOP-EP*
/V denotes an automotive qualified part.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
EP = Exposed pad.
Typical Operating Circuit
MAX16955
RFOSC
CL
SGND BIAS
FB
OUT
CS
CIN
FOSC
RCOMP
RSENSE
COMP
FSYNC
EN
PGOOD
CCOMP1
CCOMP2
CBST
SUP
VBAT
DH
BST
NL
NH
PGND
DL
L
LX
COUT
VOUT
5V
MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
2Maxim Integrated
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VSUP = VEN = 14V, CIN = 10μF, COUT = 94μF, CBIAS = 2.2μF, CBST = 0.1μF, RFOSC = 76.8kΩ, TA= TJ= -40°C to +125°C, unless
otherwise noted. Typical values are at TA= +25°C.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
SUP and EN to SGND ............................................-0.3V to +42V
LX to PGND ..............................................................-1V to +42V
BST to LX .................................................................-0.3V to +6V
BIAS, FB, PGOOD, FSYNC to SGND .......................-0.3V to +6V
DH to LX ...................................................................-0.3V to +6V
DL to PGND .............................................-0.3V to (VBIAS + 0.3V)
FOSC to SGND ........................................-0.3V to (VBIAS + 0.3V)
CS and OUT to SGND ............................................-0.3V to +11V
PGND to SGND .....................................................-0.3V to +0.3V
Continuous Power Dissipation (TA= +70°C)
TSSOP (derate 26.1mW/°C above +70°C) .............2088.8mW*
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TSSOP
Junction-to-Ambient Thermal Resistance (θJA) .........38.3°C/W
Junction-to-Case Thermal Resistance (θJC) ...................3°C/W
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SUP Input Voltage Range VSUP (Note 3) 3.5 36 V
SUP Operating Supply Current ISUP
Fixed 5V output, fixed-frequency, PWM
mode, VFB = VBIAS, no external FETs
connected
1 mA
Skip Mode Supply Current ISKIP No load, fixed 5V output 50 90 μA
SUP Shutdown Supply Current ISHDN,SUP VEN = 0V 10 20 μA
VSUP = 3.5V, IBIAS = 45mA 3.0
BIAS Voltage VBIAS 6V < VSUP < 36V 4.7 5.0 5.3 V
BIAS Undervoltage Lockout VUVBIAS VBIAS rising 3.1 3.4 V
BIAS Undervoltage Lockout
Hysteresis VBIAS falling 200 mV
BIAS Minimum Load IBIAS(MIN) VSUP - VBIAS > 200mV 45 mA
OUTPUT VOLTAGE (OUT)
Output Voltage Adjustable
Range 1.0 10 V
OUT Pulldown Resistance RPULL_D V
EN = 0V or fault condition active 30
Output Voltage (5V Fixed Mode) VOUT VSUP = 6V to 36V, VFB = VBIAS, fixed-
frequency mode (Note 4) 4.925 5.0 5.075 V
FB Feedback Voltage
(Adjustable Mode) VFB VSUP = 6V to 36V, 0V < (VCS - VOUT)
< 80mV, fixed-frequency mode 0.99 1.0 1.01 V
FB Current IFB VFB = 1.0V 0.02 μA
*
As per JEDEC51 standard (multilayer board).
MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
3
Maxim Integrated
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
FB Line Regulation VEN = VSUP, 6V < VSUP < 36V (Note 4) 0.02 %/V
Transconductance (from FB to
COMP) gm,EA 1200 μS
Error-Amplifier Output
Impedance ROUT,EA 30 M
RFOSC = 76.8k 360 400 440
Operating Frequency fSW RFOSC = 30.1k 1000 kHz
Minimum On-Time tON(MIN) 80 ns
Maximum FSYNC Frequency fFSYNC(MAX) 1100 kHz
Minimum FSYNC Frequency fFSYNC(MIN) fFSYNC > 110% of internal frequency (20%
duty cycle), fSW = 220kHz 242 kHz
FSYNC Switching Threshold
High VFSYNC,HI 1.4 V
FSYNC Switching Threshold Low VFSYNC,LO 0.4 V
FSYNC Internal Pulldown
Resistance 1 M
CURRENT LIMIT
CS Input Current ICS VCS = VOUT = 0V or VBIAS (Note 4) -1 +1 μA
During normal operation 22
Output Input Current IOUT VFB = VBIAS 32
μA
CS Current-Limit Voltage
Threshold VLIMIT V
CS - VOUT, VBIAS = 5V, VOUT 2.5V 68 80 92 mV
FAULT DETECTION
Output Overvoltage Trip
Threshold VFB,OV V
OUT = VFB, rising edge 108 113 118 %VFB
Output Overvoltage Trip
Hysteresis 2.5 %
Rising edge 25
Output Overvoltage Fault
Propagation Delay tOVP Falling edge 25
μs
Output Undervoltage Trip
Threshold VFB,UV VOUT = VFB; with respect to slewed FB
threshold, falling edge 83 88 93 %VFB
Output Undervoltage Trip
Hysteresis 2.5 %
Falling edge 25
Output Undervoltage
Propagation Delay Rising edge (excluding startup) 25
μs
PGOOD Output Low Voltage VPGOOD,L ISINK = 3mA 0.4 V
PGOOD Leakage Current IPGOOD 1 μA
Thermal Shutdown Threshold TSHDN (Note 5) +175 °C
Thermal Shutdown Hysteresis (Note 5) 15 °C
ELECTRICAL CHARACTERISTICS (continued)
(VSUP = VEN = 14V, CIN = 10μF, COUT = 94μF, CBIAS = 2.2μF, CBST = 0.1μF, RFOSC = 76.8kΩ, TA= TJ= -40°C to +125°C, unless
otherwise noted. Typical values are at TA= +25°C.) (Note 2)
MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
4Maxim Integrated
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
GATE DRIVE
DH = high state 10
DH Gate-Driver On-Resistance RDH DH = low state 2
DL = high state 3.5
DL Gate-Driver On-Resistance RDL DL = low state 2
DL rising (Note 5) 60
DH/DL Dead Time (Note 4) tDEAD DH rising (Note 5) 60
ns
BST Input Current IBST VLX = 0V, VBST = 5V,
VDH - VLX = VDL - VPGND = 0V 1 μA
BST On-Resistance (Note 5) 5 15
ENABLE INPUT
EN Input Threshold Low VEN,LO 1.2 V
EN Input Threshold High VEN,HI 2.2 V
EN Threshold Voltage
Hysteresis 0.2 V
EN Input Current IEN 0.5 μA
SOFT-START
Soft-Start Ramp Time tSS 5 ms
Note 2: Devices tested at TA= +25°C. Limits over temperature are guaranteed by design.
Note 3: For 3.5V operation, the n-channel MOSFET’s threshold voltage should be compatible to (lower than) this input voltage.
Note 4: Device not in dropout condition.
Note 5: Guaranteed by design; not production tested.
ELECTRICAL CHARACTERISTICS (continued)
(VSUP = VEN = 14V, CIN = 10μF, COUT = 94μF, CBIAS = 2.2μF, CBST = 0.1μF, RFOSC = 76.8kΩ, TA= TJ= -40°C to +125°C, unless
otherwise noted. Typical values are at TA= +25°C.) (Note 2)
Typical Operating Characteristics
(VSUP = VEN = 14V, CIN = 10μF, COUT = 94μF, CBIAS = 2.2μF, CBST = 0.1μF, RFOSC = 66.5kΩ, fOSC = 468kHz, VFB = VBIAS,
VOUT = 5V, TA= +25°C, unless otherwise noted.)
MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
5
Maxim Integrated
VOUT = 3.3V STARTUP RESPONSE
(SKIP MODE)
MAX16955 toc01
IOUT
2A/div
VOUT
2V/div
5V/div
VPGOOD
10V/div
2ms
MAX16955 toc02
IOUT
2A/div
VOUT
2V/div
5V/div
VPGOOD
10V/div
2ms
VOUT = 5V STARTUP RESPONSE
(SKIP MODE)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX16955 toc03
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
302412 18
5
10
15
20
30
25
35
40
0
636
FIXED-FREQUENCY MODE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX16955 toc04
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
30241812
10
20
30
40
50
60
70
80
90
100
0
636
SKIP MODE
EFFICIENCY vs. LOAD CURRENT
MAX16955 toc05
LOAD CURRENT (A)
EFFICIENCY (%)
3.53.02.0 2.51.0 1.50.5
10
20
30
40
50
60
70
80
90
100
0
0 4.0
VOUT = 5V VOUT = 3.3V
FIXED-FREQUENCY MODE
EFFICIENCY vs. LOAD CURRENT
MAX16955 toc06
LOAD CURRENT (A)
EFFICIENCY (%)
10.10.010.001
10
20
30
40
50
60
70
80
90
100
0
0.0001 10
SKIP MODE
VOUT = 5V
VOUT = 3.3V
SWITCHING FREQUENCY vs. RFOSC
MAX16955 toc07
RFOSC (kI)
FREQUENCY (kHz)
135125105 11545 55 65 75 85 9535
250
300
350
400
450
500
550
600
650
700
750
800
850
900
950
1000
1050
1100
1150
1200
200
25 145
0 TO 4A LOAD-TRANSIENT RESPONSE,
VOUT = 5V, PWM MODE
MAX16955 toc08
IOUT
2A/div
VOUT
200mV/div
100µs
0 TO 4A LOAD-TRANSIENT RESPONSE,
VOUT = 3.3V, PWM MODE
MAX16955 toc09
IOUT
2A/div
VOUT
200mV/div
100µs
SYNCHRONIZATION WITH EXTERNAL CLOCK
fFSYNC = 1MHz
MAX16955 toc10
VFSYNC
2V/div
VLX
5V/div
1µs
COLD CRANK (PWM MODE)
MAX16955 toc11
IL
5A/div
VPGOOD
5V/div
VSUP
5V/div
VOUT
5V/div
10ms
LOAD DUMP RESPONSE (SKIP MODE)
MAX16955 toc12
ILX
5A/div
VPGOOD
5V/div
VSUP
20V/div
VOUT
5V/div
100ms
36V
8V
LOAD DUMP RESPONSE (PWM MODE)
MAX16955 toc13
ILX
5A/div
VPGOOD
5V/div
VSUP
20V/div
VOUT
5V/div
100ms
SLOW INPUT RESPONSE (PWM MODE)
MAX16955 toc14
VLX
10V/div
VPGOOD
5V/div
VSUP
10V/div
VOUT
5V/div
10s
14V
SLOW INPUT RESPONSE (SKIP MODE)
MAX16955 toc15
VLX
10V/div
VPGOOD
5V/div
VSUP
10V/div
VOUT
5V/div
10s
Typical Operating Characteristics (continued)
(VSUP = VEN = 14V, CIN = 10μF, COUT = 94μF, CBIAS = 2.2μF, CBST = 0.1μF, RFOSC = 66.5kΩ, fOSC = 468kHz, VFB = VBIAS,
VOUT = 5V, TA= +25°C, unless otherwise noted.)
MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
6Maxim Integrated
SHORT-CIRCUIT RESPONSE, VOUT = 3.3V
MAX16955 toc17
VPGOOD
5V/div
IOUT
5A/div
VOUT
2V/div
400µs
3.3V
0V
LOAD REGULATION
MAX16955 toc18
LOAD CURRENT (A)
ERROR (%)
321
-4
-3
-2
-1
0
1
2
3
4
5
-5
04
TA = +125°C
FIXED-FREQUENCY MODE
TA = +25°C TA = -40°C
LOAD REGULATION
MAX16955 toc19
LOAD CURRENT (A)
ERROR (%)
321
-4
-3
-2
-1
0
1
2
3
4
5
-5
04
TA = +125°C
SKIP MODE
TA = +25°C TA = -40°C
OUTPUT-VOLTAGE ERROR
vs. TEMPERATURE
MAX16955 toc20
TEMPERATURE (°C)
ERROR (%)
1109565 80-10 5 20 35 50-25
-4
-3
-2
-1
0
1
2
3
4
5
-5
-40 125
FIXED-FREQUENCY MODE
SKIP MODE
LINE REGULATION
MAX16955 toc21
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE (V)
30241812
-2.5
-2.0
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
-3.0
636
TA = +125°C
FIXED-FREQUENCY MODE
TA = +25°C TA = -40°C
LINE REGULATION
MAX16955 toc22
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE (V)
30241812
-2.5
-2.0
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
-3.0
636
TA = +125°C
SKIP MODE
TA = +25°C TA = -40°C
BIAS VOLTAGE vs. BIAS CURRENT
MAX16955 toc23
BIAS CURRENT (mA)
BIAS VOLTAGE ERROR (%)
806020 40
-4
-3
-2
-1
0
1
2
3
4
5
-5
0 100
TA = +125°C
TA = +25°C
TA = -40°C
SHORT-CIRCUIT RESPONSE, VOUT = 5V
MAX16955 toc16
VPGOOD
5V/div
IOUT
5A/div
VOUT
5V/div
400µs
5V
MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
7
Maxim Integrated
Typical Operating Characteristics (continued)
(VSUP = VEN = 14V, CIN = 10μF, COUT = 94μF, CBIAS = 2.2μF, CBST = 0.1μF, RFOSC = 66.5kΩ, fOSC = 468kHz, VFB = VBIAS,
VOUT = 5V, TA= +25°C, unless otherwise noted.)
SHUTDOWN CURRENT vs. VSUP
MAX16955 toc24
VSUP (V)
SHUTDOWN CURRENT (µA)
333024 279 12 15 18 216
2
4
6
8
10
12
14
16
18
20
0
336
SHUTDOWN CURRENT vs. TEMPERATURE
MAX16955 toc25
TEMPERATURE (°C )
SHUTDOWN CURRENT (µA)
1109580655035205-10-25
10.35
10.40
10.45
10.50
10.55
10.60
10.30
-40
VSUP = 14V
VEN = 0V
125
SWITCHING FREQUENCY
vs. LOAD CURRENT
MAX16955 toc26
LOAD CURRENT (A)
FREQUENCY (kHz)
321
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
04
DIPS AND DROPS TEST,
PWM MODE, VOUT = 5V
MAX16955 toc27
VLX
10V/div
VPGOOD
5V/div
VSUP
10V/div
VOUT
2V/div
10ms
0V
14V
DIPS AND DROPS TEST,
SKIP MODE, VOUT = 5V
MAX16955 toc28
VLX
10V/div
VPGOOD
5V/div
VSUP
10V/div
VOUT
2V/div
10ms
0V
14V
DIPS AND DROPS TEST,
PWM MODE, VOUT = 3.3V
MAX16955 toc29
VLX
10V/div
VPGOOD
5V/div
VSUP
10V/div
VOUT
2V/div
10ms
DIPS AND DROPS TEST,
SKIP MODE, VOUT = 3.3V
MAX16955 toc30
VLX
10V/div
VPGOOD
5V/div
VSUP
10V/div
VOUT
2V/div
10ms
MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
8Maxim Integrated
Typical Operating Characteristics (continued)
(VSUP = VEN = 14V, CIN = 10μF, COUT = 94μF, CBIAS = 2.2μF, CBST = 0.1μF, RFOSC = 66.5kΩ, fOSC = 468kHz, VFB = VBIAS,
VOUT = 5V, TA= +25°C, unless otherwise noted.)
MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
9
Maxim Integrated
Pin Configuration
MAX16955
16
TSSOP
+
BST1SUP
15 DH2EN
14 LX3FOSC
13 BIAS4FSYNC
12 DL5SGND
11 PGND6COMP
10 PGOOD7FB
9
TOP VIEW
OUT8CS
EP
Pin Description
PIN NAME FUNCTION
1 SUP
Input Supply Voltage. SUP is the input voltage to the internal linear regulator. Bypass SUP to PGND with
a 1μF minimum value ceramic capacitor. Connect BIAS and SUP to a 5V rail, if available.
2 EN
Active-High Enable Input. EN is compatible with 5V and 3.3V logic levels. Drive EN logic-high to enable
the output or drive EN logic-low to put the controller in low-power shutdown mode. Connect EN to SUP
for always-on operation. Do not leave EN unconnected.
3 FOSC
Oscillator-Timing Resistor Input. Connect a resistor from FOSC to SGND to set the oscillator frequency
from 220kHz to 1MHz. See the Setting the Switching Frequency section.
4 FSYNC
Synchronization and Mode Selection Input. Connect FSYNC to BIAS to select fixed-frequency PWM
mode and disable skip mode. Connect FSYNC to SGND to select skip mode. Connect FSYNC to an
external clock for synchronization. FSYNC is internally pulled down to ground with a 1M resistor.
5 SGND
Signal Ground. Connect SGND directly to the local ground plane. Connect SGND to PGND at a single
point, typically near the output capacitor return terminal.
6 COMP
Error Amplifier Output. Connect COMP to the compensation feedback network. See the Compensation
Design section.
7 FB
Feedback Regulation Point. Connect FB to BIAS for a fixed 5V output voltage. In adjustable mode,
connect to the center tap of a resistive divider from the output (VOUT) to SGND to set the output voltage.
The FB voltage regulates to 1V (typ).
8 CS
Positive Current-Sense Input. Connect CS to the positive terminal of the current-sense element. Figure
4 shows two different current-sensing options: 1) accurate sense with a sense resistor or 2) lossless
inductor DCR sensing.
MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
10 Maxim Integrated
Pin Description (continued)
PIN NAME FUNCTION
9 OUT
Output Sense and Negative Current-Sense Input. When using the internal preset 5V feedback divider
(FB = BIAS), the controller uses OUT to sense the output voltage. Connect OUT to the negative
terminal of the current-sense element.
10 PGOOD
Open-Drain Power-Good Output. A logic-high voltage on PGOOD indicates that the output voltage is in
regulation. PGOOD is pulled low when the output voltage is out of regulation. Connect a 10k pullup
resistor from PGOOD to the digital interface voltage.
11 PGND
Power Ground. Connect the input and output filter capacitors’ negative terminals to PGND. Connect
PGND externally to SGND at a single point, typically at the output capacitor return terminal.
12 DL
Low-Side Gate-Driver Output. DL swings from VBIAS to PGND. If a resistor is needed between DL and the
gate of the MOSFET, proper resistance value could be provided based on application circuit review result.
13 BIAS
Internal 5V Linear Regulator Output. BIAS provides power for bias and gate drive. Connect a 1μF to
10μF ceramic capacitor from BIAS to PGND. Connect BIAS and SUP to a 5V rail, if available.
14 LX
External Inductor Connection. Connect LX to the switched side of the inductor. LX serves as the lower
supply rail for the DH high-side gate driver.
15 DH
High-Side Gate-Driver Output. DH swings from LX to BST. If a resistor is needed between DH and the gate
of the MOSFET, proper resistance value could be provided based on application circuit review result.
16 BST
Boost Flying Capacitor Connection. Connect a ceramic capacitor between BST and LX. See the Boost-
Flying Capacitor Selection section for details.
— EP
Exposed Pad. Internally connected to ground. Connect EP to a large contiguous copper plane at SGND
potential to improve thermal dissipation. Do not use as the main ground connection.
MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
11
Maxim Integrated
Functional Diagram
MAX16955
EN
LDO
REF
BIAS
OSC
BUCK
CONTROLLER
SUP
BST
SWITCH
BST
EN
SGND
PGOOD
FB
COMP EA
CS
ZX
UG
LG
PWM
ILIM
EAFB
REF
DH
LX
BIAS
PGND
DL
CLK
FOSC
MODE
SYNC
FSYNC MODE
CS
OUT
SGND
FBI
MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
12 Maxim Integrated
Detailed Description
The MAX16955 is a current-mode, synchronous PWM
buck controller designed to drive logic-level MOSFETs.
The device tolerates a wide 3.5V to 42V input voltage
range and generates an adjustable 1V to 10V or fixed
5V output voltage. This device can operate in dropout
mode, making it ideal for automotive and industrial
applications with undervoltage transients.
The internal switching frequency is adjustable from
220kHz to 1MHz with an external resistor and can be
synchronized to an external clock. The high switching
frequency reduces output ripple and allows the use of
small external components. The device operates in
both fixed-frequency PWM mode and a low quiescent
current skip mode. While working in skip mode, the
operating current is as low as 50μA.
The device features an enable logic input to disable the
device and reduce its shutdown current to 10μA.
Protection features include cycle-by-cycle current limit,
overvoltage detection, and thermal shutdown. The
device also features integrated soft-start and a power-
good monitor to help with power sequencing.
Supply Voltage Range (SUP)
The supply voltage range (VSUP) of the MAX16955 is com-
patible to the typical automotive battery voltage range
from 3.5V to 36V and can tolerate up to 42V transients.
If an external 5V rail is available, use this rail to power
the MAX16955 to increase efficiency by bypassing the
internal LDO. Connect both BIAS and SUP to this rail,
while connecting the half-bridge rectifier to the battery.
Slow Ramp-Up of the Input Voltage
If the input voltage (VSUP) ramps up slowly, the device
operates in dropout mode until VSUP is greater than the
regulated output voltage. The dropout mode is detect-
ed by monitoring high-side FET on for eight clock
cycles. Once dropout mode is detected, the controller
issues a forced low-side pulse at the rising edge of
switching clock to refresh BST capacitor. This maintains
the proper BST voltage to turn on the high-side MOS-
FET when the device is in dropout mode.
System Enable (EN) and Soft-Start
An enable control input (EN) activates the MAX16955
from its low-power shutdown mode. EN is compatible
with inputs from automotive battery level down to 3.5V.
The high-voltage compatibility allows EN to be connect-
ed to SUP, KEY/KL30, or the inhibit pin (INH) of a CAN
transceiver.
A logic-high at EN turns on the internal regulator. Once
VBIAS is above the internal lockout level, VUVL = 3.1V
(max), the controller starts up with a 5ms fixed soft-start
time. Once regulation is reached, PGOOD goes high
impedance.
A logic-low at EN shuts down the device. During shut-
down, the internal linear regulator and gate drivers turn
off. Shutdown is the lowest power state and reduces
the quiescent current to 10μA (typ).
To protect the low-side MOSFET during shutdown, the
step-down regulator cannot be enabled until the output
voltage drops below 1.25V. An internal 30Ωpulldown
switch helps discharge the output. If the EN pin is tog-
gled low then high, the switching regulator shuts down
and remains off until the output voltage decays to
1.25V. At this point, the MAX16955 turns on using the
soft-start sequence.
Fixed 5V Linear Regulator (BIAS)
The MAX16955 has an internal 5V linear regulator to
provide its own 5V bias from a high-voltage input sup-
ply at SUP. This bias supply powers the gate drivers for
the external n-channel MOSFETs and provides the
power required for the analog controller, reference, and
logic blocks. The bias rail needs to be stabilized by a
1μF or greater capacitance at BIAS, and can provide
up to 50mA (typ) total current.
Oscillator Frequency and External
Synchronization
The MAX16955 provides an internal oscillator
adjustable from 220kHz to 1MHz. To set the switching
frequency, connect a resistor from FOSC to SGND. See
the
Setting the Switching Frequency
section.
The MAX16955 can also be synchronized to an external
clock by connecting the external clock signal to
FSYNC. For proper frequency synchronization,
FSYNC’s input frequency must be at least 10% higher
than the programmed internal oscillator frequency. A
rising clock edge on FSYNC is interpreted as a syn-
chronization input. If the FSYNC signal is lost, the inter-
nal oscillator takes control of the switching rate,
returning to the switching frequency set by the resistor
connected to FOSC. This maintains output regulation
even with intermittent FSYNC signals. The maximum
synchronizable frequency is 1.1MHz.
When FSYNC is connected to SGND, the device oper-
ates in skip mode. When FSYNC is connected to BIAS
or driven by an external clock, the MAX16955 operates
in skip mode during soft-start and transitions to fixed-
frequency PWM mode after soft-start is over.
MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
13
Maxim Integrated
Error Detection and Fault Behavior
Several error-detection mechanisms prevent damage to
the MAX16955 and the application circuit:
• Overcurrent protection
• Output overvoltage protection
• Undervoltage lockout at BIAS
• Power-good detection of the output voltage
• Overtemperature protection of the IC
Overcurrent Protection
The MAX16955 provides cycle-by-cycle current limiting
as long as the FB voltage is greater than 0.7V (i.e., 70%
of the regulated output voltage). If the output voltage
drops below 70% of the regulation point due to overcur-
rent event, 16 consecutive current-limit events initiate
restart. If the overcurrent is still present during restart,
the MAX16955 shuts down and initiates restart. This
automatic restart continues until the overcurrent condi-
tion disappears. If the overcurrent condition disappears
at any restart attempt, the device enters the normal
soft-start routine.
Output Overvoltage Protection
The MAX16955 features an internal output overvoltage
protection. If VOUT increases by 13% (typ) of the intended
regulation voltage, the high-side MOSFET turns off and
the low-side MOSFET turns on. The low-side MOSFET
stays on until VOUT goes back into regulation. Once VOUT
is in regulation, the normal switching cycles continue.
Undervoltage Lockout (UVLO)
The BIAS input undervoltage lockout (UVLO) circuitry
inhibits switching if the 5V bias supply (BIAS) is below
its UVLO threshold, 3.1V (typ). If the BIAS voltage
drops below the UVLO threshold, the controller stops
switching and turns off both high-side and low-side
gate drivers until the BIAS voltage recovers.
Power-Good Detection (PGOOD)
The MAX16955 includes a power-good comparator with
added hysteresis to monitor the step-down controller’s
output voltage and detect the power-good threshold.
The PGOOD output is open drain and should be pulled
up with an external resistor to the supply voltage of the
logic input it drives. This voltage should not exceed 6V.
Pullup resistor should not be less than 1kΩsuch that
pulldown voltage is less than 400mV with a 5V supply.
PGOOD can sink up to 4mA of current while low.
PGOOD asserts low during the following conditions:
• Standby mode
• Undervoltage with VOUT below 90% (typ) its set
value
• Overvoltage with VOUT above 111% (typ) its set
value
The power-good levels are measured at FB if a feed-
back divider is used. If the MAX16955 is used in 5V
mode with FB connected to BIAS, OUT is used as a
feedback path for voltage regulation and power-good
determination.
Overtemperature Protection
Thermal-overload protection limits total power dissipa-
tion in the MAX16955. When the junction temperature
exceeds +175°C (typ), an internal thermal sensor shuts
down the step-down controller, allowing the IC to cool.
The thermal sensor turns on the IC again after the junc-
tion temperature cools by 15°C and the output voltage
has dropped below 1.25V (typ).
A continuous overtemperature condition can cause
on-/off-cycling of the device.
Fixed-Frequency, Current-Mode
PWM Controller
The MAX16955’s step-down controller uses a PWM,
current-mode control scheme. An internal transconduc-
tance amplifier establishes an integrated error voltage.
The heart of the PWM controller is an open-loop com-
parator that compares the integrated voltage-feedback
signal against the amplified current-sense signal plus
the slope compensation ramp, which are summed into
the main PWM comparator to preserve inner-loop sta-
bility and eliminate inductor stair casing. At each falling
edge of the internal clock, the high-side MOSFET turns
on until the PWM comparator trips, the maximum duty
cycle is reached, or the peak current limit is reached.
During this on-time, current ramps up through the
inductor, storing energy in its magnetic field and sourc-
ing current to the output. The current-mode feedback
system regulates the peak inductor current as a func-
tion of the output-voltage error signal. The circuit acts
as a switch-mode transconductance amplifier and elim-
inates the influence of the output LC filter double pole.
During the second half of the cycle, the high-side
MOSFET turns off and the low-side MOSFET turns on.
The inductor releases the stored energy as the current
ramps down, providing current to the output. The out-
put capacitor stores charge when the inductor current
exceeds the required load current and discharges
when the inductor current is lower, smoothing the volt-
age across the load. Under soft-overload conditions,
when the peak inductor current exceeds the selected
current limit, the high-side MOSFET is turned off imme-
diately. The low-side MOSFET is turned on and
remains on to let the inductor current ramp down until
the next clock cycle.
MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
14 Maxim Integrated
Forced Fixed-Frequency PWM Mode
The low-noise forced fixed-frequency PWM mode
(FSYNC connected to BIAS or an external clock) dis-
ables the zero-crossing comparator, which controls the
low-side switch on-time. This forces the low-side gate-
driver waveform to constantly be the complement of the
high-side gate-drive waveform. The inductor current
reverses at light loads while DH maintains a duty factor
of VOUT/VSUP.
The benefit of forced fixed-frequency PWM mode is to
keep the switching frequency fairly constant. However,
forced fixed-frequency PWM operation comes at a cost:
the no-load 5V supply current can be up to 45mA,
depending on the external MOSFETs and switching fre-
quency. Forced fixed-frequency PWM mode is most
useful for avoiding audio frequency noises and improv-
ing load-transient response.
Light-Load Low-Quiescent Operating
(Skip) Mode
The MAX16955 includes a light-load operating mode
control input (FSYNC = SGND) used to enable or dis-
able the zero-crossing comparator. When the zero-
crossing comparator is enabled, the regulator forces
DL low when the current-sense inputs detect zero
inductor current. This keeps the inductor from discharg-
ing the output capacitor and forces the regulator to skip
pulses under light-load conditions to avoid overcharg-
ing the output.
The lowest operating currents can be achieved in skip
mode. When the MAX16955 operates in skip mode with
no external load current, the overall current consump-
tion can be as low as 50μA. A disadvantage of skip
mode is that the operating frequency is not fixed.
Skip-Mode Current-Sense Threshold
When skip mode is enabled, the on-time of the step-
down controller terminates when the output voltage
exceeds the feedback threshold and when the current-
sense voltage exceeds the idle-mode current-sense
threshold (VCS,IDLE). See Figure 1. Under light-load
conditions, the on-time duration depends solely on the
skip-mode current-sense threshold, which is 25mV
(typ). This forces the controller to source a minimum
amount of power with each cycle. To avoid overcharg-
ing the output, another on-time cannot begin until the
output voltage drops below the feedback threshold.
Because the zero-crossing comparator prevents the
switching regulator from sinking current, the controller
must skip pulses. Therefore, the controller regulates the
valley of the output ripple under light-load conditions.
Automatic Pulse-Skipping Crossover
In skip mode, an inherent automatic switchover to pulse
frequency modulation (PFM) takes place at light loads.
This switchover is affected by a comparator that trun-
cates the low-side switch on-time at the inductor cur-
rent’s zero crossing. The zero-crossing comparator
senses the inductor current across CS to OUT. Once
(VCS - VOUT) drops below the 6mV zero-crossing, cur-
rent-sense threshold, the comparator forces DL low.
This mechanism causes the threshold between pulse-
skipping PFM and nonskipping PWM operation to coin-
cide with the boundary between continuous and
discontinuous inductor-current operation (also known
as the critical conduction point). The load-current level
at which PFM/PWM crossover occurs, ILOAD(SKIP), is
given by:
The switching waveforms can appear noisy and asyn-
chronous when light-loading causes pulse-skipping
operation. This is a normal operating condition that
results in high light-load efficiency. Trade-offs in PFM
noise vs. light-load efficiency is made by varying the
inductor value. Generally, low inductor values produce
a higher efficiency under light load, while higher values
result in higher full-load efficiency (assuming that the
coil resistance remains constant) and less output-volt-
age ripple. Drawbacks of using higher inductor values
include larger physical size and degraded load-tran-
sient response (especially at low input-voltage levels).
MOSFET Gate Drivers (DH and DL)
The DH and DL drivers are optimized for driving logic-
level n-channel power MOSFETs. The DH high-side
n-channel MOSFET driver is powered by charge pump-
ing at BST, while the DL synchronous rectifier drivers
are powered directly by the 5V linear regulator (BIAS).
An adaptive dead-time circuit monitors the DH and DL
outputs and prevents the opposite-side MOSFET from
turning on until the other MOSFET is fully off. Thus, the
circuit allows the high-side driver to turn on only when
the DL gate driver has been turned off. Similarly, it pre-
vents the low-side (DL) from turning on until the DH
gate driver has been turned off.
The adaptive driver dead-time allows operation without
shoot-through with a wide range of MOSFETs, minimiz-
ing delays and maintaining efficiency. To minimize stray
impedance, use very short, wide traces (50 mils to 100
mils wide if the MOSFET is 1in from the controller).
IA
VVV
VfMHz
LOAD SKIP SUP OUT OUT
SUP SW
()
[]
=−
()
××2
[[]
×
[]
LμH
MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
15
Maxim Integrated
Synchronous rectification reduces conduction losses in
the rectifier by replacing the normal low-side Schottky
catch diode with a low-resistance MOSFET switch. The
internal pulldown transistor that drives DL low is
robust, with a 1.6Ω(typ) on-resistance. This low on-
resistance helps prevent DL from being pulled up dur-
ing the fast rise time of the LX node, due to capacitive
coupling from the drain to the gate of the low-side syn-
chronous rectifier MOSFET. Applications with high
input voltages and long-inductive driver traces can
require additional gate-to-source capacitance. This
ensures that fast-rising LX edges do not pull up the
low-side MOSFET’s gate, causing shoot-through cur-
rents. The capacitive coupling between LX and DL cre-
ated by the MOSFET’s gate-to-drain capacitance (CGD
= CRSS), gate-to-source capacitance (CGS = CISS -
CGD), and additional board parasitic should not
exceed the following minimum threshold:
Although a low resistive path from DH and DL to the
MOSFET gates is encouraged, there are cases where
series resistors can be added. For instance, a series resis-
tor can be added to the DL path. However, in this case,
should have at least as much resistance in series with the
BST capacitor to help prevent shoot-through current.
High-Side Gate-Drive Supply (BST)
The high-side MOSFET is turned on by closing an inter-
nal switch between BST and DH. This provides the
necessary gate-to-source voltage to turn on the high-
side MOSFET, an action that boosts the gate-drive signal
above VSUP. The boost capacitor connected between
BST and LX holds up the voltage across the flying gate
driver during the high-side MOSFET on-time.
The charge lost by the boost capacitor for delivering
the gate charge is refreshed when the high-side
MOSFET is turned off and the LX node swings down
to ground. When the LX node is low, an internal high-
voltage switch connected between BIAS and BST
recharges the boost capacitor to the BIAS voltage.
See the
Boost-Flying Capacitor Selection
section to
choose the right size of the boost capacitor.
Dropout Behavior During Undervoltage Transients
The controller generates a low-side pulse every four
clock cycles to refresh the BST capacitor during low-
dropout operation. This guarantees that the MAX16955
operates in dropout mode during undervoltage tran-
sients like cold crank.
Current Limiting and Current-Sense Inputs
(CS and OUT)
The current-limit circuit uses differential current-sense
inputs (CS and OUT) to limit the peak inductor current.
If the magnitude of the current-sense signal exceeds
the current-limit threshold, the PWM controller turns off
the high-side MOSFET. The actual maximum load cur-
rent is less than the peak current-limit threshold by an
amount equal to half the inductor ripple current.
Therefore, the maximum load capability is a function of
the current-sense resistance, inductor value, switching
frequency, and duty cycle (VOUT/VSUP). See the
Current Sensing
section.
Design Procedure
Effective Input Voltage Range
Although the MAX16955 controller can operate from
input supplies up to 42V and regulate down to 1V, the
minimum voltage conversion ratio (VOUT/VSUP) might
be limited by the minimum controllable on-time. For
proper fixed-frequency PWM operation, the voltage
conversion ratio should obey the following condition:
where tON(MIN) is 80ns and fSW is the switching fre-
quency in Hz. If the desired voltage conversion does
not meet the above condition, then pulse skipping
occurs to decrease the effective duty cycle. To avoid
this, decrease the switching frequency or lower the
input voltage (VSUP).
V
Vtf
OUT
SUP ON MIN SW
>×
()
VV
C
C
GS TH SUP RSS
ISS
()
>⎛
⎝
⎜⎞
⎠
⎟
Figure 1. Pulse-Skipping/Discontinuous Crossover Point
INDUCTOR CURRENT
TIME
0
VOUT
VSUPfSW
tON(SKIP) =
ON-TIME
IPK
IL
ILOAD = IPK/2
MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
16 Maxim Integrated
Setting the Output Voltage
Connect FB to BIAS to enable the fixed step-down con-
troller output voltage (5V), set by a preset, internal
resistive voltage-divider connected between the output
(OUT) and SGND.
To achieve other output voltages between 1V to 10V,
connect a resistive divider from OUT to FB to SGND
(Figure 2). Select RFB2 (FB to SGND resistor) less than
or equal to 100kΩ. Calculate RFB1 (OUT to FB resistor)
with the following equation:
where VFB = 1V (typ) (see the
Electrical Characteristics
table) and VOUT can range from 1V to 10V.
Setting the Switching Frequency
The switching frequency, fSW, is set by a resistor
(RFOSC) connected from FOSC to SGND. See Figure 3
to select the correct RFOSC value for the desired
switching frequency.
For example, a 400kHz switching frequency is set with
RFOSC = 76.8kΩ. Higher frequencies allow designs with
lower inductor values and less output capacitance.
Consequently, peak currents and I2R losses are lower
at higher switching frequencies, but core losses, gate-
charge currents, and switching losses increase.
Inductor Selection
Three key inductor parameters must be specified for
operation with the MAX16955: inductance value (L),
inductor saturation current (ISAT), and DC resistance
(RDCR). To select inductance value, the ratio of inductor
peak-to-peak AC current to DC average current (LIR)
must be selected first. A good compromise between
size and loss is a 30% peak-to-peak ripple current to
average-current ratio (LIR = 0.3). The switching fre-
quency, input voltage, output voltage, and selected LIR
then determine the inductor value as follows:
where VSUP(MIN) is the minimum supply voltage, VOUT is
the typical output voltage, and IOUT(MAX) is the maximum
load current. The switching frequency is set by RFOSC
(see the
Setting the Switching Frequency
section).
The MAX16955 uses internal frequency independent
slope compensation to ensure stable operation at duty
cycles above 50%. The maximum slope compensation
ramp voltage over a full clock period is 200mV. Use the
equation below to select the inductor value:
However, if it is necessary, higher inductor values can
be selected.
VV
LH f MHz
OUT
SW
[]
[] [ ] %
μ× =±125
LVV V
VfI
OUT SUP MIN OUT
SUP MIN SW OUT MA
=−
()
××
()
() (
XX LIR
)×
RR V
V
FB FB OUT
FB
12 1=⎛
⎝
⎜⎞
⎠
⎟−
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
Figure 2. Adjustable Output Voltage
MAX16955
RFB2
RFB1
OUT
FB
Figure 3. Switching Frequency vs. RFOSC
SWITCHING FREQUENCY vs. RFOSC
MAX16955 toc07
RFOSC (kI)
FREQUENCY (kHz)
135125105 11545 55 65 75 85 9535
250
300
350
400
450
500
550
600
650
700
750
800
850
900
950
1000
1050
1100
1150
1200
200
25 145
MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
17
Maxim Integrated
The exact inductor value is not critical and can be
adjusted to make trade-offs among size, cost, efficiency,
and transient response requirements. Table 1 shows a
comparison between small and large inductor sizes.
The minimum practical inductor value is one that causes
the circuit to operate at the edge of critical conduction
(where the inductor current just touches zero with every
cycle at maximum load). Inductor values lower than this
grant no further size-reduction benefit. The optimum
operating point is usually found between 25% and 45%
ripple current. When pulse skipping (FSYNC low and
light loads), the inductor value also determines the load-
current value at which PFM/PWM switchover occurs.
For the selected inductance value, the actual peak-to-
peak inductor ripple current (ΔIINDUCTOR) is defined by:
where ΔIINDUCTOR is in mA, L is in μH, and fSW is in kHz.
The core must be large enough not to saturate at the
peak inductor current (IPEAK):
Transient Response
The inductor ripple current also impacts transient
response performance, especially at low VSUP - VOUT
differentials. Low inductor values allow the inductor cur-
rent to slew faster, replenishing charge removed from
the output filter capacitors by a sudden load step. The
total output voltage sag is the sum of the voltage sag
while the inductor is ramping up and the voltage sag
before the next pulse can occur:
where DMAX is the maximum duty factor, L is the induc-
tor value in μH, COUT is the output capacitor value in
μF, t is the switching period (1/fSW) in μs, and Δt equals
(VOUT/VSUP) ×t when in fixed-frequency PWM mode, or
L ×0.2 ×IMAX/(VSUP - VOUT) when in skip mode. The
amount of overshoot (VSOAR) during a full-load to no-
load transient due to stored inductor energy can be cal-
culated as:
Current Sensing
For the most accurate current sensing, use a current-
sense resistor (RSENSE) between the inductor and the
output capacitor. Connect CS to the inductor side of
RSENSE, and OUT to the capacitor side. Dimension
RSENSE so its maximum current (IOC) induces a voltage
of VLIMIT (72mV minimum) across RSENSE.
If a higher voltage drop across RSENSE must be tolerat-
ed, divide the voltage across the sense resistor with a
voltage-divider between CS and OUT to reach VLIMIT
(72mV minimum).
The current-sense method (Figure 4) and magnitude
determine the achievable current-limit accuracy and
power loss. Typically, higher current-sense limits
provide tighter accuracy, but also dissipate more
power. For the best current-sense accuracy and over-
current protection, use a ±1% tolerance current-sense
resistor with low parasitic inductance between the
inductor and output as shown in Figure 4a.
Alternatively, high-power applications that do not
require highly accurate current-limit protection can
reduce the overall power dissipation by connecting a
series RC circuit across the inductor (Figure 4b) with an
equivalent time constant:
and:
where RCSHL is the required current-sense resistor and
RDCR is the inductor’s series DC resistance. Use the
typical inductance and RDCR values provided by the
inductor manufacturer.
Carefully observe the PCB layout guidelines to ensure the
noise and DC errors do not corrupt the differential cur-
rent-sense signals seen by CS and OUT. Place the sense
resistor close to the IC with short, direct traces, making a
Kelvin-sense connection to the current-sense resistor.
RL
CRR
DCR EQ
=+
⎛
⎝
⎜⎞
⎠
⎟
1
1
1
2
RR
RRR
CSHL DCR
=+
⎛
⎝
⎜⎞
⎠
⎟
2
12
VIL
CV
SOAR
LOAD MAX
OUT OUT
≈Δ
()
()
2
2
VLI
CVD V
SAG
LOAD MAX
OUT SUP MAX OUT
=Δ
()
×
()
−
()
()
2
2++ Δ−Δ
()
Itt
C
LOAD MAX
OUT
()
II I
PEAK LOAD MAX INDUCTOR
=+
Δ
() 2
Δ= −
()
××
IVV V
VfL
INDUCTOR OUT SUP OUT
SUP SW
INDUCTOR SIZE
SMALLER LARGER
Lower price Smaller ripple
Smaller form factor Higher efficiency
Faster load response Larger fixed-frequency range
in skip mode
Table 1. Inductor Size Comparison
MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
18 Maxim Integrated
Input Capacitor
The input filter capacitor reduces peak currents drawn
from the power source and reduces noise and voltage
ripple on the input caused by the circuit’s switching.
The input capacitor RMS current requirement (IRMS) is
defined by the following equation:
IRMS has a maximum value when the input voltage
equals twice the output voltage (VSUP = 2VOUT), so
IRMS(MAX) = ILOAD(MAX)/2.
Choose an input capacitor that exhibits less than +10°C
self-heating temperature rise at the RMS input current
for optimal long-term reliability.
The input-voltage ripple comprises ΔVQ(caused by the
capacitor discharge) and ΔVESR (caused by the ESR of
the capacitor). Use low-ESR ceramic capacitors with
high-ripple-current capability at the input. Assume the
contribution from the ESR and capacitor discharge is
equal to 50%. Calculate the input capacitance and ESR
required for a specified input voltage ripple using the
following equations:
ESR V
II
IN ESR
OUT L
=Δ
+Δ
2
II VV V
V
RMS LOAD MAX
OUT SUP OUT
SUP
=−
()
()
Figure 4. Current-Sense Configurations
MAX16955
DH
DL
L
NH
NL
LX
CS
OUT
DL
GND
RSENSE
COUT
CIN
INPUT (VIN)
a) OUTPUT SERIES RESISTOR SENSING
MAX16955
DH
DL
L
NH
NL
LX
CS
OUT
DL
GND
RDCR
RCSHL = ( )RDCR
R2
R1 + R2
R1 R2
CEQ
INDUCTOR
COUT
CIN
INPUT (VIN)
b) LOSSLESS INDUCTOR SENSING
RDCR = [ + ]
L
CEQ
1
R1
1
R2
MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
19
Maxim Integrated
where:
and:
where:
Output Capacitor
The output filter capacitor must have low enough ESR
to meet output ripple and load-transient requirements,
yet have high enough ESR to satisfy stability require-
ments. The output capacitance must be high enough to
absorb the inductor energy while transitioning from full-
load to no-load conditions without tripping the overvolt-
age fault protection. When using high-capacitance,
low-ESR capacitors, the filter capacitor’s ESR dominates
the output-voltage ripple. The size of the output capaci-
tor depends on the maximum ESR required to meet the
output-voltage ripple (VRIPPLE(P-P)) specifications:
In skip mode, the inductor current becomes discontinu-
ous, with the peak current set by the skip-mode cur-
rent-sense threshold (forced-peak IL). In skip mode, the
no-load output ripple can be determined as follows:
The actual capacitance value required relates to the
physical size needed to achieve low ESR, as well as to
the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value.
When using low-value filter capacitors, such as ceramic
capacitors, size is usually determined by the capacity
needed to prevent VSAG and VSOAR from causing
problems during load transients. Generally, once
enough capacitance is added to meet the overshoot
requirement, undershoot at the rising load edge is no
longer a problem (see the VSAG and VSOAR equations
in the
Transient Response
section). However, low-value
filter capacitors typically have high-ESR zeros that can
affect the overall stability.
Compensation Design
The MAX16955 uses an internal transconductance error
amplifier with its inverting input and its output available
to the user for external frequency compensation. The
output capacitor and compensation network determine
the loop stability. The inductor and the output capacitor
are chosen based on performance, size, and cost.
Additionally, the compensation network optimizes the
control-loop stability.
The controller uses a current-mode control scheme that
regulates the output voltage by forcing the required
current through the external inductor. The MAX16955
uses the voltage drop across the DC resistance of the
inductor or the alternate series current-sense resistor to
measure the inductor current. Current-mode control
eliminates the double pole in the feedback loop caused
by the inductor and output capacitor, resulting in a
smaller phase shift and requiring less elaborate error-
amplifier compensation than voltage-mode control. A
simple single-series resistor (RC) and capacitor (CC)
are required to have a stable, high-bandwidth loop in
applications where ceramic capacitors are used for
output filtering (Figure 5). For other types of capacitors,
due to the higher capacitance and ESR, the frequency
of the zero created by the capacitance and ESR is
lower than the desired closed-loop crossover frequen-
cy. To stabilize a nonceramic output capacitor loop,
add another compensation capacitor (CF) from COMP
to SGND to cancel this ESR zero.
VV ESR
R
RIPPLE P P SKIP
SENSE
()−=×
V ESR I LIR
RIPPLE P P LOAD MAX() ( )−=× ×
DV
V
OUT
SUP
=
CIDD
Vf
IN OUT
QSW
=×−
()
Δ×
1
Δ= −
()
×
××
IVV V
VfL
LSUP OUT OUT
SUP SW
Figure 5. Compensation Network
R1
RC
R2
CCCF
VOUT
VREF
gmCOMP
MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
20 Maxim Integrated
The basic regulator loop is modeled as a power modu-
lator, output feedback divider, and an error amplifier.
The power modulator has a DC gain set by gmc ×
RLOAD, with a pole and zero pair set by RLOAD, the out-
put capacitor (COUT), and its ESR. The following equa-
tions determine the approximate value for the gain of
the power modulator (GAINMOD(dc)), neglecting the
effect of the ramp stabilization. Ramp stabilization is
necessary when the duty cycle is above 50% and is
internally and automatically done for the MAX16955:
where RLOAD = VOUT/IOUT(MAX) in Ω, fSW is the switch-
ing frequency in MHz, L is the output inductance in μH,
and gmc = 1/(AV_CS ×RDC) in S. AV_CS is the voltage
gain of the current-sense amplifier and is typically
11V/V (see the
Electrical Characteristics
table). RDC is
the DC-resistance of the inductor or the current-sense
resistor in Ω.
In a current-mode step-down converter, the output
capacitor, its ESR, and the load resistance introduce a
pole at the following frequency:
The output capacitor and its ESR also introduce a zero at:
When COUT is composed of n identical capacitors in
parallel, the resulting COUT = n ×COUT(EACH), and ESR
= ESR(EACH)/n. Note that the capacitor zero for a paral-
lel combination of like capacitors is the same as for an
individual capacitor.
The feedback voltage-divider has a gain of GAINFB =
VFB/VOUT, where VFB is 1V (typ).
The transconductance error amplifier has a DC gain of
GAINEA(dc) = gm,EA ×ROUT,EA, where gm,EA is the
error amplifier transconductance, and ROUT,EA is the
output resistance of the error amplifier. Use gm,EA of
2500μS (max) and ROUT,EA of 30MΩ(typ) for compen-
sation design with the highest phase margin.
A dominant pole (fdpEA) is set by the compensation
capacitor (CC), the compensation resistor (RC), and the
amplifier output resistance (ROUT,EA). A zero (fzEA) is
set by the compensation resistor (RC) and the compen-
sation capacitor (CC). There is an optional pole (fpEA)
set by CFand RCto cancel the output capacitor ESR
zero if it occurs near the crossover frequency (fC,
where the loop gain equals 1 (0dB)).
Thus:
The loop-gain crossover frequency (fC) should be set
below 1/5 the switching frequency and much higher
than the power-modulator pole (fpMOD):
The total loop gain as the product of the modulator
gain, the feedback voltage-divider gain, and the error
amplifier gain at fCshould be equal to 1. So:
For the case where fzMOD is greater than fC:
Therefore:
Solving for RC:
Set the error-amplifier compensation zero formed by RC
and CC(fzEA) at the fpMOD. Calculate the value of CC
as follows:
CfR
CpMOD C
=××
1
2π
RV
g V GAIN
COUT
mEA FB MOD fC
=××
()
,
GAIN V
VgR
MOD fC FB
OUT mEA C
()
×××=
,1
GAIN g R
GAIN GAIN
EA fC mEA C
MOD fC MOD dc
()
()
=×
=×
,
()
ff
f
pMOD
C
GAIN V
VGAIN
MOD fC FB
OUT EA fC
() ()
×× =1
ff
f
pMOD C SW
<< ≤ 5
fCR R
fCR
f
dpEA COUTEAC
zEA CC
pEA
=×× +
()
=××
1
2
1
2
π
π
,
== ××
1
2πCR
FC
fESR C
zMOD OUT
=××
1
2π
fCR
pMOD OUT LOAD
=××
1
2π
GAIN g R
MOD dc mc LOAD()
≅×
MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
21
Maxim Integrated
If fzMOD is less than 5 x fC, add a second capacitor,
CF, from COMP to SGND and set the compensation
pole formed by RCand CF(fpEA) at the fzMOD.
Calculate the value of CFas follows:
As the load current decreases, the modulator pole also
decreases; however, the modulator gain increases
accordingly and the crossover frequency remains the
same.
For the case where fzMOD is less than fC:
The power-modulator gain at fCis:
The error-amplifier gain at fCis:
Therefore:
Solving for RC:
Set the error-amplifier compensation zero formed by RC
and CCat the fpMOD (fzEA = fpMOD):
If fzMOD is less than 5 ×fC, add a second capacitor CF
from COMP to SGND. Set fpEA = fzMOD and calculate
CFas follows:
MOSFET Selection
The MAX16955’s controller drives two external logic-
level n-channel MOSFETs as the circuit switch ele-
ments. The key selection parameters to choose these
MOSFETs include:
• On-resistance (RDS(ON))
• Maximum drain-to-source voltage (VDS(MAX))
• Minimum threshold voltage (VTH(MIN))
• Total gate charge (QG)
• Reverse-transfer capacitance (CRSS)
• Power dissipation
Both n-channel MOSFETs must be logic-level types
with guaranteed on-resistance specifications at VGS =
4.5V. Ensure that the conduction losses at minimum
input voltage do not exceed MOSFET package thermal
limits or violate the overall thermal budget. Also, ensure
that the conduction losses, plus switching losses at the
maximum input voltage, do not exceed package ratings
or violate the overall thermal budget. The MAX16955’s
DL gate driver must drive the low-side MOSFET (NL). In
particular, check that the dV/dt caused by the high-side
MOSFET (NH) turning on does not pull up the NL gate
through its drain-to-gate capacitance. This is the most
frequent cause of cross-conduction problems.
Gate-charge losses are dissipated by the driver and do
not heat the MOSFET. Therefore, if the drive current is
taken from the internal LDO regulator, the power dissi-
pation due to drive losses must be checked. Both
MOSFETs must be selected so that their total gate
charge is low enough; therefore, BIAS can power both
drivers without overheating the IC:
PDRIVE = (VSUP - VBIAS) ×QG_TOTAL ×fSW
where QG_TOTAL is the sum of the gate charges of both
MOSFETs.
Boost-Flying Capacitor Selection
The bootstrap capacitor stores the gate voltage for the
internal switch. Its size is constrained by the switching
frequency and the gate charge of the high-side
MOSFET. Ideally the bootstrap capacitance should be
at least nine times the gate capacitance:
This results in a 10% voltage drop when the gate is
driven. However, if this value becomes too large to be
recharged during the minimum off-time, a smaller
capacitor must be chosen.
CQ
V
BST TYP G
BIAS
()
=×9
CRf
FCzMOD
=××
1
2π
CfR
CMOD C
=××
1
22
π
RVf
g V GAIN f
COUT C
mEA FB MOD fC zMOD
=×
×× ×
()
,
GAIN V
VgR
f
f
MOD fC FB
OUT mEA C zMOD
C
()
×××× =
,1
GAIN g R f
f
EA fC mEA C zMOD
C
()
=××
,
GAIN GAIN f
f
MOD fC MOD dc
pMOD
zMOD
() ()
=×
CfR
FzMOD C
=××
1
2π
MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
22 Maxim Integrated
During recharge, the internal bootstrap switch acts as a
resistor, resulting in an RC circuit with the associated
time constants. Two τs (time constants) are necessary
to charge from 90% to 99%. The maximum allowable
capacitance is, therefore:
When in dropout, tOFF(MIN) is the minimum on-time of
the low-side switch and is approximately half the clock
period. When not in dropout, tOFF(MIN) = 1 - DMAX.
Should this value be lower than the ideal capacitance
and assuming that the minimum bootstrap capacitor
should be large enough to supply 2V (typ) effective
gate voltage:
Should the minimum value still be too large to be
recharged sufficiently, a parallel bootstrap Schottky
diode may be necessary.
Power Dissipation
The MAX16955’s maximum power dissipation depends
on the thermal resistance from the die to the ambient
environment and the ambient temperature. The thermal
resistance depends on the device package, PCB cop-
per area, other thermal mass, and airflow.
The device’s power dissipation depends on the internal
linear regulator current consumption (PLIN) and the
dynamic gate current (PGATE):
PT= PLIN + PGATE
Linear power is the average bias current times the volt-
age drop from VSUP to VBIAS:
PLIN = IBIAS,AV ×(VSUP - VBIAS)
where IBIAS,AV = ISUP(MAX) + fSW × (QG_DH(MAX) +
QG_DL(MAX)), ISUP(MAX) is 2mA, fSW is the switching
frequency programmed at FOSC, and QG_ is the MOS-
FET data sheet’s total gate-charge specification limits
at VGS = 5V.
Dynamic power is the average power during charging
and discharging of both the external gates per period
of oscillation:
where:
is the frequency-dependent power, dissipated during
one turn-on and turn-off cycle of each of the external
n-channel MOSFETs. RHS/LS is the on-resistance of the
NH and NL.
To estimate the temperature rise of the die, use the fol-
lowing equation:
TJ= TA+ (PT×θ
JA)
where θJA is the junction-to-ambient thermal resistance
of the package, PTis power dissipated in the device,
and TAis the ambient temperature. The θJA is 38.3°C/W
for the 16-pin TSSOP package on multilayer boards,
with the conditions specified by the respective JEDEC
standards (JESD51-5, JESD51-7). If actual operating
conditions significantly deviate from those described in
the JEDEC standards, then an accurate estimation of
the junction temperature requires a direct measurement
of the case temperature (TC). Then, the junction temper-
ature can be calculated using the following equation:
TJ= TC+ (PT×θ
JC)
Use 3°C/W as θJC thermal resistance for the 16-pin
TSSOP package. The case-to-ambient thermal resis-
tance (θCA) is dependent on how well the heat is trans-
ferred from the PCB to the ambient. Therefore, solder
the exposed pad of the TSSOP package to a large
copper area to spread heat through the board surface,
minimizing the case-to-ambient thermal resistance. Use
large copper areas to keep the PCB temperature low.
20210
26
××≈×
−
V
RtW
Hz
BIAS
HS LS GRISE
/,.
PV
Rtf
GATE BIAS
HS LS GRISE SW
=× × ×2
2
/,
CQ
VVV
BST MIN G
BIAS MIN TH TYP
() () ()
=−−2
Ct
R
BST MAX OFF MIN
BST MAX
() ()
()
=×2
MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
23
Maxim Integrated
Applications Information
PCB Layout Guidelines
Make the controller ground connections as follows: cre-
ate a small analog ground plane near the IC by using
any of the PCB layers. Connect this plane to SGND and
use this plane for the ground connection for the SUP
bypass capacitor, compensation components, feed-
back dividers, and FOSC resistor.
Place all power components on the top side of the
board and run the power stage currents, especially
large high-frequency components, using traces or cop-
per fills on the top side only, without adding vias.
On the top side, lay out a large PGND copper area for
the output, and connect the bottom terminals of the high-
frequency input capacitors, output capacitors, and the
source terminals of the low-side MOSFET to that area.
Keep the power traces and load connections short,
especially at the ground terminals. This practice is
essential for high efficiency and jitter-free operation. Use
thick copper PCBs (2oz. vs. 1oz.) to enhance efficiency.
Place the controller IC adjacent to the synchronous
rectifier MOSFET (NL) and keep the connections for LX,
PGND, DH, and DL short and wide. Use multiple small
vias to route these signals from the top to the bottom
side if these signals need to be routed in the bottom
layer. The gate current traces must be short and wide,
measuring 50 mils to 100 mils wide if the low-side
MOSFET is 1in from the controller IC. Connect the
PGND trace from the IC close to the source terminal of
the low-side MOSFET.
Route high-speed switching nodes (BST, LX, DH, and
DL) away from the sensitive analog areas (FOSC,
COMP, and FB). Group all SGND-referred and feed-
back components close to the IC. Keep the FB and
compensation network nets as small as possible to pre-
vent noise pickup.
Place the sense resistor close to the IC with short,
direct traces, making a Kelvin-sense connection to the
current-sense resistor.
Place BIAS capacitor close to the IC and minimize vias in
the path in order to minimize transients on the BIAS line.
Figure 6. Typical Operating Circuit for VOUT = 5V
MAX16955
R4
R2
D2
RED
D1
BIAS FB
OUT
C2
FOSC
FSYNC
SGND
R5
R1
R3
COMP
C9
C8
C7
C1 C3
C4
SUP
BST
N1-A
N1-B
PGND
DL
L1
LX
VOUT
5V
6
4
3
PGOOD
10
5
VL_IN
EN
2
VEN
1
VBAT
5.5V TO 28V
713 C6 C5
9
11
12
14
CS 8
16
DH 15
MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
24 Maxim Integrated
Figure 7. Typical Operating Circuit for Adjustable Output Voltage, VOUT = 1.2V/5A
Chip Information
PROCESS: BiCMOS
MAX16955
R5
R7
D1
BIAS FB
OUT
C2
FOSC
FSYNC
SGND
R6
R1
R2
R3
COMP
C8
C9
C7
C1 C3
C4
SUP
BST
N1-A
N1-B
PGND
DL
L1
LX
VOUT
1.2V/5A
*CONNECT FSYNC TO BIAS FOR FIXED-FREQUENCY PWM MODE.
CONNECT FSYNC TO SGND FOR SKIP MODE.
6
4
3
PGOOD
10
5
*VBIAS
EN
2
VEN
1
VBAT
5.5V TO 28V
713 C5 C6
9
11
12
14
CS 8
16
DH 15
R4
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
16 TSSOP-EP U16E+3 21-0108 90-0120
MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________________________
25
© 2014 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
0 3/11 Initial release —
1 9/12 Updated limiting output range to 10V 1, 2, 10,
12, 16, 20
2 1/13 Added MAX16955AUE+ to Ordering Information 1
3 12/13 Updated Transient Response section 17
47/14
Updated Electrical Characteristics for DH and DL gate-driver on-resistance, TOCs
11, 12, 14, 16, 17, 27–30, pins 12 and 15 in Pin Description; and updated the
Fixed 5V Linear Regulator (BIAS), Overcurrent Protection, Power-Good Detection
(PGOOD), Automatic Pulse-Skipping Crossover, MOSFET Gate Drivers (DH and
DL), Output Capacitor, and PCB Layout Guidelines sections
4, 6–8, 10,
12–15, 19
