Preliminary W24256 32K x 8 CMOS STATIC RAM GENERAL DESCRIPTION The W24256 is a normal speed, very low power CMOS static RAM organized as 32768 x 8 bits that operates on a single 5-volt power supply. This device is manufactured using Winbond's high performance CMOS technology. FEATURES * Low power consumption: Access time: 70 nS (max.) * Active :300 mW Standby :250 W * Single 5V power supply * Fully static operation * All inputs and outputs directly TTL compatible * * * PIN CONFIGURATIONS BLOCK DIAGRAM * * Three-state outputs Battery back-up operation capability Data retention voltage: 2V (min.) Packaged in 28-pin 600 mil DIP, 330 mil SOP and standard type one TSOP (8 mm x 13.4 mm) CLK GEN. PRECHARGE CKT. A12 A14 A2 A3 A14 1 28 VDD A12 2 27 WE A4 A7 3 26 A13 A5 A6 4 25 A8 A6 A5 5 24 A9 A7 A4 6 23 A11 A13 22 OE A10 28-pin DIP A3 7 A2 8 21 A1 9 20 CS A0 10 19 I/O8 I/O1 11 18 I/O7 I/O2 12 17 I/O6 I/O3 13 16 I/O5 VSS 14 15 I/O4 I/O1 I/O8 R O W D E C O D E R DATA CNTRL. CORE CELL ARRAY 512 ROWS 64 X 8 COLUMNS I/O CKT. COLUMN DECODER CLK GEN. A11 A10 A1 A0 A8 A9 WE CS OE PIN DESCRIPTION OE A11 A9 A8 A13 WE VDD A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28-pin TSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 SYMBOL CS DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Input WE Write Enable Input OE VDD VSS Output Enable Input A0-A14 I/O1-I/O8 -1- Power Supply Ground Publication Release Date: October 1999 Revision A1 Preliminary W24256 TRUTH TABLE MODE VDD CURRENT I/O1-I/O8 CS OE WE H X X Not Selected High Z ISB, ISB1 L H H Output Disable High Z IDD L L H Read Data Out IDD L X L Write Data In IDD DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER Supply Voltage to VSS RATING Potential UNIT -0.5 to +7.0 V Input/Output to VSS Potential -0.5 to VDD +0.5 V Allowable Power Dissipation 1.0 W -65 to +150 C 0 to 70 C Storage Temperature Operating Temperature Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Operating Characteristics (VDD = 5V 10%; VSS = 0V; TA = 0 C to 70 C) PARAMETER SYM. TEST CONDITIONS Input Low Voltage VIL MIN. TYP.* Input High Voltage VIH Input Leakage Current ILI Output Leakage Current ILO MAX. UNIT - -0.5 - +2.2 - +0.8 V - VDD +1 V VIN = VSS to VDD -5 - +5 A VI/O = VSS to VDD, CS = VIH (min.) or OE = VIH (min.) or -5 - +5 A - 0.4 V WE = VIL (max.) Output Low Voltage VOL IOL = +2.1 mA - Output High Voltage VOH IOH = -1.0 mA 2.4 - - V Operating Power IDD CS = VIL (max.), I/O = 0 mA , Cycle = min , Duty = 100 % - - 60 mA ISB CS = VIH (min.), Cycle = min. Duty = 100% - - 3 mA ISB1 CS VDD -0.2V L - - 100 A LL - - 50 A Supply Current Standby Power Supply Current Note: Typical parameter is measured under ambient temperature TA = 25 C and VDD = 5V. -2- Preliminary W24256 CAPACITANCE (VDD = 5V, TA = 25 C, f = 1 MHz) PARAMETER SYM. CONDITIONS MAX. UNIT Input Capacitance CIN VIN = 0V 6 pF Input/Output Capacitance CI/O VOUT 8 pF = 0V Note: These parameters are sampled but not 100% tested. AC CHARACTERISTICS AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels 0V to 3.0V Input Rise and Fall Times 5 nS Input and Output Timing Reference Level 1.5V Output Load See the drawing below AC TEST LOADS AND WAVEFORM 1 TTL 1 TTL OUTPUT OUTPUT 5 pF Including Jig and Scope 100 pF Including Jig and Scope (For TCLZ, TOLZ, TCHZ, TOHZ, TWHZ, TOW ) 3.0V 90% 10% 0V 90% 10% 5 nS 5 nS -3- Publication Release Date: October 1999 Revision A1 Preliminary W24256 AC Characteristics, continued (VDD = 5V 10%; VSS = 0V; TA = 0 C to 70 C) Read Cycle PARAMETER SYM. W24256-70L/LL MIN. MAX. UNIT Read Cycle Time TRC 70 - nS Address Access Time TAA - 70 nS Chip Select Access Time TACS - 70 nS Output Enable to Output Valid TAOE - 30 nS Chip Selection to Output in Low Z TCLZ* 5 - nS Output Enable to Output in Low Z TOLZ* 5 - nS Chip Deselection to Output in High Z TCHZ* - 20 nS Output Disable to Output in High Z TOHZ* - 20 nS Output Hold from Address Change TOH 3 - nS SYM. W24256-70L/LL These parameters are sampled but not 100% tested Write Cycle PARAMETER MIN. MAX. UNIT Write Cycle Time TWC 70 - nS Chip Selection to End of Write TCW 70 - nS Address Valid to End of Write TAW 70 - nS Address Setup Time TAS 0 - nS Write Pulse Width TWP 50 - nS TWR 0 - nS Data Valid to End of Write TDW 30 - nS Data Hold from End of Write TDH 0 - nS Write Recovery Time CS, WE Write to Output in High Z TWHZ* - 25 nS Output Disable to Output in High Z TOHZ* - 30 nS Output Active from End of Write TOW 5 - nS These parameters are sampled but not 100% tested -4- Preliminary W24256 TIMING WAVEFORMS Read Cycle 1 (Address Controlled) TRC Address TAA TOH TOH DOUT Read Cycle 2 (Chip Select Controlled) CS TACS TCHZ TCLZ DOUT Read Cycle 3 (Output Enable Controlled) T RC Address T AA OE T OH T AOE T OLZ CS T ACS D OUT T CHZ T OHZ TCLZ -5- Publication Release Date: October 1999 Revision A1 Preliminary W24256 Timing Waveforms, continued Write Cycle 1 TWC Address T WR OE TCW CS T AW WE T WP TAS TOHZ (1, 4) D OUT T DW TDH D IN Write Cycle 2 ( OE = VIL Fixed) T WC Address TWR TCW CS TAW WE TOH T WP TAS TWHZ (1, 4) D OUT TDW (2) (3) TOW TDH DIN Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from DOUT are the same as the data written to DIN during the write cycle. 3. DOUT provides the read data for the next address. 4. Transition is measured 500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested. -6- Preliminary W24256 DATA RETENTION CHARACTERISTICS (TA = 0 C to 70 C) PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT 2.0 - 5.5 V VDD for Data Retention VDR CS VDD -0.2V Data Retention Current IDDDR CS VDD -0.2V, VDD = 3V - - 20 A Chip Deselect to Data Retention Time TCDR See data retention waveform 0 - - nS Operation Recovery Time TR TRC* - - nS * Read Cycle Time DATA RETENTION WAVEFORM VDD 0.9 V DD VDR > = 2V 0.9 V DD TCDR TR CS > = V DD - 0.2V V IH CS VIH ORDERING INFORMATION PART NO. ACCESS TIME (nS) OPERATING CURRENT MAX. (mA) STANDBY CURRENT MAX. ( A) PACKAGE W24256-70L 70 60 100 600 mil DIP W24256-70LL 70 60 50 600 mil DIP W24256S-70L 70 60 100 330 mil SOP W24256S-70LL 70 60 50 330 mil SOP W24256Q-70L 70 60 100 Standard type one TSOP W24256Q-70LL 70 60 50 Standard type one TSOP Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. -7- Publication Release Date: October 1999 Revision A1 Preliminary W24256 PACKAGE DIMENSIONS 28-pin P-DIP Dimension in Inches Symbol A A1 A2 B B1 c D E E1 e1 L D 28 15 a E1 eA S Notes: 1 14 E S c A A2 A1 L Base Plane Seating Plane B e1 eA a B1 Min. Nom. Max. Dimension in mm Min. Nom. Max. 0.210 0.010 5.33 0.25 0.150 0.155 0.160 3.81 3.94 4.06 0.016 0.018 0.022 0.41 0.46 0.56 0.058 0.060 0.064 1.47 1.52 0.008 0.010 0.014 0.20 1.460 1.470 0.590 0.600 0.610 0.540 0.545 0.550 0.090 0.100 0.130 0.120 0 0.630 0.650 1.63 0.25 0.36 37.08 37.34 14.99 15.24 15.49 13.72 13.84 13.97 0.110 2.29 2.54 2.79 0.140 3.05 3.30 3.56 15 0 0.670 16.00 16.51 17.02 15 0.090 2.29 1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimensions D & E1 include mold mismatch and are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. . 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. 28-pin SOP Wide Body Symbol 28 A A1 A2 b c D E e HE L LE S y 15 e1 E HE L Detail F 14 1 b Dimension in Inches Dimension in mm Min. Nom. Max. Min. Nom. Max. 2.85 0.112 0.004 0.093 0.10 0.098 0.103 2.36 2.49 0.014 0.016 0.020 0.36 0.41 0.51 0.008 0.010 0.014 0.20 0.25 0.36 0.713 0.733 18.11 18.62 0.326 0.331 0.336 8.28 8.41 0.044 0.050 0.056 1.12 1.27 1.42 0.453 0.465 0.477 11.51 11.81 12.12 0.028 0.036 0.044 0.71 0.91 1.12 0.059 0.067 0.075 1.50 1.70 1.91 0 2.62 8.53 0.047 1.19 0.004 0.10 10 0 10 Notes: e1 D c A2 A S e Seating Plane y LE A1 See Detail F -8- 1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion/intrusion. 3. Dimensions D & E include mold mismatch . and determined at the mold parting line. 4. Controlling dimension: Inches. 5. General appearance spec should be based on final visual inspection spec. Preliminary W24256 Package Dimensions, continued 28-pin Standard Type One TSOP HD Dimension In Inches Dimension In mm Symbol Min. D c A A1 A2 b c D E HD e L L1 Y 1 e E b A2 A A1 L Nom. Max. Min. Nom. 0.002 Max. 1.20 0.047 0.006 0.05 0.15 0.035 0.040 0.041 0.95 1.00 0.007 0.008 0.011 0.17 0.20 0.27 0.004 0.006 0.008 0.10 0.15 0.21 11.90 1.05 0.461 0.465 0.469 11.70 11.80 0.311 0.315 0.319 7.90 8.00 8.10 0.520 0.528 0.536 13.20 13.40 13.60 0.028 0.50 0.60 0.022 0.020 0.024 0.55 0.010 0.000 0 3 0.70 0.25 0.004 0.00 5 0 0.10 3 5 Controlling dimension: Millimeters Y L1 -9- Publication Release Date: October 1999 Revision A1 Preliminary W24256 VERSION HISTORY VERSION DATE PAGE A1 Oct. 1999 - Headquarters DESCRIPTION Initial issued Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. - 10 - Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798