Preliminary W24256
32K × 8 CMOS STATIC RAM
Publication Release Date: October 1999
- 1 - Revision A1
GENERAL DESCRIPTION
The W24256 is a normal speed, very low power CMOS static RAM organized as 32768 × 8 bits that
operates on a single 5-volt power supply. This device is manufactured using Winbond's high
performance CMOS technology.
FEATURES
• Low power consumption:
• Access time: 70 nS (max.)
• Active :300 mW
Standby :250 µW
• Single 5V power supply
• Fully static operation
• All inputs and outputs directly TTL compatible
• Three-state outputs
• Battery back-up operation capability
• Data retention voltage: 2V (min.)
• Packaged in 28-pin 600 mil DIP, 330 mil SOP
and standard type one TSOP (8 mm × 13.4
mm)
PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28-pin
DIP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
WE
A13
A8
A9
A11
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28-pin
TSOP
OE
A11
A9
A8
A13
WE
VDD
A14
A12
A7
A6
A5
A4
A3
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
A0
A1
A2
VSS
BLOCK DIAGRAM
CLK GEN. PRECHARGE CKT.
CORE CELL ARRAY
512 ROWS
64 X 8 COLUMNS
DATA
CNTRL.
CLK
GEN.
R
O
W
D
E
C
O
D
E
R
A12
A14
A2
A3
A4
A5
A6
A7
A13
A11
I/O CKT.
COLUMN DECODER
OE
WE
CS
I/O1
I/O8
A10 A1 A0 A8 A9
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0−A14 Address Inputs
I/O1−I/O8 Data Inputs/Outputs
CS Chip Select Input
WE Write Enable Input
OE Output Enable Input
VDD Power Supply
VSS Ground
Preliminary W24256
- 2 -
TRUTH TABLE
CS
OE
WE
MODE I/O1
−
I/O8 VDD CURRENT
H X X Not Selected High Z ISB, ISB1
L H H Output Disable High Z IDD
L L H Read Data Out IDD
L X L Write Data In IDD
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER RATING UNIT
Supply Voltage to VSS Potential -0.5 to +7.0 V
Input/Output to VSS Potential -0.5 to VDD +0.5 V
Allowable Power Dissipation 1.0 W
Storage Temperature -65 to +150 °C
Operating Temperature 0 to 70 °C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
Operating Characteristics
(VDD = 5V ±10%; VSS = 0V; TA = 0° C to 70° C)
PARAMETER SYM.
TEST CONDITIONS MIN. TYP.*
MAX. UNIT
Input Low Voltage VIL - -0.5 - +0.8 V
Input High Voltage VIH - +2.2 - VDD +1 V
Input Leakage Current ILI VIN = VSS to VDD -5 - +5
µA
Output Leakage Current ILO VI/O = VSS to VDD, CS = VIH
(min.) or OE = VIH (min.) or
WE = VIL (max.)
-5 - +5
µA
Output Low Voltage VOL IOL = +2.1 mA - - 0.4 V
Output High Voltage VOH IOH = -1.0 mA 2.4 - - V
Operating Power
Supply Current
IDD CS = VIL (max.), I/O = 0 mA ,
Cycle = min , Duty = 100 %
- - 60 mA
Standby Power Supply
Current
ISB CS = VIH (min.), Cycle = min.
Duty = 100%
- - 3 mA
ISB1 CS ≥ VDD -0.2V L - - 100
µA
LL - - 50 µA
Note: Typical parameter is measured under ambient temperature TA = 25° C and VDD = 5V.
Preliminary W24256
Publication Release Date: October 1999
- 3 - Revision A1
CAPACITANCE
(VDD = 5V, TA = 25° C, f = 1 MHz)
PARAMETER SYM. CONDITIONS MAX. UNIT
Input Capacitance CIN V
IN = 0V 6 pF
Input/Output Capacitance CI/O V
OUT = 0V 8 pF
Note: These parameters are sampled but not 100% tested.
AC CHARACTERISTICS
AC Test Conditions
PARAMETER CONDITIONS
Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 5 nS
Input and Output Timing Reference Level 1.5V
Output Load See the drawing below
AC TEST LOADS AND WAVEFORM
90% 90%
5 nS
10%
5 nS
10%
OUTPUT OUTPUT
3.0V
0V
100 pF
Including
Jig and
Scope
5 pF
Including
Jig and
Scope
1 TTL 1 TTL
CLZ, OLZ, CHZ, OHZ, WHZ, OW
(For T T T T T T )
Preliminary W24256
- 4 -
AC Characteristics, continued
(VDD = 5V ±10%; VSS = 0V; TA = 0° C to 70° C)
Read Cycle
PARAMETER SYM. W24256-70L/LL UNIT
MIN. MAX.
Read Cycle Time TRC 70 - nS
Address Access Time TAA - 70 nS
Chip Select Access Time TACS - 70 nS
Output Enable to Output Valid TAOE - 30 nS
Chip Selection to Output in Low Z TCLZ* 5 - nS
Output Enable to Output in Low Z TOLZ* 5 - nS
Chip Deselection to Output in High Z TCHZ* - 20 nS
Output Disable to Output in High Z TOHZ* - 20 nS
Output Hold from Address Change TOH 3 - nS
∗ These parameters are sampled but not 100% tested
Write Cycle
PARAMETER SYM. W24256-70L/LL UNIT
MIN. MAX.
Write Cycle Time TWC 70 - nS
Chip Selection to End of Write TCW 70 - nS
Address Valid to End of Write TAW 70 - nS
Address Setup Time TAS 0 - nS
Write Pulse Width TWP 50 - nS
Write Recovery Time CS, WE TWR 0 - nS
Data Valid to End of Write TDW 30 - nS
Data Hold from End of Write TDH 0 - nS
Write to Output in High Z TWHZ* - 25 nS
Output Disable to Output in High Z TOHZ* - 30 nS
Output Active from End of Write TOW 5 - nS
∗ These parameters are sampled but not 100% tested
Preliminary W24256
Publication Release Date: October 1999
- 5 - Revision A1
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
Address
TRC
T
AA
TOH TOH
DOUT
Read Cycle 2
(Chip Select Controlled)
CS
DOUT
TCLZ
TACS
CHZ
T
Read Cycle 3
(Output Enable Controlled)
Address
TRC
CS
DOUT
TAA
OE
TAOE
TOLZ
TOH
CLZ
T
CHZ
T
TACS TOHZ
Preliminary W24256
- 6 -
Timing Waveforms, continued
Write Cycle 1
Address
OE
CS
WE
DOUT
DIN
TWC
TWR
TCW
TWP
TAS
TOHZ (1, 4)
TDW TDH
TAW
Write Cycle 2
(
OE
= VIL Fixed)
Address
CS
WE
DOUT
DIN
TWC
TCW
TAS
TDH
TWR
TWP
TWHZ
DW
T
(2) (3)
TOW
TOH
AW
T
(1, 4)
Notes:
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.
2. The data output from DOUT are the same as the data written to DIN during the write cycle.
3. DOUT provides the read data for the next address.
4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
Preliminary W24256
Publication Release Date: October 1999
- 7 - Revision A1
DATA RETENTION CHARACTERISTICS
(TA = 0° C to 70° C)
PARAMETER SYM. TEST CONDITIONS MIN. TYP.
MAX. UNIT
VDD for Data Retention VDR CS ≥ VDD -0.2V 2.0 - 5.5 V
Data Retention Current IDDDR CS ≥ VDD -0.2V, VDD = 3V - - 20
µA
Chip Deselect to Data
Retention Time
TCDR See data retention waveform 0 - - nS
Operation Recovery Time TR T
RC* - - nS
* Read Cycle Time
DATA RETENTION WAVEFORM
TCDR
VDD
VIH
TR
VIH
CS
VDR 2V
=
>
- 0.2V
DD
VCS =
>
0.9 DD
V0.9 DDV
ORDERING INFORMATION
PART NO. ACCESS
TIME
(nS)
OPERATING
CURRENT MAX.
(mA)
STANDBY
CURRENT MAX.
(
µ
A)
PACKAGE
W24256-70L 70 60 100 600 mil DIP
W24256-70LL 70 60 50 600 mil DIP
W24256S-70L 70 60 100 330 mil SOP
W24256S-70LL 70 60 50 330 mil SOP
W24256Q-70L 70 60 100 Standard type one TSOP
W24256Q-70LL 70 60 50 Standard type one TSOP
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.
Preliminary W24256
- 8 -
PACKAGE DIMENSIONS
28-pin P-DIP
Seating Plane
1. Dimensions D Max. & S include mold flash or
tie bar burrs.
2. Dimension E1 does not include interlead flash.
3. Dimensions D & E1 include mold mismatch and
are determined at the mold parting line.
6. General appearance spec. should be based on
final visual inspection spec.
.
1.631.47
0.0640.058
Notes:
Symbol Min. Nom. Max. Max.Nom.Min.
Dimension in Inches Dimension in mm
A
B
c
D
e
A
L
S
A
A
1
2
E
0.060 1.52
0.210 5.33
0.010
0.150
0.016
0.155
0.018
0.160
0.022
3.81
0.41
0.25
3.94
0.46
4.06
0.56
0.008
0.120
0.670
0.010
0.130
0.014
0.140
0.20
3.05
0.25
3.30
0.36
3.56
0.540 0.5500.545 13.72 13.9713.84
17.02
15.24
14.99 15.49
0.6000.590 0.610
2.29 2.54 2.79
0.090 0.100 0.110
B1
1
e
E1
a
1.460 1.470 37.08 37.34
015
0.090 2.29
0.650
0.630 16.00 16.51
4. Dimension B1 does not include dambar
protrusion/intrusion.
5. Controlling dimension: Inches.
150
eA
2A
a
c
E
Base Plane
1
A
1
e
L
A
S
1
E
D
1
B
B
28
1
15
14
28-pin SOP Wide Body
2
1
A
28 15
14
1
e
S
EH
b
Seating Plane
AA
yL
L
e
c
See Detail F
D
E
E
1
1e
Detail F
1. Dimensions D Max. & S include mold flash
or tie bar burrs.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Dimensions D & E include mold mismatch
and determined at the mold parting line.
.
0.250.20
0.0100.008
Notes:
Symbol Min. Nom. Max. Max.
Nom.
Min.
Dimension in Inches Dimension in mm
0.014 0.36
0.112 2.85
0.004
0.093
0.014
0.098
0.016
0.103
0.020
2.36
0.36
0.10
2.49
0.41
2.62
0.51
0.059
0.004
010
0.713
0.067
0.733
0.075 1.50
18.11
1.70
18.62
1.91
0.4770.4650.453 12.1211.8111.51
010
0.10
8.53
8.41
8.28
0.3360.3310.326
0.71 0.91 1.12
0.028 0.036 0.044
4. Controlling dimension: Inches.
5. General appearance spec should be based
on final visual inspection spec.
1.12 1.27 1.420.044 0.050 0.056
1.19
0.047
A
b
c
D
e
HE
L
y
A
A
LE
1
2
E
S
θ
θ
Preliminary W24256
Publication Release Date: October 1999
- 9 - Revision A1
Package Dimensions, continued
28-pin Standard Type One TSOP
A
A
A
2
1
L
L1
Y
c
E
H
D
D
b
e
Controlling dimension: Millimeters
Min.
Dimension In Inches
Nom. Max. Min. Nom. Max.
Symbol
1.20
0.05 0.15
1.05
1.000.95
0.17
0.10
11.70
7.90
13.20
0.50
0.00
0
0.20 0.27
0.15 0.21
11.80 11.90
8.00 8.10
13.40 13.60
0.55
0.60 0.70
0.25
0.10
35
0.047
0.006
0.041
0.040
0.035
0.007 0.008 0.011
0.004 0.006 0.008
0.461 0.465 0.469
0.311 0.315 0.319
0.520 0.528 0.536
0.022
0.020 0.024 0.028
0.010
0.000 0.004
035
0.002
A
A
b
c
D
E
e
L
L
Y
1
1
2
A
HD
θ
Dimension In mm
θ
1
Preliminary W24256
- 10 -
VERSION HISTORY
VERSION DATE PAGE DESCRIPTION
A1 Oct. 1999 - Initial issued
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798
Note: All data and specifications are subject to change without notice.
