74373 - Fairchild Semiconductor

April 1986

Revised March 2000

DM74LS373 • DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

DM74LS373 • DM74LS374

3-STATE Octal D-Type Transparent Latches

and Edge-Triggered Flip-Flops

General Descript ion

These 8-bit registers feature totem-pole 3-STATE outputs

designed specifically for driving highly-capacitive or rela-

tively low- impedance loads. The hi gh -im ped ance state and

increased high-logic level drive provide these registers with

the capability of being connecte d directly to and driving the

bus line s in a bu s-or ga ni zed sy stem wi th ou t n eed fo r inte r-

face or pull-up components. They are parti cularly attractive

for implementing buffer registers, I/O ports, bidirectional

bus drivers, and working registers.

The eight latches of the DM74LS373 are transparent D-

type latches meaning that while the enable (G) is HIGH the

Q outputs will follow the data (D) inputs. When the enable

is taken LOW the outp ut will be l atched at the l evel of the

data that was set up.

The eight flip-flops of the DM74LS374 are edge-triggered

D-type flip flops . On the p ositive transitio n of the clock, the

Q outputs will be set to the logic states that were set up at

the D inputs.

A buffered output control input can be used to place the

eight o utputs in either a normal log ic state (HIGH or LOW

logic levels) or a high-impedance state. In the high-imped-

ance state th e outputs neit her load nor dr ive the bus lines

significantly.

The output co ntrol does not affect th e internal operation of

the latches or flip-flops. That is, the old data can be

reta i n ed o r ne w d at a ca n be e nt e re d ev e n w hile th e ou t put s

are OFF.

Features

■Choice of 8 latches or 8 D-type flip-flops in a single

package

■3-STATE bus-driving outputs

■Full parallel-access for loading

■Buffered control inputs

■P-N-P inputs reduce D-C loading on data lines

Ordering Code:

Devices also available in Tape and R eel. Spe ci fy by append ing the suffix let t er “X” to the o rdering code.

Order Number Package Number Package Description

DM74LS373WM M20B 20-Lead Small Outline Integrated Circuit ( SOIC), JEDEC MS-013, 0.300 Wide

DM74LS373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

DM74LS373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

DM74LS374WM M20B 20-Lead Small Outline Integrated Circuit ( SOIC), JEDEC MS-013, 0.300 Wide

DM74LS374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

IDM29901NC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

www.fairchildsemi.com 2

DM74LS373 • DM74LS374

Connection Diagrams

DM74LS373 DM74LS374

Function Tables

DM74LS373 DM74LS374

H = HIGH Level (Steady State) L = LOW Level (Steady State) X = Don’t Care Z = High Impedance State

↑ = Transition f rom LO W-to-HIGH lev el Q0 = The level of t he output b ef ore steady-stat e input conditions w ere established.

Logic Diagrams

DM74LS373

Transpar en t Lat ch e s DM74LS374

Positive-Edge-Triggered Flip-Flops

Output Enable D Output

Control G

LHHH

LHLL

LLXQ

HXXZ

Output Clock D Output

Control

L↑HH

L↑LL

LLXQ

HXXZ

3 www.fairchildsemi.com

DM74LS373 • DM74LS374

Absolute Maximum Ratings(Note 1) Note 1: The “Abso lute Maxim um Ratings” ar e those value s beyond which

the safety of the device cannot be guaranteed. The device should not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum ratings.

The “Re comm ended Operat ing Co ndition s” table will de fine the cond itions

for actu al device operation.

DM74LS373 Recommended Operating Conditions

Note 2: The symbol (↓) indicates t he falling edge of the clo c k puls e is used for refer enc e.

Note 3: TA = 25°C and VCC = 5V.

DM74LS373 Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Note 4: All typicals are at VCC = 5V, TA = 25°C.

Note 5: N ot m ore than one output sh ould be sh orted at a tim e, and the duration sh ould not ex c eed one sec ond.

Supply Voltage 7V

Input Voltage 7V

Storage Temperature Range −65°C to +150°C

Operating Free Air Temperature Range 0°C to +70°C

Symbol Parameter Min Nom Max Units

VCC Supply Voltage 4.75 5 5.25 V

VIH HIGH Level Input Voltage 2 V

VIL LOW Level Input Voltage 0.8 V

IOH HIGH Level Output Current −2.6 mA

IOL LOW Level Output Current 24 mA

tWPulse Width Enable HIGH 15 ns

(Note 3) Enable LOW 15

tSU Data Setup Time (Note 2) (Note 3) 5↓ns

tHData Hold Time (Note 2) (Note 3) 20↓ns

TAFree Air Operating Temperature 0 70 °C

Symbol Parameter Conditions Min Typ Max Units

(Note 4)

VIInput Clamp Voltage VCC = Min, II = −18 mA −1.5 V

VOH HIGH Level VCC = Min, IOH = Max 2.4 3.1 V

Output Voltage VIL = Max, VIH = Min

VOL LOW Level VCC = Min, IOL = Max

Output Voltage VIL = Max, VIH = Min 0.35 0.5 V

IOL = 12 mA, VCC = Min 0.4

IIInput Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 mA

IIH HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA

IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.4 mA

IOZH Off-State Output Current with VCC = Max, VO = 2.7V 20 µA

HIGH Level Output Voltage Applied VIH = Min, VIL = Max

IOZL Off-State Output Current with VCC = Max, VO = 0.4V −20 µA

LOW Level Output Voltage Applied VIH = Min, VIL = Max

IOS Short Circuit Output Current VCC = Max (Note 5) −50 −225 mA

ICC Supply Current VCC = Max, OC = 4.5V, 24 40 mA

Dn, Enable = GND

www.fairchildsemi.com 4

DM74LS373 • DM74LS374

DM74LS373 Switching Characteristics

at VCC = 5V and TA = 25°C

Note 6: CL = 5 pF.

DM74LS374 Recommended Operating Conditions

Note 7: The symbol (↑) in dic ates th e ris ing edge of the clock pulse is used for reference.

Note 8: TA = 25°C an d VCC = 5V.

RL = 667Ω

Symbol Parameter From (Input) CL = 45 pF CL = 150 pF Units

To (Output) Min Max Min Max

tPLH Propagati on Delay T i me Data to Q 18 26 ns

LOW-to-HIGH Level Output

tPHL Propagation Del ay T ime Data to Q 18 27 ns

HIGH-to-LOW Level Output

tPLH Propagati on Delay T i me Enable to Q 30 38 ns

LOW-to-HIGH Level Output

tPHL Propagation Del ay T ime Enable to Q 30 36 ns

HIGH-to-LOW Level Output

tPZH Output Enable Time Output Control to Any Q 28 36 ns

to HIGH Level Output

tPZL Output Enable Time Output Control to Any Q 36 50 ns

to LOW Level Output

tPHZ Output Disable Time Output Control to Any Q 20 ns

from HIGH Level Output (Note 6)

tPLZ Output Disable Time Output Control to Any Q 25 ns

from LOW Level Output (Note 6)

Symbol Parameter Min Nom Max Units

VCC Supply Voltage 4.75 5 5.25 V

VIH HIGH Level Input Voltage 2 V

VIL LOW Level Input Voltage 0.8 V

IOH HIGH Level Output Current −2.6 mA

IOL LOW Level Output Current 24 mA

tWPulse Width Clock HIGH 15 ns

(Note 8) Clock LOW 15

tSU Data Setup Time (Note 7) (Note 8) 20↑ns

tHData Hold Time (Note 7) (Note 8) 1↑ns

TAFree Air Operating Temperature 0 70 °C

5 www.fairchildsemi.com

DM74LS373 • DM74LS374

DM74LS374 Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Note 9: All typicals are at VCC = 5V, TA = 25°C.

Note 10: Not more than one output should be shorted at a time, and the duration should not exceed one second.

DM74LS374 Switching Characteristics

at VCC = 5V and TA = 25°C

Note 11: CL = 5 pF.

Symbol Parameter Conditions Min Typ Max Units

(Note 9)

VIInput Clamp Voltage V CC = Min, II = −18 mA −1.5 V

VOH HIGH Level VCC = Min, IOH = Max 2.4 3.1 V

Output Voltage VIL = Max, VIH = Min

VOL LOW Level VCC = Min, IOL = Max 0.35 0.5 VOutput Voltage VIL = Max, VIH = Min

IOL = 12 mA, VCC = Min 0.25 0.4

IIInput Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 mA

IIH HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA

IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.4 mA

IOZH Off-State Output Current with VCC = Max, VO = 2.7V 20 µA

HIGH Level Output Voltage Applied VIH = Min, VIL = Max

IOZL Off-State Output Current with VCC = Max, VO = 0.4V −20 µA

LOW Level Output Voltage Applied VIH = Min, VIL = Max

IOS Short Circuit Output Current VCC = Max (Note 10) −50 −225 mA

ICC Supply Current VCC = Max, Dn = GND, OC = 4.5V 27 45 mA

RL = 667Ω

Symbol Parameter CL = 45 pF CL = 150 pF Units

MinMaxMinMax

fMAX Maximum Clock Frequency 35 20 MHz

tPLH Propagation Delay Time 28 32 ns

LOW-to-HIGH Level Output

tPHL Propagation Delay Time 28 38 ns

HIGH-to-LOW Level Output

tPZH Output Enable Time 28 44 ns

to HIGH Level Output

tPZL Output Enable Time 28 44 ns

to LOW Level Output

tPHZ Output Disable Time 20 ns

from HIGH Level Output (Note 11)

tPLZ Output Disable Time 25 ns

from LOW Level Output (Note 11)

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DM74LS373 • DM74LS374

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M20B

7 www.fairchildsemi.com

DM74LS373 • DM74LS374

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

www.fairchildsemi.com 8

DM74LS373 • DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N20A

Fairchild does no t assume any responsibility for use of any circuitry de scribed, no circuit patent licenses ar e implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r systems a re devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent i n any compon ent of a life su pport

device or system whose failure to perform can be rea-

sonabl y ex pect ed to ca use the fa i lure of the life su pp ort

device or system, or to affect its safety or effectiveness.