PRODUCT DATASHEET AAT2601178 Total Power Solution for Portable Applications General Description Features The AAT2601 is a member of AnalogicTech's Total Power Management ICTM (TPMICTM) product family. It contains a single-cell Lithium Ion/Polymer battery charger, a fully integrated step-down converter and 5 low dropout (LDO) regulators. The device also includes 2 load switches for dynamic power path/sleep mode operation, making it ideal for small handheld portable GSM or CDMA mobile telephones. All six voltage regulators operate with low quiescent current. The total no load current when the step-down converter and 2 LDOs are enabled is only 170A. * Voltage Regulator VIN Range: 4.5V to 6V * Complete Power Integration Integrated Load Switches to Power Converters from AC Adapter or Battery Automatically * Low Standby Current 170A (typ) w/ Buck (Core), LDO1 (PowerDigital), and LDO2 (PowerAnalog) Active, No Load * One Step-Down Buck Converter (Core) 1.8V, 300mA Output 1.5MHz Switching Frequency Fast Turn-On Time (120s typ) * Five LDOs Programmable with I2C LDO1: 3.0V, 300mA (PowerDigital) LDO2: 3.0V, 150mA (PowerAnalog or PLL) LDO3: 3.0V, 150mA (TCXO) LDO4: 3.0V, 150mA (TX) LDO5: 3.0V, 150mA (RX) PSRR: 60dB@10kHz Noise: 50Vrms for LDO3, LDO4, and LDO5 * One Battery Charger Digitized Thermal Regulation Charge Current Programming up to 1.4A Charge Current Termination Programming Automatic Trickle Charge for Battery Preconditioning (2.8V Cutoff) * Adapter OK (ADPP) and Reset (RESET) Timer Outputs * Separate Enable Pins for Supply Outputs * Over-Current Protection * Over-Temperature Protection * 5x5mm TQFN55-36 Package The AAT2601 is available in a thermally enhanced low profile 5x5x0.8mm 36-pin TQFN package. Applications The battery charger is a complete thermally regulated constant current/constant voltage linear charger. It includes an integrated pass device, reverse blocking protection, high accuracy current and voltage regulation, charge status, and charge termination. The charging current, charge termination current, and recharge voltage are programmable with an external resistor and/or by a standard I2C interface. The step-down DC/DC converter is integrated with internal compensation and operates at a switching frequency of 1.5MHz, thus minimizing the size of external components while keeping switching losses low and efficiency greater than 95%. All LDO output voltages are programmable using the I2C interface. The five LDOs offer 60dB power supply rejection ratio (PSRR) and low noise operation making them suitable for powering noise-sensitive loads. * * * * * 2601.2008.01.1.0 Digital Cameras GSM or CDMA Cellular Phones Handheld Instruments PDAs and Handheld Computers Portable Media Players www.analogictech.com 1 PRODUCT DATASHEET AAT2601178 Total Power Solution for Portable Applications Typical Application To AVIN1,AVIN2, PVIN SYSOUT System Supply SYSOUT LDO 500m 100m BAT CHGIN 5V from AC Adapter or USB Port + 10F To SYSOUT - 10F 1 cell Li+ battery 100k ADPP Charger Control STAT ISET TS CT ENBAT Ref 10k NTC For BAT Temp sense USE_USB To SYSOUT 100k To SYSOUT 100k 1.24k 0.1F SDA SCL To SYSOUT EN_TEST PVIN C UVLO EN_HOLD I 2C and Enable Control EN_KEY LX VIN 3.3H Step-down BUCK Ref ON_KEY Core : 1.8V 300mA 10F 4.7F OUTBUCK PGND Enable RESET To OUT1 100k EN2 EN3 EN4 EN5 VIN REF CNOISE AVIN2 AVIN1 VIN Ref To SYSOUT 0.01F LDO1 LDO2 Enable VIN Ref LDO3 Enable VIN Ref LDO4 LDO5 Enable VIN Ref Enable Ref VIN Enable To SYSOUT AGND OUT5 RX 3.0V 150mA OUT4 TX 3.0V 150mA 4.7F 2 OUT3 TCXO 3.0V 150mA 4.7 F OUT2 OUT1 PowerAnalog 3.0V 150mA PowerDigital 3.0V 300mA 4.7F 4.7 F www.analogictech.com 22F 2601.2008.01.1.0 PRODUCT DATASHEET AAT2601178 Total Power Solution for Portable Applications Pin Descriptions Pin # Symbol 1 EN_TEST 2 EN_HOLD 3 EN_KEY 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ON_KEY EN2 EN3 EN4 EN5 OUT5 OUT4 AVIN2 OUT3 OUT2 AVIN1 OUT1 AGND CNOISE 18 RESET 19 ADPP 20 21 22 23 LX PGND PVIN OUTBUCK 24, 25 SYSOUT 26, 27 28 BAT CHGIN 29 USE_USB 30 ENBAT 31 TS 32 ISET 33 CT 34 STAT 35 36 SDA SCL EP EP 2601.2008.01.1.0 Function Similar to EN_HOLD but intended for use with the automatic tester or as a hands free enable input pin indicating hands free phone operation with a headset. It is also internally pulled to GND when floating. Enable for the system. EN_HOLD must be held high by the processor to maintain core power. It is internally pulled to GND when floating. Enable for the system. An internal pull-up resistor keeps the pin pulled up to an internal supply to keep the system off when there is no CHGIN input. Connect a normally-open pushbutton switch from this pin to GND. There is an internal 300ms debounce delay circuit to filter noise. Buffered logic output of the EN_KEY pin with a logic signal from ground to OUT1. Enable for LDO2 (PowerAnalog or PLL). (Internally pulled low when floating) Enable for LDO3 (TCXO). (Internally pulled low when floating) Enable for LDO4 (TX) (Internally pulled low when floating) Enable for LDO5 (RX) (Internally pulled low when floating) Output for LDO5 (RX) (when shut down, pulled down with 10k) Output for LDO4 (TX) (when shut down, pulled down with 10k) Analog voltage input. Must be tied to SYSOUT on the PCB. Output for LDO3 (TCXO) Output for LDO2 (PowerAnalog) Analog voltage input. Must be tied to SYSOUT on the PCB. Output for LDO1 (PowerDigital) Signal ground Noise Bypass pin for the internal reference voltage. Connect a 0.01F capacitor to AGND. RESET is the open drain output of a 50ms reset timer. RESET is released after the 50ms timer times out. RESET is active low and is held low during shutdown. RESET should be tied to a 10K or larger pullup to OUTBUCK. Open Drain output. Will pull low when VCHGIN > 4.5V. When this happens, depending on the status of the USE_USB pin, the charge current will be reset to the default values (see Battery Charger and I2C Serial Interface and Programmability section) Step-down Buck converter (Core) switching node. Connect an inductor between this pin and the output. Power Ground for step-down Buck converter (Core) Input power for step-down Buck converter (Core). Must be tied to SYSOUT. Feedback input for the step-down Buck converter (Core) System Power output. Connect to the input voltage pins PIN, AVIN1/2 for the step-down converter and LDOs and other external supply requirements. Connect to a Lithium Ion battery. Power input from either external adapter or USB port. When pulled high, fast charge current is set to 100mA regardless of the resistor value present on the ISET pin. Additionally, the CHGIN-SYSOUT LDO will be disabled and the BAT-SYSOUT load switch will be enabled. Active low enable for the battery charger (Internally pulled low when floating) Battery Temperature Sense pin with 75A output current. Connect the battery's NTC resistor to this pin and ground. Charge current programming input pin (Tie a 1k to GND for maximum fast charge current). Can be used to monitor charge current. Charger Safety Timer Pin. A 0.1F ceramic capacitor should be connected between this pin and GND. Connect directly to GND to disable the timer function. Battery charging status pin output. Connected internally between GND and OUT1 (PowerDigital). Used to monitor battery charge status. I2C serial data pin, open drain; requires a pullup resistor. I2C serial clock pin, open drain; requires a pullup resistor. The exposed thermal pad (EP) must be connected to board ground plane and pins 16 and 21. The ground plane should include a large exposed copper pad under the package for thermal dissipation (see package outline). www.analogictech.com 3 PRODUCT DATASHEET AAT2601178 Total Power Solution for Portable Applications Pin Configuration SCL SDA STAT CT ISET TS ENBAT USE_USB CHGIN TQFN55-36 (Top View) 36 EN_TEST EN_HOLD EN_KEY ON_KEY EN2 EN3 EN4 EN5 OUT5 35 34 33 32 31 30 29 28 1 27 2 26 3 25 4 24 5 23 6 22 7 21 8 20 9 19 11 12 13 14 15 16 17 18 OUT4 AVIN2 OUT3 OUT2 AVIN1 OUT1 AGND CNOISE RESET 10 BAT BAT SYSOUT SYSOUT OUTBUCK PVIN PGND LX ADPP 4 www.analogictech.com 2601.2008.01.1.0 PRODUCT DATASHEET AAT2601178 Total Power Solution for Portable Applications Absolute Maximum Ratings1 TA = 25C unless otherwise noted. Symbol VIN Power and logic pins TJ TS TLEAD Description Input Voltage, CHGIN, BAT Maximum Rating Operating Junction Temperature Range Storage Temperature Range Maximum Soldering Temperature (at leads, 10 sec) Value Units -0.3 to 6.5 VIN + 0.3 -40 to 85 -65 to 150 300 V V C C C Value Units 25 4 C/W W Recommended Operating Conditions2 Symbol JA PD Description Thermal Resistance Maximum Power Dissipation 1. Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation at conditions other than the operating conditions specified is not implied. Only one Absolute Maximum rating should be applied at any one time. 2. Thermal Resistance was measured with the AAT2601 device on the 4-layer FR4 evaluation board in a thermal oven. The amount of power dissipation which will cause the thermal shutdown to activate will depend on the ambient temperature and the PC board layout ability to dissipate the heat. See Figures 11-14. 2601.2008.01.1.0 www.analogictech.com 5 PRODUCT DATASHEET AAT2601178 Total Power Solution for Portable Applications Electrical Characteristics1 VIN = 5V, VBAT = 3.6V, -40C TA +85C, unless noted otherwise. Typical values are TA = 25C. Symbol Description Conditions Power Supply CHGIN Input Voltage VIN Battery Standby Current IQ ISHDN Typ Max Units 6 V A 10.0 A 4.5 V 5 V V V A 4.5 Buck, LDO1 + LDO2, no load EN_TEST, EN_HOLD, EN2, EN3, EN4, EN5 = GND, EN_KEY floating CHGIN rising CHGIN falling BAT rising BAT falling VBAT = 4V, VCHGIN = 0V Battery Shutdown Current Under-Voltage Lockout for CHGIN UVLO Battery Under-Voltage Lockout Leakage Current from BAT Pin IBAT Startup Timers RESET Reset Timer Charger Voltage Regulation VBAT_REG Output Charge Voltage Regulation Preconditioning Voltage Threshold VMIN VRCH Min Initiated when OUT1 = 90% of final value 0C TA +70C (No trickle charge option available) I2C Recharge Code = 00 (default) I2C Recharge Code = 01 I2C Recharge Code = 10 I2C Recharge Code = 11 Battery Recharge Voltage Threshold 170 4.25 4.15 2.6 2.35 2 35 ms 4.158 2.6 4.200 2.8 4.00 4.05 4.10 4.15 4.242 3.0 720 800 880 V V V V V V Charger Current Regulation ICH_CC KI_SET ICH_PRE Constant-Current Mode Charge Current Charge Current Set Factor: ICH_CC/IISET Preconditioning Charge Current RISET = 1.24k (for 0.8A), USE_USB = Low, I2C ISET code = 000, VBAT = 3.6V, VCHGIN = 5.0V USE_USB = High, I2C ISET Code = 000, VBAT = 3.6V Constant Current Mode, VBAT = 3.6V Charge Termination Threshold Current Charging Devices Charging Transistor ON Resistance RDS(ON) Logic Control / Protection VEN_HOLD, Input High Threshold VEN_KEY, Input Low Threshold VEN_TEST VADPP IADPP VSTAT ISTAT VOVP Output Low Voltage Output Pin Current Sink Capability Output High Voltage Output Pin Current Source Capability Over-Voltage Protection Threshold 85 100 115 800 RISET = 1.24k, USE_USB = Low 12 IC I2C I2C I2C I2C 50 5 10 15 20 2 ICH_TERM mA ISET Code = 000, USE_USB = High Term Code = 00 (default) Term Code = 01 Term Code = 10 Term Code = 11 VIN = 5V 0.6 mA % ICH_CC mA % ICH_CC 0.9 1.4 V Pin Sinks 4mA 0.4 V 0.4 8 VOUT1 1.5 V mA V mA V 4.3 1. Specification over the -40C to +85C operating temperature range is assured by design, characterization and correlation with statistical process controls. 6 www.analogictech.com 2601.2008.01.1.0 PRODUCT DATASHEET AAT2601178 Total Power Solution for Portable Applications Electrical Characteristics1 VIN = 5V, VBAT = 3.6V, -40C TA +85C, unless noted otherwise. Typical values are TA = 25C. Symbol Description Conditions Logic Control / Protection (continued) Over Current Protection Threshold VOCP TC Constant Current Mode Time Out TK Trickle Charge Time Out Constant Voltage Mode Time Out TV ITS Current Source from TS Pin TS1 TS Hot Temperature Fault TS2 TS Cold Temperature Fault TLOOP_IN TLOOP_OUT TREG Load Switches / RDS(ON),BAT-SYSOUT RDS(ON),CHGIN-SYSOUT Sysout LDO Output Voltage Step-Down Buck VOUTBUCK ILIMOUTBUCK RDS(ON)L RDS(ON)H FOSC TS LDO1 (PowerDigital) VOUT1 Output Voltage Accuracy Output Current IOUT1 Output Current Limit ILIM1 Dropout Voltage VDO1 VOUT1(VOUT1VIN1) Line Regulation Load Regulation VOUT1 PSRR Power Supply Rejection Ratio TS Start Up Time 71 318 2.30 Typ 105 3 TC/8 3 75 331 25 2.39 25 115 85 100 Max 79 346 Units %VCS Hours Hours Hours A mV 2.48 V mV C C C VBAT = 3.6V 100 150 m VCHGIN = 4.5V 0.5 0.75 3.4 3.9 4.2 V 1.71 1.80 0.8 0.8 0.8 1.5 1.89 V A MHz 4.5 ISYSOUT < 900mA, VCHGIN = 4.5V ~ 6.0V Converter (Core) Output Voltage Accuracy P-Channel Current Limit High Side Switch On-Resistance Low Side Switch On-Resistance Oscillator Frequency Start-Up Time CCT = 100nF, VCHGIN = 5V Falling Threshold Hysteresis Rising Threshold Hysteresis Thermal Loop Entering Threshold Thermal Loop Exiting Threshold Thermal Loop Regulation SYSOUT LDO On-Resistance of BAT-SYSOUT Load Switch On-Resistance of CHGIN-SYSOUT Load Switch Sysout LDO Input Voltage Range Min IOUTBUCK = 0 ~ 300mA; VIN = 2.7V ~ 5.5V TA = 25C From Enable to Regulation; COUTBUCK = 4.7F, CNOISE = On IOUT1 = 0~300mA, VAVINx = 3.3V ~ 5.5V IOUT1 = 300mA IOUT1 = 100mA, 3.3V < VAVINx < 5.5V IOUT1 = 0.5mA ~ 150mA IOUT1 = 10mA, COUT1=22F, 100Hz ~ 10KHz From Enable to Regulation; C OUT1 = 22F, CNOISE = On V 100 s -3 300 +3 40 60 % mA mA mV %/V mV dB 175 s 1000 150 300 0.07 1. Specification over the -40C to +85C operating temperature range is assured by design, characterization and correlation with statistical process controls. 2601.2008.01.1.0 www.analogictech.com 7 PRODUCT DATASHEET AAT2601178 Total Power Solution for Portable Applications Electrical Characteristics1 VIN = 5V, VBAT = 3.6V, -40C TA +85C, unless noted otherwise. Typical values are TA = 25C. Symbol Description LDO2 (PowerAnalog) Output Voltage Accuracy VOUT2 Output Current IOUT2 Output Current Limit ILIM2 Dropout Voltage VDO2 VOUT2/ Line Regulation (VOUT2VIN2) VOUT2 Load Regulation PSRR Power Supply Rejection Ratio Ts Min IOUT2 = 0 ~ 150mA, VAVINx: 3.3V ~ 5.5V -3 150 Typ IOUT2 = 100mA, 3.3VCHGIN UVLO) is connected to the charger input CHGIN. 3) A hands free device or headset is connected, asserting EN_TEST high. The startup sequence for the AAT2601 core (Buck and LDO1) is typically initiated by pulling the EN_KEY pin low with a pushbutton switch, see Figure 1. The Buck (Core) is the first block to be turned on. When the output of the Buck reaches 90% of its final value, then LDO1 is enabled. When LDO1 (PowerDigital) reaches 90% of its final value, the 65ms RESET timer is initiated holding the microprocessor in reset. When the RESET pin goes High, the P can begin a power up sequence. After the startup sequence has commenced, LDO2 (PowerAnalog), 20 LDO3 (TCXO), LDO4 (TX) and LDO5 (RX) can be enabled and disabled as desired using their independent enable pins, even while the Buck and LDO1 are still starting up. However, if they are shut down, then LDO2, LDO3, LDO4, and LDO5 cannot be enabled. The P must pull the EN_HOLD signal high before the EN_KEY signal can be released by the push-button. This procedure requires that the push-button be held until the P assumes control of EN_HOLD, providing protection against inadvertent momentary assertions of the pushbutton. Once EN_HOLD is high the startup sequence is complete. If the P is unable to complete its power-up routine successfully before the user lets go of the push-button, the AAT2601 will automatically shut itself down. (EN_KEY and EN_HOLD are OR'd internally to enable the two core converters.) Alternatively, the startup sequence is automatically started without the pushbutton switch when the CHGIN pin rises above its UVLO threshold. The system cannot be disabled until the voltage at the CHGIN pin drops below the falling UVLO threshold. Thirdly, the EN_TEST pin can be used to startup the device for test purposes or for hands free operation such as when connecting a headset to the system. Typical Power Down Sequence If only the battery is connected and the voltage level is above the BAT UVLO , then the EN_KEY pin can be held low in order to power down AAT2601. The user can initiate a shutdown process by pressing the push-button a second time. Upon detecting a second assertion of EN_ KEY (by depressing the push-button), the AAT2601 asserts ON_KEY to interrupt the microprocessor which initiates an interrupt service routine that the user pressed the push-button. If EN_TEST and CHGIN are both low, the microprocessor then initiates a powerdown routine, the final step of which will be to de-assert EN_HOLD, disabling LDO2, LDO3, LDO4, and LDO5. When the voltage at the CHGIN pin is above the CHGIN UVLO, the device cannot be powered down. If the voltage at the CHGIN pin is below the CHGIN UVLO, both the EN_KEY and EN_HOLD pins must be held low in order to power down AAT2601. If LDO2, LDO3, LDO4, and LDO5 have not been disabled individually prior to global power down, then they will be turned off simultaneously with the Buck. The outputs of LDO4 and LDO5 are internally pulled to ground with 10k during shutdown to discharge the output capacitors and ensure a fast turn-off response time. www.analogictech.com 2601.2008.01.1.0 PRODUCT DATASHEET AAT2601178 Total Power Solution for Portable Applications CHGIN UVLO Debounce BAT EN_KEY Push-button On Switch Enable for SYSOUT and Regulators OUT1 ON_KEY Micro EN_HOLD Processor P EN_BAT Automatic Tester or Handsfree Operation Enable for Battery Charger EN_TEST Figure 1: Enable Function Detailed Schematic. Power Up Sequence Power Down Sequence 300ms debounce delay EN_KEY ON_KEY EN_HOLD must be held high before EN _KEY can be released . EN_HOLD OUTBuck (Core) OUT1 (PowerDigital) 90% Regulation 90% Regulation 65ms RESET Figure 2: Typical Power Up/Down Sequence. 2601.2008.01.1.0 www.analogictech.com 21 PRODUCT DATASHEET AAT2601178 Total Power Solution for Portable Applications Battery Charger Figure 3 illustrates the entire battery charging profile which consists of three phases. 1. 2. 3. Preconditioning Current Mode (Trickle) Charge Constant Current Mode Charge Constant Voltage Mode Charge Preconditioning Trickle Charge Battery charging commences only after the AAT2601 battery charger checks several conditions in order to maintain a safe charging environment. The system operation flow chart for the battery charger operation is shown in Figure 4. The input supply must be above the minimum operating voltage (UVLO) and the enable pin (ENBAT) must be low (it is internally pulled down). When the battery is connected to the BAT pin, the battery charger checks the condition of the battery and determines which charging mode to apply. internal series pass MOSFET when the input-output voltage differential is at its highest. Constant Current Mode Charge Current Trickle charge continues until the battery voltage reaches VMIN. At this point the battery charger begins constant-current charging. The current level default for this mode is programmed using a resistor from the ISET pin to ground. Once that resistor has been selected for the default charge current, then the current can be adjusted through I2C from a range of 40% to 180% of the programmed default charge current. Programmed current can be set at a minimum of 100mA and up to a maximum of 1A. When the ADPP signal goes high, the default I2C setting of 100% is reset. If the USE_USB signal is high when this happens, the charge current is reset to an internally set 100mA current until the microcontroller sends another I2C signal to change the charge current. (see I2C Programming section). Constant Voltage Mode Charge Preconditioning Current Mode Charge Current If the battery voltage is below the preconditioning voltage threshold VMIN, then the battery charger initiates precondition trickle charge mode and charges the battery at 12% of the programmed constant-current magnitude. For example, if the programmed current is 500mA, then the trickle charge current will be 60mA. Trickle charge is a safety precaution for a deeply discharged cell. It also reduces the power dissipation in the Constant current charging will continue until the battery voltage reaches the Output Charge Voltage Regulation point VBAT_REG. When the battery voltage reaches the regulation voltage (VBAT_REG), the battery charger will transition to constant-voltage mode. VBAT_REG is factory programmed to 4.2V (nominal). Charging in constant-voltage mode will continue until the charge current has reduced to the end of charge termination current programmed using the I2C interface (5%, 10%, 15%, or 20%). I (mA) V (V) Preconditioning Trickle Charge Phase Constant Current Charge Phase Constant Voltage Charge Phase FAST-CHARGE to TOP-OFF Charge Threshold Constant-Current Mode Charge Current (ICH_CC) Battery End of Charge Voltage Regulation (VBAT_REG) Charge Voltage Preconditioning Threshold Voltage (VMiN) Charge Current Preconditioning Charge Current (ICH_PRE) Charge Termination Threshold Current (ICH_TERM) T (s) Trickle Charge Timeout (TK) Constant Current Timeout (TC) Constant Voltage Timeout (TV) Figure 3: Current vs. Voltage and Charger Time Profile. 22 www.analogictech.com 2601.2008.01.1.0 PRODUCT DATASHEET AAT2601178 Total Power Solution for Portable Applications Enable No Power On Reset Yes Power Input Voltage VCHGIN > VUVLO Enable Expired Yes Shut Down Yes Charge Timer Control Fault Conditions Monitoring OV, OT, VTS1 < VTS < V TS2 No Preconditioning Test VBAT < VMIN Yes Preconditioning (Trickle Charge) Thermal Loop Thermal Loop Current Current ReductionininADP Reduction C.C. ModeMode Charging Yes No No No Recharge Test VBAT < VRCH Yes Current Phase Test VBAT < VBAT_REG Yes Constant Current Charge Mode Yes Constant Voltage Charge Mode Device Thermal Loop Monitor TJ > 115C No Voltage Phase Test ICH > ICH_TERM No Charge Completed Figure 4: System Operation Flow Chart for the Battery Charger. 2601.2008.01.1.0 www.analogictech.com 23 PRODUCT DATASHEET AAT2601178 Total Power Solution for Portable Applications Power Saving Mode After the charge cycle is complete, the battery charger turns off the series pass device and automatically goes into a power saving sleep mode. During this time, the series pass device will block current in both directions to prevent the battery from discharging through the battery charger. The battery charger will remain in sleep mode even if the charger source is disconnected. It will come out of sleep mode if either the battery terminal voltage drops below the VRCH threshold, the charger EN pin is recycled, or the charging source is reconnected. In all cases, the battery charger will monitor all parameters and resume charging in the most appropriate mode. Temperature Sense (TS) The TS pin is available to monitor the battery temperature. Connect a 10k NTC resistor from the TS pin to ground. The TS pin outputs a 75A constant current into the resistor and monitors the voltage to ensure that the battery temperature does not fall outside the limits depending on the temperature coefficient of the resistor used. When the voltage goes above 2.39V or goes below 0.331V, the charging current will be suspended. in the internal timing control circuit. The constant current provided to charge the timing capacitor is very small, and this pin is susceptible to noise and changes in capacitance value. Therefore, the timing capacitor should be physically located on the printed circuit board layout as close as possible to the CT pin. Since the accuracy of the internal timer is dominated by the capacitance value, a 10% tolerance or better ceramic capacitor is recommended. Ceramic capacitor materials, such as X7R and X5R types, are a good choice for this application. Programming Charge Current (ISET) The default constant current mode charge level is user programmed with a set resistor placed between the ISET pin and ground. The accuracy of the constant charge current, as well as the preconditioning trickle charge current, is dominated by the tolerance of the set resistor. For this reason, a 1% tolerance metal film resistor is recommended for the set resistor function. The constant charge current levels from 100mA to 1A may be set by selecting the appropriate resistor value from Table 1 and Figure 5. The ISET pin current to charging current ratio is 1 to 800. It is regulated to 1.25V during constant current mode unless changed using I2C commands. It can be used as a charging current monitor, based on the equation: Charge Safety Timer (CT) While monitoring the charge cycle, the AAT2601 utilizes a charge safety timer to help identify damaged cells and to ensure that the cell is charged safely. Operation is as follows: upon initiating a charging cycle, the AAT2601 charges the cell at 12% of the programmed maximum charge until VBAT >2.8V. If the cell voltage fails to reach the preconditioning threshold of 2.8V (typ) before the safety timer expires, the cell is assumed to be damaged and the charge cycle terminates. If the cell voltage exceeds 2.8V prior to the expiration of the timer, the charge cycle proceeds into fast charge. There are three timeout periods: 1 hour for Trickle Charge mode, 3 hours for Constant Current mode, and 3 hours for Constant Voltage mode. The CT pin is driven by a constant current source and will provide a linear response to increases in the timing capacitor value. Thus, if the timing capacitor were to be doubled from the nominal 0.1F value, the time-out periods would be doubled. If the programmable watchdog timer function is not needed, it can be disabled by terminating the CT pin to ground. The CT pin should not be left floating or unterminated, as this will cause errors 24 ICH = 800 VISET RISET During preconditioning charge, the ISET pin is regulated to 12% of the fast charge current ISET voltage level (Figure 5), but the equation stays the same. During constant voltage charge mode, the ISET pin voltage will slew down and be directly proportional to the battery current at all times. Constant Charging Current ICH_CC (mA) Set Resistor Value (k) 100 200 300 400 500 600 700 800 900 1000 10 4.99 3.32 2.49 2 1.65 1.43 1.24 1.1 1 Table 1: Constant Current Charge vs. ISET Resistor Value. www.analogictech.com 2601.2008.01.1.0 PRODUCT DATASHEET AAT2601178 Total Power Solution for Portable Applications Constant Current Mode Charge Current vs. ISET Resistor ISET Voltage vs. Battery Voltage (CHGIN = 5.0V, RISET = 1.24k ) (VIN = 5V; VBAT = 3.6V) 1.4 1400 1.2 1 1000 VISET (V) ICH_CC (mA) 1200 800 600 0.8 0.6 400 0.4 200 0.2 0 0.1 1 10 0 2.5 100 ) ISET Resistor (k 2.9 3.3 3.7 4.1 4.5 Battery Voltage (V) Figure 5: Constant Current Mode Charge ICH_CC Setting vs. ISET Resistor and ISET Voltage vs. Battery Voltage. Reverse Battery Leakage CHGIN Bypass Capacitor Selection The AAT2601 includes internal circuitry that eliminates the need for series blocking diodes, reducing solution size and cost as well as dropout voltage relative to conventional battery chargers. When the input supply is removed or when CHGIN goes below the AAT2601's under voltage-lockout (UVLO) voltage, or when CHGIN drops below VBAT, the AAT2601 automatically reconfigures its power switches to minimize current drain from the battery. CHGIN is the power input for the AAT2601 battery charger. The battery charger is automatically enabled whenever a valid voltage is present on CHGIN. In most applications, CHGIN is connected to either a wall adapter or USB port. Under normal operation, the input of the charger will often be "hot-plugged" directly to a powered USB or wall adapter cable, and supply voltage ringing and overshoot may appear at the CHGIN pin. A high quality capacitor connected from CHGIN to G, placed as close as possible to the IC, is sufficient to absorb the energy. Wall-adapter powered applications provide flexibility in input capacitor selection, but the USB specification presents limitations to input capacitance selection. In order to meet both the USB 2.0 and USB OTG (On The Go) specifications while avoiding USB supply under-voltage conditions resulting from the current limit slew rate (100mA/s) limitations of the USB bus, the CHGIN bypass capacitance value must be between 1F and 4.7F. Ceramic capacitors are often preferred for bypassing due to their small size and good surge current ratings, but care must be taken in applications that can encounter hot plug conditions as their very low ESR, in combination with the inductance of the cable, can create a high-Q filter that induces excessive ringing at the CHGIN pin. This ringing can couple to the output and be mistaken as loop instability, or the ringing may be large enough to damage the input itself. Although the CHGIN pin is designed for maximum robustness and an absolute Adapter Power Indicator (ADPP) This is an open drain output which will pull low when VCHGIN > 4.5V. When this happens, depending on the status of the USE_USB pin, the charge current will be reset to the default ISET values or I2C programmed values. Charge Status Output (STAT) The AAT2601 provides battery charging status via a status pin. This pin is a buffered output with a supply level up to the LDO1 output (PowerDigital). The status pin can indicate the following conditions: Event Description STAT No battery charging activity Battery charging Charging completed Low (to GND) High (to VOUT1) Low (to GND) Table 2: Charge Status Output (STAT). 2601.2008.01.1.0 www.analogictech.com 25 PRODUCT DATASHEET AAT2601178 Total Power Solution for Portable Applications maximum voltage rating of +6.5V for transients, attention must be given to bypass techniques to ensure safe operation. As a result, design of the CHGIN bypass must take care to "de-Q" the filter. This can be accomplished by connecting a 1 resistor in series with a ceramic capacitor (as shown in Figure 6A), or by bypassing with a tantalum or electrolytic capacitor to utilize its higher ESR to dampen the ringing (as shown in Figure 6A). For additional protection, Zener diodes with 6V clamp voltages may also be used. In any case, it is always critical to evaluate voltage transients at the CHGIN pin with an oscilloscope to ensure safe operation. Thermal Considerations The actual maximum charging current is a function of charge adapter input voltage, the state of charge of the battery at the moment of charge, the system supply current from SYSOUT, and the ambient temperature and the thermal impedance of the package and printed circuit board. The maximum programmable current may not be achievable under all operating parameters. One issue to consider is the amount of current being sourced to the SYSOUT pin from the CHGIN LDO while the battery is being charged. The AAT2601 is offered in a TQFN55-36 package which can provide up to 4W of power dissipation when it is properly bonded to a printed circuit board and has a maximum thermal resistance of 25C/W. Many considerations should be taken into account when designing the printed circuit board layout, as well as the placement of the charger IC package in proximity to other heat generating devices in a given application design. The ambient temperature around the charger IC will also have an effect on the thermal limits of a battery charging application. The maximum limits that can be expected for a given ambient condition can be estimated by the following discussion. First, the maximum power dissipation for a given situation should be calculated: PD(MAX) = (TJ(MAX) - TA) JA Where: PD(MAX) = Maximum Power Dissipation (W) JA = Package Thermal Resistance (C/W) TJ(MAX) = Maximum Device Junction Temperature (C) [150C] TA = Ambient Temperature (C) CHGIN To USB Port or Wall Adapter To USB Port or Wall Adapter 1 CHGIN 4.7F ESR > 1 1F Ceramic (XR5/XR7) (A) (B) Figure 6: Hot Plug Requirements. 26 www.analogictech.com 2601.2008.01.1.0 PRODUCT DATASHEET AAT2601178 Total Power Solution for Portable Applications Next, the power dissipation for the charger can be calculated by the following equation: PD = (VCHGIN - VBAT) * ICH_CC + (VCHGIN * IOP) + (VCHGIN - VSYSOUT) * ISYSOUT + (VSYSOUT - VOUT1) * IOUT1 + (VSYSOUT - VOUT2) * IOUT2 + (VSYSOUT - VOUT3) * IOUT3 + (VSYSOUT - VOUT4) * IOUT4 + (VSYSOUT - VOUT5) * IOUT5 VOUTBUCK RDS(ON)H * [VSYSOUT - VOUTBUCK] + IOUTBUCK2 * RDS(ON)L * V + VSYSOUT SYSOUT Where: PD = Total Power Dissipation by the Device VCHGIN = CHGIN Input Voltage VBAT = Battery Voltage at the BAT Pin ICH_CC = Constant Charge Current Programmed for the Application IOP = Quiescent Current Consumed by the IC for Normal Operation [0.5mA] VSYSOUT and ISYSOUT = Output voltage and load current from the SYSOUT pin for the system LDOs and stepdown converter [3.9V out for SYSOUT] RDS(ON)H and RDS(ON)L = On-resistance of step-down high and low side MOSFETs [0.8 each] VOUTX and IOUTX = Output voltage and load currents for the LDOs and step-down converter [3V out for each LDO] By substitution, we can derive the maximum charge current before reaching the thermal limit condition (TREG = 100C, Thermal Loop Regulation). The maximum charge current is the key factor when designing battery charger applications. ICH_CC(MAX) = (TREG - TA) - (VCHGIN * IOP) - (VCHGIN - VSYSOUT) * ISYSOUT) JA - [(VSYSOUT - VOUT1) * IOUT1] - (VSYSOUT - VOUT2) * IOUT2 - [(VSYSOUT - VOUT3) * IOUT3] - (VSYSOUT - VOUT4) * IOUT4 - (VSYSOUT - VOUT5) * IOUT5 VOUTBUCK RDS(ON)H * (VSYSOUT - VOUTBUCK) - IOUTBUCK2 * RDS(ON)L * V + VSYSOUT SYSOUT VCHGIN - VBAT 2601.2008.01.1.0 In general, the worst condition is when there is the greatest voltage drop across the charger, when battery voltage is charged up to just past the preconditioning voltage threshold and the LDOs and step-down converter are sourcing full output current. For example, if 913mA is being sourced from the 3.9V SYSOUT pin to the LDOs and Buck channels (300mA to LDO1, 100mA to LDO2-5, and 213mA to the Buck; see buck efficiency graph for 300mA output current) with a CHGIN supply of 5V, and the battery is being charged at 3.0V with 800mA charge current, then the power dissipated will be 3.32W. A reduction in the charge current (through I2C) may be necessary in addition to the reduction provided by the internal thermal loop of the charger itself. For the above example at TA = 30C, the ICH_CC(MAX) = 546mA. Thermal Overload Protection The AAT2601 integrates thermal overload protection circuitry to prevent damage resulting from excessive thermal stress that may be encountered under fault conditions, for example. This circuitry disables all regulators if the AAT2601 die temperature exceeds 140C, and prevents the regulators from being enable until the die temperature drops by 15C (typ). Synchronous Step-Down Converter (Buck) The AAT2601 contains a high performance 300mA, 1.5MHz synchronous step-down converter. The stepdown converter operates to ensure high efficiency performance over all load conditions. It requires only three external power components (CIN, COUT, and L). A high DC gain error amplifier with internal compensation controls the output. It provides excellent transient response and load/line regulation. Transient response time is typically less than 20s. The converter has soft start control to limit inrush current and transitions to 100% duty cycle at drop out. The step-down converter input pin PVIN should be connected to the SYSOUT LDO output pin. The output voltage is internally fixed at 1.8V. Power devices are sized for 300mA current capability while maintaining over 90% efficiency at full load. www.analogictech.com 27 PRODUCT DATASHEET AAT2601178 Total Power Solution for Portable Applications Input/Output Capacitor and Inductor Apart from the input capacitor that is shared with the LDO inputs, only a small L-C filter is required at the output side for the step-down converter to operate properly. Typically, a 3.3H inductor such as the Sumida CDRH2D11NP3R3NC and a 4.7F ceramic output capacitor are recommended for low output voltage ripple and small component size. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. A 10F ceramic input capacitor is sufficient for most applications. Control Loop The converter is a peak current mode step-down converter. The inner, wide bandwidth loop controls the inductor peak current. The inductor current is sensed through the P-channel MOSFET (high side) which is also used for short circuit and overload protection. A fixed slope compensation signal is added to the sensed current to maintain stability for duty cycles greater than 50%. The peak current mode loop appears as a voltage programmed current source in parallel with the output capacitor. The output of the voltage error amplifier programs the current mode loop for the necessary peak inductor current to force a constant output voltage for all load and line conditions. The voltage feedback resistive divider is internal and the error amplifier reference voltage is 0.45V. The voltage loop has a high DC gain making for excellent DC load and line regulation. The internal voltage loop compensation is located at the output of the transconductance voltage error amplifier. Soft Start Soft start slowly increases the internal reference voltage when the input voltage or enable input is initially applied. It limits the current surge seen at the input and eliminates output voltage overshoot. Current Limit and Over-Temperature Protection For overload conditions the peak input current is limited. As load impedance decreases and the output voltage falls closer to zero, more power is dissipated internally, 28 raising the device temperature. Thermal protection completely disables switching when internal dissipation becomes excessive, protecting the device from damage. The junction over-temperature threshold is 140C with 15C of hysteresis. Linear LDO Regulators (OUT1-5) The advanced circuit design of the linear regulators has been specifically optimized for very fast start-up and shutdown timing. These proprietary LDOs are tailored for superior transient response characteristics. These traits are particularly important for applications which require fast power supply timing. There are two LDO input pins, AVIN1/2, which should be connected to the SYSOUT LDO output pin. All LDO outputs are initially fixed at 3.0V. The user can program the output voltages for the LDOs to 2.8V, 2.85V, or 2.9V using I2C. The high-speed turn-on capability is enabled through the implementation of a fast start control circuit, which accelerates the power up behavior of fundamental control and feedback circuits within the LDO regulator. For LDO4 and LDO5, fast turn-off time response is achieved by an active output pull down circuit, which is enabled when the LDO regulator is placed in the shutdown mode. This active fast shutdown circuit has no adverse effect on normal device operation. Input/Output Capacitors The LDO regulator output has been specifically optimized to function with low cost, low ESR ceramic capacitors. However, the design will allow for operation over a wide range of capacitor types. The input capacitor is shared with all LDO inputs and the step-down converter. A 10F is sufficient. A 4.7F ceramic output capacitor is recommended for LDO2-5 and a 22F output capacitor for LDO1. Current Limit and Over-Temperature Protection The regulator comes with complete short circuit and thermal protection. The combination of these two internal protection circuits gives a comprehensive safety system to guard against extreme adverse operating conditions. www.analogictech.com 2601.2008.01.1.0 PRODUCT DATASHEET AAT2601178 Total Power Solution for Portable Applications I2C Serial Interface and Programmability The timing diagram in Figure 7 depicts the transmission protocol. START and STOP Conditions Serial Interface Many of the features of the AAT2601 can be controlled via the I2C serial interface. The I2C serial interface is a widely used interface where it requires a master to initiate all the communications with the slave devices. The I2C protocol consists of 2 active wire SDA (serial data line) and SCL (serial clock line). Both wires are open drain and require an external pull up resistor to VCC (SYSOUT may be used as VCC). The SDA pin serves I/O function, and the SCL pin controls and references the I2C bus. I2C protocol is a bidirectional bus which allows both read and write actions to take place, but the AAT2601 supports the write protocol only. Since the protocol has a dedicated bit for Read or Write access (R/W), when communicating with AAT2601, this bit must be set to "0". ACK from slave START MSB Chip Address 1 0 LSB W ACK MSB START and STOP conditions are always generated by the master. Prior to initiating a START condition, both the SDA and SCL pin are idle mode (idle mode is when there is no activity on the bus and SDA and SCL are pulled to VCC via external resistor). As depicted in Figure 7, a START condition is defined to be when the master pulls the SDA line low and after a short period pulls the SCL line low. A START condition acts as a signal to all IC's that something is about to be transmitted on the BUS. A STOP condition, also shown in Figure 7, is when the master releases the bus and SCL changes from low to high followed by SDA low to high transition. The master does not issue an ACKNOWLEGE and releases the SCL and SDA pins. ACK from slave Register Address LSB ACK MSB ACK from slave Data LSB ACK STOP SCL SDA 0 1 1 0 0 0 including R/W bit, Chip Address = 0x98 Figure 7: I2C Timing Diagram. 2601.2008.01.1.0 www.analogictech.com 29 PRODUCT DATASHEET AAT2601178 Total Power Solution for Portable Applications Transferring Data Every byte on the bus must be 8 bits long. A byte is always sent with a most significant bit first (see Figure 8). Acknowledge Bit The acknowledge bit is the ninth bit of data. It is used to send back a confirmation to the master that the data has been received properly. For acknowledge to take place, the MASTER must first release the SDA line, then the SLAVE will pull the data line low as shown in Figure 7. R/W LSB MSB address including the R/W bit is 0x98 (hex) or 10011000 in binary. Figure 8: Bit Order. The address is embedded in the first seven bits of the byte. The eighth bit is reserved for the direction of the information flow for the next byte of information. For the AAT2601, this bit must be set to "0". The full 8-bit Serial Programming Code After sending the chip address, the master should send an 8-bit data stream to select which register to program and then the codes that the user wishes to enter. Register 0x00: Timer RCHG1 RCHG0 CHG2 CHG1 CHG0 Term1 Term0 Not used Not used Not used Not used SYS LDO11 LDO10 LDO50 LDO41 LDO40 LDO31 LDO30 LDO21 LDO20 Register 0x01: Not used Register 0x02: LDO51 Figure 9: Serial Programming Register Codes. USE_USB Pin CHG2 CHG1 CHG0 1 0 0 0 0 0 0 0 X X X X X X X 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 Constant Current Charge ICH_CC 100mA (fixed internally) 800mA (set by ISET resistor) 640mA 480mA 320mA 960mA 1120mA 1280mA 1440mA Constant Current Charge as % of ISET Current (default) 100% (default) 80% 60% 40% 120% 140% 160% 180% Table 3: CHG Bit Setting for the Constant Current Charge Level (assuming ISET resistor is set to default 800mA charge current). 30 www.analogictech.com 2601.2008.01.1.0 PRODUCT DATASHEET AAT2601178 Total Power Solution for Portable Applications Notes concerning the operation of the CHG2, CHG1 and CHG0 bits or ISET code: * Once the part is turned on using the EN_KEY pin (and there is a BAT and/or CHGIN supply), and data is sent through I2C, the I2C codes in the registers will always be preserved until the part is shut down using the EN_HOLD (going low) or if the BAT and CHGIN supply are removed. * If the part is turned on by connecting supply CHGIN (and not through EN_KEY), then when the CHGIN is removed, the part will shut down and all I2C registers will be cleared. If USE_USB = L: * The charge current is set by the ISET code in Register 0x00, bits 2,3,4. (code 000 will equal 100%) * If the part has been turned on by EN_KEY and CHGIN is disconnected then reconnected, it will still contain the code it had before (if it was 60% then it will remain 60%). * If the part has NOT been turned on by EN_KEY and CHGIN is disconnected then reconnected, it will be reset to 100% (since the whole part was shutdown). If USE_USB = H: * ISET Code 000 in Register 0x00, bits 2,3,4 = 100mA. The other codes stay the same as if USE_USB=H. * If the part has been turned on by EN_KEY and CHGIN is disconnected then reconnected, the ISET code will be forced to 000 and the current will be set to 100mA. * The next time any I2C register is programmed (even if it is not for the ISET code), the ISET code will revert back to what it was before. For example, if the ISET code is set to 010 and USE_USB=H and the part was turned on with EN_KEY, then when CHGIN is disconnected then reconnected, the charger will be set to 100mA. Then if any other command is sent, the ISET code will remain 010. Term1 Term0 Termination Current (as % of Constant Current Charge) 0 0 1 1 0 1 0 1 5% (default) 10% 15% 20% Table 4: Term Bit Setting for the Termination Current Level. RCHG1 RCHG0 Recharge Threshold 0 0 1 1 0 1 0 1 4.00V (default) 4.05V 4.10V 4.15V Table 5: RCHG Bit Setting for the Battery Charger Recharge Voltage Level. 2601.2008.01.1.0 www.analogictech.com 31 PRODUCT DATASHEET AAT2601178 Total Power Solution for Portable Applications Timer Charger Watchdog Timer 0 1 ON (default) OFF (and reset to zero) Table 6: Timer Bit Setting for the Charger Watchdog Timer. LDO11 LDO10 LDO1 Output Voltage 0 0 1 1 0 1 0 1 3.00V (default) 2.90V 2.85V 2.80V LDO21 LDO20 LDO2 Output Voltage 0 0 1 1 0 1 0 1 3.00V (default) 2.90V 2.85V 2.80V LDO31 LDO30 LDO3 Output Voltage 0 0 1 1 0 1 0 1 3.00V (default) 2.90V 2.85V 2.80V LDO41 LDO40 LDO4 Output Voltage 0 0 1 1 0 1 0 1 3.00V (default) 2.90V 2.85V 2.80V LDO51 LDO50 LDO5 Output Voltage 0 0 1 1 0 1 0 1 3.00V (default) 2.90V 2.85V 2.80V Table 7: LDO Bit Setting for LDO Output Voltage Level. SYS Bit 0 1 SYSOUT Power Source Layout Guidance Figure 10 is the schematic for the evaluation board. The evaluation board has extra components for easy evaluation; the actual BOM need for a system is shown in Table 9. When laying out the PC board, the following layout guideline should be followed to ensure proper operation of the AAT2601: 1. 2. 3. 4. 5. 6. 7. The exposed pad EP must be reliably soldered to PGND/AGND and multilayer GND. The exposed thermal pad should be connected to board ground plane and pins 2 and 16. The ground plane should include a large exposed copper pad under the package with VIAs to all board layers for thermal dissipation. The power traces, including GND traces, the LX traces and the VIN trace should be kept short, direct and wide to allow large current flow. The L1 connection to the LX pins should be as short as possible. Use several via pads when routing between layers. The input capacitors (C1 and C2) should be connected as close as possible to CHGIN (Pin 28) and PGND (Pin 2) to get good power filtering. Keep the switching node LX away from the sensitive OUTBUCK feedback node. The feedback trace for the OUTBUCK pin should be separate from any power trace and connected as closely as possible to the load point. Sensing along a high current load trace will degrade DC load regulation. The output capacitor C4 and L1 should be connected as close as possible and there should not be any signal lines under the inductor. The resistance of the trace from the load return to the PGND (Pin 2) should be kept to a minimum. This will help to minimize any error in DC regulation due to differences in the potential of the internal signal ground and the power ground. If USE_USB = H, SYSOUT powered from BAT If USE_USB = L, SYSOUT powered from CHGIN SYSOUT always powered from BAT Table 8: SYS Bit Setting for SYSOUT Power Path. 32 www.analogictech.com 2601.2008.01.1.0 PRODUCT DATASHEET AAT2601178 Total Power Solution for Portable Applications Quantity Value Designator Footprint Description 5 2 4 3 1 1 9 8 1 10F 22F 4.7F 0.1F 0.01F 3.3H 100K 10K 1.24K C1, C2, C3, C14, C15 C9 C4, C5, C6, C7, C8 C10, C11, C12 C13 L1 R5, R8, R20, R21, R22, R23, R25, R26, R27 R17, R19, R24, R29, R31, R32, R33, R37 R18 0603 0805 0603 0402 0402 CDRH2D 0402 0402 0402 Capacitor, Ceramic, X5R, 6.3V, 20% Capacitor, Ceramic, 20%, 6.3V, X5R Capacitor, Ceramic, 20%, 6.3V, X5R Capacitor, Ceramic, 16V, 10%, X5R Capacitor, Ceramic, 16V, 10%, X7R Inductor, Sumida CDRH2D11NP-3R3NC Resistor, 5% Resistor, 5% Resistor, 1% Table 9: Minimum AAT2601 Bill of Materials. 2601.2008.01.1.0 www.analogictech.com 33 PRODUCT DATASHEET AAT2601178 Total Power Solution for Portable Applications D1 R30 1K J1 STA T R32 BA T_I D 10K R1 0 USE_USB V DIG PON_N TP11 Sysout 1 3 5 7 9 11 13 15 17 19 21 23 25 LED GREEN 1 2 4 6 8 10 12 14 16 18 20 22 24 26 3 EXT PWR VANA A COK_N VTCXO J12 I NT/EXT PWR 2 J10 R31 1 2 3 4 10K RESET_N R33 TX _EN PW R_HOLD 10K SDA SCL GND TP1 DA TA HEA DER VCORE V BATT VB ATT Header 13X2H J11 TP2 CHGIN CHG_EN J3 V BATT U1 3 2 CHGIN 28 1 C1 10F V B US/V CHG R2 0 30 R3 0 29 R4 0 35 36 R6 0 VBATT R7 3 2 1 DNP VD IG R5 100K R8 J2 VTX SDA SCL TCXO_EN VRX A NA_EN 100K V BUS VBA TT V CHG 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 R9 0 R10 0 R12 0 R14 0 5 6 7 8 CHGIN BAT BAT 32 B AT_I D SYSOUT SYSOUT A VIN1 A VIN2 PVI N USE_USB SDA SCL EN_KEY EN_HOLD EN_TEST A AT2601 OUT1 OUT2 OUT3 OUT4 OUT5 LX OUTBUCK 31 CT ISET ADPP ON-KEY RESET STAT TS CNOISE R28 PW R_ON RX_EN HF_PW R 4.75K C10 0.1F Header 13X2H Q1 CMPT3904 C11 0.1F TP10 Sysout 25 24 14 11 22 C12 0.1F R18 1.24K AGND PGND EP 15 13 12 10 9 20 23 V DIG R19 10K VD IG R20 100K VDI G R21 100K J13 SW 1 PW R_ON RX _EN PW R_ON 1 2 3 J14 TX _EN RX _EN BAT V DIG R24 10K R25 100K J17 1 HF_PW R 2 3 VANA J8 OUT2 VD IG J9 OUT1 buckout L1 3.3H LX 17 R11 0 ACOK _N R13 0 PON_N R15 0 RESET_N R16 0 C4 4.7F C5 4.7F C6 4.7F C7 4.7F C8 4.7F C9 22F STAT R29 10K 16 21 37 A COK_N TP3 R37 10K RESET_N TP5 V DIG VCORE STA T_N TP6 R23 100K J16 A NA_EN TCX O_EN R27 100K J19 1 USE_USB 2 3 PWR_HOLD V TCX O J7 OUT3 1 2 3 ANA _EN CHGIN R26 100K J18 1 PWR_HOLD 2 3 HF_PW R TX_EN VTX J6 OUT4 10F OUT1 OUT2 OUT3 OUT4 OUT5 C13 0.01F J15 1 TCX O_EN 2 3 CHGIN VRX V DIG R22 100K 1 2 3 J5 OUT5 C2 10F 10F (TBD) 19 4 18 34 R17 10K J4 BUCK C15 PON_N TP4 BAT C3 10F Sysout R34 0 R35 0 R36 0 TP9 33 VCORE BA T C14 ENBAT EN2 EN3 EN4 EN5 27 26 TP7 GND TP8 GND TP12 GND J20 1 CHG_EN 2 3 USE_USB CHG_EN Figure 10: AAT2601 Evaluation Kit Schematic. 34 www.analogictech.com 2601.2008.01.1.0 PRODUCT DATASHEET AAT2601178 Total Power Solution for Portable Applications Figure 11: AAT2601 Evaluation Kit Top Layer. Figure 12: AAT2601 Evaluation Kit Mid1 Layer. 2601.2008.01.1.0 www.analogictech.com 35 PRODUCT DATASHEET AAT2601178 Total Power Solution for Portable Applications Figure 13: AAT2601 Evaluation Kit Mid2 Layer. Figure 14: AAT2601 Evaluation Kit Bottom Layer. 36 www.analogictech.com 2601.2008.01.1.0 PRODUCT DATASHEET AAT2601178 Total Power Solution for Portable Applications Ordering Information Package Part Marking1 Part Number (Tape and Reel)2 TQFN55-36 XPXYY AAT2601IIH-T1 All AnalogicTech products are offered in Pb-free packaging. The term "Pb-free" means semiconductor products that are in compliance with current RoHS standards, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. For more information, please visit our website at http://www.analogictech.com/about/quality.aspx. Packaging Information TQFN55-36 R = 0.1 3.600 0.050 5.000 0.050 Index Area (D/2 x E/2) C = 0.3 5.000 0.050 Detail "A" 3.600 0.050 Bottom View Top View 0.750 0.050 0.450 0.050 0.200 0.050 0.203 REF + 0.050 0.000 - 0.000 Side View 0.40 BSC Detail "A" All dimensions in millimeters. 1. XYY = assembly and date code. 2. Sample stock is generally held on part numbers listed in BOLD. 3. The leadless package family, which includes QFN, TQFN, DFN, TDFN and STDFN, has exposed copper (unplated) at the end of the lead terminals due to the manufacturing process. A solder fillet at the exposed copper edge cannot be guaranteed and is not required to ensure a proper bottom solder connection. 2601.2008.01.1.0 www.analogictech.com 37 PRODUCT DATASHEET AAT2601178 Total Power Solution for Portable Applications Advanced Analogic Technologies, Inc. 3230 Scott Boulevard, Santa Clara, CA 95054 Phone (408) 737-4600 Fax (408) 737-4611 (c) Advanced Analogic Technologies, Inc. AnalogicTech cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in an AnalogicTech product. No circuit patent licenses, copyrights, mask work rights, or other intellectual property rights are implied. AnalogicTech reserves the right to make changes to their products or specifications or to discontinue any product or service without notice. Except as provided in AnalogicTech's terms and conditions of sale, AnalogicTech assumes no liability whatsoever, and AnalogicTech disclaims any express or implied warranty relating to the sale and/or use of AnalogicTech products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. Testing and other quality control techniques are utilized to the extent AnalogicTech deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed. AnalogicTech and the AnalogicTech logo are trademarks of Advanced Analogic Technologies Incorporated. All other brand and product names appearing in this document are registered trademarks or trademarks of their respective holders. 38 www.analogictech.com 2601.2008.01.1.0