Philips Semiconductors Product specification
74ABT74Dual D-type flip-flop
1853-1813 157931995 Sep 22
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS
Tamb = 25°C;
GND = 0V TYPICAL UNIT
tPLH
tPHL
Propagation
delay
CPn to
Qn, QnCL = 50pF;
VCC = 5V
3.0
2.5 ns
tOSLH
tOSHL Output to
Output skew
CC
0.5 ns
CIN Input
capacitance VI = 0V or VCC 3pF
ICC Total supply
current Outputs disabled;
VCC = 5.5V 50 µA
PIN CONFIGURATION
14
13
12
11
10
9
87
6
5
4
3
2
1
GND
VCC
SD1
Q1
Q1
CP1
RD1
D1
RD1
D0
Q0
CP0
SD1
Q0
SF00045
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
1, 2, 3, 4, 10,
11, 12, 13 RDn, Dn,
CPn, SDn Data inputs
5, 6, 8, 9 Qn, Qn Data outputs
7 GND Ground (0V)
14 VCC Positive supply voltage
LOGIC SYMBOL
Q0 Q0Q1Q1
56 98
V
CC = Pin 14
GND = Pin 7
3
4
1
11
10
13
CP0
SD0
RD0
CP1
SD1
RD1
D0 D1
212
SA00359
DESCRIPTION
The 74ABT74 is a dual positive edge-triggered D-type flip-flop
featuring individual data, clock, set, and reset inputs; also true and
complementary outputs. Set (SD) and reset (RD) are asynchronous
active low inputs and operate independently of the clock input.
When set and reset are inactive (high), data at the D input is
transferred to the Q and Q outputs on the low-to-high transition of
the clock. Data must be stable just one setup time prior to the
low-to-high transition of the clock for predictable operation. Clock
triggering occurs at a voltage level and is not directly related to the
transition time of the positive-going pulse. Following the hold time
interval, data at the D input may be changed without affecting the
levels of the output.
LOGIC SYMBOL (IEEE/IEC)
4
3
2
1
10
11
12
13
5
6
9
8
&
S
S
C1
C2
R
1D
2D
R
SF00047
LOGIC DIAGRAM
VCC = Pin 14
GND = Pin 7
5, 9
6, 8
Q
Q
4, 10
1, 13
3, 11
2, 12
SD
RD
CP
D
SF00048
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
14-Pin Plastic DIP –40°C to +85°C74ABT74 N 74ABT74 N SOT27-1
14-Pin plastic SO –40°C to +85°C74ABT74 D 74ABT74 D SOT108-1
14-Pin Plastic SSOP Type II –40°C to +85°C74ABT74 DB 74ABT74 DB SOT337-1
14-Pin Plastic TSSOP Type I –40°C to +85°C74ABT74 PW 74ABT74PW DH SOT402-1
Philips Semiconductors Product specification
74ABT74Dual D-type flip-flop
1995 Sep 22 2
FUNCTION TABLE
INPUTS OUTPUTS OPERATING
SD RD CP D Q Q
OPERATING
MODE
L H X X H L Asynchronous set
H L X X L H Asynchronous
reset
L L X X H H Undetermined*
H H ↑h H L Load “1”
H H ↑l L H Load “0”
H H ↑X NC NC Hold
NOTES:
H = High voltage level
h = High voltage level one setup time prior to low-to-high
clock transition
L = Low voltage level
l = Low voltage level one setup time prior to low-to-high
clock transition
NC= No change from the previous setup
X = Don’t care
↑= Low-to-high clock transition
↑= Not low-to-high clock transition
* = This setup is unstable and will change when either set
or reset return to the high level.
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage –0.5 to +7.0 V
IIK DC input diode current VI < 0 –18 mA
VIDC input voltage3–1.2 to +7.0 V
IOK DC output diode current VO < 0 –50 mA
VOUT DC output voltage3output in Off or High state –0.5 to +5.5 V
IOUT DC output current output in Low state 40 mA
Tstg Storage temperature range –65 to 150 °C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN MAX
UNIT
VCC DC supply voltage 4.5 5.5 V
VIInput voltage 0 VCC V
VIH High-level input voltage 2.0 V
VIL Low-level input voltage 0.8 V
IOH High-level output current –15 mA
IOL Low-level output current 20 mA
∆t/∆vInput transition rise or fall rate 0 10 ns/V
Tamb Operating free-air temperature range –40 +85 °C
Philips Semiconductors Product specification
74ABT74Dual D-type flip-flop
1995 Sep 22 3
DC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
SYMBOL PARAMETER TEST CONDITIONS Tamb = +25°CTamb = –40°C
to +85°CUNIT
MIN TYP MAX MIN MAX
VIK Input clamp voltage VCC = 4.5V ; IIK = –18mA –0.9 –1.2 –1.2 V
VOH High-level output voltage VCC = 4.5V ; IOH = –15mA; VI = VIL or VIH 2.5 2.9 2.5 V
VOL Low-level output voltage VCC = 4.5V; IOL = 20mA; VI = VIL or VIH 0.35 0.5 0.5 V
IIInput leakage current VCC = 5.5V ; V I = GND or 5.5V ±0.01 ±1.0 ±1.0 µA
IOFF Power-of f leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA
ICEX Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or VCC 5.0 50 50 µA
IOOutput current1VCC = 5.5V; VO = 2.5V –50 –75 –180 –50 –180 mA
ICC Quiescent supply current VCC = 5.5V ; V I = GND or VCC 250 50 µA
∆ICC Additional supply current per
input pin2VCC = 5.5V ; One data input at 3.4V, other
inputs at VCC or GND 0.25 500 500 µA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flop or latch after applying the power.
AC ELECTRICAL CHARACTERISTICS
GND = 0V ; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω
SYMBOL
WAVEFORM
LIMITS
UNIT
SYMBOL PARAMETER WAVEFORM Tamb = +25°C
VCC = +5.0V Tamb = –40°C to +85°C
VCC = +5.0V ±0.5V UNIT
MIN TYP MAX MIN MAX
fMAX Maximum clock frequency 1 180 250 150 MHz
tPLH
tPHL Propagation delay
CPn to Qn, Qn11.0
1.0 3.0
2.5 4.2
3.5 1.0
1.0 4.7
4.0 ns
tPLH
tPHL Propagation delay
Sn, Rn to Qn, Qn 31.0
1.0 3.4
2.9 4.9
4.5 1.0
1.0 6.2
5.2 ns
tOSHL
tOSLH1Output to Output skew
An or Bn to Yn4 0.5 0.6 0.6 ns
NOTE:
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same
device. The specification applies to any outputs switching in the the same direction, either HIGH–to-LOW (tOSHL) or LOW-to-HIGH (tOSLH);
parameter guaranteed by design.
AC SETUP REQUIREMENTS
GND = 0V ; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω
SYMBOL
PARAMETER
WAVEFORM
LIMITS
UNIT
SYMBOL PARAMETER WAVEFORM Tamb = +25°C
VCC = +5.0V Tamb = –40°C to +85°C
VCC = +5.0V ±0.5V UNIT
MIN TYP MIN
tsu (H)
tsu (L) Setup time, high or low
Dn to CPn 12.6
2.4 1.4
1.4 2.6
2.4 ns
th (H)
th (L) Hold time, high or low
Dn to CPn 10
0–1.4
–1.4 0
0ns
tw (H)
tw (L) CPn pulse width,
high or low 11.7
1.7 1.0
1.0 2.1
2.1 ns
tw (L) SDn, RDn pulse width, low 3 2.0 1.3 2.2 ns
trec Recovery time
SDn, RDn to CPn 2 2.1 1.4 2.4 ns
Philips Semiconductors Product specification
74ABT74Dual D-type flip-flop
1995 Sep 22 4
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
The shaded areas indicate when the input is permitted to change for predictable output performance
VM
VM
CPn
VMVMVMVM
VMVM
tsu(H) th(H)
Dn
Qn
VM
tw(H)
1/fmax
tsu(L) th(L)
VM
VM
tPLH
Qn
tw(L)
tPHL
tPHL
tPLH
SF00049
W aveform 1. Propagation delay for data to output,
data setup time and hold times, and clock width,
and maximum clock frequency
SDn or RDn VM
VM
trec
CPn
SF00051
W aveform 2. Recovery time for set or reset to clock
VM
VM
RDn VM
Qn
VM
VM
VM
tPLH
Qn
tw(L)
tPHL
tPHL
tPLH
SDn VM
VMtw(L)
SF00050
W aveform 3. Propagation delay for set and reset to output,
set and reset pulse width
OUTPUT N
same part
INPUT
SA00381
OUTPUT
tPLH
MIN
tPHL
MIN
tPLH MAX tPHLMAX
tOSLH tOSHL
W aveform 4. Common edge skew
Philips Semiconductors Product specification
74ABT74Dual D-type flip-flop
1995 Sep 22 5
TEST CIRCUIT AND WAVEFORMS
PULSE
GENERATOR
RT
VIN D.U.T. VOUT
CLRL
VCC
Test Circuit for Outputs
VMVM
tWAMP (V)
NEGATIVE
PULSE 10% 10%
90% 90%
0V
VMVM
tW
AMP (V)
POSITIVE
PULSE
90% 90%
10% 10% 0V
tTHL (tF)
tTLH (tR)t
THL (tF)
tTLH (tR)
VM = 1.5V
Input Pulse Definition
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
INPUT PULSE REQUIREMENTS
FAMILY
74ABT
SH00067
Amplitude Rep. Rate tWtF
3.0V 1MHz 500ns 2.5ns
tR
2.5ns