W942508CH 8M x 4 BANKS x 8 BIT DDR SDRAM Table of Contents- 10. 1. GENERAL DESCRIPTION .................................................................................................. 3 2. FEATURES .......................................................................................................................... 3 3. KEY PARAMETERS ............................................................................................................ 4 4. PIN CONFIGURATION ........................................................................................................ 5 5. PIN DESCRIPTION.............................................................................................................. 6 6. BLOCK DIAGRAM ............................................................................................................... 7 7. ELECTRICAL CHARACTERISTICS .................................................................................... 8 7.1 Absolute Maximum Ratings ................................................................................................. 8 7.2 Recommended DC Operating Conditions............................................................................ 8 7.3 Capacitance ......................................................................................................................... 9 7.4 Leakage and Output Buffer Characteristics ......................................................................... 9 7.5 DC Characteristics ............................................................................................................. 10 7.6 AC Characteristics and Operating Condition ..................................................................... 11 7.7 AC Test Conditions ............................................................................................................ 13 8. Operation Mode ................................................................................................................. 15 8.1 Simplified Truth Table ........................................................................................................ 15 8.2 Function Truth Table .......................................................................................................... 16 8.3 Function Truth Table for CKE ............................................................................................ 19 8.4 Simplified State Diagram.................................................................................................... 20 9. FUNCTIONAL DESCRIPTION........................................................................................... 21 9.1 Power Up Sequence .......................................................................................................... 21 9.2 Command Function............................................................................................................ 21 9.3 Read Operation.................................................................................................................. 24 9.4 Write Operation .................................................................................................................. 24 9.5 Precharge........................................................................................................................... 24 9.6 Burst Termination............................................................................................................... 25 9.7 Refresh Operation.............................................................................................................. 25 9.8 Power Down Mode............................................................................................................. 25 9.9 Mode Register Operation ................................................................................................... 25 TIMING WAVEFORMS ............................................................................................................. 29 10.1 Command Input Timing...................................................................................................... 29 10.2 Timing of the CLK Signals.................................................................................................. 29 10.3 Read Timing (Burst Length = 4) ......................................................................................... 30 10.4 Write Timing (Burst Length = 4) ......................................................................................... 31 10.5 DM, DATA MASK (W942508CH/W942504CH) ................................................................. 32 -1- Publication Release Date: May 21, 2003 Revision A3 W942508CH 11. 10.6 DM, DATA MASK (W942516CH)....................................................................................... 32 10.7 Mode Register Set (MRS) Timing ...................................................................................... 33 10.8 Extend Mode Register Set (EMRS) Timing........................................................................ 34 10.9 Auto Precharge Timing (Read Cycle, CL = 2).................................................................... 35 10.10 Auto Precharge Timing (Write Cycle)................................................................................. 37 10.11 Read Interrupted by Read (CL = 2, BL = 2, 4, 8) ............................................................... 38 10.12 Burst Read Stop (BL = 8) ................................................................................................... 38 10.13 Read Interrupted by Write & BST (BL = 8)......................................................................... 39 10.14 Read Interrupted by Precharge (BL = 8) ............................................................................ 39 10.15 Write Interrupted by Write (BL = 2, 4, 8) ............................................................................ 40 10.16 Write Interrupted by Read (CL = 2, BL = 8) ....................................................................... 40 10.17 Write Interrupted by Read (CL = 2.5, BL = 4) .................................................................... 41 10.18 Write Interrupted by Precharge (BL = 8) ............................................................................ 41 10.19 2 Bank Interleave Read Operation (CL = 2, BL = 2) .......................................................... 42 10.20 2 Bank Interleave Read Operation (CL = 2, BL = 4) .......................................................... 42 10.21 4 Bank Interleave Read Operation (CL = 2, BL = 2) .......................................................... 43 10.22 4 Bank Interleave Read Operation (CL = 2, BL = 4) .......................................................... 43 10.23 Auto Refresh Cycle ............................................................................................................ 44 10.24 Active Power Down Mode Entry and Exit Timing............................................................... 44 10.25 Precharged Power Down Mode Entry and Exit Timing ...................................................... 44 10.26 Self Refresh Entry and Exit Timing .................................................................................... 45 PACKAGE DIMENSION ........................................................................................................... 46 11.1 12. TSOP 66l - 400 mil ............................................................................................................ 46 REVISION HISTORY ................................................................................................................ 47 -2- W942508CH 1. GENERAL DESCRIPTION W942508CH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM), organized as 8,388,608 words x 4 banks x 8 bits. Using pipelined architecture and 0.13 m process technology, W942508CH delivers a data bandwidth of up to 400M words per second (-5). To fully comply with the personal computer industrial standard, W942508CH is sorted into four speed grades: -5, -6, -7, -75 The -5 is compliant to the 200MHz/CL2.5 & CL3 specification, The -6 is compliant to the 166MHz/CL2.5 specification, the -7 is compliant to the 143MHz/CL2.5 or DDR266/CL2 specification, the -75 is compliant to the DDR266/CL2.5 specification. All Inputs reference to the positive edge of CLK (except for DQ, DM, and CKE). The timing reference point for the differential clock is when the CLK and CLK signals cross during a transition. And Write and Read data are synschronized with the both edges of DQS (Data Strobe). By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W942508CH is ideal for main memory in high performance applications. 2. FEATURES * 2.5V 0.2V Power Supply for DDR266 * 2.5V 0.2V Power Supply for DDR333 * 2.6V 0.1V Power Supply for DDR400 * Up to 200 MHz Clock Frequency * Double Data Rate architecture; two data transfers per clock cycle * Differential clock inputs (CLK and CLK ) * DQS is edge-aligned with data for Read; center-aligned with data for Write * CAS Latency: 2, 2.5 and 3 * Burst Length: 2, 4 and 8 * Auto Refresh and Self Refresh * Precharged Power Down and Active Power Down * Write Data Mask * Write Latency = 1 * 8K Refresh cycles / 64 mS * Interface: SSTL-2 * Packaged in TSOP II 66-pin, 400 x 875mil, 0.65mm pin pitch -3- Publication Release Date: May 21, 2003 Revision A3 W942508CH 3. KEY PARAMETERS SYMBOL DESCRIPTION MIN./MAX. -7 -75 CL = 2 Min. 7.5 nS 8 nS CL = 2.5 Min. 7 nS 7.5 nS Active to Precharge Command Period Min. 45 nS 45 nS tRC Active to Ref/Active Command Period Min. 65 nS 65 nS IDD1 OPERATION CURRENT (SINGLE BANK) Max. 120 mA 120 mA IDD4 Burst Operation Current Max. 165 mA 155 mA IDD6 SELF-REFRESH CURRENT Max. 3 mA 3 mA -5 -6 tCK Clock Cycle Time tRAS SYMBOL DESCRIPTION MIN./MAX. CL = 2.5 Min. 5 nS 6 nS CL = 3 Min. 5 nS 6 nS Active to Precharge Command Period Min. 40 nS 42 nS tRC Active to Ref/Active Command Period Min. 55 nS 60 nS IDD1 OPERATION CURRENT (SINGLE BANK) Max. 120 mA 120 mA IDD4 Burst Operation Current Max. 165 mA 165 mA IDD6 SELF-REFRESH CURRENT Max. 3 mA 3 mA tCK Clock Cycle Time tRAS -4- W942508CH 4. PIN CONFIGURATION VDD 1 66 VSS DQ7 DQ0 2 65 VDDQ 3 64 VSSQ NC2 4 63 NC2 DQ1 5 62 DQ6 VSSQ 6 61 VDDQ NC2 7 60 NC2 DQ5 VSSQ DQ2 8 59 VDDQ 9 58 NC2 10 57 NC2 DQ3 11 56 DQ4 VSSQ 12 55 VDDQ NC2 13 54 NC2 NC1 14 53 NC1 VDDQ 15 52 VSSQ NC2 16 51 DQS NC1 17 50 NC1 VDD 18 49 VREF NC1 19 48 VSS NC2 20 47 DM WE 21 46 CLK CAS 22 45 CLK RAS 23 44 CKE CS 24 43 NC1 NC1 25 42 A12 BS0 26 41 A11 BS1 27 40 A9 A10/AP 28 39 A8 A0 29 38 A7 A1 30 37 A6 A2 31 36 A5 A3 32 35 A4 VDD 33 34 VSS -5- Publication Release Date: May 21, 2003 Revision A3 W942508CH 5. PIN DESCRIPTION PIN NUMBER PIN NAME FUNCTION DESCRIPTION Multiplexed pins for row and column address. 28 - 32, 35 - 42 A0 - A12 26, 27 BS0, BS1 Bank Select Select bank to activate during row address latch time, or bank to read/write during column address latch time. 2, 5, 8, 11, 56, 59, 62, 65 DQ0 - DQ7 Data Input/ Output The DQ0 - DQ7 input and output data are synchronized with both edges of DQS. 51 DQS Data Strobe DQS is Bi-directional signal. DQS is input signal during write operation and output signal during read operation. It is Edgealigned with read data, Center-aligned with write data. 24 CS Chip Select Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. RAS , CAS , WE Command Inputs Command inputs (along with CS ) define the command being entered. 47 DM Write Mask When DM is asserted "high" in burst write, the input data is masked. DM is synchronized with both edges of DQS. 45, 46 CLK, CLK Differential Clock Inputs All address and control input signals are sampled on the crossing of the positive edge of CLK and negative edge of CLK . 44 CKE 49 VREF Reference Voltage 1, 18, 33 VDD Power (+2.5) Power for logic circuit inside DDR SDRAM. 34, 48, 66 VSS Ground Ground for logic circuit inside DDR SDRAM. 3, 9, 15, 55, 61 VDDQ Power (+2.5V) Separated power from VDD, used for output buffer, to improve for I/O Buffer noise. 6, 12, 52, 58, 64 VSSQ Ground for I/O Separated ground from VSS, used for output buffer, to improve noise. Buffer 4, 7, 10, 13, 14, 16, 17, 19, 20, 25, 43, 50, 53, 54, 57, 60, 63 NC1, NC2 23, 22, 21 Address Row address: A0 - A12. Column address: A0 - A9. (A10 is used for Auto Precharge) CKE controls the clock activation and deactivation. When CKE Clock Enable is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. VREF is reference voltage for inputs. No Connection No connection -6- W942508CH 6. BLOCK DIAGRAM CLK CLK DLL CLOCK BUFFER CKE CONTROL CS RAS SIGNAL GENERATOR COMMAND CAS DECODER COLUMN DECODER A10 MODE REGISTER A0 CELL ARRAY BANK #1 SENSE AMPLIFIER SENSE AMPLIFIER ADDRESS BUFFER PREFETCH REGISTER DQ DATA CONTROL BUFFER DQ0 DQ7 CIRCUIT COLUMN COUNTER COUNTER DQS DM COLUMN DECODER CELL ARRAY BANK #2 COLUMN DECODER ROW DECODER REFRESH ROW DECODER A9 A11 A12 BA1 BA0 CELL ARRAY BANK #0 COLUMN DECODER ROW DECODER ROW DECODER WE SENSE AMPLIFIER CELL ARRAY BANK #3 SENSE AMPLIFIER NOTE: The cell array configuration is 8912 * 1024 * 8 -7- Publication Release Date: May 21, 2003 Revision A3 W942508CH 7. ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings PARAMETER SYMBOL RATING UNIT Input/Output Voltage VIN, VOUT -0.3 - VDDQ +0.3 V Power Supply Voltage VDD, VDDQ -0.3 - 3.6 V Operating Temperature TOPR 0 - 70 C Storage Temperature TSTG -55 - 150 C TSOLDER 260 C PD 1 W IOUT 50 mA Soldering Temperature (10s) Power Dissipation Short Circuit Output Current Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 7.2 Recommended DC Operating Conditions (TA = 0 to 70 C) SYMBOL PARAMETER MIN. TYP. MAX. UNIT NOTES VDD Power Supply Voltage 2.3 2.5 2.7 V 2 VDDQ Power Supply Voltage (for I/O Buffer) 2.3 2.5 VDD V 2 VREF Input reference Voltage 0.49 x VDDQ 0.50 x VDDQ 0.51 x VDDQ V 2, 3 Termination Voltage (System) VREF -0.04 VREF VREF +0.04 V 2, 8 VIH (DC) VTT Input High Voltage (DC) VREF +0.15 - VDDQ +0.3 V 2 VIL (DC) Input Low Voltage (DC) -0.3 - VREF -0.15 V 2 VICK (DC) Differential Clock DC Input Voltage -0.3 - VDDQ +0.3 V 15 VID (DC) Input Differential Voltage. CLK and CLK inputs (DC) 0.36 - VDDQ +0.6 V 13, 15 VIH (AC) Input High Voltage (AC) VREF +0.31 - - V 2 VIL (AC) Input Low Voltage (AC) - - VREF -0.31 V 2 VID (AC) Input Differential Voltage. CLK and CLK inputs (AC) 0.7 - VDDQ +0.6 V 13, 15 VX (AC) Differential AC input Cross Point Voltage VDDQ/2 -0.2 - VDDQ/2 +0.2 V 12, 15 Differential Clock AC Middle Point VDDQ/2 -0.2 - VDDQ/2 +0.2 V 14, 15 VISO (AC) Notes: Undershoot Limit: VIL (min) = -0.9V with a pulse width < 5 nS Overshoot Limit: VIH (max) = VDDQ +0.9V with a pulse width < 5 nS VIH (DC) and VIL (DC) are levels to maintain the current logic state. VIH (AC) and VIL (AC) are levels to change to the new logic state. -8- W942508CH 7.3 Capacitance (VDD = VDDQ = 2.5V 0.2V, f = 1 MHz, TA = 25 C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) = 0.2V) MIN. MAX. DELTA (MAX.) UNIT Input Capacitance (except for CLK pins) 2.0 3.0 0.5 pF CCLK Input Capacitance (CLK pins) 2.0 3.0 0.25 pF CI/O DQ, DQS, DM Capacitance 4.0 5.0 0.5 pF CNC1 NC1 Pin Capacitance - 1.5 - pF CNC2 NC2 Pin Capacitance 4.0 5.0 - pF SYMBOL CIN PARAMETER Notes: These parameters are periodically sampled and not 100% tested. The NC2 pins have additional capacitance for adjustment of the adjacent pin capacitance. The NC2 pins have Power and Ground clamp. 7.4 Leakage and Output Buffer Characteristics SYMBOL II(L) IO(L) VOH VOL PARAMETER Input Leakage Current (0V < VIN < VDDQ, All other pins not under test = 0V) Output Leakage Current (Output disabled, 0V < VOUT < VDDQ) Output High Voltage (under AC test load condition) Output Low Voltage (under AC test load condition) Full Strength MIN. MAX. UNITS -2 2 A -5 5 A VTT +0.76 - V - VTT -0.76 V NOTES IOH (DC) Output Minimum Source DC Current -15.2 - mA 4, 6 IOL (DC) Output Minimum Sink DC Current 15.2 - mA 4, 6 IOH (DC) Output Minimum Source DC Current -10.4 - mA 5 IOL (DC) Output Minimum Sink DC Current 10.4 - mA 5 Half Strength -9- Publication Release Date: May 21, 2003 Revision A3 W942508CH 7.5 DC Characteristics SYM. IDD0 IDD1 IDD2P MAX. PARAMETER OPERATING CURRENT: One Bank Active-Precharge; tRC = tRC min; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle; Address and control inputs changing once per clock cycle OPERATING CURRENT: One Bank Active-Read-Precharge; Burst = 2; tRC = tRC min; CL = 2.5; tCK = tCK min; IOUT = 0 mA; Address and control inputs changing once per clock cycle. PRECHARGE-POWER-DOWN STANDBY CURRENT: All Banks Idle; Power down mode; CKE < VIL max; tCK = tCK min; Vin = VREF for DQ, DQS and DM UNIT NOTES -5 -6 -7 -75 110 110 110 110 7 120 120 120 120 7, 9 8 8 8 8 IDD2F IDLE FLOATING STANDBY CURRENT: CS > VIH min; All Banks Idle; CKE > VIH min; Address and other control inputs changing once per clock cycle; Vin = Vref for DQ, DQS and DM 45 45 45 40 7 IDD2N IDLE STANDBY CURRENT: CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min; Address and other control inputs changing once per clock cycle; Vin > VIH min or Vin < VIL max for DQ, DQS and DM 45 45 45 40 7 40 40 40 35 IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 IDLE QUIET STANDBY CURRENT: CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min; Address and other control inputs stable; Vin > VREF for DQ, DQS and DM ACTIVE POWER-DOWN STANDBY CURRENT: One Bank Active; Power down mode; CKE < VIL max; tCK = tCK min 7 mA ACTIVE STANDBY CURRENT: CS > VIH min; CKE > VIH min; One Bank Active-Precharge; tRC = tRAS max; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One Bank Active; Address and control inputs changing once per clock cycle; CL=2.5; tCK = tCK min; IOUT = 0mA OPERATING CURRENT: Burst = 2; Write; Continuous burst; One Bank Active; Address and control inputs changing once per clock cycle; CL = 2.5; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle AUTO REFRESH CURRENT: tRC = tRFC min SELF REFRESH CURRENT: CKE < 0.2V RANDOM READ CURRENT: 4 Banks Active Read with activate every 20ns, Auto-Precharge Read every 20 nS; Burst = 4; tRCD = 3; IOUT = 0mA; DQ, DM and DQS inputs changing twice per clock cycle; Address changing once per clock cycle 20 20 20 20 70 70 70 65 7 165 165 165 155 7, 9 165 165 165 155 7 190 9 190 9 190 9 190 9 7 270 270 270 270 tCK = 10ns tRC CK CK tRCD COMMAND ADDRESS ACT READ AP ACT READ AP ACT READ AP ACT READ AP ACT Bank 0 Row d Bank 3 Row Col cc Bank 1 Row e Bank 0 Row Col dd Bank 2 Row f Bank 1 Row Col ee Bank 3 Row q Bank 2 Col f Bank 0 Row h DQS DQ Qa Qa Qb Qb Qb Qb Qc Qc Qc Qc Qd Qd RANDOM READ CURRENT Timing (IDD7) - 10 - Qd Qd Qe Qe W942508CH 7.6 AC Characteristics and Operating Condition (Notes: 10, 12) SYM. -7 PARAMETER Active to Ref/Active Command Period Ref to Ref/Active Command Period Active to Precharge Command Period Active to Read/Write Command Delay Time Active to Read with Auto Precharge Enable Read/Write(a) to Read/Write(b) Command Period Precharge to Active Command Period Active(a) to Active(b) Command Period Write Recovery Time Auto Precharge Write Recovery + Precharge Time CL = 2 CLK Cycle Time CL = 2.5 MIN. 65 75 45 20 15 1 20 15 15 30 7.5 7 Data Access Time from CLK, CLK tDQSCK DQS Output Access Time from CLK, CLK tDQSQ tCH tCL Data Strobe Edge to Output Data Edge Skew CLk High Level Width CLK Low Level Width tHP CLK Half Period (minimum of actual tCH, tCL) tQH DQ Output Data Hold Time from DQS tRC tRFC tRAS tRCD tRAP tCCD tRP tRRD tWR tDAL tCK tAC tRPRE tRPST tDS tDH tDIPW tDQSH tDQSL tDSS tDSH tWPRES tWPRE tWPST tDQSS tDSSK tIS tIH tIPW DQS Read Preamble Time DQS Read Postamble Time DQ and DM Setup Time DQ and DM Hold Time DQ and DM Input Pulse Width (for each input) DQS Input High Pulse Width DQS Input Low Pulse Width DQS Falling Edge to CLK Setup Time DQS Falling Edge Hold Time from CLK Clock to DQS Write Preamble Set-up Time DQS Write Preamble Time DQS Write Postamble Time Write Command to First DQS Latching Transition UDQS - LDQS Skew (x 16) Input Setup Time Input Hold Time Control & Address Input Pulse Width (for each input) -75 15 15 MIN. 65 75 45 20 15 1 20 15 15 30 8 7.5 -0.75 0.75 -0.75 0.75 -0.75 0.75 -0.75 0.75 0.45 0.45 Min. (tCL,tCH) THP -0.75 0.9 0.4 0.5 0.5 1.75 0.35 0.35 0.2 0.2 0 0.25 0.4 0.75 -0.25 0.9 0.9 2.2 MAX. 100000 0.5 0.55 0.55 1.1 0.6 1.25 0.25 0.45 0.45 Min. (tCL,tCH) THP -0.75 0.9 0.4 0.5 0.5 1.75 0.35 0.35 0.2 0.2 0 0.25 0.4 0.75 -0.25 0.9 0.9 2.2 MAX. 100000 15 15 0.5 0.55 0.55 1.1 0.6 1.25 0.25 0.75 tLZ Data-out Low-impedance Time from CLK, CLK -0.75 0.75 -0.75 0.75 0.5 1 75 10 1.5 0.5 1 75 10 1.5 - 11 - 11 tCK 11 11 nS -0.75 64 15 tCK tCK 0.75 64 16 nS -0.75 15 nS nS Data-out High-impedance Time from CLK, CLK SSTL Input Transition Internal Write to Read Command Delay Exit Self Refresh to non-Read Command Exit Self Refresh to Read Command Refresh Time (8k) Mode Register Set Cycle Time nS tCK tHZ tT(SS) tWTR tXSNR tXSRD tREF tMRD UNITS NOTES tCK 11 nS tCK ns tCK mS nS Publication Release Date: May 21, 2003 Revision A3 W942508CH SYM. -5 PARAMETER Active to Ref/Active Command Period Ref to Ref/Active Command Period Active to Precharge Command Period Active to Read/Write Command Delay Time Active to Read with Auto Precharge Enable Read/Write(a) to Read/Write(b) Command Period Precharge to Active Command Period Active(a) to Active(b) Command Period Write Recovery Time Auto Precharge Write Recovery + Precharge Time 2.5 CLK Cycle Time 3 MIN. 55 70 40 15 15 1 15 10 15 30 5 5 Data Access Time from CLK, CLK tDQSCK DQS Output Access Time from CLK, CLK tDQSQ tCH tCL Data Strobe Edge to Output Data Edge Skew CLk High Level Width CLK Low Level Width tHP CLK Half Period (minimum of actual tCH, tCL) tQH DQ Output Data Hold Time from DQS tRC tRFC tRAS tRCD tRAP tCCD tRP tRRD tWR tDAL tCK tAC tRPRE tRPST tDS tDH tDIPW tDQSH tDQSL tDSS tDSH tWPRES tWPRE tWPST tDQSS tDSSK tIS tIH tIPW DQS Read Preamble Time DQS Read Postamble Time DQ and DM Setup Time DQ and DM Hold Time DQ and DM Input Pulse Width (for each input) DQS Input High Pulse Width DQS Input Low Pulse Width DQS Falling Edge to CLK Setup Time DQS Falling Edge Hold Time from CLK Clock to DQS Write Preamble Set-up Time DQS Write Preamble Time DQS Write Postamble Time Write Command to First DQS Latching Transition UDQS - LDQS Skew (x 16) Input Setup Time Input Hold Time Control & Address Input Pulse Width (for each input) tHZ Data-out High-impedance Time from CLK, CLK tLZ Data-out Low-impedance Time from CLK, CLK SSTL Input Transition Internal Write to Read Command Delay Exit Self Refresh to non-Read Command Exit Self Refresh to Read Command Refresh Time (8k) Mode Register Set Cycle Time tT(SS) tWTR tXSNR tXSRD tREF tMRD -6 10 10 MIN. 60 72 42 18 15 1 18 12 15 30 6 6 -0.7 0.7 -0.7 0.7 -0.55 0.55 -0.6 0.6 0.45 0.45 min (tCL,tCH) tHP -0.5 0.9 0.4 0.4 0.4 1.75 0.35 0.35 0.2 0.2 0 0.25 0.4 0.72 -0.25 0.6 0.6 2.2 MAX. 70000 0.4 0.55 0.55 1.1 0.6 0.6 1.28 0.25 0.45 0.45 Min, (tCL,tCH) tHP -0.55 0.9 0.4 0.45 0.45 1.75 0.35 0.35 0.2 0.2 0 0.25 0.4 0.75 -0.25 0.75 0.75 2.2 100000 12 12 0.45 0.55 0.55 1.1 0.6 nS 16 tCK 11 tCK 11 nS tCK 11 nS 0.6 1.25 0.25 -0.7 0.7 -0.7 0.7 0.5 2 75 10 1.5 0.5 2 75 10 1.5 0.7 64 12 nS nS -0.7 64 UNITS NOTES tCK Max tAC 10 - 12 - MAX. tCK nS tCK ns tCK mS nS 11 W942508CH 7.7 AC Test Conditions PARAMETER SYMBOL VALUE UNIT Input High Voltage (AC) VIH VREF +0.31 V Input Low Voltage (AC) VIL VREF -0.31 V Input Reference Voltage VREF 0.5 x VDDQ V Termination Voltage VTT 0.5 x VDDQ V Input Signal Peak to Peak Swing VSWING 1.0 V Differential Clock Input Reference Voltage VR Vx (AC) V Input Difference Voltage. CLK and CLK Inputs (AC) VID (AC) 1.5 V Input Signal Minimum Slew Rate SLEW 1.0 V/nS Output Timing Measurement Reference Voltage VOTR 0.5 x VDDQ V VTT VDDQ VIH min (AC) Measurement point VREF V SWING (MAX) RT= 50 ohms VIL max (AC) VSS T output T Z = 50 ohms 30pF Output A.C. TEST LOAD (A) SLEW = (VIH min (AC) - VILmax (AC)) / T Notes: (1) Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device. (2) All voltages are referenced to VSS, VSSQ.(2.6V0.1V for DDR400) (3) Peak to peak AC noise on VREF may not exceed 2% VREF(DC). (4) VOH = 1.95V, VOL = 0.35V (5) VOH = 1.9V, VOL = 0.4V (6) The values of IOH (DC) is based on VDDQ = 2.3V and VTT = 1.19V. The values of IOL (DC) is based on VDDQ = 2.3V and VTT = 1.11V. (7) These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of tCK and tRC. - 13 - Publication Release Date: May 21, 2003 Revision A3 W942508CH (8) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. (9) These parameters depend on the output loading. Specified values are obtained with the output open. (10) Transition times are measured between VIH min.(AC) and VIL max.(AC).Transition (rise and fall) of input signals have a fixed slope. (11) IF the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to the nearest decimal place. (i.e., tDQSS = 0.75 x tCK, Tck = 7.5 nS, 0.75 x 7.5 nS = 5.625 nS is rounded up to 5.6 nS.) (12) VX is the differential clock cross point voltage where input timing measurement is referenced. (13) VID is magnitude of the difference between CLK input level and CLK input level. (14) VISO means {VICK(CLK)+VICK( CLK )}/2. (15) Refer to the figure below. CLK VX VX VX VICK VX CLK VICK VICK VSS VID(AC) 0 V Differential VISO VISO(min) VISO(max) VSS (16) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock. - 14 - VICK VX VID(AC) W942508CH 8. OPERATION MODE The following table shows the operation commands. 8.1 Simplified Truth Table SYM. ACT COMMAND Bank Active DEVICE STATE (3) Idle (3) PRE Bank Precharge PREA Precharge All WRIT Write Active Write with Auto Precharge Active READ Read Active READA Read with Auto Precharge MRS CKEN H X DM (4) X BS0 BS1 A10 A12, A11, A9-A0 CS RAS CAS WE V V V L L H H H X X V L X L L H L H X X X H X L L H L (3) H X X V L V L H L L (3) H X X V H V L H L L (3) H X X V L V L H L H (3) Active H X X V H V L H L H Mode Register Set Idle H X X L, L C C L L L L EMRS Extended Mode Regiser Set Idle H X X H, L V V L L L L NOP No Operation Any H X X X X X L H H H BST Burst Read Stop Active H X X X X X L H H L DSL Device Deselect Any H X X X X X H X X X AREF Auto Refresh Idle H H X X X X L L L H SELF Self Refresh Entry Idle H L X X X X WRITA SELEX Self Refresh Exit Any CKEN-1 Any Idle (Self Refresh) L H X X X X L L L H H X X X L H H X H X X X L H H X H X X X L H H X PD Power Down Mode Entry Idle/ (5) Active H L X X X X PDEX Power Down Mode Exit Any (Power Down) L H X X X X WDE Data Write Enable Active H X L X X X X X X X WDD Data Write Disable Active H X H X X X X X X X Notes: 1. V = Valid 2. CKEn signal is input level when commands are issued. X = Don't Care L = Low level H = High level CKEn-1 signal is input level one clock cycle before the commands are issued. 3. These are state designated by the BS0, BS1 signals. 4. LDM, UDM (W942516CH) 5. Power Down Mode can not entry in the burst cycle. - 15 - Publication Release Date: May 21, 2003 Revision A3 W942508CH 8.2 Function Truth Table (Note 1) CURRENT STATE CS RAS CAS Idle H X X X X DSL Nop L H H X X NOP/BST Nop L H L H BS, CA, A10 READ/READA ILLEGAL 3 L H L L BS, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BS, RA ACT Row activating L L H L BS, A10 PRE/PREA Nop L L L H X AREF/SELF Refresh or Self refresh 2 2 Row Active Read Write WE ADDRESS COMMAND ACTION L L L L Op-Code MRS/EMRS Mode register accessing H X X X X DSL Nop L H H X X NOP/BST Nop NOTES L H L H BS, CA, A10 READ/READA Begin read: Determine AP 4 L H L L BS, CA, A10 WRIT/WRITA Begin write: Determine AP 4 L L H H BS, RA ACT ILLEGAL 3 L L H L BS, A10 PRE/PREA Precharge 5 L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL H X X X X DSL Continue burst to end L H H H X NOP Continue burst to end L H H L X BST Burst stop L H L H BS, CA, A10 READ/READA Term burst, new read: Determine AP L H L L BS, CA, A10 WRIT/WRITA ILLEGAL L L H H BS, RA ACT ILLEGAL L L H L BS, A10 PRE/PREA Term burst, precharging L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL H X X X X DSL Continue burst to end 6 3 L H H H X NOP Continue burst to end L H H L X BST ILLEGAL L H L H BS, CA, A10 READ/READA Term burst, start read: Determine AP L H L L BS, CA, A10 WRIT/WRITA Term burst, start read: Determine AP 6 L L H H BS, RA ACT ILLEGAL 3 L L H L BS, A10 PRE/PREA Term burst. precharging 8 L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL - 16 - 6, 7 W942508CH Function Truth Table, continued CURRENT STATE Read with Auto Prechange Write with Auto Precharge Precharging Row Activating CS RAS CAS WE H X X X L H H H X NOP Continue burst to end L H H L X BST ILLEGAL ILLEGAL ADDRESS X COMMAND DSL ACTION NOTES Continue burst to end L H L H BS, CA, A10 READ/READA L H L L BS, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BS, RA ACT ILLEGAL 3 L L H L BS, A10 PRE/PREA ILLEGAL L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL H X X X X DSL Continue burst to end L H H H X NOP Continue burst to end L H H L X BST ILLEGAL ILLEGAL L H L H BS, CA, A10 READ/READA L H L L BS, CA, A10 WRIT/WRITA ILLEGAL L L H H BS, RA ACT ILLEGAL 3 L L H L BS, A10 PRE/PREA ILLEGAL 3 L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL H X X X X DSL Nop-> Idle after tRP L H H H X NOP Nop-> Idle after tRP L H H L X BST ILLEGAL L H L H BS, CA, A10 READ/READA ILLEGAL L H L L BS, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BS, RA ACT ILLEGAL 3 L L H L BS, A10 PRE/PREA Nop->Idle after tRP L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL H X X X X DSL Nop-> Row active after L H H H X NOP Nop-> Row active after L H H L X BST ILLEGAL 3 L H L H BS, CA, A10 READ/READA ILLEGAL L H L L BS, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BS, RA ACT ILLEGAL 3 L L H L BS, A10 PRE/PREA ILLEGAL 3 L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL - 17 - 3 Publication Release Date: May 21, 2003 Revision A3 W942508CH Function Truth Table, continued CURRENT STATE CS RAS CAS Write Recovering H X X X X DSL L H H H X NOP Nop->Row active after tWR L H H L X BST ILLEGAL Write Recovering with Auto Precharge Refreshing Mode Register Accessing WE ADDRESS COMMAND ACTION NOTES Nop->Row active after tWR L H L H BS, CA, A10 READ/READA ILLEGAL 3 L H L L BS, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BS, RA ACT ILLEGAL 3 L L H L BS, A10 PRE/PREA ILLEGAL 3 L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL H X X X X DSL Nop->Enter precharge after tWR L H H H X NOP Nop->Enter precharge after tWR L H H L X BST ILLEGAL L H L H BS, CA, A10 READ/READA ILLEGAL 3 L H L L BS, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BS, RA ACT ILLEGAL 3 L L H L BS, A10 PRE/PREA ILLEGAL 3 L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL H X X X X DSL Nop->Idle after tRC L H H H X NOP Nop->Idle after tRC L H H L X BST ILLEGAL L H L H X READ/WRIT ILLEGAL ILLEGAL L L H X X ACT/PRE/PREA L L L X X AREF/SELF/MRS/EM ILLEGAL H X X X X DSL Nop->Row after tMRD L H H H X NOP Nop->Row after tMRD L H H L X BST ILLEGAL L H L X X READ/WRIT ILLEGAL L L X X X ACT/PRE/PREA/ARE F/SELF/MRS/EMRS ILLEGAL Notes: 1. 2. 3. 4. 5. 6. 7. 8. All entries assume that CKE was active (High level) during the preceding clock cycle and the current clock cycle. Illegal if any bank is not idle. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BS), depending on the state of that bank. Illegal if tRCD is not satisfied. Illegal if tRAS is not satisfied. Must satisfy burst interrupt condition. Must avoid bus contention, bus turn around, and/or satisfy write recovery requirements. Must mask preceding data which don't satisfy tWR Remark: H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data - 18 - W942508CH 8.3 Function Truth Table for CKE CURRENT STATE Self Refresh Power Down All Banks Idle Row Active Any State Other Than Listed Above CKE CS RAS CAS WE ADDRESS X X X X X X INVALID L H H X X X X Exit Self Refresh->Idle after tXSNR L H L H H X X Exit Self Refresh->Idle after tXSNR L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X Maintain Self Refresh H X X X X X X INVALID L H X X X X X Exit Power down->Idle after tIS L L X X X X X Maintain power down mode H H X X X X X Refer to Function Truth Table H L H X X X X Enter Power down 2 H L L H H X X Enter Power down 2 1 n-1 n H ACTION H L L L L H X Self Refresh H L L H L X X ILLEGAL NOTES H L L L X X X ILLEGAL L X X X X X X Power down H H X X X X X Refer to Function Truth Table H L H X X X X Enter Power down 2 H L L H H X X Enter Power down 2 H L L L L H X ILLEGAL H L L H L X X ILLEGAL H L L L X X X ILLEGAL L X X X X X X Power down H H X X X X X Refer to Function Truth Table 2 Notes: 1. Self refresh can enter only from the all banks idle state. 2. Power down can enter only from bank idle or row active state. Remark: H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data - 19 - Publication Release Date: May 21, 2003 Revision A3 W942508CH 8.4 Simplified State Diagram SELF REFRESH SREF SREFX MRS/EMRS MODE REGISTER SET AREF IDLE AUTO REFRESH PD PDEX ACT POWER DOWN ACTIVE POWERDOWN PDEX PD ROW ACTIVE BST Read Write Write Read Write Read Read Read A Write A Read A Write A Read A PRE Write A POWER APPLIED POWER ON PRE PRE PRE Read A PRE CHARGE Automatic Sequence Command Sequence - 20 - W942508CH 9. FUNCTIONAL DESCRIPTION 9.1 Power Up Sequence (1) Apply power and attempt to CKE at a low state ( 0.2V), all other inputs may be undefined 1) Apply VDD before or at the same time as VDDQ. 2) Apply VDDQ before or at the same time as VTT and VREF. (2) (3) (4) (5) Start Clock and maintain stable condition for 200 S (min.). After stable power and clock, apply NOP and take CKE high. Issue EMRS (Extended Mode Register Set) to enable DLL and establish Output Driver Type. Issue MRS (Mode Register Set) to reset DLL and set device to idle with bit A8. (an additional 200 cycles(min) of clock are required for DLL Lock) Issue precharge command for all banks of the device. Issue two or more Auto Refresh commands. Issue MRS-Initialize device operation. (If device operation mode is set at sequence 5, sequence 8 can be skipped.) (6) (7) (8) 9.2 Command Function 1. Bank Activate Command ( RAS = "L", CAS = "H", WE = "H", BS0, BS1 = Bank, A0 to A12 = Row Address) The Bank Activate command activates the bank designated by the BS (Bank address) signal. Row addresses are latched on A0 to A12 when this command is issued and the cell data is read out of the sense amplifiers. The maximum time that each bank can be held in the active state is specified as tRAS (max). After this command is issued, Read or Write operation can be executed. 2. Bank Precharge Command ( RAS = "L", CAS = "H", WE = "L", BS0, BS1 = Bank, A10 = "L", A0 to A9, A11, A12 = Don't care) The Bank Precharge command percharges the bank designated by BS. The precharged bank is switched from the active state to the idle state. 3. Precharge All Command ( RAS = "L", CAS = "H", WE = "L", BS0, BS1 = Don't care, A10 = "H", A0 to A9, A11, A12 = Don't care) The Precharge All command precharges all banks simultaneously. Then all banks are switched to the idle state. 4. Write Command ( RAS = "H", CAS = "L", WE = "L", BS0, BS1 = Bank, A10 = "L", A0 to A9, A11 = Column Address) - 21 - Publication Release Date: May 21, 2003 Revision A3 W942508CH The write command performs a Write operation to the bank designated by BS. The write data are latched at both edges of DQS. The length of the write data (Burst Length) and column access sequence (Addressing Mode) must be in the Mode Register at power-up prior to the Write operation. 5. Write with Auto Precharge Command ( RAS ="H", CAS = "L", WE = "L", BS0, BS1 = Bank, A10= "H", A0 to A9, A11 = Column Address) The Write with Auto Precharge command performs the Precharge operation automatically after the Write operation. This command must not be interrupted by any other commands. 6. Read Command ( RAS ="H", CAS = "L", WE = "H", BS0, BS1 = Bank, A10 = "L", A0 to A9, A11 = Column Address) The Read command performs a Read operation to the bank designated by BS. The read data are synchronized with both edges of DQS. The length of read data (Burst Length), Addressing Mode and CAS Latency (access time from CAS command in a clock cycle) must be programmed in the Mode Register at power-up prior to the Read operation. 7. Read with Auto Precharge Command ( RAS = "H", CAS = "L", WE = "H", BS0, BS1 = Bank, A10 = "H", A0 to A9, A11 = Column Address) The Read with Auto precharge command automatically performs the Precharge operation after the Read operation. 1) READA tRAS (min) - (BL/2) x tCK Internal precharge operation begins after BL/2 cycle from Read with Auto Precharge command. 2) tRCD(min) READA < tRAS(min) - (BL/2) x tCK Data can be read with shortest latency, but the internal Precharge operation does not begin until after tRAS (min) has completed. This command must not be interrupted by any other command. 8. Mode Register Set Command ( RAS = "L", CAS = "L", WE = "L", BS0 = "L", BS1 = "L", A0 to A12 = Register Data) The Mode Register Set command programs the values of CAS latency, Addressing Mode, Burst Length and DLL reset in the Mode Register. The default values in the Mode Register after power-up are undefined, therefore this command must be issued during the power-up sequence. Also, this command can be issued while all banks are in the idle state. Refer to the table for specific codes. - 22 - W942508CH 9. Extended Mode Register Set Command ( RAS = "L", CAS = "L", WE = "L", BS0 = "H", BS1 = "L", A0 to A12 = Register data) The Extended Mode Register Set command can be implemented as needed for function extensions to the standard (SDR-SDRAM). Currently the only available mode in EMRS is DLL enable/disable, decoded by A0. The default value of the extended mode register is not defined; therefore this command must be issued during the power-up sequence for enabling DLL. Refer to the table for specific codes. 10. No-Operation Command ( RAS = "H", CAS = "H", WE = "H") The No-Operation command simply performs no operation (same command as Device Deselect). 11. Burst Read Stop Command ( RAS = "H", CAS = "H", WE = "L") The Burst stop command is used to stop the burst operation. This command is only valid during a Burst Read operation. 12. Device Deselect Command ( CS = "H") The Device Deselect command disables the command decoder so that the RAS , CAS , WE and Address inputs are ignored. This command is similar to the No-Operation command. 13. Auto Refresh Command ( RAS = "L", CAS = "L", WE = "H", CKE = "L", BS0, BS1, A0 to A12 = Don't care) The Auto Refresh command is used to refresh the row address provided by the internal refresh counter. The Refresh operation must be performed 8192 times within 64ms. The next command can be issued after tREF from the end of the Auto Refresh command. When the Auto Refresh command is used, all banks must be in the idle state. 14. Self Refresh Entry Command ( RAS = "L", CAS = "L", WE = "H", CKE = "L", BS0, BS1, A0 to A12 = don't care) The Self Refresh Entry command is used to enter Self Refresh mode. While the device is in Self Refresh mode, all input and output buffer (except the CKE buffer) are disabled and the Refresh operation is automatically performed. Self Refresh mode is exited by taking CKE "high" (the Self Refresh Exit command). During self refresh, DLLl is disable. 15. Self Refresh Exit Command (CKE = "H", CS = "H" or CKE = "H", RAS = "H", CAS = "H") This command is used to exit from Self Refresh mode. Any subsequent commands can be issued after tXSNR (tXSRD for Read Command) from the end of this command. - 23 - Publication Release Date: May 21, 2003 Revision A3 W942508CH 16. Data Write Enable /Disable Command (DM = "L/H" or LDM, UDM = "L/H") During a Write cycle, the DM or LDM, UDM signal functions as Data Mask and can control every word of the input data. The LDM signal controls DQ0 to DQ7 and UDM signal controls DQ8 to DQ15. 9.3 Read Operation Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read command is issued after tRCD from the Bank Activate command, the data is read out sequentially, synchronized with both edges of DQS (Burst Read operation). The initial read data becomes available after CAS latency from the issuing of the Read command. The CAS latency must be set in the Mode Register at power-up. When the Precharge Operation is performed on a bank during a Burst Read and operation, the Burst operation is terminated. When the Read with Auto Precharge command is issued, the Precharge operation is performed automatically after the Read cycle, then the bank is switched to the idle state. This command cannot be interrupted by any other commands. Refer to the diagrams for Read operation. 9.4 Write Operation Issuing the Write command after tRCD from the bank activate command. The input data is latched sequentially, synchronizing with both edges(rising &falling) of DQS after the Write command (Burst write operation). The burst length of the Write data (Burst Length) and Addressing Mode must be set in the Mode Register at power-up. When the Precharge operation is performed in a bank during a Burst Write operation, the Burst operation is terminated. When the Write with Auto Precharge command is issued, the Precharge operation is performed automatically after the Write cycle, then the bank is switched to the idle state, The Write with Auto Precharge command cannot be interrupted by any other command for the entire burst data duration. Refer to the diagrams for Write operation. 9.5 Precharge There are two Commands, which perform the precharge operation (Bank Precharge and Precharge All). When the Bank Precharge command is issued to the active bank, the bank is precharged and then switched to the idle state. The Bank Precharge command can precharge one bank independently of the other bank and hold the unprecharged bank in the active state. The maximum time each bank can be held in the active state is specified as tRAS (max). Therefore, each bank must be precharged within tRAS(max) from the bank activate command. The Precharge All command can be used to precharge all banks simultaneously. Even if banks are not in the active state, the Precharge All command can still be issued. In this case, the Precharge operation is performed only for the active bank and the precharge bank is then switched to the idle state. - 24 - W942508CH 9.6 Burst Termination When the Precharge command is used for a bank in a Burst cycle, the Burst operation is terminated. When Burst Read cycle is interrupted by the Precharge command, read operation is disabled after clock cycle of ( CAS latency) from the Precharge command. When the Burst Write cycle is interrupted by the Precharge command . the input circuit is reset at the same clock cycle at which the precharge command is issued. In this case, the DM signal must be asserted "high": during tWR to prevent writing the invalided data to the cell array. When the Burst Read Stop command is issued for the bank in a Burst Read cycle, the Burst Read operation is terminated. The Burst read Stop command is not supported during a write burst operation. Refer to the diagrams for Burst termination. 9.7 Refresh Operation Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh. By repeating the Auto Refresh cycle, each bank in turn refreshed automatically. The Refresh operation must be performed 8192 times(rows) within 64 mS. The period between the Auto Refresh command and the next command is specified by tRFC. Self Refresh mode enter issuing the Self Refresh command (CKE asserted "low"). while all banks are in the idle state. The device is in Self Refresh mode for as long as cke held "low". In the case of 8192 burst Auto Refresh commands, 8192 burst Auto Refresh commands must be performed within 7.8 S before entering and after exiting the Self Refresh mode. In the case of distributed Auto Refresh commands, distributed auto refresh commands must be issued every 7.8 S and the last distributed Auto Refresh commands must be performed within 7.8 S before entering the self refresh mode. After exiting from the Self Refresh mode, the refresh operation must be performed within 7.8 S. In Self Refresh mode, all input/output buffers are disable, resulting in lower power dissipation (except CKE buffer). Refer to the diagrams for Refresh operation. 9.8 Power Down Mode Two types of Power Down Mode can be performed on the device: Active Standby Power Down Mode and Precharge Standby Power Down Mode. When the device enters the Power Down Mode, all input/output buffers and DLL are disabled resulting in low power dissipation (except CKE buffer). Power Down Mode enter asserting CKE "low" while the device is not running a burst cycle. Taking CKE: "high" can exit this mode. When CKE goes high, a No operation command must be input at next CLK rising edge. Refer to the diagrams for Power Down Mode. 9.9 Mode Register Operation The mode register is programmed by the Mode Register Set command (MRS/EMRS) when all banks are in the idle state. The data to be set in the Mode Register is transferred using the A0 to A12 and BS0, BS1 address inputs. The Mode Register designates the operation mode for the read or write cycle. The register is divided into five filed: (1) Burst Length field to set the length of burst data (2) Addressing Mode selected bit to designate the column access sequence in a Burst cycle (3) CAS Latency field to set the assess time in clock cycle (4) DLL reset field to reset the dll (5) Regular/Extended Mode Register filed to select a - 25 - Publication Release Date: May 21, 2003 Revision A3 W942508CH type of MRS (Regular/Extended MRS). EMRS cycle can be implemented the extended function (DLL enable/Disable mode) The initial value of the Mode Register (including EMRS) after power up is undefined; therefore the Mode Register Set command must be issued before power operation. (1) Burst Length field (A2 to A0) This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length to be 2, 4, and 8 words. A2 A1 A0 BURST LENGTH 0 0 0 Reserved 0 0 1 2 words 0 1 0 4 words 0 1 1 8 words 1 x x Reserved (2) Addressing Mode Select (A3) The Addressing Mode can be one of two modes; Interleave mode or Sequential Mode, When the A3 bit is "0", Sequential mode is selected. When the A3 bit is "1", Interleave mode is selected. Both addressing Mode support burst length 2, 4, and 8 words. A3 ADDRESSING MODE 0 Sequential 0 Interleave - 26 - W942508CH * Address Sequence of Sequential Mode A column access is performed by incrementing the column address input to the device. The address is varied by the Burst Length as the following. Addressing Sequence of Sequential Mode * DATA ACCESS ADDRESS BURST LENGTH Data 0 n 2 words (address bits is A0) Data 1 n+1 not carried from A0 to A1 Data 2 n+2 4 words (address bit A0, A1) Data 3 n+3 Not carried from A1 to A2 Data 4 n+4 Data 5 n+5 8 words (address bits A2, A1 and A0) Data 6 n+6 Not carried from A2 to A3 Data 7 n+7 Addressing Sequence of Interleave Mode A Column access is started from the inputted column address and is performed by interleaving the address bits in the sequence shown as the following. 9.9.1.1 DATA Address Sequence for Interleave Mode ACCESS ADDRESS Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 1 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 2 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 3 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 4 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 5 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 6 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 7 A8 A7 A6 A5 A4 A3 A2 A1 A0 - 27 - BURST LENGTH 2 words 4 words 8 words Publication Release Date: May 21, 2003 Revision A3 W942508CH (3) CAS Latency field (A6 to A4) This field specifies the number of clock cycles from the assertion of the Read command to the first data read. The minimum values of CAS Latency depends on the frequency of CLK. A6 A5 A4 CAS LATENCY 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 2.5 1 1 1 Reserved (4) DLL Reset bit (A8) This bit is used to reset DLL. When the A8 bit is "1", DLL is reset. (5) Mode Register /Extended Mode register change bits (BS0, BS1) These bits are used to select MRS/EMRS. BS1 BS0 A12-A0 0 0 Regular MRS Cycle 0 1 Extended MRS Cycle 1 x Reserved (6) Extended Mode Register field 1) DLL Switch field (A0) This bit is used to select DLL enable or disable A0 DLL 0 Enable 1 Disable 2) Output Driver Size Control field (A1) This bit is used to select Output Driver Size, both Full strength and Half strength are based on JEDEC standard. A1 OUTPUT DRIVER 0 Full Strength 1 Half Strength (7) Reserved field * Test mode entry bit (A7) This bit is used to enter Test mode and must be set to "0" for normal operation. * Reserved bits (A9, A10, A11, A12) These bits are reserved for future operations. They must be set to "0" for normal operation. - 28 - W942508CH 10. TIMING WAVEFORMS 10.1 Command Input Timing tCK tCK tCH tCL CLK CLK tIS tIH CS tIS tIH tIS tIH tIS tIH tIS tIH RAS CAS WE A0~A12 BS0, 1 Refer to the Command Truth Table 10.2 Timing of the CLK Signals tCL tCH CLK CLK tT tT VIH VIH(AC) VIL(AC) VIL tCK CLK CLK VIH VX VX - 29 - VX VIL Publication Release Date: May 21, 2003 Revision A3 W942508CH Timing Waveforms, continued 10.3 Read Timing (Burst Length = 4) tCH tCL tCK CLK CLK tIH tIS READ CMD tIS ADD tIH Col tDQSCK CAS latency=2 tDQSCK tRPST tDQSCK tRPRE Hi-Z Hi-Z DQS tQH Preamble Hi-Z Output (Data) tDQSQ tQH QA0 DA0 QA1 DA1 tDQSQ tDQSQ QA2 DA2 QA3 DA3 tAC tDQSCK tLZ Postamble Hi-Z tHZ tDQSCK tDQSCK CAS latency=2.5 tRPE tRPST Hi-Z Hi-Z DQS tQH Preamble Hi-Z Output (Data) tDQSQ tQH QA0 DA0 QA1 DA1 Postamble tDQSQ tDQSQ QA2 DA2 QA3 DA3 tAC tLZ Note: The correspondence of LDQS, UDQS to DQ. ( W942516AH) LDQS DQ0~7 UDQS DQ8~15 - 30 - tHZ Hi-Z W942508CH Timing Waveforms, continued 10.4 Write Timing (Burst Length = 4) tCH tCL tCK CLK CLK CMD WRIT tIS ADD x4, x8 device tIH tDSS tDSH tDSS tDQSL tDQSH tWPST tDS tDS tDSH Col tWPRES tDQSH tWPRE DQS Preamble Postamble tDS tDH Input (Data) DA0 tDQSS x16 device tWPRES tDH tDH DA1 DA2 DA3 tDSH tDSS tDSH tDSS tDQSH tDQSL tDQSH tWPST tWPRE LDQS Preamble Postamble tDS tDS tDH DA0 DQ0~7 tDQSS DA1 tDSH tWPRES UDQS DA2 tDSSK tDSS tDSSK tDSS tDQSH tWPST tWPRE Preamble tDS tDS tDS tDH DQ8~15 DA3 tDSH tDQSL tDQSH tDH tDH tDSSK tDSSK tDS DA0 tDQSS Postamble tDH DA1 DA2 tDH DA3 tDSH Note: x16 has 2DQS's (UDQS for uper byte and LDQS for lower byte). Even if one of the 2 bytes is not used, both UDQS and LDQS must be toggled. - 31 - Publication Release Date: May 21, 2003 Revision A3 W942508CH Timing Waveforms, continued 10.5 DM, DATA MASK (W942508CH/W942504CH) CLK /CLK CMD WRIT DQS tDS tDS tDH tDH DM tDIPW DQ D0 D1 D3 Masked tDIPW 10.6 DM, DATA MASK (W942516CH) CLK /CLK CMD WRIT LDQS tDS tDS tDH tDH LDM tDIPW DQ0~ DQ7 D0 D1 tDIPW D3 Masked UDQS tDS tDS tDH tDH UDM tDIPW DQ8~ DQ15 D2 D0 Masked D3 tDIPW - 32 - W942508CH Timing Waveforms, continued 10.7 Mode Register Set (MRS) Timing CLK CLK tMRD CMD MRS ADD Register Set data NEXT CMD Burst Length A0 Burst Length A1 A2 Addressing Mode A3 A4 CAS Latency A5 A2 A1 A0 Sequential Interleaved 0 0 0 Reserved Reserved 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 1 1 0 1 1 1 A6 A7 "0" A10 Reserved DLL Reset A8 A9 Addressing Mode A3 "0" A12 "0" BS0 "0" BS1 "0" Interleaved CAS Latency A5 A4 0 0 0 0 0 1 0 1 0 2 0 1 1 3 1 0 0 Reserved Reserved "0" Sequential 1 A6 "0" A11 0 Reserved 1 0 1 1 1 0 2.5 1 1 1 Reserved Mode Register Set or Extended Mode Register Set DLL Reset A8 * "Reserved" should stay "0" during MRS cycle. - 33 - 0 No 1 Yes BS1 BS0 MRS or EMRS 0 0 Regular MRS cycle 0 1 Extended MRS cycle 1 0 1 1 Reserved Publication Release Date: May 21, 2003 Revision A3 W942508CH Timing Waveforms, continued 10.8 Extend Mode Register Set (EMRS) Timing CLK CLK tMRD CMD EMRS ADD Register Set data NEXT CMD DLL Switch A0 A0 DLL Switch A1 Output Driver A2 "0" A3 "0" A4 "0" A5 "0" A6 "0" A7 "0" A8 "0" A9 "0" A10 "0" A11 "0" A12 "0" BS0 "0" BS1 "0" 0 Enable 1 Disable A1 Output Driver Size 0 Full Strength 1 Hall Strength Reserved Mode Register Set or Extended Mode Register Set * "Reserved" should stay "0" during EMRS cycle. - 34 - BS1 BS0 MRS or EMRS 0 0 Regular MRS cycle 0 1 Extended MRS cycle 1 0 1 1 W942508CH Timing Waveforms, continued 10.9 Auto Precharge Timing (Read Cycle, CL = 2) 1) tRCD (READA) tRAS (min) - (BL/2) x tCK tRAS tRP CLK CLK BL=2 CMD ACT READA ACT AP DQS DQ Q0 Q1 BL=4 CMD ACT AP READA ACT DQS DQ Q0 Q1 Q2 Q3 BL=8 CMD ACT AP READA ACT DQS DQ Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Notes: CL2 shown; same command operation timing with CL = 2.5 In this case , the internal precharge operation begin after BL/2 cycle from READA command. AP represents the start of internal precharging . The Read with Auto precharge command cannot be interrupted by any other command. - 35 - Publication Release Date: May 21, 2003 Revision A3 W942508CH Timing Waveforms, continued 2) tRCD/RAP(min) tRCD (READA) < tRAS (min) - (BL/2) x tCK tRAS tRP CLK CLK BL=2 CMD ACT READA AP ACT AP ACT tRAP tRCD DQS DQ Q0 Q1 BL=4 CMD ACT READA tRAP tRCD DQS DQ Q0 Q1 Q2 Q3 BL=8 CMD ACT READA ACT AP tRAP tRCD DQS DQ Q0 Q1 Q2 Q3 Q4 Q5 Q6 Notes: CL2 shown; same command operation timing with CL = 2.5 In this case , the internal precharge operation does not begin until after tRAS (min) has command. AP represents the start of internal precharging . The Read with Auto Precharge command cannot be interrupted by any other command. - 36 - Q7 W942508CH Timing Waveforms, continued 10.10 Auto Precharge Timing (Write Cycle) CLK CLK tDAL BL=2 CMD AP WRITA ACT DQS DQ D0 D1 tDAL BL=4 CMD AP WRITA ACT DQS DQ D0 D1 D2 D3 tDAL BL=8 CMD WRITA AP ACT DQS DQ D0 D1 D2 D3 D4 D5 D6 D7 The Write with Auto Precharge command cannot be interrupted by any other command. AP represents the start of internal precharging . - 37 - Publication Release Date: May 21, 2003 Revision A3 W942508CH Timing Waveforms, continued 10.11 Read Interrupted by Read (CL = 2, BL = 2, 4, 8) CLK CLK CMD ACT READ A tRCD tCCD Row Address ADD READ B COl,Add,A READ C tCCD Col,Add,B READ D tCCD Col,Add,C READ E tCCD Col,Add,D Col,Add,E DQS DQ QA0 10.12 Burst Read Stop (BL = 8) CLK CLK CMD READ BST CAS Latency=2 DQS CAS Latency DQ Q0 Q1 Q2 Q3 Q4 Q5 CAS Latency=2.5 DQS CAS Latency DQ Q0 Q1 Q2 Q3 - 38 - Q4 Q5 QA1 QB0 QB1 QC0 W942508CH Timing Waveforms, continued 10.13 Read Interrupted by Write & BST (BL = 8) CLK CLK CAS Latency=2 CMD READ BST WRIT DQS DQ Q0 Q1 Q2 Q3 Q4 Q5 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 CAS Latency=2.5 CMD READ BST WRIT DQS DQ Q0 Q1 Q2 Q3 Q4 Q5 D7 Burst Read cycle must be terminated by BST Command to avoid I/O conflict. 10.14 Read Interrupted by Precharge (BL = 8) CLK CLK CMD READ PRE CAS Latency=2 DQS CAS Latency DQ Q0 Q1 Q2 Q3 Q4 Q5 CAS Latency=2.5 DQS CAS Latency DQ Q0 Q1 Q2 Q3 - 39 - Q4 Q5 Publication Release Date: May 21, 2003 Revision A3 W942508CH Timing Waveforms, continued 10.15 Write Interrupted by Write (BL = 2, 4, 8) CLK CLK CMD ACT ADD Row Address WRIT A tRCD WRIT B tCCD COl. Add. A WRIT C tCCD Col.Add.B WRIT D tCCD Col. Add. C WRIT E tCCD Col. Add. D Col. Add. E DQS DQ DA0 DA1 DB0 DB1 DC0 DC1 DD0 DD1 10.16 Write Interrupted by Read (CL = 2, BL = 8) CLK CLK CMD WRIT READ DQS DM tWTR DQ D0 D1 D2 D3 Data must be masked by DM D4 D5 D6 D7 Q0 Q1 Q2 Data masked by READ command, DQS input ignored. - 40 - Q3 Q4 Q5 Q6 Q7 W942508CH Timing Waveforms, continued 10.17 Write Interrupted by Read (CL = 2.5, BL = 4) CLK CLK CMD WRIT READ DQS DM tWTR DQ D0 D1 D2 D3 Q0 Q1 Q2 Q3 Data must be masked by DM 10.18 Write Interrupted by Precharge (BL = 8) CLK CLK CMD WRIT PRE ACT tWR tRP DQS DM DQ D0 D1 D2 D3 D4 Data must be masked by DM D5 D6 D7 Data masked by PRE command, DQS input ignored. - 41 - Publication Release Date: May 21, 2003 Revision A3 W942508CH Timing Waveforms, continued 10.19 2 Bank Interleave Read Operation (CL = 2, BL = 2) tCK = 100 MHz CLK CLK tRC(b) tRC(a) tRRD tRRD CMD ACTa ACTb READAa READAb ACTa ACTb tRCD(a) tRAS(a) tRP(a) tRCD(b) tRAS(b) tRP(b) DQS Preamble Postamble CL(a) Q0a DQ ACTa/b : Bank Act. CMD of bank a/b READAa/b : Read with Auto Pre.CMD of bank a/b APa/b : Auto Pre. of bank a/b Preamble Postamble CL(b) Q1a APa Q0b Q1b APb 10.20 2 Bank Interleave Read Operation (CL = 2, BL = 4) CLK CLK tRC(b) tRC(a) tRRD tRRD CMD ACTa ACTb READAa READAb ACTa ACTb tRCD(a) tRAS(a) tRP(a) tRCD(b) tRAS(b) tRP(b) DQS Preamble Postamble CL(a) CL(b) Q0a DQ ACTa/b : Bank Act. CMD of bank a/b READAa/b : Read with Auto Pre.CMD of bank a/b APa/b : Auto Pre. of bank a/b - 42 - APa Q1a Q2a Q3a Q0b APb Q1b Q2b Q3b W942508CH Timing Waveforms, continued 10.21 4 Bank Interleave Read Operation (CL = 2, BL = 2) CLK CLK tRC(a) tRRD tRRD CMD ACTa ACTb tRRD ACTc tRRD READAa ACTd READAb ACTa READAc tRCD(a) tRAS(a) tRP tRCD(b) tRAS(b) tRCD(c) tRAS(c) tRCD(d) tRAS(d) DQS Preamble CL(a) Postamble Preamble CL(b) Q0a DQ ACTa/b/c/d : Bank Act. CMD of bank a/b/c/d READAa/b/c/d : Read with Auto Pre.CMD of bank a/b/c/d APa/b/c/d : Auto Pre. of bank a/b/c/d Q1a APa Q0b Q1b APb 10.22 4 Bank Interleave Read Operation (CL = 2, BL = 4) CLK CLK tRC(a) tRRD tRRD CMD ACTa ACTb READAa tRRD ACTc tRRD READAb ACTd READAc ACTa READAd tRCD(a) tRAS(a) tRP(a) tRCD(b) tRAS(b) tRCD(c) tRAS(c) tRCD(d) tRAS(d) DQS Preamble CL(a) CL(b) CL(c) Q0a DQ ACTa/b/c/d : Bank Act. CMD of bank a/b/c/d READAa/b/c/d : Read with Auto Pre.CMD of bank a/b/c/d APa/b/c/d : Auto Pre. of bank a/b/c/d - 43 - APa Q1a CL(b) Q0a Q1a Q2a APb Q3a Q0b Q1b Q2b Q3b APc Publication Release Date: May 21, 2003 Revision A3 W942508CH Timing Waveforms, continued 10.23 Auto Refresh Cycle CLK CLK CMD PREA NOP AREF tRP NOP AREF NOP tRFC CMD tRFC CKE has to be kept "High" level for Auto-Refresh cycle. 10.24 Active Power Down Mode Entry and Exit Timing CLK CLK tIH tIS tCK tIH tIS CKE Entry CMD NOP Exit NOP NOP CMD NOP 10.25 Precharged Power Down Mode Entry and Exit Timing CLK CLK tIH tIS tCK tIH tIS CKE Entry CMD NOP Exit NOP NOP - 44 - CMD NOP W942508CH Timing Waveforms, continued 10.26 Self Refresh Entry and Exit Timing CLK CLK tIH tIS tCK tIH tIS CKE CMD PREA NOP SELF SELFX NOP CMD tRP Entry Exit tXSNR tXSRD SELF Entry SELFX NOP ACT NOP READ NOP Exit - 45 - Publication Release Date: May 21, 2003 Revision A3 W942508CH 11. PACKAGE DIMENSION 11.1 TSOP 66l - 400 mil - 46 - W942508CH 12. REVISION HISTORY REVISION DATE PAGE Aug. 28, 2002 - Jan. 9, 2003 28 Feb. 14, 2003 - A2 Feb. 14, 2003 10 A3 May 21, 2003 A1 DESCRIPTION Preliminary datasheet Add CAS Latency = 3 option Modified AC timing spec. Change IDD2p current to 8 mA Change IDD6 current to 9 mA Add CL2.5 optional in DDR400 Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd. 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 47 - Publication Release Date: May 21, 2003 Revision A3