Z9960
Document #: 38-07087 Rev. *C Page 4 of 7
Absolute Maximum Ratings[2]
Input Voltage Relative to VSS:...............................VSS – 0.3V
Input Voltage Relative to VDD: ............................. VDD + 0.3V
Storage Temperature: .................................-65°C to + 150°C
Operating Temperature:................................-40°C to + 85°C
Maximum ESD Protection................................................ 2kV
Maximum Power Supply: ................................................5.5V
Maximum Input Current:..................................................± 20mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, VIN and VOUT should be constrained to
the range
VSS < (VIN or VOUT) < VDD.
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
Note:
2. The voltage on any input or I/O or pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Characteristics VDD = 2.5V ±5%, TA = –40°C to +85°C
Parameter Description Test Condition Min. Typ. Max. Unit
VIL[3] Input Low Voltage VSS –0.7V
VIH[3] Input High Voltage 1.7 – VDD V
VPP Peak-to-Peak Input Voltage
PECL_CLK
500 – 1000 mV
VCMR[4] Common Mode Range
PECL_CLK
VDD –1.4 – VDD –0.6 V
IIL[5] Input Low Current (@ VIL = VSS) – – –120 µA
IIH[5] Input High Current (@ VIH =
VDD)
––120µA
VOL[6] Output Low Voltage IOL = 15 mA – – 0.6 V
VOH[6] Output High Voltage IOH = –15 mA 1.8 – V
IDD Quiescent Supply Current VDD and AVDD –1013mA
CIN Input Pin Capacitance – 4 – pF
DC Electrical Characteristics VDD = 3.3V +5%, TA = –40°C to +85°C
Parameter Description Test Condition Min. Typ. Max. Unit
VIL[3] Input Low Voltage VSS –0.8V
VIH[3] Input High Voltage 2.0 – VDD V
VPP Peak-to-Peak Input Voltage
PECL_CLK
500 – 1000 mV
VCMR[4] Common Mode Range PECL_CLK VDD –1.4 – VDD –0.6 V
IIL[5] Input Low Current (@ VIL = VSS) – – –120 µA
IIH[5] Input High Current (@ VIH = VDD)––120µA
VOL[6] Output Low Voltage IOL = 24 mA – – 0.55 V
VOH[6] Output High Voltage IOH = –24 mA 2.4 – – V
IDD Quiescent Supply Current VDD and AVDD –1520mA
CIN Input Pin Capacitance – 4 – pF
Notes:
3. The LVCMOS inputs threshold is at 30% of VDD.
4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when HIGH input is within the VCMR range
and the input lies within the VPP specification.
5. Inputs have pull-up/pull-down resistors that affect input current.
6. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines.