IS61LV12816L
IS61LV12816LL
ISSI®
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
1
PRELIMINARY INFORMATION Rev. 00B
07/30/02
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
FEATURES
• High-speed access time:
IS61LV12816L: 8, 10 ns
IS61LV12816LL: 12, 15 ns
• Operating Current:
IS61LV12816L: 50mA (typ.)
IS61LV12816LL: 25mA (typ.)
• Stand by Current:
IS61LV12816L: 500µA (typ.)
IS61LV12816LL: 250µA(typ.)
• TTL and CMOS compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
128K x 16 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY
DESCRIPTION
The ISSI IS61LV12816L/IS61LV12816LL is a high-speed,
2,097,152-bit static RAM organized as 131,072 words by
16 bits. It is fabricated using ISSI's high-performance
CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields access
times as fast as 8 ns with low power consumption.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS61LV12816L/IS61LV12816LL is packaged in the
JEDEC standard 44-pin TSOP, 44-pin LQFP, and 48-pin
mini BGA (6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
PRELIMINARY INFORMATION
JULY 2002
A0-A16
CS1
OE
WE
128Kx16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
CS2
IS61LV12816L, IS61LV12816LL
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION Rev.00B
07/30/02
ISSI
®
1
2
3
4
5
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7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
44-Pin TSOP (T) PIN DESCRIPTIONS
A0-A16 Address Inputs
I/O0-I/O15 Data Inputs/Outputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB Lower-byte Control (I/O0-I/O7)
UB Upper-byte Control (I/O8-I/O15)
NC No Connection
Vcc Power
GND Ground
TRUTH TABLE
I/O PIN
Mode WEWE
WEWE
WE CECE
CECE
CE OEOE
OEOE
OE LBLB
LBLB
LB UBUB
UBUB
UB I/O0-I/O7 I/O8-I/O15 Vcc Current
Not Selected X H X X X High-Z High-Z ISB1, ISB2
Output Disabled H L H X X High-Z High-Z ICC
X L X H H High-Z High-Z
Read H L L L H DOUT High-Z ICC
H L L H L High-Z DOUT
HLLLL DOUT DOUT
Write L L X L H DIN High-Z ICC
L L X H L High-Z DIN
LLXLL DIN DIN
PIN CONFIGUREATION
IS61LV12816L, IS61LV12816LL
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
3
PRELIMINARY INFORMATION Rev. 00B
07/30/02
ISSI
®
PIN DESCRIPTIONS
A0-A16 Address Inputs
I/O0-I/O15 Data Inputs/Outputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB Lower-byte Control (I/O0-I/O7)
UB Upper-byte Control (I/O8-I/O15)
NC No Connection
Vcc Power
GND Ground
48-Pin mini BGA (B) 44-Pin LQFP (LQ)
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 345
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
TOP VIEW
WE
A0
A1
A2
A3
A4
NC
A5
A6
A7
A8
A16
A15
A14
A13
A12
A11
A10
A9
OE
UB
LB
PIN CONFIGUREATION
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB OE A0 A1 A2 NC
I/O8UB A3 A4 CE I/O0
I/O9I/O10 A5 A6 I/O1I/O2
GND I/O11 NC A7 I/O3Vcc
Vcc I/O12 NC A16 I/O4GND
I/O14 I/O13 A14 A15 I/O5I/O6
I/O15 NC A12 A13 WE I/O7
NC A8 A9 A10 A11 NC
IS61LV12816L, IS61LV12816LL
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION Rev.00B
07/30/02
ISSI
®
OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to + 70°C 3.3V + 10%, -5%
Industrial –40°C to + 85°C 3.3V + 10%, -5%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage(1) 2VCC + 0.3 V
VIL Input LOW Voltage(1) –0.3 0.8 V
ILI Input Leakage GND - VIN - VCC –1 1 µA
ILO Output Leakage GND - VOUT - VCC, Outputs Disabled – 1 1 µA
Note:
1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width - 2.0 ns).
VIH (max.) = VCC + 0.3V DC; VIH (max.) = VCC + 2.0V AC (pulse width - 2.0 ns).
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VCC Power Supply Voltage Relative to GND –0.5 to 4.0V V
VTERM Terminal Voltage with Respect to GND –0.5 to Vcc + 0.5 V
TSTG Storage Temperature –65 to + 150 °C
PTPower Dissipation 1.0 W
IOUT DC Output Current ±20 mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
IS61LV12816L, IS61LV12816LL
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
5
PRELIMINARY INFORMATION Rev. 00B
07/30/02
ISSI
®
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
IS61LV12816L
-8 ns -10 ns
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
ICC Vcc Operating VCC = Max., CE = VIL Com. — 65 — 60 mA
Supply Current IOUT = 0 mA, f = Max. Ind. — 70 — 65
ISB1TTL Standby VCC = Max., Com. — 30 — 25 mA
Current VIN = VIH or VIL Ind. — 35 — 30
(TTL Inputs) CE • VIH, f = max
ISB2CMOS Standby VCC = Max., Com. — 3 — 3 mA
Current CE - VCC – 0.2V, Ind. — 4 — 4 mA
(CMOS Inputs) VIN > VCC – 0.2V, or
VIN - 0.2V, f = 0
Note:
1 . At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
IS61LV12816LL
-12 ns -15 ns
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
ICC Vcc Operating VCC = Max., CE = VIL Com. — 50 — 45 mA
Supply Current IOUT = 0 mA, f = Max. Ind. — 60 — 50
ISB1TTL Standby VCC = Max., Com. — 15 — 15 mA
Current VIN = VIH or VIL Ind. — 20 — 20
(TTL Inputs) CE • VIH, f = max
ISB2CMOS Standby VCC = Max., Com. — 200 — 200 µA
Current CE - VCC – 0.2V, Ind. — 300 — 300 µA
(CMOS Inputs) VIN > VCC – 0.2V, or
VIN - 0.2V, f = 0
Note:
1 . At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE(1)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 p F
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
IS61LV12816L, IS61LV12816LL
6
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION Rev.00B
07/30/02
ISSI
®
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1 and 2
AC TEST LOADS
Figure 1.
319 Ω
5 pF
Including
jig and
scope
353 Ω
OUTPUT
3.3V
Figure 2.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
IS61LV12816L IS61LV12816LL
-8 ns -10 ns -12 ns -15 ns
Symbol Parameter Min. Max Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 8 — 10 — 12 — 15 — n s
tAA Address Access Time — 8 — 10 — 12 — 15 ns
tOHA Output Hold Time 3 — 3 — 3 — 3 — n s
tACE CE Access Time 8 — — 10 — 12 — 15 ns
tDOE OE Access Time — 3.5 — 4 — 5 — 6 ns
tHZOE
(2)
OE to High-Z Output — 3.5 — 4 — 5 0 6 n s
tLZOE
(2)
OE to Low-Z Output 0 — 0 — 0 — 0 — ns
tHZCE
(2)
CE to High-Z Output 0 3.5 0 4 0 5 0 8 n s
tLZCE
(2)
CE to Low-Z Output 3.5 — 3 — 3 — 3 — n s
tBA LB, UB Access Time — 3.5 — 4 — 5 — 6 n s
tHZB
(2)
LB, UB to High-Z Output 0 3.5 0 4 0 5 0 6 n s
tLZB
(2)
LB, UB to Low-Z Output 0 — 0 — 0 — 0 — n s
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to
3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
ZO = 50Ω 1.5
V
50Ω
OUTPUT
30 pF
Including
jig and
scope
IS61LV12816L, IS61LV12816LL
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
7
PRELIMINARY INFORMATION Rev. 00B
07/30/02
ISSI
®
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
DOUT
ADDRESS
t RC
t OHA
t AA
t DOE
t LZOE
t ACE
t LZCE
t HZOE
HIGH-Z DATA VALID
UB_CEDR2.eps
t HZB
ADDRESS
OE
CE
LB, UB
DOUT
t HZCE
t BA
t LZB
READ CYCLE NO. 2(1,3)
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = V IL)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
IS61LV12816L, IS61LV12816LL
8
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION Rev.00B
07/30/02
ISSI
®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
IS61LV12816L IS61LV12816LL
-8 ns -10 ns -12 ns -15 ns
Symbol Parameter Min. Max Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time 8 — 10 — 12 — 15 — ns
tSCE CE to Write End 7 — 8 — 8 — 10 — ns
tAW Address Setup Time 7 — 8 — 8 — 10 — ns
to Write End
tHA Address Hold from Write End 0 — 0 — 0 — 0 — n s
tSA Address Setup Time 0 — 0 — 0 — 0 — n s
tPWB LB, UB Valid to End of Write 6.5 — 8 — 9 — 10 — ns
tPWE1WE Pulse Width (OE = HIGH) 6 — 7 — 8 — 10 — n s
tPWE2WE Pulse Width (OE = LOW) 6. 5 — 8 — 10 — 11 — ns
tSD Data Setup to Write End 4 — 5 — 6 — 7 — ns
tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns
tHZWE
(3)
WE LOW to High-Z Output — 3 — 4 — 5 — 6 n s
tLZWE
(3)
WE HIGH to Low-Z Output 0 — 0 — 0 — 0 — n s
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V
and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
IS61LV12816L, IS61LV12816LL
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
9
PRELIMINARY INFORMATION Rev. 00B
07/30/02
ISSI
®
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
DOUT
DIN DATA
IN
VALID
t
LZWE
t
SD
UB_CEWR1.eps
IS61LV12816L, IS61LV12816LL
10
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION Rev.00B
07/30/02
ISSI
®
WRITE CYCLE NO. 2(1)
(WE Controlled, OE = HIGH during Write Cycle)
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
UB_CEWR2.e
p
s
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
DOUT
DIN
OE
DATAIN VALID
t
LZWE
t
SD
UB_CEWR3.eps
IS61LV12816L, IS61LV12816LL
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
11
PRELIMINARY INFORMATION Rev. 00B
07/30/02
ISSI
®
DATA UNDEFINED
t
WC
ADDRESS 1 ADDRESS 2
t
WC
HIGH-Z
t
PBW
WORD 1
LOW
WORD 2
UB_CEWR4.eps
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
DOUT
DIN
OE
DATAIN
VALID
t
LZWE
t
SD
t
PBW
DATAIN
VALID
t
SD
t
HD
t
SA
t
HA
t
HA
WRITE CYCLE NO. 4
(LB, UB Controlled, Back-to-Back Write)
(1,3)
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is refer
enced to the rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
IS61LV12816L, IS61LV12816LL
12
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION Rev.00B
07/30/02
ISSI
®
IS61LV12816L
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
8 IS61LV12816L-8B mini BGA
(6mm x 8mm)
IS61LV12816L-8LQ LQFP
IS61LV12816L-8T Plastic TSOP
10 IS61LV12816L-10B mini BGA
(6mm x 8mm)
IS61LV12816L-10LQ LQFP
IS61LV12816L-10T Plastic TSOP
IS61LV12816L
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
8 IS61LV12816L-8BI mini BGA
(6mm x 8mm)
IS61LV12816L-8LQI LQFP
IS61LV12816L-8TI Plastic TSOP
10 IS61LV12816L-10BI mini BGA
(6mm x 8mm)
IS61LV12816L-10LQI LQFP
IS61LV12816L-10TI Plastic TSOP
IS61LV12816LL
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
12 IS61LV12816LL-12B mini BGA
(6mm x 8mm)
IS61LV12816LL-12LQ LQFP
IS61LV12816LL-12T Plastic TSOP
15 IS61LV12816LL-15B mini BGA
(6mm x 8mm)
IS61LV12816LL-15LQ LQFP
IS61LV12816LL-15T Plastic TSOP
IS61LV12816LL
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
12 IS61LV12816LL-12BI mini BGA
(6mm x 8mm)
IS61LV12816LL-12LQI LQFP
IS61LV12816LL-12TI Plastic TSOP
15 IS61LV12816LL-15BI mini BGA
(6mm x 8mm)
IS61LV12816LL-15LQI LQFP
IS61LV12816LL-15TI Plastic TSOP
