FLASH
AS8F512K32
AS8F512K32
Rev. 5.4 08/10
Micross Components reserves the right to change products or specifi cations without notice.
1
PIN ASSIGNMENT
(Top View)
68 Lead CQFP (Q & Q1)
66 Lead PGA (P)
GENERAL DESCRIPTION
The AS8F512K32 is a 16 Megabit CMOS FLASH Memory
Module organized as 512Kx32 bits. The AS8F512K32 achieves
high speed access (70 to 150 ns), low power consumption and high
reliability by employing advanced CMOS memory technology.
An on-chip state machine controls the program and erase func-
tions. The embedded byte-program and sector/chip erase functions
are fully automatic. Data-protection of any sector combination is
accomplished using a hardware sector-protection feature.
The Erase/Resume function allows the sector erase operation to
read data from, or program to a non-erasing sector, then resume the
erase operation.
Device operations are selected by using standard commands into
the command register using standard microprocessor write timings.
The command register acts as an input to an internal state machine
that interprets the commands, controls the erase and programming
operations, outputs the status of the device, and outputs data stored
in the device. On initial power-up operation, the device defaults to
the read mode.
FEATURES
• Fast Access Times: 70, 90, 120 and 150ns
• Operation with single 5V (±10%)
• Theta JC= 1.00°C/w
• User confi gurable as 512Kx32, 1Mx16, or 2Mx8
• Eight Equal Sectors of 64K Bytes for each 512Kx8
• Compatible with JEDEC EEPROM command set
• Any Combination of Sectors can be Erased
• Supports Full Chip Erase
• Embedded Erase and Program Algorithms
• TTL Compatible Inputs and CMOS Outputs
• Built in decoupling caps for low noise operation
• Suspend Erase/Resume Function
• Individual Byte Read/ Write Control
• 20 years data retention
• 1,000,000 Program/Erase Cycles per sector minimum
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-94612
• MIL-STD-883
OPTIONS MARKINGS
• Timing
70ns -70
90ns -90
120ns -120
150ns -150
• Package
Ceramic Quad Flat pack Q No. 702
Ceramic Quad Flatpack Q1
Pin Grid Array P No. 904
For more products and information
please visit our web site at
www.micross.com
512K x 32 FLASH
FLASH MEMORY ARRAY
FLASH
AS8F512K32
AS8F512K32
Rev. 5.4 08/10
Micross Components reserves the right to change products or specifi cations without notice.
2
OPERATIONS
Read Mode
A low-level logic signal is applied to CE\ and OE\ pins to
read the output of the AS8F512K32. The CE\ is power control
and is used for device selection.
The delay from stable address to valid output data is the address
access time (tAVQA). The delay from CE\ equals logic low and
stable addresses to valid output data is the chip-enable access
time (tELQV). The output-enable access time (tGLQV) is the delay
from OE\ =low logic to valid output data, when CE\ =low logic
and addresses are stable for at least tAVQA-tGLQV.
Standby Mode
Icc supply current is reduced by applying a logic-high on the
CE\ to enter the standby mode. In the standby mode, the outputs
are placed in the high impedance state.
If the device is deselected during erasure or programming, the
device continues to draw active current until the operation is
complete.
Output Disable
OE\= VIL or CE\=VIH, output from the device is disabled and
the output pins (DQ0 - DQ7) are placed in the high-impedance
state.
Erasure and Programming
Erasure and programming of the AS8F512K32 are accom-
plished by writing a sequence of commands using standard
microprocessor write timings. The commands are written to
a command register and input to the command state machine.
The command state machine interprets the command entered
and initiates program, erase, suspend, and resume operations
as instructed. The command state machine acts as the interface
between the write-state machine and external chip operations.
The write-state machine controls all voltage generation, pulse
generation, preconditioning and verifi cation of the contents of
the memory . Program and block/chip-erase functions are fully
automatic. Once the end of a program or erase operation has
been reached, the device internally resets to the read mode. If
Vcc drops below the low-voltage-detect level (VLKO), any
operation in progress is aborted and the device resets to the
read mode. If a byte-program or chip-erase operation is in
progress, additional program/erase operations are ignored until
the operation completes.
Command Defi nitions
Operating modes are selected by writing particular address and
data sequences into the command register Command Sequence
Table . The device will reset to read mode if an incorrect ad-
dress and data value or writing them in the incorrect sequence
transpires. The command register does not fi ll an addressable
memory location. The register is used to store the command se-
quence, along with the address and data needed by the memory
array . Commands are written by setting CE\=VIL and OE\= VIH
and bring WE\ from logic-high to logic-low. Addresses are
latched on the falling edge of WE\ and data is latched on the
rising edge of WE\. Holding WE\ =VIL and toggling CE\ can
be used as an alternative.
Read/Reset Command
The read/reset mode is activated by writing either of the two
read/reset command register . The device remains in this mode
until one of the other valid command sequences is input into
the command register . Memory data can be read with standard
microprocessor read-cycle timing in the read mode.
On power up, the device defaults to the read/reset mode. A
read/reset command sequence if not required and memory
data is available.
Algorithm-Selection Command
The algorithm-selection command allows access to binary code
that matches the device with the proper programming -and
erase-command operations. After writing the three bus cycle
command sequence, the fi rst byte of the algorithm-selection
code (01) can be read from address XX00. The second byte
of the code (A4) can be read from address XX01. This mode
remains in effect until another valid command sequence is
written to the device.
Byte-Program Command
Byte-programming is a four-bus-cycle-command sequence.
The fi rst three bus cycles put the device into the program-setup
state. The fourth bus cycle loads the address location and the
data to be programmed into the device. The addresses are
latched on the falling edge of WE\ and the data is latched on
the rising edge of WE\ in the fourth cycle. The raising edge of
WE\ starts the byte-program operation. The embedded byte-
programming function automatically provides needed voltage
and timing to program and verify the cell margin. Any further
commands written to the device during the program operation
are ignored.
Programming can be preformed at any address location in
any order. When erased, all bits are in a logic state 1. Logic
0s are programmed into the device. Attempting to program
logic 1 into a bit that has been previously programmed to logic
0 causes the internal pulse counter to exceed the pulse-count
limit. This sets the exceed-timing-limit indicator (DQ5) to a
logic high state. Only an erase operation can change bits from
logic 0 to logic 1.
The status of the device during the automatic programming
operation can be monitored for the completion using the data-
polling feature or the toggle-bit feature . See the “operation
status” for the full description.
FLASH
AS8F512K32
AS8F512K32
Rev. 5.4 08/10
Micross Components reserves the right to change products or specifi cations without notice.
3
Chip Erase Command
Chip-erase is a six-bus-cycle command sequence. The
fi rst three bus cycles put the device into the erase-setup state.
The next two bus cycles unlock the erase mode. The sixth bus
cycle loads the chip erase command. This command sequence
is required to ensure that the memory contents are not erased
accidentally. The rising edge of WE\ starts the chip erase op-
eration. Any further commands written to the device during
the chip erase operation is ignored.
The embedded chip erase function automatically provides volt-
age and timings needed to program and verify all the memory
cells prior to electrical erase. It then erases and verifi es the cell
margin automatically. The user is not required to program the
memory cells prior to erase. The status of the device during the
automatic chip erase operation can be monitored for comple-
tion using the data-polling feature. See the "operation status"
section for a full description.
Sector-Erase Command
Sector erase is a six-bus-cycle command sequence. The fi rst
three bus cycles put the device into the erase-setup state. The
next two bus cycles unlock the erase mode. The sixth bus cycle
loads the sector erase command and the sector address location
to be erased. Any address location within the desired sector
can be used. The addresses are latched on the falling edge of
WE\ in the sixth bus cycle. After a delay of 100-ms from the
rising edge of WE\, the sector erase operation begins in the
selected source.
Sectors can be selected to be erased concurrently during the
sector-erase command sequence. For each additional sector
selected for erase, another bus cycle is issued. The bus cycle
loads the next sector-address location and the sector-erase com-
mand. The time between the end of the previous bus cycle and
the start of the next bus cycle must be less than 100 ms-other
wise, the new sector location is not loaded. A time delay of
100 ms from the raising edge of the last WE\ starts the sector
erase operation. If there is a falling edge of WE\ within the
100 ms time delay, the timer is reset.
One to eight sector address locations can be loaded in any
order. The state of the delay timer can be monitored using the
sector-erase-delay indicator (DQ3). If DQ3 is logic low, the
time delay has not expired. See the “operation status” for the
full description.
Any commands other than erase-suspend (B0) or sector erase
(30) written to the device during the sector erase operation
causes the device to exit the sector erase mode. The contents
of the sector(s) selected for erase is not valid. To complete the
sector-erase operation, reissue the sector erase command.
The embedded sector erase function automatically provides
voltage and timings needed to program and verify all the
memory cells prior to electrical erase and then erases and
verifi es the cell margin automatically . The user is not required
to program the memory cells prior to erase. The status of the
device during the automatic sector erase operation can be
monitored for completion using the data-polling feature or
the toggle bit feature. See the "operation status" section for a
full description.
Erase-Suspend Command
Sector-erase operations may be interrupted by the erase-sus-
pend command (B0) , in order to read data from an unaltered
sectors of the device. Erase-suspend is a one-bus-cycle com-
mand. The addresses can be VIL or VIH and the erase-suspend
command (B0) is latched on the rising edge of WE\. Once the
sector-erase operation is in progress, the erase-suspend com-
mand request the internal write-state-machine to halt operation
at predetermined break points. The erase-suspend command
is valid only during the sector-erase operation and is valid
only during the byte-programming and chip-erase operations.
The sector-erase delay timer expires immediately if the erase-
suspend command is issued while the delay is active.
After erase-suspend is issued, the device takes between
0.1ms and 15 ms to suspend the operation. The toggle bit must
be monitored to determine when the suspend has been executed.
When the toggle bit stops toggling, data can be read from sec-
tors that are not selected for erase. See the “operation status”
section for a full defi nition. Reading from a sector marked for
erase can result in invalid data.
Once the sector-erase operation is suspended, further writes of
the erase-suspend command are ignored. Any command other
than erase-suspend (B0) or erase-resume (30H) written to the
device during the erase-suspend mode causes the device to exit
the suspend mode. To complete the sector-erase operation,
reissue the sector-erase command sequence.
Erase-Resume Command
The erase-resume command (30H) restarts a suspended sector
erase operation from where it was halted to completion. Erase-
resume is a one-bus-cycle command. The addresses can be VIL
or VIH and the erase-resume command (30H) is latched on the
rising edge of WE\. When an erase-suspend/ erase-resume
command combination is written, the internal pulse counter
(exceed timing limit) is reset. The erase-resume command is
valid only in the erase-suspend state. After the erase-resume
command is executed, the device returns to the valid sector-
erase state and further writes of the erase-resume commands
are ignored. After the device has resumed the sector-erase
operation, another erase-resume command can be issued to
the device.
FLASH
AS8F512K32
AS8F512K32
Rev. 5.4 08/10
Micross Components reserves the right to change products or specifi cations without notice.
4
OPERATION STATUS
NOTES:
1. T= toggle, D=data, X=data undefi ned
2. DQ4, DQ2, DQ1, DQ0 are reserved for future use.
Status Bit Defi nition
During operation of the automatic embedded program and
erase functions, the status of the device can be determined by
reading the data state of designated outputs. The data-polling
bit (DQ7) and toggle-bit (DQ6) require multiple successive
reads to observe a change in the state of the designated output.
Operation Status Flags Table defi nes the values of the Flag
status.
Data-Polling DQ7
The data-polling status outputs the complement of the
data latched into the DQ7 data register while the write-state
machine is engaged in a program or erase operation. Data bit
DQ7 changing from complement to true indicates the end of
an operation. Data-polling is available only during the byte-
programming, chip-erase, sector-erase, and sector-erase timing
delay . Data-polling is valid after the rising edge of ?W/E in the
last bus cycle of the command sequence loaded into the com-
mand register . During a byte-program operation, reading DQ7
outputs the complement of the DQ7 data to be programmed at
the selected address location. Upon completion, reading DQ7
outputs the true DQ7 data loaded into the program data register .
During the erase operations, reading DQ7 outputs a 0. Upon
completion, reading DQ7 outputs a 1. Also, data polling must
be performed at a new sector address that is within a sector
being erased; otherwise the status is not valid. When using
data-polling, the address should remain stable throughout the
operation.
During a data-polling read, while ?W/E is low, data bit
DQ7 can change asynchronously. Depending on the read tim-
ing, the system can read valid data on DQ7, while other DQ pins
are still invalid. A subsequent read of the device is valid.
Data-Polling DQ6
The function of toggle-bit status, is to output data on DQ6
that toggles between 1 and 0 while the write-state machine is
engaged in a program or erase operation. When toggle-bit DQ6
stops toggling after two consecutive reads to the same address,
the operation is complete. The toggle-bit is only available dur-
ing the byte-programming, chip-erase, and sector-erase timing
delay. Toggle-bit data is valid after the raising edge of ?W/E
in the last bus cycle of the command sequence loaded into the
command register . Depending on the read timing, DQ6 can stop
toggling while other DQ pins are still invalid. A subsequent
read of the device is valid.
Exceed Time Limit DQ5
The program and erase operations use an internal pulse
counter to limit the number of pulses applied. If the pulse count
limit is exceeded, DQ5 is set to a 1 data state. This indicates
that the program or erase operation has failed. DQ7 will not
change from complemented data to true data and DQ6 will not
stop toggling when read. To continue operation, the device
must be reset.
This condition occurs when attempting to program a logic
1 state into a bit that has been programmed previously to a
logic 0. Only an erase operation can change bits from 0 to
1. After reset, the device is functional and can be erased and
reprogrammed.
Sector-Load- Timer DQ3
DQ3 is the sector-load timer status bit it determines if
the time to load additional sector addresses has expired. DQ3
remains a logic low for 80 μs after completion of a sector-
erase sequence. This indicates another sector -erase command
sequence can be issued. If DQ3 is at logic high, it indicates
that the delay has expired and attempts to issue additional
sector-erase commands are ignored.
The data polling bit and toggle bit are valid during the 100
μs time delay and can be used to determine if a valid sector erase
command has been issued. To ensure additional sector erase
commands have been accepted, the status of DQ3 should be
read before and after each additional sector-erase command. If
DQ3 is at a logic low on both reads, then the additional sector-
erase was accepted.
Device Operations
2
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Byte-programming in progress D\ T0X0XXX
Byte-programming exceed time limit D\ T1X0XXX
Byte-programming complete DDDDDDDD
Sector/chip erase in progress 0 T 0 X 1 X X X
Sector/chip erase exceed time limit 0 T 1 X 1 X X X
Sector/chip erase complete 1 1 1 1 1 1 1 1
Operation Status Flags
1
Table
FLASH
AS8F512K32
AS8F512K32
Rev. 5.4 08/10
Micross Components reserves the right to change products or specifi cations without notice.
5
DATA PROTECTION
Hardware-Sector Protection Feature
This feature disables both programming and erase opera-
tions on any combination of one to eight sectors. Commands
to program or erase a protected sector do not change the data
contained in the sector . The data-polling and toggle bits operate
for 2ms to 100ms and then return to valid data. This feature
is enabled using high-voltage VID (11.5V to 12V) on address
pin A9 and control pin OE\ and VIL on control pin CE\.
The device is delivered with all sector unprotected.
Sector-unprotected mode is available to unprotect protected
sectors.
Sector Protect Operation
The sector protect mode is activated when WE\=VIH,
CE\=VIL , and address pin A9 and control pin OE\ are forced
to VID. The sector-select address pins A18, A17, and A16 are
used to select the sector to be protected. Address pins A0-A15
and I/O pins DQ0- DQ7 must be stable and can be VIL or VIH.
Once the addresses are stable, WE\ is pulsed low for 100 ms.
The operation begins on the falling edge of WE\ and terminates
on the raising edge of WE\.
Sector Protect Verify
Verification of sector protection is activated when
WE\=VIH, CE\=VIL , OE\=VIL , and address pin A9 is VID. Ad-
dress pins A0 and A6 are set to VIL , and A1 is set to VIH. The
sector address pins A18, A17, and A16 select the sector to be
verifi ed. The other addresses can be VIH or VIL. If the sector
selected if protected, the DQs output O1. If the sector selected
is unprotected the DQs output is 00.
Sector protection can also be verifi ed using the algorithm-
selection command. After issuing the three bus-cycle command
sequence, the sector protection status can be read on DQ0. Set
address pins A0 = VIL, A1 = VIH, and A6 = VIL. Sector ad-
dress pins A18, A17, and A16 select the sector to be verifi ed.
The remaining addresses are set to VIL. If the sector selected
is protected. DQ0 outputs a 1 state, and if the sector selected
is unprotected DQ0 outputs a 0 state. This mode remains in
effect until another valid sequence is written to the device.
Sector Unprotect
Prior to sector unprotected, all sectors should be protected
using the sector unprotect mode. The sector unprotect is acti-
vated when WE\=VIH, and control pin CE\, OE\, and address
pin A9 are forced to VID. Address pins A6, A12, and A16 are
set to VIH. The sector select address pins A18, A17, and A16
can be VIL or VIH. All eight sectors are unprotected in parallel.
Once the inputs are stable, WE\ is pulsed low for 10ms. The
unprotect operation begins on the falling edge of WE\ and
terminates on the raising edge of WE\.
Sector Unprotect Verify
Verifi cation of the sector unprotected is activated when
WE\ = VIH, OE\ = VIL, CE\ = VIL, and address pin A9 = VID.
Select the sector to be verifi ed. Address A1 and A6 are set to
VIH and A0 to VIL. The other addresses can be VIL or VIH. If
the sector selected is protected, the DQs output a 01, if sector
selected is unprotected the DQs output a 00. Sector unprotect
can also be read using the algorithm selection command.
Low VCC Write Lock Out
During power-up and power-down , are locked out for
VCC less than VLKO If VCC<VLKO, the command inputs is
disabled and the device is reset to the read mode. On power-up,
if CE\=VIL, WE\= VIL, and OE\=VIH, the device does not accept
commands on the raising edge of WE. The device automatically
powers up in the read mode.
Glitiching
Pulses of less than 5ns (typical) on WE\, OE\, and CE\ will
not issue a write cycle.
Power Supply Consideration
Each device should have as a maximum of 0.1 mF ceramic
capacitor connected between Vcc and Vss to suppress circuit
noise. Printed circuit traces to Vcc should have be appropriate
to handle the current demand and minimize inductance.
FLASH
AS8F512K32
AS8F512K32
Rev. 5.4 08/10
Micross Components reserves the right to change products or specifi cations without notice.
6
Flow Chart 1.
Sector Protect Algorithm
No
No
Yes
Yes
Yes
Yes
Select Sector Address
A18,A17,A16
X=1
OE and, A9=V
ID
CE=V
IL
OE, A0 and A6 = V
IL
A1 = V
IH
Apply One
100 μs Pulse
Select Sector Address
A18, A17, A16 = V
IL
Read Data
Data = 01
?
Protect
Additional
Sector
?
A9=V
IH
or V
IL
Write Reset Command
X = 25
?
Sector-Protect Failed
X = X+1
End
Start
FLASH
AS8F512K32
AS8F512K32
Rev. 5.4 08/10
Micross Components reserves the right to change products or specifi cations without notice.
7
Flow Chart 2.
Sector Unprotect Algorithm
No
No
Yes
Yes
No
Yes
Protect All Sectors
X=1
CE,OE,A9=VID
A6, A12, A16=VIH
CE, OE, A0 = VIL
A6, A1 = VIH
Apply One
10 ms Pulse
Select Sector Address
A18, A17, A16 = VIL
Read Data
Data = 00
Last Sector?
A9=VIH or VIL
Write Reset Command
Next Sector Address
X = 1000
Sector-unprotect Failed
X = X+1
Start
End
FLASH
AS8F512K32
AS8F512K32
Rev. 5.4 08/10
Micross Components reserves the right to change products or specifi cations without notice.
8
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operation section of this specifi cation is not implied, Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc Supply Relative to Vss
Vcc (Note 1) .................................................-2.0V to +7.0V
A9 (Note 2)….........................................….. -2.0V to +14V
All Other Pins (Note 1)............…….............-2.0V to +7.0V
Operating Temperature, TA (Ambient).........55°C to +125°C
Storage Temperature .................................-65°C to +150°C
Power Dissipation………………..........................…...1.5W
Short Circuit Output Current (Note 3)…...................200mA
Lead Temperature (soldering 10 seconds).................+300°C
Junction Temperature................................................+165°C
Data Retention (Mil Temp).....................................20 Years
Endurance - Write / Erase Cycles.............. 1,000,000 Cycles
(Mil Temp)
NOTES:
1. Minimum DC voltage on input or I/O pins is -0.5V. During Voltage transitions, inputs may overshoot Vss to -2.0V for periods of
up to 20 ns. Maximum DC voltage on input or I/O pins is Vcc +0.5V. During Voltage transitions, inputs may overshoot Vcc
to +2.0V for periods of up to 20 ns.
2. Minium DC input voltage on A9 pin is -0.5V. During voltage transitions, A9 pins may overshoot Vss to -2.0V for periods of up
to 20 nS. Maximum DC input voltage on A9 is +12.5V inputs which may overshoot to +13.5V for periods of up to 20 ns.
3. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.
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FLASH
AS8F512K32
AS8F512K32
Rev. 5.4 08/10
Micross Components reserves the right to change products or specifi cations without notice.
9
LEGEND:
L = VIL, H = VIH, X = Don't Care, VID = 12V, See DC Charateristics for voltage levels
NOTE:
1. See Chip/Sector Erase Operation Timings and Alternate CE\ Controlled Write Operation Timings.
Operation CS\ 1-4 OE\ WE\ 1-4 A0 A1 A6 A9 I/O
Read L L H X X X X Data Out
Output Disable L H H X X X X HIGH Z
Standby and Write Inhibit H X X X X X X HIGH Z
Write L H L A0 A1 A6 A9 Data In
Sector Protect L VID L X X X VID X
Verify Sector Protect L L H L H L VID Data Out
Sector Unprotect
See Chart 1 See Chart 1
LLHH
See Chart 1
Data Out
Verify Sector Unprotect L L H L H H VID Data Out
Erase Operations L H
See Note 1 See Note 1 See Note 1 See Note 1 See Note 1
See Note 1
User Bus Operations
elbaTsserddArotceS
ROTCES81A71A61AEGNARSSERDDA
0AS000 FFFF0-00000
1AS001 FFFF1-00001
2AS010 FFFF2-00002
3AS011 FFFF3-00003
4AS100 FFFF4-00004
5AS101 FFFF5-00005
6AS110 FFFF6-00006
7AS111 FFFF7-00007
Pin
A0-A18
I/O 0-31
CE\ 1-4
WE\ 1-4
OE\
VSS
VCC Device Internal Power Supply (5.0 V+/- 10%)
Data Input/Outputs
Chip Enable
Write Enable
Output Enable
Pin Description
Function
Address Inputs
Device Ground
FLASH
AS8F512K32
AS8F512K32
Rev. 5.4 08/10
Micross Components reserves the right to change products or specifi cations without notice.
10
NOTES:
1. Icc active while Embedded Program or Embedded Erase Algorithm is in progress.
2. Not 100% tested.
3. Applies to 32 bit operations.
LEGEND:
RA = Address of the location to be read
PA = Address of the location to be programed
SA = Address of the sector to erased
Addresses A18, A17, A16 select 1 of 8 sectors
RD = Data to be read at selected address location
PD = Data to be programmed at selected address location
*Address pin A18, A17, A16, A15 = VIL or VIH for al bus cycle addresses except for program address (PA), sector
address(SA), and read address (RA).
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55°C < TA < 125°C; VCC = 5V +5%/-10%)
μΑ
μΑ
μΑ
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Reset 1 XXXX F0
Read 4 5555 AA 2AAA 55 5555 F0 RA RD
Algorithm Selection 4 5555 AA 2AAA 55 5555 90 RA RD
4 5555 AA 2AAA 55 5555 A0 PA PD
6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10
6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA 30
Sector Erase Supend XXXX B0 Erase-supend vaild during sector-erase operation
Sector Erase Resume XXXX 30 Erase-resume vaild only after erase supend
Fifth
Command Denfinitions Table
SixthFirst
Bus Cycles
Cycles
FourthSecond Third
Sector Erase
Chip Erase
Program
Command Sequence
FLASH
AS8F512K32
AS8F512K32
Rev. 5.4 08/10
Micross Components reserves the right to change products or specifi cations without notice.
11
Read Operation Timings
NOTES:
1. See Test Specifi cation for test conditions.
2. Output driver disable time.
3. Guaranteed but not Tested.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(-55°C < TA < 125°C; VCC = 5V -5%/+10%)
Addresses
WE\
Outputs
Addresses Stable
Output Valid
OV
High-Z
tDF
tCE
tCE tOH
High-Z
JEDEC Std. -70 -90 -120 -150
t
AVAV
t
RC
CE\=V
IL
,
OE\=V
IL
Min 70 90 120 150 ns
t
AVQV
t
ACC
CE\=V
IL
,
OE\=V
IL
Max 70 90 120 150 ns
t
ELQV
t
CE
Max 70 90 120 150 ns
t
GLQV
t
OE
Max 30 35 50 55 ns
Read Min 0 0 0 0ns
Toggle and
Data\Polling Min 10 10 10 10 ns
t
EHQZ
t
HZ
Max 20 20 30 35 ns
t
GHQZ
t
DF
20 20 30 35 ns
t
AXQX
t
OH
Min 0 0 0 0 ns
Output Hold Time from Addresses, CE\
or OE\, Whichever Occurs First
Output Enable to Output High Z
(Note 2,3)
t
OEH
Chip Enable High to Output High Z
(Note 2, 3)
Read Cycle Time (Note 3)
Address to Output Delay
Chip Enable Low to Output Valid
Output Enable to Output Delay
Output Enable Hold Time
(Note 3)
Parameter Description Units
Parameter
Symbol
Test Setup
Speed Options
FLASH
AS8F512K32
AS8F512K32
Rev. 5.4 08/10
Micross Components reserves the right to change products or specifi cations without notice.
12
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(-55°C < TA < 125°C; VCC = 5V +/- 10%)
Erase and Program WE\ Controlled
Units
JEDEC Std. -70 -90 -120 -150
t
AVAV
t
WC
Write Cycle Time Min 70 90 120 150 ns
t
AVWL
t
AS
Address Setup Time Min ns
t
WLAX
t
AH
Address Hold Time Min45455050ns
t
DVWH
t
DS
Data Setup Time Min 30 45 50 50 ns
t
WHDX
t
DH
Write Enable High to Input Transition Min ns
t
OES
Output Enable Setup Time Min ns
t
GHWL
t
GHWL
Read Recover time Before Write
(OE\ high to WE\ low) Min ns
t
ELWL
t
CS
CE\ Setup Time Min ns
t
WHEH
t
CH
CE\ Hold Time Min ns
t
WLWH
t
WP
Write Pulse Width Min 35 45 50 50 ns
t
WHWL
t
WPH
Write Pulse Width High Min ns
t
WHWH1
t
WHWH1
Programming Operation Min us
t
WHWH2
t
WHWH2
Sector Erase Operation Max sec
t
WHWH3
t
WHWH3
Chip Erase Operation Max sec
t
VCHEL
V
CC
Setup Time Min us
Chip Program Time Max sec
16
30
120
50
Parameter
Symbol Parameter Description Speed Options
0
0
0
0
0
0
20
50
FLASH
AS8F512K32
AS8F512K32
Rev. 5.4 08/10
Micross Components reserves the right to change products or specifi cations without notice.
13
Program Operation Timings
NOTE: PA= Program Address, PD= Program data, DOUT is the true data at the program address.
Addresses
CE\
OE\
Data
Vcc
555h PA PA PA
AOh PD Status DOUT
tWC tAS
tAH
tCH
tGH-
tWP
tCS tDS tDH
tWPH
tWHWH1
FLASH
AS8F512K32
AS8F512K32
Rev. 5.4 08/10
Micross Components reserves the right to change products or specifi cations without notice.
14
Chip/Sector Erase Operation Timings
NOTE: SA= Sector Address. VA = Valid Address for reading status data.
Addresses
CE\
OE\
Data
Vcc
2AAh SA VA VA
55h In Prog-
ress Complete
tWC tAS
tAH
tCH
tGH-
tWP
tCS tDS tDH
tWPH
tWHWH2
30th
10 for Chip Erase
555h for Chip Erase
FLASH
AS8F512K32
AS8F512K32
Rev. 5.4 08/10
Micross Components reserves the right to change products or specifi cations without notice.
15
Toggle Bit Timings ( During Embedded Algorithms)
Data Polling Timings (During Embedded Algorithms)
Addresses VA VA VA
CE\
OE\
WE\
DQ7
DQ0-DQ6
High-Z
Valid Data
True
Complement
Complement
High-Z
Valid Data
True
Status Data
Status Data
tRC
tCE
tCH tOE
tOEH tDF
tOH
Addresses VA VA
CE\
OE\
WE\
DQ6/DQ2 Valid Status
tRC
tCE
tCH tOE
tOEH tDF
tOH
VA VA
(fi rst read)
Valid Status Valid Status Valid Status
NOTE: VA=Valid address; not required for DQ6. Illustration shows fi rst two status cycles after command sequence, last
status read cycle, and array data read cycle.
NOTE: VA=Valid address. Illustration shows fi rst status cycle after command sequence, last status read cycle, and array
data read cycle.
FLASH
AS8F512K32
AS8F512K32
Rev. 5.4 08/10
Micross Components reserves the right to change products or specifi cations without notice.
16
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(-55°C < TA < 125°C; VCC = 5V +/- 10%)
Units
JEDEC Std. -70 -90 -120 -150
tAVAV tWC Write Cycle Time Min 70 90 120 150 ns
tAVEL tAS Address Setup Time Min ns
tELAX tAH Address Hold Time Min 45 45 50 50 ns
tDVEH tDS Data Setup Time Min 30 45 50 50 ns
tEHDX tDH Data Hold Time Min ns
tGHEL tGHEL Read Recover time Before Write Min ns
tWLEL tWS Setup Time, WE\ Min ns
tEHWH tWH Hold Time, WE\ Min ns
tELEH tCP Pulse Duration CE\ Low Min 35 45 50 50 ns
tEHEL tCPH Pulse Duration CE\ High Min ns
tWHWH1 tWHWH1 Byte Programming Operation Min us
tWHWH2 tWHWH2 Sector Erase Operation Max sec
Chip Erase Max sec
Chip Programming Max sec
30
16
120
50
Speed Options
0
0
0
0
0
20
Erase and Program CE\ Controlled (Alternate CE\ Controlled Writes)
Parameter
Symbol Parameter Description
FLASH
AS8F512K32
AS8F512K32
Rev. 5.4 08/10
Micross Components reserves the right to change products or specifi cations without notice.
17
Alternate CE\ Controlled Write Operation Timings
FLASH
AS8F512K32
AS8F512K32
Rev. 5.4 08/10
Micross Components reserves the right to change products or specifi cations without notice.
18
NOTES:
Vz is programable from -2V to + 7V.
IOL and IOH programmable from 0 to 16 mA.
Vz is typically the midpoint of VOH and VOL.
IOL and IOH are adjusted to simulate a typical resistive load circuit.
AC TEST CONDITIONS
FLASH
AS8F512K32
AS8F512K32
Rev. 5.4 08/10
Micross Components reserves the right to change products or specifi cations without notice.
19
MECHANICAL DEFINITIONS*
Micross Case #702 (Package Designator Q)
SMD 5962-94612, Case Outline M
*All measurements are in inches.
A
D2
D1
D
b
e
DETAIL A
L1
1o - 7o
R
B
A2
SEE DETAIL A
E
MIN MAX
A 0.123 0.200
A1 0.118 0.186
A2 0.005 0.015
B
b 0.013 0.017
D
D1 0.870 0.890
D2 0.980 1.000
E 0.936 0.956
e
R
L1 0.035 0.045
0.010 TYP
SYMBOL
0.800 BSC
0.050 BSC
SMD SPECIFICATIONS
0.010 REF
FLASH
AS8F512K32
AS8F512K32
Rev. 5.4 08/10
Micross Components reserves the right to change products or specifi cations without notice.
20
MECHANICAL DEFINITIONS*
Micross Case (Package Designator Q1)
SMD 5962-94612, Case Outline A
*All measurements are in inches.
MIN MAX
A--- 0.200
A1 0.054 ---
b0.013 0.017
B
c0.0090.012
D/E 0.980 1.000
D1/E1 0.870 0.890
D2/E2
e
L0.035 0.045
R
SYMBOL
SMD SPECIFICATIONS
0.010 TYP
0.010 TYP
0.800 BSC
0.050 BSC
FLASH
AS8F512K32
AS8F512K32
Rev. 5.4 08/10
Micross Components reserves the right to change products or specifi cations without notice.
21
Micross Case #904 (Package Designator P)
SMD 5962-94612, Case Outline 4
MECHANICAL DEFINITIONS*
*All measurements are in inches.
4 x D
D1
D2
E1
Pin 66 ePin 11
Pin 1
(identifi ed by
0.060 square pad)
Pin 56
φb2
A
A1
L
φ b
e
φb1
E
MIN MAX
A 0.135 0.195
A1 0.025 0.035
φ
b0.016 0.020
φ
b1 0.045 0.055
φ
b2 0.065 0.075
D 1.064 1.086
D1/E1
D2
E 1.020 1.060
e
L 0.145 0.155
0.600 BSC
0.100 BSC
SYMBOL
1.000 BSC
SMD SPECIFICATIONS
FLASH
AS8F512K32
AS8F512K32
Rev. 5.4 08/10
Micross Components reserves the right to change products or specifi cations without notice.
22
ORDERING INFORMATION
*AVAILABLE PROCESSES
CT = Commercial Temperature Range 0oC to +70oC
IT = Industrial Temperature Range -40oC to +85oC
XT = Extended Temperature Range -55oC to +125oC
883C = Full Military Processing -55oC to +125oC
Device Number Package
Type
Speed
ns Process Device Number Package
Type
Speed
ns Process
AS8F512K32 Q -70 /* AS8F512K32 Q1 -70 /*
AS8F512K32 Q -90 /* AS8F512K32 Q1 -90/*
AS8F512K32 Q -120 /* AS8F512K32 Q1 -120 /*
AS8F512K32 Q -150 /* AS8F512K32 Q1 -150 /*
Device Number Package
Type
Speed
ns Process
AS8F512K32 P -70 /*
AS8F512K32 P -90/*
AS8F512K32 P -120 /*
AS8F512K32 P -150 /*
EXAMPLE: AS8F512K32Q-120/XT
EXAMPLE: AS8F512K32P-70/IT
EXAMPLE: AS8F512K32Q-150/883C
FLASH
AS8F512K32
AS8F512K32
Rev. 5.4 08/10
Micross Components reserves the right to change products or specifi cations without notice.
23
MICROSS TO DSCC PART NUMBER*
CROSS REFERENCE
Micross Package Designator Q
Micross Part # SMD Part #
AS8F512K32Q-150/883C 5962-9461201HMX
AS8F512K32Q-120/883C 5962-9461202HMX
AS8F512K32Q-90/883C 5962-9461203HMX
AS8F512K32Q-70/883C 5962-9461204HMX
AS8F512K32Q-150/883C 5962-9461201HMX
AS8F512K32Q-120/883C 5962-9461202HMX
AS8F512K32Q-90/883C 5962-9461203HMX
AS8F512K32Q-70/883C 5962-9461204HMX
Micross Package Designator P
Micross Part # SMD Part #
AS8F512K32P-150/883C 5962-9461201H4X
AS8F512K32P-120/883C 5962-9461202H4X
AS8F512K32P-90/883C 5962-9461203H4X
AS8F512K32P-70/883C 5962-9461204H4X
AS8F512K32P-150/883C 5962-9461201H4X
AS8F512K32P-120/883C 5962-9461202H4X
AS8F512K32P-90/883C 5962-9461203H4X
AS8F512K32P-70/883C 5962-9461204H4X
*Micross part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.
Micross Package Designator Q
Micross Part # SMD Part #
AS8F512K32Q1-150/883C 5962-9461201HMX
AS8F512K32Q1-120/883C 5962-9461202HMX
AS8F512K32Q1-90/883C 5962-9461203HMX
AS8F512K32Q1-70/883C 5962-9461204HMX
AS8F512K32Q1-150/883C 5962-9461201HMX
AS8F512K32Q1-120/883C 5962-9461202HMX
AS8F512K32Q1-90/883C 5962-9461203HMX
AS8F512K32Q1-70/883C 5962-9461204HMX
FLASH
AS8F512K32
AS8F512K32
Rev. 5.4 08/10
Micross Components reserves the right to change products or specifi cations without notice.
24
DOCUMENT TITLE
512K x 32 FLASH FLASH MEMORY ARRAY
REVISION HISTORY
Rev # History Release Date Status
5.4 Added data retention data to pg 1 August 2010 Release
& pg 8
