CY7C185A 8K x 8 Static RAM Features * High speed -- 20 ns * CMOS for optimum speed/power * Low active power -- 743 mW * Low standby Power -- 220 mW * TTL-compatible inputs and outputs * Easy memory expansion with CE1, CE2 and OE features * Automatic power-down when deselected Functional Description The CY7C185A is a high-performance CMOS static RAM organized as 8192 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE), and three-state drivers. The device has an automatic power-down feature (CE1), reducing the power consumption by over 70% when deselected. The CY7C185A is in the standard 300-mil-wide DIP package and leadless chip carrier. Writing to the device is accomplished when the Chip Enable one (CE1) and Write Enable (WE) inputs are both LOW, and the Chip Enable two (CE2) input is HIGH. Data on the eight I/O pins (I/O 0 through I/O 7) is written into the memory location specified on the address pins (A0 through A12). Reading the device is accomplished by taking Chip Enable one (CE1) and Output Enable (OE) LOW, while taking Write Enable (WE) and Chip Enable two (CE 2) HIGH. Under these conditions, the contents of the memory location specified on the address pins will appear on the I/O pins. The I/O pins remain in a high-impedance state when Chip Enable one (CE1) or Output Enable (OE) is HIGH, or Write Enable (WE) or Chip Enable two (CE2) is LOW. A die coat is used to ensure alpha immunity. Logic Block Diagram Pin Configurations LCC Top View I/O0 INPUT BUFFER I/O2 SENSE AMPS A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER I/O1 8K x 8 ARRAY I/O3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 I/O4 VCC WE CE2 A3 A2 A1 OE A0 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 NC A7 A8 A9 A10 A11 A12 I/O0 I/O1 3 2 1 28 27 4 26 5 25 6 24 7 23 8 22 9 21 10 20 11 19 12 18 1314151617 CE2 A3 A2 A1 OE A0 CE1 I/O7 I/O6 I/O2 GND I/O3 I/O4 I/O5 NC A4 A5 A6 A7 A8 A9 A10 A11 A12 I/O0 I/O1 I/O2 GND A6 A5 A4 VCC WE DIP Top View C185A-3 C185A-2 I/O5 I/O6 POWER DOWN I/O7 A12 A11 A10 A0 COLUMN DECODER A9 CE1 CE2 WE OE C185A-1 Selection Guide[1] Maximum Access Time (ns) Maximum Operating Current (mA) Military Maximum Standby Current (mA) Military 7C185A-20 7C185A-25 7C185A-35 7C185A-45 20 25 35 45 135 125 125 125 40/20 40/20 30/20 30/20 Note: 1. For commercial specifications, see the CY7C185 data sheet. Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 October 4, 1999 CY7C185A DC Input Voltage[2] ................................................. -0.5V to +7.0V Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Storage Temperature .................................. -65C to +150C Latch-Up Current .................................................... >200 mA Ambient Temperature with Power Applied .............................................. -55C to +125C Operating Range Supply Voltage to Ground Potential (Pin 28 to Pin 14) ........................................... -0.5V to +7.0V Range DC Voltage Applied to Outputs in High Z State[2] .....................................................-0.5V to +7.0V Military [4] Ambient Temperature[3] VCC -55C to +125C 5V 10% Electrical Characteristics Over the Operating Range[4] 7C185A-20 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = -4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage Min. Max. 2.4 [2] Unit V 0.4 V 2.2 VCC V -0.5 0.8 V VIL Input LOW Voltage IIX Input Load Current GND VI VCC -10 +10 A IOZ Output Leakage Current GND VI VCC, Output Disabled VCC = Max., VOUT = GND -10 +10 A -300 mA [5] IOS Output Short Circuit Current ICC VCC Operating Supply Current VCC = Max. IOUT = 0 mA Military 135 mA ISB1 Automatic CE1 Power-Down Current Max. V CC, CE1 VIH, Min. Duty Cycle = 100% Military 40 mA ISB2 Automatic CE1 Power-Down Current Max. V CC, CE1 VCC -0.3V VIN VCC -0.3Vor VIN 0.3V Military 20 mA Electrical Characteristics Over the Operating Range[4] (continued) 7C185A-25 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = -4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage Min. Max. 2.4 7C185A-35, 45 Min. 2.4 0.4 2.2 [2] Max. VCC 2.2 Unit V 0.4 V VCC V VIL Input LOW Voltage -0.5 0.8 -0.5 0.8 V IIX Input Load Current GND VI VCC -10 +10 -10 +10 A IOZ Output Leakage Current GND VI VCC, Output Disabled -10 +10 -10 +10 A IOS Output Short Circuit Current[5] VCC = Max., VOUT = GND -300 -300 mA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA Military 125 125 mA ISB1 Automatic CE1 Power-Down Current Max. VCC, CE1 VIH, Min. Duty Cycle=100% Military 40 30 mA ISB2 Automatic CE1 Power-Down Current Max. VCC, CE1 VCC -0.3V Military VIN VCC -0.3Vor VIN 0.3V 20 20 mA Notes: 2. VIL (min.) = - 3.0V for pulse durations less than 30 ns. 3. TA is the case temperature. 4. See the last page of this specification for Group A subgroup testing information. 5. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 2 CY7C185A Capacitance[6] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. Unit 10 pF 10 pF Note: 6. Tested initially and after any design or process changes that may affect these parameters. AC Test Loads and Waveforms R1 481 R1 481 5V OUTPUT 5V OUTPUT R2 255 30 pF INCLUDING JIG AND SCOPE ALL INPUT PULSES 3.0V INCLUDING JIG AND SCOPE (a) Equivalent to: R2 255 5 pF GND 5 ns C185A-4 (b) THEVENIN EQUIVALENT 167 OUTPUT 10% 1.73V 3 90% 90% 10% 5 ns C185A-5 CY7C185A Switching Characteristics Over the Operating Range[7] Parameter Description 7C185A-20 7C185A-25 7C185A-35 7C185A-45 Min. Min. Min. Min. Max. Max. Max. Max. Unit READ CYCLE tRC Read Cycle Time 20 25 tAA Address to Data Valid tOHA Data Hold from Address Change tACE1 CE1 LOW to Data Valid 20 25 35 45 ns tACE2 CE2 HIGH to Data Valid 20 25 35 30 ns tDOE OE LOW to Data Valid 10 12 15 20 ns tLZOE OE LOW to Low Z 20 3 35 25 3 3 45 3 3 ns 3 ns OE HIGH to High Z CE1 LOW to Low Z[9] 5 5 5 5 ns tLZCE2 CE2 HIGH to Low Z 3 3 3 3 ns tHZCE CE1 HIGH to High Z CE2 LOW to High Z tPU CE1 LOW to Power-Up tPD CE1 HIGH to Power-Down 8 0 12 ns tLZCE1 [8, 9] 10 ns tHZOE WRITE CYCLE 8 35 3 3 [8] 45 10 0 20 15 15 0 20 15 0 20 ns ns ns 25 ns [10] tWC Write Cycle Time 20 20 25 40 ns tSCE1 CE1 LOW to Write End 15 20 25 30 ns tSCE2 CE2 HIGH to Write End 15 20 25 30 ns tAW Address Set-Up to Write End 15 20 25 30 ns tHA Address Hold from Write End 0 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 0 ns tPWE WE Pulse Width 15 15 20 20 ns tSD Data Set-Up to Write End 10 10 15 15 ns tHD Data Hold from Write End 0 0 0 0 ns tLZWE WE HIGH to Low Z 3 5 5 5 ns tHZWE [8] WE LOW to High Z 7 7 10 15 ns Notes: 7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OL/IOH and 30-pF load capacitance. 8. t HZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device. 10. Device is continuously selected. OE, CE = VIL. CE2 = VIH. 4 CY7C185A Switching Waveforms Read Cycle No. 1[10, 11] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID C185A-6 Read Cycle No. 2[11, 12] tRC CE1 CE2 tACE OE OE tHZOE tDOE DATA OUT tHZCE tLZOE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU ICC 50% 50% ISB C185A-7 Write Cycle No. 1 (WE Controlled)[13, 14] tWC ADDRESS tSCE1 CE1 CE2 tSCE2 OE tAW tHA tSA WE tPWE tSD tHD DATAIN VALID DATA IN tHZOE tLZWE HIGH IMPEDANCE DATA I/O DATA UNDEFINED C185A-8 Notes: 11. Address valid prior to or coincident with CE transition LOW. 12. WE is HIGH for read cycle. 13. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 14. Data I/O is high impedance if OE = VIH. 5 CY7C185A Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled)[13, 14, 15] tWC ADDRESS tSCE1 CE1 tSA CE2 tSCE2 tHA tAW tPWE WE tSD DATAIN VALID DATA IN DATA I/O tHD HIGH IMPEDANCE C185A-9 Note: 15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 6 CY7C185A NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.2 NORMALIZED I CC, I SB 1.2 I CC 0.8 0.6 0.4 0.0 4.0 0.8 0.6 0.4 4.5 5.0 5.5 SUPPLY VOLTAGE (V) 1.3 1.4 NORMALIZED tAA NORMALIZED t AA 1.6 1.2 1.1 TA =25C 1.0 1.2 1.0 VCC =5.0V 0.8 0.9 4.5 5.0 5.5 0.6 -55 6.0 25 30.0 2.5 25.0 DELTA t AA (ns) 3.0 2.0 1.5 1.0 3.0 4.0 SUPPLY VOLTAGE (V) 100 80 VCC =5.0V TA =25C 60 40 20 0 0.0 OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 VCC =5.0V TA =25C 80 60 40 20 0 0.0 125 5.0 20.0 15.0 10.0 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) C185A-10 NORMALIZED I CC vs. CYCLE TIME 1.25 VCC =4.5V TA =25C 5.0 0.5 2.0 120 TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 1.0 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE AMBIENT TEMPERATURE (C) SUPPLY VOLTAGE (V) NORMALIZED IPO 25 125 AMBIENT TEMPERATURE (C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 1.4 0.0 0.0 VCC =5.0V VIN =5.0V ISB 0.0 -55 6.0 NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 0.8 4.0 I CC 0.2 I SB 0.2 1.0 OUTPUT SINK CURRENT (mA) 1.0 0 200 400 600 800 1000 CAPACITANCE (pF) NORMALIZED I CC NORMALIZED I CC, ISB 1.4 OUTPUT SOURCE CURRENT (mA) Typical DC and AC Characteristics VCC =5.0V TA =25C VCC =0.5V 1.00 0.75 0.50 10 20 30 40 CYCLE FREQUENCY (MHz) C185A-11 7 CY7C185A Truth Table Address Designators CE1 CE2 WE OE Input/Output Mode H X X X High Z Deselect/ Power-Down X L X X High Z Deselect L H H L Data Out Read L H L X Data In Write L H H H High Z Deselect Address Name Address Function Pin Number A4 X3 2 A5 X4 3 A6 X5 4 A7 X6 5 A8 X7 6 A9 Y1 7 A10 Y4 8 A11 Y3 9 A12 Y0 10 A0 Y2 21 A1 X0 23 A2 X1 24 Ordering Information Speed (ns) Ordering Code Package Name Package Type Operating Range 20 CY7C185A-20DMB D22 28-Lead (300-Mil) CerDIP Military 25 CY7C185A-25DMB D22 28-Lead (300-Mil) CerDIP Military 35 CY7C185A-35DMB D22 28-Lead (300-Mil) CerDIP Military 45 CY7C185A-45DMB D22 28-Lead (300-Mil) CerDIP Military 8 CY7C185A MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Switching Characteristics Subgroups Parameter Subgroups VOH 1, 2, 3 READ CYCLE VOL 1, 2, 3 tRC 7, 8, 9, 10, 11 VIH 1, 2, 3 tAA 7, 8, 9, 10, 11 VIL Max. 1, 2, 3 tOHA 7, 8, 9, 10, 11 IIX 1, 2, 3 tACE1 7, 8, 9, 10, 11 IOZ 1, 2, 3 tACE2 7, 8, 9, 10, 11 IOS 1, 2, 3 tDOE 7, 8, 9, 10, 11 ICC 1, 2, 3 WRITE CYCLE ISB1 1, 2, 3 tWC 7, 8, 9, 10, 11 ISB2 1, 2, 3 tSCE1 7, 8, 9, 10, 11 tSCE2 7, 8, 9, 10, 11 tAW 7, 8, 9, 10, 11 tHA 7, 8, 9, 10, 11 tSA 7, 8, 9, 10, 11 tPWE 7, 8, 9, 10, 11 tSD 7, 8, 9, 10, 11 tHD 7, 8, 9, 10, 11 Document #: 38-00114-C 9 CY7C185A Package Diagram 28-Lead (300-Mil) CerDIP D22 MIL-STD-1835 D-15 Config. A 51-80032 (c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.